Semiconductor devices and inverter circuits
By connecting a freewheeling diode in parallel with the MOS power device and optimizing the overlap area between the source electrode and the contact region, the problem of poor reverse recovery characteristics of the MOS power device is solved, and the improvement of low loss and high efficiency reverse recovery characteristics is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HISENSE HOME APPLIANCES GRP CO LTD
- Filing Date
- 2026-01-31
- Publication Date
- 2026-05-26
AI Technical Summary
Existing silicon-based MOS power devices suffer from poor reverse recovery characteristics due to the parasitic PN junction body diode freewheeling during reverse freewheeling, resulting in large reverse recovery losses and reverse recovery currents.
In a MOS power device, a freewheeling diode is connected in parallel. By configuring the overlap area of the source electrode and the contact area, the current carrying capacity of the parasitic PN junction body diode is made less than half that of the MOS transistor, while the current carrying capacity of the freewheeling diode is greater than that of the parasitic PN junction body diode. The total current carrying capacity is less than or equal to the current carrying capacity of the MOS power device, thus realizing the anti-parallel connection of the MOS transistor and the parasitic PN junction body diode into a single unit.
It effectively reduces the reverse recovery loss and switching loss of MOS power devices, improves the reverse recovery characteristics, and maintains the current carrying capacity and forward voltage drop characteristics of MOS transistors without sacrificing the withstand voltage and leakage characteristics, thereby reducing the complexity of system control.
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Figure CN122094162A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of semiconductors, and in particular relates to a semiconductor device and an inverter circuit. Background Technology
[0002] Semiconductor devices incorporating MOS power devices are widely used in numerous fields due to their advantages such as voltage control, fast switching speed, wide safe operating area, and high reliability.
[0003] However, when silicon-based MOS power devices are reverse-following current, the current is entirely driven by the parasitic PN junction body diode. When the freewheeling current flows, a large number of minority carriers are accumulated, resulting in a large reverse recovery loss when disconnected, i.e., a large amount of reverse recovery charge and a large reverse recovery current. The switching loss of the MOS power device is also large.
[0004] Therefore, the related semiconductor devices have poor reverse recovery characteristics, and there is an urgent need to provide a semiconductor device to improve the reverse recovery characteristics. Summary of the Invention
[0005] The purpose of this application is to provide a semiconductor device and an inverter circuit that aims to solve the problem of poor reverse recovery characteristics in related semiconductor devices.
[0006] This application provides a semiconductor device, which includes a MOS power device and a freewheeling diode connected in anti-parallel to the MOS power device. The MOS power device is a silicon-based MOS power device and has a MOS transistor and a parasitic PN junction diode. The MOS transistor and the parasitic PN junction diode are integrally formed in anti-parallel configuration. The MOS power device includes: A substrate having a drain layer between an upper surface of the substrate and a lower surface of the substrate opposite to the upper surface of the substrate; A drift layer, which is located on the upper surface side of the drain layer; A trap layer, which is selectively located on the upper surface side of the drift layer; The contact area is selectively disposed on the upper surface side of the trap layer; The source region is selectively disposed on the upper surface side of the well layer and in contact with the contact region; A gate trench that extends through the source region and the well layer into the drift layer; A gate insulating layer that covers the inner surface of the gate trench; A gate electrode is disposed inside the gate trench and faces the source region, the well layer and the drift layer through the gate insulating layer; An interlayer insulating film covers the gate electrode, exposing a portion of the source region and a portion of the well layer in the interlayer insulating film to form a contact hole; a source electrode covers the interlayer insulating film and contacts the upper surface of the source region and a portion of the upper surface of the well layer via the contact hole; Drain electrode, which is located on the lower surface side of the drain layer; The drain layer, the drift layer, and the source region are of a first semiconductor type, and the well layer and the contact region are of a second semiconductor type. Specifically, by configuring the overlap area of the source electrode and the contact region, the current-carrying capacity of the parasitic PN junction body diode is less than or equal to half the current-carrying capacity of the MOS transistor, and the current-carrying capacity of the freewheeling diode is greater than or equal to the current-carrying capacity of the parasitic PN junction body diode. The total current-carrying capacity of the freewheeling diode and the parasitic PN junction body diode is less than or equal to the current-carrying capacity of the MOS power device.
[0007] In one embodiment, the current-carrying capacity of the freewheeling diode is less than or equal to 6 times the current-carrying capacity of the parasitic PN junction diode.
[0008] In one embodiment, the current-carrying capacity of the freewheeling diode is greater than or equal to half the current-carrying capacity of the MOS transistor.
[0009] In one embodiment, the MOS power device satisfies the following three relationships: Z≤1.2Y, Z>0, Y+Z=J; Wherein, Y is the length of overlap between the source region and the contact hole in the lateral direction, Z is the length of overlap between the contact region and the contact hole in the lateral direction, and J is the length of a single contact hole in the lateral direction; the lateral direction is the direction in which the two source regions sandwich the contact region.
[0010] In one embodiment, the MOS power device also satisfies the following relationship: Z ≥ 0.1Y.
[0011] In one embodiment, the MOS power device satisfies the following relationship: C / (L1) L2) < 1 / 2; Wherein, L1 is the length of the contact hole in the lateral direction, L2 is the length of the source region in the longitudinal direction, the lateral direction is the direction in which the two source regions sandwich the contact region, the thickness direction is perpendicular to the upper surface of the substrate, and the lateral direction, the longitudinal direction and the thickness direction are mutually perpendicular, and C is the total area of the multiple contact holes.
[0012] In one embodiment, the MOS power device also satisfies the following relationship: C / (L1) L2) > 1 / 10.
[0013] In one embodiment, the contact holes may be spaced apart in the lateral and / or longitudinal directions.
[0014] In one embodiment, the freewheeling diode is a silicon-based freewheeling diode, and the reverse withstand voltage of the MOS power device is greater than or equal to 300V.
[0015] This invention also provides an inverter circuit, including an upper bridge arm and a lower bridge arm connected in series, both of which include the aforementioned semiconductor device.
[0016] The beneficial effects of this invention compared to the prior art are as follows: When a freewheeling diode is connected in reverse parallel to a MOS power device, since the parasitic PN junction diode only bears a small portion of the freewheeling current, while the freewheeling diode bears the majority, the area of the parasitic PN junction diode built into the MOS power device can be reduced, further improving the reverse recovery characteristics of the MOS power device. By adding a freewheeling diode, when the MOS power device experiences reverse freewheeling, the freewheeling current is shunted to both the parasitic PN junction diode and the freewheeling diode. Because the freewheeling diode offers greater process freedom than the MOS power device, it is easier to reduce reverse current. Recovery loss, meaning that under the same specifications, a freewheeling diode is more likely to achieve lower reverse recovery loss (i.e., lower reverse recovery charge and reverse recovery current) than the parasitic PN junction diode of a MOS power device. Therefore, correspondingly, the switching loss of the MOS power device is lower than that without a freewheeling diode. Furthermore, this invention reduces the reverse recovery loss of the MOS power device by using a low-reverse-recovery-loss freewheeling diode for current shunting. Compared to MOS power devices employing carrier lifetime control technology, this does not sacrifice the current-carrying capacity and forward voltage drop characteristics of the MOS transistor. Compared to MOS power devices with integrated Schottky diodes... The device boasts higher withstand voltage and lower leakage current. Because the freewheeling diode's current-carrying capacity exceeds that of the parasitic PN junction diode, the freewheeling diode handles most of the freewheeling current. This allows for a smaller area of the built-in parasitic PN junction diode in the MOS power device, further reducing the impact of the poor reverse recovery characteristics of the parasitic PN junction diode. The freewheeling diode also makes it easier to reduce reverse recovery losses, further mitigating the reverse recovery losses caused by the parasitic PN junction diode. Consequently, the switching losses of the MOS power device are lower than in the case without a freewheeling diode. Furthermore, since the MOS power device is a silicon-based MOS power device... The device incorporates a MOS transistor and a parasitic PN junction body diode, which are integrally formed in an anti-parallel configuration. The current-carrying capacity of the parasitic PN junction body diode is less than or equal to half that of the MOS transistor. Therefore, the parasitic PN junction body diode has a smaller current-carrying capacity and accumulates fewer minority carriers when the freewheeling current flows, resulting in a larger reverse recovery loss (i.e., reverse recovery charge and reverse recovery current) when disconnected. Consequently, the switching loss of the MOS power device is also smaller, improving the reverse recovery characteristics of the MOS power device and thus enhancing the reverse recovery characteristics of the semiconductor device. Attached Figure Description
[0017] To more clearly illustrate the technical inventions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 An equivalent circuit diagram of a semiconductor device provided in an embodiment of this application; Figure 2 Another equivalent circuit diagram of a MOS power device in a semiconductor device provided in an embodiment of this application; Figure 3 A front view of a MOS power device in a semiconductor apparatus provided in an embodiment of this application; Figure 4 A top view of a MOS power device in a semiconductor apparatus provided in an embodiment of this application; Figure 5 A top view of a MOS power device in a semiconductor apparatus provided in an embodiment of this application; Figure 6 Another top view of a MOS power device in a semiconductor device provided in an embodiment of this application; Figure 7 Another top view of a MOS power device in a semiconductor device provided in an embodiment of this application; Figure 8 This is a partial example circuit schematic diagram of an inverter circuit provided in an embodiment of this application. Detailed Implementation
[0019] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.
[0020] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.
[0021] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.
[0023] To reduce the reverse recovery loss of the parasitic PN junction diode built into MOS power devices, related MOS power devices employ carrier lifetime control techniques such as electron beam irradiation or platinum diffusion. However, since the MOS transistor and parasitic PN junction diode are on the same chip, under the premise of the same MOS transistor area, this increases the resistance and forward voltage drop of the MOS transistor, reducing its current carrying capacity. To maintain the same resistance or current carrying capacity of the MOS transistor, the area of the MOS power device needs to be increased. Simultaneously, the area of the built-in parasitic PN junction diode also increases, further increasing its reverse recovery loss. Therefore, the design freedom for reducing the reverse recovery loss of the parasitic PN junction diode is low, and the reverse recovery characteristics of the parasitic PN junction diode built into the MOS power device remain poor. Another related approach is to integrate a Schottky diode to reduce reverse recovery loss. However, MOS power devices with integrated Schottky diodes have low breakdown voltage and high leakage current; moreover, they require additional photolithography and metallization processes, increasing cost and complicating the manufacturing process.
[0024] This invention provides a semiconductor device including a silicon-based MOS power device, which can reduce reverse recovery loss and conduction switching loss in a low cost and effectively without sacrificing the current carrying capacity, forward voltage drop characteristics, withstand voltage characteristics and leakage current characteristics of the MOS transistor.
[0025] Figure 1 This invention provides an equivalent circuit diagram of a semiconductor device according to an embodiment of the present application. Figure 2 A schematic diagram of the equivalent circuit of a MOS power device in a semiconductor device is shown. Figure 3 A front view of a MOS power device is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below: The semiconductor device includes a MOS power device M1 and a freewheeling diode D2 connected in anti-parallel to the MOS power device M1. The MOS power device M1 is a silicon-based MOS power device and has a MOS transistor Q1 and a parasitic PN junction diode D1. The MOS transistor Q1 and the parasitic PN junction diode D1 are integrally formed in an anti-parallel manner. The MOS power device M1 includes a substrate 80, a drift layer 81, a well layer 82, a contact region 84, a source region 83, a gate trench 51, a gate insulating layer 52, a gate electrode 53, an interlayer insulating film 86, a contact hole 70, a source electrode 91, and a drain electrode 92.
[0026] A drain layer 80 is provided between the upper surface of the substrate 80 and the lower surface of the substrate 80 opposite to the upper surface of the substrate 80; wherein the direction between the upper surface of the substrate 80 and the lower surface of the substrate 80 opposite to the upper surface of the substrate 80 is defined as the thickness direction.
[0027] A drift layer 81 is located on the upper surface of the drain layer 80. Specifically, the drift layer 81 is formed on the surface of the drain layer 80 by epitaxial growth, and the impurity solubility of the drift layer 81 is lower than that of the drain layer 80.
[0028] The well layer 82 is selectively located on the upper surface side of the drift layer 81; that is, the well layer 82 is selectively disposed near the upper surface of the drift layer 81. The well layer 82 can be formed on the surface of the drift layer 81 by ion implantation. It can be disposed in the drift layer 81 and at least partially exposed on the surface of the drift layer 81. That is, the surface of the well layer 82 is flush with the surface of the drift layer 81, and the well layer 82 is selectively formed on the surface of the drift layer 81.
[0029] Contact area 84 is selectively disposed on the upper surface side of trap layer 82.
[0030] The source region 83 is selectively disposed on the upper surface side of the well layer 82 and in contact with the contact region 84. Specifically, the source region 83 is formed on the surface of the well layer 82 by ion implantation. It can be disposed inside the well layer 82 and at least partially exposed on the surface of the well layer 82. That is, the surface of the source region 83 is flush with the surface of the well layer 82, and the source region 83 is selectively formed on the surface of the well layer 82.
[0031] Gate trench 51 extends through source region 83 and well layer 82 to drift layer 81.
[0032] A gate insulating layer 52 covers the inner surface of the gate trench 51; by way of example and not limitation, the gate insulating layer 52 is made of silicon dioxide (SiO2) and its thickness can be in the range of 10 nm to 200 nm, for example, about 100 nm.
[0033] The gate electrode 53 is disposed inside the gate trench 51 and faces the source region 83, the well layer 82, and the drift layer 81 through the gate insulating layer 52. It should be noted that the gate electrode 53 can be made of polysilicon. Specifically, the gate electrode 53 is disposed inside the gate trench 51 through the gate insulating layer 52, and the gate electrode 53 faces the source region 83, the well layer 82, and the drift layer 81 through the gate insulating layer 52.
[0034] Interlayer insulating film 86 covers gate electrode 53, and a portion of source region 83 and a portion of well layer 82 are exposed in interlayer insulating film 86 to form contact hole 70; Specifically, contact holes 70 are selectively disposed between interlayer insulating films 86. Contact holes 70 penetrate interlayer insulating films 86 to expose part of the surface of source region 83 and part of the surface of well layer 82. That is, in the exposed well layer 82 region, a second semiconductor type contact region 84 with a higher impurity solubility than well layer 82 can be formed by ion implantation. In other words, contact holes 70 penetrate interlayer insulating films 86 to expose part of the surface of source region 83 and the surface of contact region 84. Contact region 84 can reduce the contact resistance with source electrode 91.
[0035] The source electrode 91 is covered by an interlayer insulating film 86 and is in contact with the upper surface of the source region 83 and part of the upper surface of the well layer 82 via a contact hole 70. Specifically, the source electrode 91 is electrically insulated from the gate electrode 53 through the interlayer insulating film 86, and the source electrode 91 is electrically connected to the source region 83 and the well layer 82 via the contact hole 70.
[0036] Drain electrode 92 is located on the lower surface side of drain layer 80; specifically, drain electrode 92 can be formed by stacking multiple known metal films and disposed on the back side of drain layer 80.
[0037] Wherein, the drain layer 80, drift layer 81, and source region 83 are of the first semiconductor type, and the well layer 82 and contact region 84 are of the second semiconductor type. By way of example and not limitation, the first semiconductor type is N-type, and the second semiconductor type is P-type. By way of example and not limitation, the first semiconductor type is P-type, and the second semiconductor type is N-type.
[0038] Specifically, by configuring the overlapping area of the source electrode 91 and the contact area 84, the current-carrying capacity of the parasitic PN junction body diode D1 is less than or equal to half of the current-carrying capacity of the MOS transistor Q1, and the current-carrying capacity of the freewheeling diode D2 is greater than or equal to the current-carrying capacity of the parasitic PN junction body diode D1; the total current-carrying capacity of the freewheeling diode D2 and the parasitic PN junction body diode D1 is less than or equal to the current-carrying capacity of the MOS power device M1.
[0039] It should be noted that current carrying capacity refers to the maximum current that a device can pass.
[0040] It should be noted that when a gate driving voltage is applied to the gate electrode 53, a channel is formed in the well layer 82 that is in contact with the gate electrode 53 through the gate insulating layer 52.
[0041] exist Figure 3During the operation of the MOS power device M1 shown, when a positive voltage is applied to the gate electrode 53 relative to the source electrode 91, a channel is formed in the well layer 82, which is in contact with the gate electrode 53 through the gate insulating layer 52. Electrons then flow from the source region 83 through the channel formation region and inject into the drift layer 81, putting the MOS power device M1 into a conducting state. When the gate electrode 53 is biased, and the bias voltage is equal to or negative relative to the source electrode 91, the MOS power device M1 is in a blocking state. It is understood that the substrate 80 serves as the drain.
[0042] Since the MOS power device M1 has a MOS transistor Q1 and a parasitic PN junction body diode D1, which are integrally formed in anti-parallel configuration based on silicon, the current-carrying capacity of the parasitic PN junction body diode D1 is less than or equal to half that of the MOS transistor Q1. Therefore, the parasitic PN junction body diode D1 has a smaller current-carrying capacity and accumulates fewer minority carriers when freewheeling current flows, resulting in a larger reverse recovery loss (i.e., reverse recovery charge and reverse recovery current) when disconnected. Consequently, the switching loss of the MOS power device M1 is also smaller, improving the reverse recovery characteristics of the MOS power device M1. At the same time, when the MOS power device M1 is connected in anti-parallel to an external freewheeling diode D2, since the parasitic PN junction body diode D1 only bears a small portion of the freewheeling current and the freewheeling diode D2 bears the majority of the freewheeling current, the area of the parasitic PN junction body diode D1 built into the MOS power device M1 can be reduced, further improving the reverse recovery characteristics of the MOS power device M1.
[0043] It is understandable that in inverter applications, the sum of the current-carrying capacity of the freewheeling diode D2 and the parasitic PN junction body diode D1 is equal to the current-carrying capacity of the MOS power device M1; in the power switching transistor application of the PFC circuit, the total current-carrying capacity of the freewheeling diode D2 and the parasitic PN junction body diode D1 is less than the current-carrying capacity of the MOS power device M1.
[0044] This application adds a freewheeling diode D2. During reverse freewheeling, the freewheeling current of the MOS power device M1 is shunted to both the parasitic PN junction diode D1 and the freewheeling diode D2. Since the freewheeling diode D2 offers greater process freedom than the MOS power device M1, it is easier to reduce reverse recovery losses. Specifically, under the same specifications, the freewheeling diode D2 more easily achieves lower reverse recovery losses (i.e., lower reverse recovery charge and current) than the parasitic PN junction diode D1 in the MOS power device M1. Therefore, the switching loss of the MOS power device M1 is correspondingly lower than when the freewheeling diode D2 is not configured. Furthermore, this invention reduces the reverse recovery loss of the MOS power device M1 by using the low-reverse-recovery-loss freewheeling diode D2. Therefore, compared to the MOS power device M1 employing carrier lifetime control technology, this invention does not sacrifice the current-carrying capacity and forward voltage drop characteristics of the MOS transistor Q1. Compared to the MOS power device M1 with an integrated Schottky diode, it has a higher breakdown voltage and lower leakage current.
[0045] When the current-carrying capacity of the freewheeling diode D2 is greater than that of the parasitic PN junction body diode D1, since the freewheeling diode D2 bears most of the freewheeling current, the area of the built-in parasitic PN junction body diode D1 in the MOS power device M1 can be reduced. This further reduces the impact of the parasitic PN junction body diode D1, which has poor reverse recovery characteristics. The freewheeling diode D2 makes it easier to reduce reverse recovery losses, which is more conducive to reducing the reverse recovery losses caused by the parasitic PN junction diode D1. As a result, the switching loss of the MOS power device M1 is smaller than that without the freewheeling diode D2.
[0046] It should be noted that when the semiconductor device is flowing with freewheeling current, the freewheeling current flows from the anode to the cathode of the freewheeling diode D2, and / or the freewheeling current flows from the well layer 82 of the parasitic PN junction body diode D1 to the drift layer 81. When the semiconductor device is flowing with freewheeling current, the gate electrode 53 is supplied with a disconnect signal.
[0047] When the semiconductor device is in reverse freewheeling mode, the gate electrode 53 is supplied with a disconnect signal, meaning the channel formation region of the MOS transistor Q1 is disconnected. The freewheeling current does not flow through the channel formation region of the MOS transistor Q1; instead, most of the freewheeling current flows to the external freewheeling diode D2, and a small portion flows to the built-in parasitic PN junction diode D1. This reduces the reverse recovery loss of the semiconductor device and lowers the switching loss of the MOS power device M1. Furthermore, since the gate electrode 53 is supplied with a disconnect signal during reverse freewheeling, meaning the channel formation region of the MOS transistor Q1 is disconnected, the system control complexity is reduced, and the shoot-through defect of the upper bridge arm 10 and lower bridge arm 20 of the inverter circuit is avoided.
[0048] In a specific implementation, the freewheeling diode D2 can be a Schottky diode, or a silicon-based substrate 80 or a silicon carbide-based substrate 80.
[0049] When the freewheeling diode D2 is a Schottky diode, the main charge carriers when the freewheeling current flows are electrons, which is more conducive to reducing reverse recovery losses compared to pn junction diodes.
[0050] When the freewheeling diode D2 is on a silicon substrate 80, since the freewheeling diode D2 is made of silicon, it is not necessary to use expensive base materials such as wide-bandgap semiconductor materials such as silicon carbide, so that the reverse recovery loss can be effectively reduced at low cost.
[0051] When the freewheeling diode D2 is on a silicon carbide substrate 80, it is more advantageous to reduce reverse recovery loss compared to a silicon substrate 80.
[0052] It is worth emphasizing that even when using a silicon-based freewheeling diode D2, effective reduction of reverse recovery loss can be achieved without using expensive base materials such as wide-bandgap semiconductors like silicon carbide. The silicon-based freewheeling diode D2 (PN junction diode) relies on doping of the P and N regions to form a junction, and its breakdown voltage can be improved by adjusting the doping concentration and base width. Schottky diodes, on the other hand, are "majority carrier" devices (conducting only by electrons) and lack the "minority carrier storage" effect. This characteristic allows for extremely fast switching but also limits its ability to maintain high blocking capability under high reverse voltage, reducing its reverse breakdown voltage. While silicon carbide (SiC) Schottky diodes have high breakdown voltage, they are expensive. Therefore, using a silicon-based PN junction diode as the freewheeling diode D2 can significantly reduce cost while achieving high breakdown voltage.
[0053] In specific implementation, such as Figure 1 The MOS power device M1 and freewheeling diode D2 shown are capable of carrying both on-current and freewheeling current. The on-current flows in a first direction from the first main electrode (e.g., drain) of the MOS transistor Q1 toward the second main electrode (e.g., source) opposite to the first main electrode (e.g., drain). The freewheeling current flows through the freewheeling diode D2 and / or the parasitic PN junction body diode D1 in a second direction opposite to the first direction. When the semiconductor device carries the freewheeling current, the gate of the MOS transistor Q1 is supplied with an off signal.
[0054] During reverse freewheeling, the freewheeling current is only shunted to the freewheeling diode D2 and / or the parasitic PN junction body diode D1. The gate of the MOS transistor Q1 is connected to the disconnect signal, that is, the gate channel of the MOS transistor Q1 is disconnected. The freewheeling current does not flow through the gate channel of the MOS transistor Q1, thereby reducing the system control complexity. When applied to inverter circuits, it reduces the possibility of the upper bridge arm 10 and the lower bridge arm 20 of the inverter circuit being shot-through.
[0055] It is worth emphasizing that, when applied to power conversion devices, silicon-based MOS power devices have the advantages of lower cost and lower turn-off loss compared to RC-IGBT devices. However, the built-in parasitic PN junction diode of silicon-based MOS power devices has a large reverse recovery loss. The embodiments of the present invention can balance the low reverse recovery loss of power conversion devices, the large current carrying capacity of transistors, and the better forward voltage drop characteristics.
[0056] In one embodiment, the current-carrying capacity of the freewheeling diode D2 is less than or equal to 6 times the current-carrying capacity of the parasitic PN junction body diode D1.
[0057] The above technical solution improves the current carrying capacity of the freewheeling diode D2 while maintaining a relatively high shunting ratio growth rate. When the current carrying capacity of the freewheeling diode D2 is greater than 6 times that of the parasitic PN junction diode D1, the growth rate of the shunting ratio slows down significantly when the current carrying capacity of the freewheeling diode D2 is improved. Furthermore, the manufacturing cost increases significantly due to the excessively large area of the freewheeling diode D2.
[0058] In one embodiment, the current-carrying capacity of the freewheeling diode D2 is greater than or equal to half the current-carrying capacity of the MOS transistor Q1. That is, the current-carrying capacity of the freewheeling diode D2 is greater than or equal to the current-carrying capacity of the parasitic PN junction body diode D1.
[0059] Since the freewheeling diode D2 handles most of the freewheeling current, the area of the built-in parasitic PN junction body diode D1 in the MOS power device M1 can be reduced, further reducing the impact of the poor reverse recovery characteristics of the parasitic PN junction body diode D1. The freewheeling diode D2 makes it easier to reduce reverse recovery losses, which is more conducive to reducing the reverse recovery losses caused by the parasitic PN junction diode D1. As a result, the switching loss of the MOS power device M1 is smaller than that without the freewheeling diode D2.
[0060] In one embodiment, such as Figure 4 As shown, the MOS power device M1 satisfies the following three relationships: Z≤1.2Y, Z>0, Y+Z=J; Where Y is the length of overlap between the source region 83 and the contact hole 70 in the lateral direction, Z is the length of overlap between the contact region 84 and the contact hole 70 in the lateral direction, and J is the length of a single contact hole 70 in the lateral direction; the lateral direction is the direction in which the two source regions 83 sandwich the contact region 84.
[0061] It should be noted that, Figure 4 for Figure 3 The diagram shows a top view of the MOS power device in the semiconductor device in section AB.
[0062] Since the freewheeling circuit passes through the source electrode 91, contact region 84, well layer 82, drift layer 81, drain layer and drain electrode 92 in sequence, when the MOS transistor Q1 is forward biased, the conduction current passes through the drain electrode 92, drain (substrate 80), drift layer 81, channel formation region, source region 83 and source electrode 91 in sequence. When the freewheeling current carrying capacity of the built-in parasitic PN junction body diode D1 (a PN junction diode composed of well layer 82 and drift layer 81) is less than or equal to half of the conduction current carrying capacity of the MOS transistor Q1 when forward biased, that is, the freewheeling current of the parasitic PN junction body diode D1 is reduced, which is more conducive to reducing the reverse recovery loss of the parasitic PN junction body diode D1. The external freewheeling diode D2 takes on most of the freewheeling current, further reducing the influence of the parasitic PN junction body diode D1 with poor reverse recovery characteristics. The freewheeling diode D2 makes it easier to reduce the reverse recovery loss, thereby reducing the switching loss of the MOS power device M1.
[0063] In this application, with the freewheeling diode D2 in use, during reverse freewheeling, the gate electrode 53 supplies a disconnect signal, meaning the channel formation region of the MOS transistor Q1 is disconnected. The freewheeling current does not flow through the channel formation region of the MOS transistor Q1; instead, most of the freewheeling current flows to the external freewheeling diode D2, and a small portion flows to the built-in parasitic PN junction diode D1. This reduces reverse recovery losses and lowers the switching losses of the MOS power device M1. Furthermore, since the gate electrode 53 is supplied with a disconnect signal during reverse freewheeling, meaning the channel formation region of the MOS transistor Q1 is disconnected, system control complexity is reduced. When applied to inverter circuits, this avoids the shoot-through defect between the upper bridge arm 10 and the lower bridge arm 20 of the inverter circuit.
[0064] In practice, Y can be greater than or equal to 1 micrometer and less than or equal to 5 micrometers.
[0065] It is important to emphasize that the reverse breakdown voltage of this MOS power device M1 can reach greater than or equal to 300V. The PN junction parasitic PN junction body diode D1 is formed by the direct bonding of P-type and N-type semiconductors, resulting in a wider depletion layer (space charge region) and high reverse breakdown voltage. The Schottky parasitic PN junction body diode D1, on the other hand, forms a Schottky barrier through the contact between a metal and a semiconductor (such as N-type silicon), resulting in an extremely thin depletion layer and low reverse breakdown voltage. Compared to the Schottky parasitic PN junction body diode D1, the parasitic PN junction body diode D1 can be used in applications requiring high reverse breakdown voltage.
[0066] Since the parasitic PN junction body diode D1 is composed of a PN junction diode consisting of a well layer 82 and a drift layer 81, the MOS power device M1 provided in this embodiment controls Z≤1.2Y, Z>0, Y+Z=J, that is, within the source region 83 and contact region 84 covered by the contact hole 70, by increasing the lateral length of the source region 83 and decreasing the lateral length of the contact region 84, thus narrowing the current path of the well layer 82. This increases the resistance of the parasitic PN junction body diode D1 built into the MOS power device M1 when forward biased, thereby significantly reducing the reverse freewheeling capability of the parasitic PN junction body diode D1 and reducing its reverse recovery loss. On the other hand, increasing Y provides more current paths for the MOS transistor Q1 when it is turned on, which helps to reduce the resistance of the MOS transistor Q1 when forward biased, thereby increasing the current carrying capacity and reducing the forward voltage drop characteristics of the MOS transistor Q1. That is, while optimizing the current-carrying capacity and forward voltage drop characteristics of MOS transistor Q1, the reverse recovery loss and the switching loss of MOS power device M1 are effectively reduced. Compared with MOS power device M1 with integrated Schottky diode, the PN junction diode composed of well layer 82 and drift layer 81 of this invention has higher reverse breakdown voltage and lower reverse leakage current.
[0067] In one embodiment, the MOS power device M1 also satisfies the following relationship: Z ≥ 0.1Y.
[0068] Understandably, the parasitic NPN transistor formed by the source region 83, the well layer 82, and the drift layer 81 reduces the controllability of the MOS power device M1. By controlling Z to be greater than or equal to 0.1Y and by increasing the width of the contact region 84, the possibility of forming a parasitic bipolar transistor is reduced, thereby improving the stability of the performance of the MOS power device M1.
[0069] In one embodiment, the MOS power device M1 satisfies the following relationship: C / (L1) L2) < 1 / 2; Wherein, L1 is the length of the contact hole 70 in the lateral direction, L2 is the length of the source region 83 in the longitudinal direction, the lateral direction is the direction in which the two source regions 83 sandwich the contact region 84, the thickness direction is perpendicular to the upper surface of the substrate 80, and the lateral direction, the longitudinal direction and the thickness direction are perpendicular to each other, and C is the total area of the plurality of contact holes 70.
[0070] It should be noted that, in Figures 5 to 7 In the image, the area outlined by the red dashed line is contact hole 70. For example... Figure 5 As shown, the contact holes 70 can be arranged at intervals along the longitudinal direction; as Figure 6 As shown, the contact holes 70 can be arranged at intervals in the lateral direction; as Figure 7As shown, the contact holes 70 can be arranged at intervals along the lateral and / or longitudinal directions. The specific arrangement can be adapted to meet specific needs and will not be listed here. This technical solution improves the flexibility of the structural implementation of the MOS power device M1.
[0071] It should be noted that, Figures 5 to 7 for Figure 3 The diagram shows a top view of the MOS power device in the semiconductor device in section AB.
[0072] By controlling C / (L1) When the area of contact hole 70 is reduced to less than half of its original size (L2), the reduction in the current path area of the well layer 82 significantly increases the resistance under forward bias for the parasitic PN junction body diode D1 built into the MOSFET (which is a PN junction diode composed of a well layer 82 and a drift layer 81). This leads to a substantial decrease in the reverse freewheeling capability of the parasitic PN junction body diode D1, thereby reducing its reverse recovery loss. On the other hand, the on-current of MOS transistor Q1 is mainly affected by the channel resistance and the resistance of the drift layer 81, while the resistance of contact hole 70 has a relatively small impact. Therefore, the reduction in the area of contact hole 70 has almost no effect on the on-current and forward voltage drop of MOS transistor Q1. Thus, without sacrificing the current carrying capacity and forward voltage drop characteristics of MOS transistor Q1, MOS power device M1 effectively reduces the reverse recovery loss of the semiconductor device and the switching loss of the MOSFET.
[0073] The MOS power device M1 can be connected in reverse parallel with a freewheeling diode D2. The freewheeling diode D2 has an anode and a cathode. The anode is electrically connected to the source electrode 91, and the cathode is electrically connected to the drain electrode 92.
[0074] In one embodiment, the MOS power device M1 also satisfies the following relationship: C / (L1) L2) > 1 / 10.
[0075] That is, the total length dimension of multiple contact holes 70 in the unit cell is L3. When the width of multiple contact holes 70 is the same, L3 and L2 satisfy the relationship: 1 / 10 < L3 / L2 < 1 / 2.
[0076] Understandably, the parasitic NPN transistor formed by the source region 83, well layer 82, and drift layer 81 reduces the controllability of the MOS power device M1. This is achieved by controlling C / (L1). L2) is greater than 1 / 10, which avoids the contact hole 70 being too small, reduces the possibility of parasitic bipolar transistor conduction, and improves the stability of the MOS power device M1 performance.
[0077] Figure 4The MOS power device M1 shown may include at least one first cell. Figure 5 The MOS power device M1 shown may include at least one second cell. In one embodiment, at least the first cell and / or at least one second cell may be arranged in the lateral and / or longitudinal directions.
[0078] For example, two first cells are arranged in the horizontal direction, two second cells are arranged in the horizontal direction, and two first cells and two second cells are arranged in the vertical direction.
[0079] It is worth emphasizing that the first and second cells can be arranged alternately or continuously. The specific arrangement can be adapted to meet the needs, and will not be listed here.
[0080] The above technical solutions improve the flexibility of the structural implementation of the MOS power device M1.
[0081] This invention also provides an inverter circuit, including an upper bridge arm and a lower bridge arm connected in series, both of which include the aforementioned semiconductor device.
[0082] like Figure 8 As shown, the semiconductor device in the upper bridge arm 10 includes a first MOS power device M1 and a first freewheeling diode D2 connected in anti-parallel. The first MOS power device M1 has a first MOS transistor Q1 and a first parasitic PN junction body diode D1. The first MOS transistor Q1 and the first parasitic PN junction body diode D1 are integrally formed in anti-parallel on a silicon base.
[0083] The semiconductor device in the lower bridge arm 20 includes a second MOS power device M1 and a second freewheeling diode D2 connected in anti-parallel. The second MOS power device M1 has a second MOS transistor Q1 and a second parasitic PN junction body diode D1. The second MOS transistor Q1 and the second parasitic PN junction body diode D1 are integrally formed in anti-parallel on a silicon base.
[0084] The current-carrying capacity of the first freewheeling diode D2 is greater than or equal to the current-carrying capacity of the first parasitic PN junction diode D1. The current-carrying capacity of the second freewheeling diode D2 is greater than or equal to the current-carrying capacity of the second parasitic PN junction diode D1. The first MOS power device M1 and the second MOS power device M1 are connected in series between the first potential and the second potential; the second potential is lower than the first potential.
[0085] When reverse freewheeling current flows through the upper bridge arm 10 or the lower bridge arm 20 of the inverter circuit, the current can be shunted through the external freewheeling diode D2 of the corresponding bridge arm. This achieves low-cost and effective reduction of reverse recovery loss of semiconductor device and reduction of conduction switching loss of MOS power device M1 without sacrificing the current carrying capacity, conduction voltage characteristics and forward voltage drop characteristics of MOS transistor Q1.
[0086] The first MOS power device M1 is capable of carrying both a conduction current and a freewheeling current. The conduction current flows in a first direction from the first main electrode (e.g., drain) of the first MOS transistor Q1 toward the second main electrode (e.g., source) opposite to the first main electrode (e.g., drain). The freewheeling current flows in a second direction opposite to the first direction through the first freewheeling diode D2 and / or the first parasitic PN junction body diode D1. When the first MOS power device M1 carries the freewheeling current, the gate of the first MOS transistor Q1 is supplied with an off signal.
[0087] The second MOSFET is capable of carrying both on-current and freewheeling current. The on-current flows in a first direction from the first main electrode (e.g., drain) of the second MOSFET Q1 toward the second main electrode (e.g., source) opposite to the first main electrode (e.g., drain). The freewheeling current flows in a second direction opposite to the first direction through the second freewheeling diode D2 and / or the second parasitic PN junction body diode D1. When the second MOSFET carries the freewheeling current, the gate of the second MOSFET Q1 is supplied with an off signal.
[0088] When reverse freewheeling current flows through the upper arm 10 or lower arm 20 of the inverter circuit, the freewheeling current is only shunted to the freewheeling diode D2 and / or parasitic PN junction body diode D1 of the corresponding arm. The gate of the MOS transistor Q1 of the corresponding arm is supplied with an off signal, that is, the gate channel of the MOS transistor Q1 of the corresponding arm is open, and the freewheeling current does not flow through the gate channel of the MOS transistor Q1 of the corresponding arm. This reduces the system control complexity and avoids the shoot-through defect of the upper arm 10 and lower arm 20 of the inverter circuit.
[0089] When the first freewheeling diode D2 and / or the first parasitic PN junction diode D1 of the upper bridge arm 10 are conducting freewheeling current, the gates of the first MOS transistor Q1 and the second MOS transistor Q1 are both supplied with an off signal; in the next stage, the second MOS transistor Q1 of the lower bridge arm 20 is conducting current again, the first MOS transistor Q1 is supplied with an off signal, and the gate of the second MOS transistor Q1 is supplied with an on signal. When the second freewheeling diode D2 and / or the second parasitic PN junction diode D1 of the lower bridge arm 20 are conducting freewheeling current, the gates of the first MOS transistor Q1 and the second MOS transistor Q1 are both supplied with an off signal; in the next stage, the first MOS transistor Q1 of the upper bridge arm 10 is conducting current again, the first MOS transistor Q1 is supplied with an on signal, and the gate of the second MOS transistor Q1 is supplied with an off signal.
[0090] After one of the upper bridge arm 10 and the lower bridge arm 20 of the inverter circuit is supplied with reverse freewheeling current, the other MOS transistor Q1 of the upper bridge arm 10 and the lower bridge arm 20 is supplied with an on signal and conduction current flows again. Since one of the MOS transistors Q1 of the upper bridge arm 10 and the lower bridge arm 20 is supplied with an off signal when reverse freewheeling current and MOS transistor Q1 is turned on, the defect of shoot-through between the upper bridge arm 10 and the lower bridge arm 20 when the other MOS transistor Q1 is turned on can be avoided.
[0091] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0092] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A semiconductor device, characterized in that, The semiconductor device includes a MOS power device and a freewheeling diode connected in anti-parallel to the MOS power device. The MOS power device is a silicon-based MOS power device and has a MOS transistor and a parasitic PN junction diode. The MOS transistor and the parasitic PN junction diode are integrally formed in anti-parallel configuration. The MOS power device includes: A substrate having a drain layer between an upper surface of the substrate and a lower surface of the substrate opposite to the upper surface of the substrate; A drift layer, which is located on the upper surface side of the drain layer; A trap layer, which is selectively located on the upper surface side of the drift layer; The contact area is selectively disposed on the upper surface side of the trap layer; The source region is selectively disposed on the upper surface side of the well layer and in contact with the contact region; A gate trench that extends through the source region and the well layer into the drift layer; A gate insulating layer that covers the inner surface of the gate trench; A gate electrode is disposed inside the gate trench and faces the source region, the well layer and the drift layer through the gate insulating layer; An interlayer insulating film covers the gate electrode, exposing a portion of the source region and a portion of the well layer in the interlayer insulating film to form a contact hole; a source electrode covers the interlayer insulating film and contacts the upper surface of the source region and a portion of the upper surface of the well layer via the contact hole; Drain electrode, which is located on the lower surface side of the drain layer; The drain layer, the drift layer, and the source region are of a first semiconductor type, and the well layer and the contact region are of a second semiconductor type. Specifically, by configuring the overlap area of the source electrode and the contact area, the current-carrying capacity of the parasitic PN junction body diode is less than or equal to half of the current-carrying capacity of the MOS transistor, and the current-carrying capacity of the freewheeling diode is greater than or equal to the current-carrying capacity of the parasitic PN junction body diode; the total current-carrying capacity of the freewheeling diode and the parasitic PN junction body diode is less than or equal to the current-carrying capacity of the MOS power device.
2. The semiconductor device as claimed in claim 1, characterized in that, The current-carrying capacity of the freewheeling diode is less than or equal to 6 times the current-carrying capacity of the parasitic PN junction diode.
3. The semiconductor device as claimed in claim 1, characterized in that, The current-carrying capacity of the freewheeling diode is greater than or equal to half the current-carrying capacity of the MOS transistor.
4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The MOS power device satisfies the following three relationships: Z≤1.2Y, Z>0, Y+Z=J; Wherein, Y is the length of overlap between the source region and the contact hole in the lateral direction, Z is the length of overlap between the contact region and the contact hole in the lateral direction, and J is the length of a single contact hole in the lateral direction; the lateral direction is the direction in which the two source regions sandwich the contact region.
5. The semiconductor device as claimed in claim 4, characterized in that, The MOS power device also satisfies the following relationship: Z≥0.1Y.
6. The semiconductor device according to any one of claims 1 to 3, characterized in that, The MOS power device satisfies the following relationship: C / (L1 L2) <1 / 2; Wherein, L1 is the length of the contact hole in the lateral direction, L2 is the length of the source region in the longitudinal direction, the lateral direction is the direction in which the two source regions sandwich the contact region, the thickness direction is perpendicular to the upper surface of the substrate, and the lateral direction, the longitudinal direction and the thickness direction are mutually perpendicular, and C is the total area of the multiple contact holes.
7. The semiconductor device as claimed in claim 6, characterized in that, The MOS power device also satisfies the following relationship: C / (L1) L2) > 1 / 10.
8. The semiconductor device as claimed in claim 6, characterized in that, The contact holes can be arranged at intervals along the lateral and / or longitudinal directions.
9. The semiconductor device according to any one of claims 1 to 3, characterized in that, The freewheeling diode is a silicon-based freewheeling diode, and the reverse withstand voltage of the MOS power device is greater than or equal to 300V.
10. An inverter circuit, characterized in that, The inverter circuit includes an upper bridge arm and a lower bridge arm connected in series, and both the upper bridge arm and the lower bridge arm include a semiconductor device as described in any one of claims 1 to 9.