Gate interconnect structure and method of making, semiconductor device and method of making

Abstract

This invention discloses a gate interconnect structure and its fabrication method, as well as a semiconductor device and its fabrication method. The gate interconnect structure includes: a gate; a first insulating layer located on one side of the gate; the first insulating layer including a first groove exposing a portion of the gate; a barrier layer including a first barrier layer and a second barrier layer, the first barrier layer and the second barrier layer having the same lattice constant; the first barrier layer including a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer including a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate; and a gate metal trace located on the side of the barrier layer away from the gate. This invention can solve the problem of aluminum atoms in the gate metal trace fusing with the polycrystalline silicon gate.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a gate interconnect structure and its fabrication method, a semiconductor device and its fabrication method. Background Technology

[0002] As silicon carbide (SiC) chips move toward smaller critical dimensions (CD), the traditional low-temperature aluminum (Al) filling process is no longer sufficient to meet the demand due to insufficient filling capacity. Therefore, the high-temperature aluminum-copper (AlCu) process is being used to improve the filling capacity.

[0003] The gate interconnect structure of a metal-oxide-semiconductor field-effect transistor (MOSFET) semiconductor device uses aluminum-copper as the gate metal trace, which passes through the interlayer dielectric layer and connects to the polysilicon gate. To prevent the aluminum in the aluminum-copper layer from melting with the polysilicon at high temperatures, existing technologies place Ti / TiN double barrier layers between the aluminum-copper and polysilicon gates and on the sidewalls of the interlayer dielectric layer. However, interface defects (such as dislocations) between Ti and TiN can form "diffusion paths," allowing aluminum atoms to diffuse to the underlying polysilicon gate layer at high temperatures, leading to leakage and other problems. Summary of the Invention

[0004] This invention provides a gate interconnect structure and its fabrication method, as well as a semiconductor device and its fabrication method, to solve the problem of aluminum atoms and polysilicon gates fusing together in the gate metal traces at high temperatures.

[0005] In a first aspect, the present invention provides a gate interconnect structure, the gate interconnect structure comprising: Gate; A first insulating layer is located on one side of the gate; the first insulating layer includes a first groove that exposes a portion of the gate. The barrier layer includes a first barrier layer and a second barrier layer. The first barrier layer is located on the side of the first insulating layer away from the gate and is located at the bottom and sidewall of the first groove. The second barrier layer is located on the side of the first barrier layer away from the gate. The first barrier layer and the second barrier layer have the same lattice constant. The first barrier layer includes a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate. The second barrier layer includes a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate. The first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate. The gate metal trace is located on the side of the barrier layer away from the gate.

[0006] Optionally, the first barrier layer includes a first titanium layer, and the second barrier layer includes a second titanium layer; the first titanium layer and the second titanium layer are formed independently at intervals.

[0007] Optionally, the thickness of the first barrier layer is 90nm-100nm, and the thickness of the second barrier layer is 90nm-100nm.

[0008] Optionally, the barrier layer further includes: a third barrier layer; The third barrier layer is located on the side of the second barrier layer away from the gate; the vertical projection of the third barrier layer on the gate covers the vertical projection of the first barrier layer and the second barrier layer on the gate; the third barrier layer is used to isolate the gate metal trace from the second barrier layer and the first barrier layer.

[0009] Optionally, the third barrier layer includes a titanium nitride layer; the thickness of the third barrier layer is 50 nm.

[0010] Optionally, the gate metal trace includes an aluminum-copper alloy trace.

[0011] In a second aspect, the present invention provides a semiconductor device, the semiconductor device comprising: The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body includes a core region and an edge region, with the edge region surrounding the core region. The semiconductor body of the core region also includes at least one well region and a first region. The first region is configured with a first conductivity type and is located on the first surface. The well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. A gate insulating layer is located on the first surface, and the gate insulating layer on the first surface of the semiconductor body in the core region includes a second groove that exposes the first region; The gate is located on the side of the gate insulating layer away from the semiconductor body; A first insulating layer is located on the side of the gate away from the semiconductor body; the first insulating layer corresponding to the semiconductor body in the edge region includes a first groove, the first groove exposing a portion of the gate; A barrier layer is located on the side of the first insulating layer away from the semiconductor body corresponding to the semiconductor body in the edge region, and on the bottom and sidewalls of the first groove. The barrier layer includes a first barrier layer and a second barrier layer. The first barrier layer is located on the side of the first insulating layer away from the gate, and is located on the bottom and sidewalls of the first groove. The second barrier layer is located on the side of the first barrier layer away from the gate. The first barrier layer and the second barrier layer have the same lattice constant. The first barrier layer includes a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate. The second barrier layer includes a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate. The first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate. The gate metal trace is located on the side of the barrier layer away from the semiconductor body; The source electrode is located on the first surface of the semiconductor body in the core region and on the side of the first insulating layer corresponding to the semiconductor body in the core region that is away from the semiconductor body; the source electrode is in contact with the first region; the gate metal trace surrounds the source electrode and the source electrode is insulated from the gate metal trace. The drain electrode is located on the second surface.

[0012] Thirdly, the present invention provides a method for fabricating a gate interconnect structure, the method comprising: Provide gate; A first insulating layer is formed on one side of the gate; the first insulating layer includes a first groove that exposes a portion of the gate; A barrier layer is formed on the side of the first insulating layer away from the gate, and at the bottom and sidewall of the first groove. The barrier layer includes a first barrier layer and a second barrier layer. The first barrier layer is located on the side of the first insulating layer away from the gate, and at the bottom and sidewall of the first groove. The second barrier layer is located on the side of the first barrier layer away from the gate. The first barrier layer and the second barrier layer have the same lattice constant. The first barrier layer includes a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate. The second barrier layer includes a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate. The first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate. A gate metal trace is formed on the side of the barrier layer away from the gate.

[0013] Optionally, a barrier layer is formed on the side of the first insulating layer away from the gate, and at the bottom and sidewalls of the first recess, comprising: A first titanium layer is formed on the side of the first insulating layer away from the gate using a physical vapor deposition process, and at the bottom and sidewalls of the first groove. After a first time interval in a vacuum environment, a second titanium layer is formed on the side of the first titanium layer away from the gate using a physical vapor deposition process.

[0014] Optionally, a barrier layer is formed on the side of the first insulating layer away from the gate, and at the bottom and sidewalls of the first recess, further comprising: A third barrier layer is formed on the side of the second barrier layer away from the gate; the vertical projection of the third barrier layer on the gate covers the vertical projection of the first barrier layer and the second barrier layer on the gate; the third barrier layer is used to isolate the gate metal trace from the second barrier layer and the first barrier layer.

[0015] Optionally, a third barrier layer is formed on the side of the second barrier layer away from the gate, comprising: In an atmosphere of mixed argon and nitrogen gas, a titanium nitride layer is formed on the side of the second barrier layer away from the gate using a magnetron sputtering process.

[0016] Fourthly, the present invention provides a method for fabricating a semiconductor device, the method comprising: A semiconductor body of a first conductivity type is provided; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body includes a core region and an edge region, the edge region surrounding the core region; the semiconductor body of the core region also includes at least one well region and a first region, the first region being configured with a first conductivity type and located on the first surface, the well region being configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type being different; A gate insulating layer is formed on the first surface, and the gate insulating layer on the first surface of the semiconductor body of the core region includes a second groove that exposes the first region; A gate is formed on the side of the gate insulating layer away from the semiconductor body; A first insulating layer is formed on the side of the gate away from the semiconductor body; the first insulating layer corresponding to the semiconductor body in the edge region includes a first groove, the first groove exposing a portion of the gate; A barrier layer is formed on the side of the first insulating layer corresponding to the semiconductor body in the edge region away from the semiconductor body, and on the bottom and sidewall of the first groove; the barrier layer includes a first barrier layer and a second barrier layer, the first barrier layer is located on the side of the first insulating layer away from the gate, and is located on the bottom and sidewall of the first groove, and the second barrier layer is located on the side of the first barrier layer away from the gate; the first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer includes a first grain boundary line, which extends from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer includes a second grain boundary line, which extends from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate; A gate metal trace is formed on the side of the barrier layer away from the semiconductor body; A source electrode is formed on the first surface of the semiconductor body in the core region, and on the side of the first insulating layer corresponding to the semiconductor body in the core region away from the semiconductor body; the source electrode is in contact with the first region; the gate metal trace surrounds the source electrode, and the source electrode and the gate metal trace are insulated and isolated from each other; A drain electrode is formed on the second surface.

[0017] The technical solution of this invention involves a first barrier layer disposed on the side of the first insulating layer away from the gate, and at the bottom and sidewall of the first groove. A second barrier layer is disposed on the side of the first barrier layer away from the gate. The lattice constants of the first and second barrier layers can be the same, but lattice dislocations exist between them; that is, dislocations exist between the first grain boundary line perpendicularly penetrating the first barrier layer and the second grain boundary line perpendicularly penetrating the second barrier layer. The first barrier layer may include a titanium layer, and the second barrier layer may also include a titanium layer. The barrier layer composed of the first and second barrier layers can effectively block the diffusion of aluminum atoms at high temperatures, thereby effectively solving the problem of aluminum atoms fusing with the polysilicon gate.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is an imaging schematic diagram of a focused ion beam (FIB) experiment using a gate interconnect structure provided by related technologies; Figure 2 and Figure 3 This is a schematic diagram of a scanning electron microscope (SEM) experiment on a gate interconnect structure provided by related technologies; Figure 4 This is a schematic diagram of a gate interconnect structure provided in an embodiment of the present invention; Figure 5 This is an imaging schematic diagram of a focused ion beam (FIB) experiment on a gate interconnect structure provided in an embodiment of the present invention; Figure 6 and Figure 7This is a schematic diagram of a scanning electron microscope (SEM) experiment on a gate interconnect structure provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another gate interconnect structure provided in an embodiment of the present invention; Figure 9 This is an imaging schematic diagram of a focused ion beam (FIB) experiment of another gate interconnect structure provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 11 This is a flowchart of a method for fabricating a gate interconnect structure provided in an embodiment of the present invention; Figure 12 This is a flowchart of another method for fabricating a gate interconnect structure provided in an embodiment of the present invention; Figure 13 This is a flowchart of another method for fabricating a gate interconnect structure provided in an embodiment of the present invention; Figure 14 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Figure 1 This is an imaging schematic diagram of a focused ion beam (FIB) experiment using a gate interconnect structure provided by related technologies. Figure 2 and Figure 3This is a schematic diagram of a scanning electron microscope (SEM) experiment on a gate interconnect structure provided by related technologies, such as... Figures 1-3 As shown, the gate interconnect structure may include AlCu gate metal traces, a Ti+TiN barrier layer, an interlayer dielectric (ILD) layer, and a polysilicon gate, formed by... Figures 1-3 As can be seen, there is a problem of Al diffusion from the AlCu gate metal trace within the red coil into the polysilicon (Poly) gate, resulting in Al and Poly intermingling. To solve the above technical problem, the technical solution of this invention is as follows: Figure 4 This is a schematic diagram of a gate interconnect structure provided in an embodiment of the present invention, as shown below. Figure 4 As shown, the gate interconnect structure includes: a gate 22; a first insulating layer 3 located on one side of the gate 22; the first insulating layer 3 including a first recess 31 exposing a portion of the gate 22; and a barrier layer 4 including a first barrier layer 41 and a second barrier layer 42. The first barrier layer 41 is located on the side of the first insulating layer 3 away from the gate 22 and is located at the bottom and sidewall of the first recess 31. The second barrier layer 42 is located on the side of the first barrier layer 41 away from the gate 22. The first barrier layer 41 and the second barrier layer 42 have the same lattice constant. The first barrier layer 41 includes a first grain boundary line extending from the side of the first barrier layer 41 away from the gate 22 to the side of the first barrier layer 41 near the gate 22. The second barrier layer 42 includes a second grain boundary line extending from the side of the second barrier layer 42 away from the gate 22 to the side of the second barrier layer 42 near the gate 22. The first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate 22. Gate metal trace 51 is located on the side of barrier layer 4 away from gate 22.

[0024] Specifically, the gate interconnect structure provided in this embodiment of the invention can be applied to any type of transistor semiconductor device. The gate 22 in the gate interconnect structure may include a polysilicon gate, and a first insulating layer 3 may be disposed on one side of the gate 22, serving as an interlayer dielectric layer. A first groove 31 may be formed in the first insulating layer 3, penetrating the first insulating layer 3 to expose a portion of the gate 22. The gate metal trace 51 may include an aluminum-copper (AlCu) gate metal trace, and the gate metal trace 51 needs to be connected to the gate 22.

[0025] The gate interconnect structure provided in this embodiment of the invention may further include a barrier layer 4, which includes a first barrier layer 41 and a second barrier layer 42. The first barrier layer 41 may be disposed on the side of the first insulating layer 3 away from the gate 22, and may also be disposed on the bottom and sidewall of the first recess 31. The second barrier layer 42 is disposed on the side of the first barrier layer 41 away from the gate 22. The barrier layer 4 may completely cover the exposed gate 22. The lattice constants of the first barrier layer 41 and the second barrier layer 42 may be the same, while lattice dislocations exist between them; that is, dislocations exist between the first grain boundary line perpendicularly penetrating the first barrier layer 41 and the second grain boundary line perpendicularly penetrating the second barrier layer 42. For example, both the first barrier layer 41 and the second barrier layer 42 may include a titanium layer.

[0026] In existing technologies, Ti+TiN barrier layers are used in gate interconnect structures. TiN is directly deposited on top of the Ti layer, forming a clear, continuous, and large-area heterogeneous phase interface at the atomic level between the Ti and TiN layers. This interface is a region highly enriched with structural defects (such as dislocations and vacancies), and these defects are interconnected, forming a penetration network that runs through the entire interface, making it easy for aluminum atoms to diffuse into the polysilicon gate. In this embodiment of the invention, a first barrier layer 41 and a second barrier layer 42 with the same lattice constant are used. The first barrier layer 41 may include a titanium layer, and the second barrier layer 42 may also include a titanium layer. There is no strong strain field or ultra-high density defect between the first barrier layer 41 and the second barrier layer 42. The defect density and energy state at the interface between the first barrier layer 41 and the second barrier layer 42 are much lower than those at the heterogeneous phase boundary between the Ti and TiN layers, thus the diffusion pull on aluminum atoms is weaker. Meanwhile, the grain boundary misalignment between the first barrier layer 41 and the second barrier layer 42 causes the atomic transport path between the two barrier layers to become very tortuous and discontinuous, thus forming a diffusion path that hinders the diffusion of aluminum atoms. The gate metal trace 51 is connected to the gate 22 through the barrier layer 4. The metal gate trace 51 may include an aluminum-copper (AlCu) gate metal trace. Under high temperature conditions, aluminum atoms in the metal gate trace 51 cannot diffuse through the barrier layer 4 to the gate 22.

[0027] Figure 5 This is an imaging schematic diagram of a focused ion beam (FIB) experiment on a gate interconnect structure provided in an embodiment of the present invention. Figure 6 and Figure 7 This is a schematic diagram of a scanning electron microscope (SEM) experiment on a gate interconnect structure provided in an embodiment of the present invention, as shown below. Figures 5-7 As shown, due to the setting of the barrier layer 4, aluminum atoms in the metal gate trace 51 will not diffuse through the barrier layer 4 to the gate 22, so there will be no problem of aluminum and polysilicon fusion.

[0028] In this embodiment of the invention, a first barrier layer 41 is disposed on the side of the first insulating layer 3 away from the gate 22, and on the bottom and sidewall of the first groove 31. A second barrier layer 42 is disposed on the side of the first barrier layer 41 away from the gate 22. The lattice constants of the first barrier layer 41 and the second barrier layer 42 can be the same, while lattice dislocations exist between the first barrier layer 41 and the second barrier layer 42. That is, dislocations exist between the first grain boundary line perpendicularly penetrating the first barrier layer 41 and the second grain boundary line perpendicularly penetrating the second barrier layer 42. The first barrier layer 41 may include a titanium layer, and the second barrier layer 42 may also include a titanium layer. The barrier layer 4 formed by the first barrier layer 41 and the second barrier layer 42 can effectively block the diffusion of aluminum atoms at high temperatures, thereby effectively solving the problem of aluminum atoms fusing with the polycrystalline silicon gate.

[0029] Optionally, based on the above embodiments, refer to... Figure 4 The first barrier layer 41 includes a first titanium layer, and the second barrier layer 42 includes a second titanium layer; the first titanium layer and the second titanium layer are formed independently at intervals.

[0030] Specifically, the first barrier layer 41 provided in the embodiments of the present invention may include a first titanium layer, and the second barrier layer 42 may include a second titanium layer. When forming the first titanium layer and the second titanium layer, the first titanium layer may be formed first on the side of the first insulating layer 3 away from the gate 22 and on the bottom and sidewall of the first groove 31. Then, after a certain time interval, the second titanium layer is formed on the side of the first titanium layer away from the gate 22, so that the first titanium layer and the second titanium layer are formed independently and at intervals, and an interface is formed between the two independently deposited titanium layers.

[0031] There is no strong strain field or ultra-high density defect between the first and second titanium layers. The defect density and energy state at the interface between the first and second titanium layers are much lower than those at the heterogeneous phase boundary between the Ti and TiN layers, thus the diffusion attraction for aluminum atoms is weaker. Simultaneously, the first and second titanium layers are formed independently with higher lattice dislocations than a single titanium layer. This grain boundary dislocation between the first and second titanium layers results in a highly tortuous and discontinuous atomic transport path, forming a diffusion path that hinders aluminum atom diffusion and physically blocks it. Furthermore, the dangling bonds on the titanium layer surface preferentially adsorb aluminum atoms, further reducing their mobility. The gate metal trace 51 is connected to the gate 22 through the barrier layer 4. The metal gate trace 51 can include an aluminum-copper (AlCu) gate metal trace. Under high-temperature conditions, aluminum atoms in the metal gate trace 51 cannot diffuse through the barrier layer 4 to the gate 22.

[0032] The technical solution of this invention provides a first titanium layer and a second titanium layer as barrier layers. The physical barrier between the first titanium layer and the second titanium layer, as well as the adsorption effect of the dangling bonds on the surface of the titanium layer on aluminum atoms, effectively prevent aluminum atoms from diffusing into the gate 22 and causing the aluminum atoms to fuse with the gate 22.

[0033] Optionally, based on the above embodiments, refer to... Figure 4 The thickness of the first barrier layer 41 is 90nm-100nm, and the thickness of the second barrier layer 42 is 90nm-100nm.

[0034] Specifically, the thickness of the first barrier layer 41 and the second barrier layer 42 can both be set to 90nm-100nm. In some embodiments of the present invention, the thickness of the first barrier layer 41 and the second barrier layer 42 can be arbitrarily set according to the actual situation, without specific limitation, to ensure that the first barrier layer 41 and the second barrier layer 42 can effectively block aluminum atoms from diffusing into the gate 22.

[0035] Optionally, based on the above embodiments, Figure 8 This is a schematic diagram of another gate interconnect structure provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the barrier layer 4 further includes a third barrier layer 43. The third barrier layer 43 is located on the side of the second barrier layer 42 away from the gate 22. The vertical projection of the third barrier layer 43 on the gate 22 covers the vertical projections of the first barrier layer 41 and the second barrier layer 42 on the gate 22. The third barrier layer 43 is used to isolate the gate metal trace 51 from the second barrier layer 42 and the first barrier layer 41.

[0036] Specifically, the barrier layer 4 may also include a third barrier layer 43, which may cover the side of the second barrier layer 42 away from the gate 22. The third barrier layer 43 may completely cover the first barrier layer 41 and the second barrier layer 42 to prevent the gate metal trace 51 from contacting the first barrier layer 41 or the second barrier layer 42.

[0037] For example, the first barrier layer 41 may include a first titanium layer, the second barrier layer 42 may include a second titanium layer, and the gate metal trace 51 may include an aluminum-copper (AlCu) gate metal trace. To avoid the problem of titanium and aluminum fusing together, causing a rough surface in the barrier layer 4 and affecting the filling of the gate metal trace 51, this embodiment of the invention provides a third barrier layer 43 on the side of the second barrier layer 42 away from the gate 22. The third barrier layer 43 can completely cover the first barrier layer 41 and the second barrier layer 42, preventing the gate metal trace 51 from contacting the first barrier layer 41 or the second barrier layer 42, thereby effectively avoiding the problem of titanium and aluminum fusing together.

[0038] In the technical solution of this embodiment of the invention, the barrier layer 4 may include a first barrier layer 41, a second barrier layer 42 and a third barrier layer 43. The first barrier layer 41 and the second barrier layer 42 can effectively block aluminum atoms from diffusing into the gate 22, and the third barrier layer 43 can further achieve physical blockage of aluminum atom diffusion. Figure 9 This is an imaging schematic diagram of a focused ion beam (FIB) experiment of another gate interconnect structure provided in an embodiment of the present invention, as shown below. Figure 9 As shown, due to the setting of the barrier layer 4, aluminum atoms in the metal gate trace 51 will not diffuse through the barrier layer 4 to the gate 22, so there will be no problem of aluminum and polysilicon fusion.

[0039] Optionally, based on the above embodiments, refer to... Figure 8 The third barrier layer 43 includes a titanium nitride layer, and the thickness of the third barrier layer 43 is 50 nm.

[0040] Specifically, the third barrier layer 43 may include a titanium nitride layer, and the thickness of the third barrier layer 43 may be set to 50 nm. In some embodiments of the present invention, the thickness of the third barrier layer 43 may be arbitrarily set according to actual needs, and no specific limitation is made here.

[0041] The third barrier layer 43, made of titanium nitride, can block the contact between the first barrier layer 41 and the second barrier layer 42 and the metal gate trace 51, thus preventing the gate metal trace 51 from contacting the first barrier layer 41 or the second barrier layer 42, effectively avoiding the problem of titanium and aluminum interfacial fusion. Although the heterogeneous phase interface between titanium nitride and the second barrier layer 42, made of titanium, may have interface defects, forming diffusion paths for aluminum atoms, the double titanium layer effectively blocks the aluminum atoms. The first and second titanium layers are formed independently with a higher lattice dislocation than a single titanium layer. That is, the grain boundary dislocation between the first and second titanium layers makes the atomic transport path between the first and second titanium layers very tortuous and discontinuous, thus forming a diffusion path that hinders the diffusion of aluminum atoms, achieving physical blockage of aluminum atom diffusion. At the same time, the dangling bonds on the surface of the titanium layer can preferentially adsorb aluminum atoms, thereby further reducing the mobility of aluminum atoms.

[0042] The technical solution of this invention adds a titanium layer to the traditional Ti+TiN barrier layer, thereby forming a multi-dimensional barrier of physical barrier at the double titanium layer interface and adsorption effect of aluminum atoms by the dangling bonds at the titanium layer interface. The thickness of the titanium layer in a traditional Ti+TiN barrier layer is typically 100 nm, and the thickness of the titanium nitride layer is typically 130 nm. In this invention, the thickness of the first titanium layer can be 90 nm, the thickness of the second titanium layer can also be 90 nm, and the thickness of the titanium nitride layer can be 50 nm, meaning the total thickness of the new barrier layer can be the same as the total thickness of the traditional barrier layer. Compared to the traditional Ti+TiN barrier layer, the barrier layer provided by this invention reduces the aluminum atom penetration rate from 100% to 0%, and the aluminum atom penetration rate is the probability of aluminum atoms diffusing to the gate 22 and intermingling with it. Compared to the traditional Ti+TiN barrier layer, the resistivity of the three-layer barrier layer 4 provided by this invention is reduced by 22%, the intrinsic stress is reduced by 62%, and after continuous annealing at 500°C for 30 minutes, no aluminum diffuses to the gate 22.

[0043] The double-layer Ti+TiN barrier layer structure not only significantly improves puncture resistance compared to the traditional Ti+TiN barrier layer, but also reduces film stress and resistivity, all of which are beneficial. This invention's embodiment forms an interface through two independent Ti layer depositions, effectively blocking the diffusion of aluminum atoms at high temperatures, reducing the puncture defect rate from 100% to 0%. While maintaining conductivity, this structure reduces the TiN barrier layer thickness by 30%-50% compared to traditional solutions, reduces resistivity by 22%, and reduces stress by 62%. It is suitable for AlCu formation processes at 470℃, seamlessly integrating with existing AlCu processes without requiring additional equipment investment, providing technical support for the miniaturization and reliability improvement of SiC chips.

[0044] Figure 10 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention, such as... Figure 10As shown, the semiconductor device includes: a semiconductor body 1 configured with a first conductivity type, the semiconductor body 1 including a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body 1 includes a core region 103 and an edge region 104, the edge region 104 surrounding the core region 103. The semiconductor body 1 of the core region 103 also includes at least one well region 13 and a first region 14, the first region 14 configured with the first conductivity type and located on the first surface 101, the well region 13 configured with the second conductivity type and located on the side of the first region 14 away from the first surface 101, the first conductivity type and the second conductivity type being different. A gate insulating layer 21 is located on the first surface 101, the gate insulating layer 21 of the first surface 101 of the semiconductor body 1 of the core region 103 includes a second groove 23, the second groove 23 exposing the first region 14. A gate 22 is located on the side of the gate insulating layer 21 away from the semiconductor body 1. A first insulating layer 3 is located on the side of the gate 22 away from the semiconductor body 1; the first insulating layer 3 corresponding to the semiconductor body 1 of the edge region 104 includes a first groove 31, the first groove 31 exposing a portion of the gate 22.

[0045] A barrier layer 4 is located on the side of the first insulating layer 3 opposite to the semiconductor body 1 in the edge region 104, and on the bottom and sidewalls of the first recess 31. The barrier layer 4 includes a first barrier layer 41 and a second barrier layer 42. The first barrier layer 41 is located on the side of the first insulating layer 3 opposite to the gate 22, and is located on the bottom and sidewalls of the first recess 31. The second barrier layer 42 is located on the side of the first barrier layer 41 opposite to the gate 22. The first barrier layer 41 and the second barrier layer 42 have the same lattice constant. The first barrier layer 41 includes a first grain boundary line extending from the side of the first barrier layer 41 opposite to the gate 22 to the side of the first barrier layer 41 near the gate 22. The second barrier layer 42 includes a second grain boundary line extending from the side of the second barrier layer 42 opposite to the gate 22 to the side of the second barrier layer 42 near the gate 22. The first grain boundary line and the second grain boundary line are offset along a direction parallel to the gate 22. A gate metal trace 51 is located on the side of the barrier layer 4 opposite to the semiconductor body 1. The source electrode 52 is located on the first surface 101 of the semiconductor body 1 in the core region 103, and on the side of the first insulating layer 3 corresponding to the semiconductor body 1 in the core region 103 that is away from the semiconductor body 1. The source electrode 52 is in contact with the first region 14; the gate metal trace 51 surrounds the source electrode 52, and the source electrode 52 is insulated from the gate metal trace 51. The drain electrode 53 is located on the second surface 102.

[0046] Specifically, the semiconductor body 1 of the core region 103 may include multiple well regions 13 and multiple first regions 14. In this embodiment of the invention, one well region 13 corresponds to two first regions 14, and the two first regions 14 are arranged in a direction parallel to the semiconductor body 1. The semiconductor device may include multiple unit cell structures 10, each unit cell structure 10 may include one well region 13 and two first regions 14, and the unit cell structure 10 may be a semiconductor device structure that realizes the electrical function of a MOSFET.

[0047] Optionally, such as Figure 10 As shown, the semiconductor body 1 may also include a second region 15. The second region 15 in the semiconductor body 1 of the core region 103 may be located between two first regions 14. The doping concentration of the second region 15 may be greater than the doping concentration of the well region 13, and may form a good ohmic contact with the source 52.

[0048] It should be noted that the semiconductor device can include an N-channel semiconductor device or a P-channel semiconductor device. For example, for an N-channel semiconductor device, the semiconductor body 1 is an N-type semiconductor body, the well region 13 is a P-type well region, the first region 14 is an N++ doped region, and the second region 15 is a P++ doped region. For a P-channel semiconductor device, the semiconductor body 1 is a P-type semiconductor body, the well region 13 is an N-type well region, the first region 14 is a P++ doped region, and the second region 15 is an N++ doped region.

[0049] For example, such as Figure 10 As shown, the semiconductor body 1 may further include a substrate 11 and an epitaxial layer 12. For an N-channel semiconductor device, the substrate 11 includes an N+ substrate, and the epitaxial layer 12 includes an N- epitaxial layer. For a P-channel semiconductor device, the substrate 11 includes a P+ substrate, and the epitaxial layer 12 includes a P- epitaxial layer. In some embodiments of the present invention, the semiconductor body 1 may only include the epitaxial layer 12. In other embodiments of the present invention, the semiconductor body 1 may further include a substrate 11 and a semiconductor layer formed by other processes. The epitaxial layer 12 is a semiconductor layer formed on the substrate 11 by a single epitaxial process, including chemical vapor deposition (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0050] The gate structure 2 includes a gate insulating layer 21 and a gate 22. The gate structure 2 may be located on the first surface 101 or extend from the first surface 101 into the semiconductor body 1. The first insulating layer 3 may serve as an interlayer dielectric layer to isolate the gate 22 from the source 52.

[0051] The semiconductor device may further include a barrier layer 4, which includes a first barrier layer 41, a second barrier layer 42, and a third barrier layer 43. For example, both the first barrier layer 41 and the second barrier layer 42 may comprise a titanium layer. In this embodiment, the first barrier layer 41 and the second barrier layer 42 have the same lattice constant. The first barrier layer 41 may comprise a titanium layer, and the second barrier layer 42 may also comprise a titanium layer. There is no strong strain field or ultra-high density defect between the first barrier layer 41 and the second barrier layer 42. The defect density and energy state at the interface between the first barrier layer 41 and the second barrier layer 42 are much lower than those at the heterogeneous phase boundary between the Ti layer and the TiN layer, thus resulting in a weaker diffusion pull on aluminum atoms. Simultaneously, the grain boundary misalignment between the first barrier layer 41 and the second barrier layer 42 causes the atomic transport path between the two barrier layers to become very tortuous and discontinuous, thereby forming a diffusion path that hinders the diffusion of aluminum atoms. The gate metal trace 51 is connected to the gate 22 through the barrier layer 4. The metal gate trace 51 may include an aluminum-copper (AlCu) gate metal trace. Under high temperature conditions, aluminum atoms in the metal gate trace 51 cannot diffuse through the barrier layer 4 to the gate 22.

[0052] Figure 11 This is a flowchart of a method for fabricating a gate interconnect structure provided in an embodiment of the present invention, as shown below. Figure 11 As shown, the preparation method includes: S100: Provides the gate.

[0053] Specifically, such as Figure 4 As shown, when forming the gate interconnect structure, the gate 22 can be formed first, and the gate 22 may include a polysilicon gate.

[0054] S110: A first insulating layer is formed on one side of the gate; the first insulating layer includes a first groove, the first groove exposing a portion of the gate.

[0055] Specifically, such as Figure 4 As shown, a first insulating layer 3 is formed on one side of the gate 22. The first insulating layer 3 can serve as an interlayer dielectric layer. The first insulating layer 3 can be etched using processes such as photolithography and etching to form a first groove 31. The first groove 31 penetrates the first insulating layer 3, thereby exposing a portion of the gate 22.

[0056] S120: A barrier layer is formed on the side of the first insulating layer away from the gate, and at the bottom and sidewall of the first groove; the barrier layer includes a first barrier layer and a second barrier layer, the first barrier layer is located on the side of the first insulating layer away from the gate, and at the bottom and sidewall of the first groove, and the second barrier layer is located on the side of the first barrier layer away from the gate; the first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer includes a first grain boundary line, which extends from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer includes a second grain boundary line, which extends from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate.

[0057] Specifically, such as Figure 4 As shown, a barrier layer 4 is formed on the side of the first insulating layer 3 away from the gate 22, and on the bottom and sidewalls of the first recess 31. The barrier layer 4 includes a first barrier layer 41 and a second barrier layer 42. The first barrier layer 41 can be disposed on the side of the first insulating layer 3 away from the gate 22, and can also be disposed on the bottom and sidewalls of the first recess 31. The second barrier layer 42 is disposed on the side of the first barrier layer 41 away from the gate 22. The barrier layer 4 can completely cover the exposed gate 22. The lattice constants of the first barrier layer 41 and the second barrier layer 42 can be the same, and there can be lattice dislocations between the first barrier layer 41 and the second barrier layer 42, that is, there are dislocations between the first grain boundary line perpendicularly penetrating the first barrier layer 41 and the second grain boundary line perpendicularly penetrating the second barrier layer 42. For example, both the first barrier layer 41 and the second barrier layer 42 can include a titanium layer.

[0058] S130: A gate metal trace is formed on the side of the barrier layer away from the gate.

[0059] Specifically, such as Figure 4 As shown, a gate metal trace 51 is formed on the side of the barrier layer 4 away from the gate 22. For example, AlCu alloy deposition can be performed at a temperature of 470°C, and the thickness can be adjusted according to the size of the first groove 31.

[0060] To prevent aluminum atoms in the gate metal trace 51 from diffusing to the gate 22, this embodiment of the invention employs a first barrier layer 41 and a second barrier layer 42 with the same lattice constant. The first barrier layer 41 may include a titanium layer, and the second barrier layer 42 may also include a titanium layer. There is no strong strain field or ultra-high density defect between the first barrier layer 41 and the second barrier layer 42. The defect density and energy state at the interface between the first barrier layer 41 and the second barrier layer 42 are much lower than those at the heterogeneous phase boundary between the Ti layer and the TiN layer, thus the diffusion pull on aluminum atoms is weaker. Simultaneously, the grain boundary misalignment between the first barrier layer 41 and the second barrier layer 42 causes the atomic transport path between the two barrier layers to become very tortuous and discontinuous, thereby forming a diffusion path that hinders the diffusion of aluminum atoms. The gate metal trace 51 is connected to the gate 22 through the barrier layer 4. The metal gate trace 51 may include an aluminum-copper (AlCu) gate metal trace. Under high-temperature conditions, aluminum atoms in the metal gate trace 51 cannot diffuse through the barrier layer 4 to the gate 22.

[0061] Optionally, based on the above embodiments, Figure 12 This is a flowchart of another method for fabricating a gate interconnect structure provided in an embodiment of the present invention, as shown below. Figure 12 As shown, the preparation method includes: S200: Provides the gate.

[0062] S210: A first insulating layer is formed on one side of the gate; the first insulating layer includes a first groove that exposes a portion of the gate.

[0063] S220: A first titanium layer is formed on the side of the first insulating layer away from the gate using a physical vapor deposition process, and at the bottom and sidewalls of the first groove. The first titanium layer serves as a first barrier layer.

[0064] Specifically, such as Figure 4 As shown, after forming the first insulating layer 3, surface cleaning, oxide layer removal, and surface activation can be performed. Then, using physical vapor deposition (PVD) (target purity ≥ 99.999%), a first titanium layer is deposited on the side of the first insulating layer 3 away from the gate 22, and on the bottom and sidewalls of the first groove 31. The first titanium layer serves as the first barrier layer 41. The deposition temperature can be 50℃, the thickness of the first titanium layer can be 90nm-100nm, and the deposition rate can be 1.8nm / s.

[0065] S230: After a first time interval in a vacuum environment, a second titanium layer is formed on the side of the first titanium layer away from the gate using a physical vapor deposition process. The second titanium layer serves as a second barrier layer, which includes both the first and second barrier layers. The first and second barrier layers have the same lattice constant; the first barrier layer includes a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer includes a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first and second grain boundary lines are staggered along a direction parallel to the gate.

[0066] Specifically, such as Figure 4 As shown, after the first titanium layer is deposited, a first time interval is established under vacuum (pressure < 1E-5 Torr). For example, the first time interval can be 5 seconds. In some embodiments of the present invention, the first time interval can be arbitrarily set according to actual needs. During the first time interval, trace amounts of gas may be adsorbed on the surface of the first titanium layer. Then, a second titanium layer is deposited on the side of the first titanium layer away from the gate 22 using a physical vapor deposition process. The second titanium layer serves as the second barrier layer 42. The deposition temperature can be 50°C, the thickness of the first titanium layer can be 90nm-100nm, and the deposition rate can be 1.8nm / s. An interface exists between the first and second titanium layers.

[0067] There is no strong strain field or ultra-high density defect between the first and second titanium layers. The defect density and energy state at the interface between the first and second titanium layers are much lower than those at the heterogeneous phase boundary between the Ti and TiN layers, thus the diffusion attraction for aluminum atoms is weaker. Simultaneously, the first and second titanium layers are formed independently with higher lattice dislocations than a single titanium layer. This grain boundary dislocation between the first and second titanium layers results in a highly tortuous and discontinuous atomic transport path, forming a diffusion path that hinders aluminum atom diffusion and physically blocks it. Furthermore, the dangling bonds on the titanium layer surface preferentially adsorb aluminum atoms, further reducing their mobility. The gate metal trace 51 is connected to the gate 22 through the barrier layer 4. The metal gate trace 51 can include an aluminum-copper (AlCu) gate metal trace. Under high-temperature conditions, aluminum atoms in the metal gate trace 51 cannot diffuse through the barrier layer 4 to the gate 22.

[0068] S240: A gate metal trace is formed on the side of the barrier layer away from the gate.

[0069] Optionally, based on the above embodiments, Figure 13 This is a flowchart of another method for fabricating a gate interconnect structure provided in an embodiment of the present invention, as shown below. Figure 13 As shown, the preparation method includes: S300: Provides the gate.

[0070] S310: A first insulating layer is formed on one side of the gate; the first insulating layer includes a first groove that exposes a portion of the gate.

[0071] S320: A first titanium layer is formed on the side of the first insulating layer away from the gate using a physical vapor deposition process, and at the bottom and sidewalls of the first groove. The first titanium layer serves as a first barrier layer.

[0072] S330: After a first time interval in a vacuum environment, a second titanium layer is formed on the side of the first titanium layer away from the gate using a physical vapor deposition process. The second titanium layer serves as a second barrier layer. The first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer includes a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer includes a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate.

[0073] S340: A third barrier layer is formed on the side of the second barrier layer away from the gate; the vertical projection of the third barrier layer onto the gate covers the first barrier layer and the vertical projection of the second barrier layer onto the gate; the third barrier layer is used to isolate the gate metal trace from the second barrier layer and the first barrier layer. The barrier layer includes the first barrier layer, the second barrier layer, and the third barrier layer.

[0074] Specifically, such as Figure 8 As shown, after the second titanium layer is formed, a third barrier layer 43 can be formed on the side of the second titanium layer away from the gate 22. The third barrier layer 43 can cover the side of the second titanium layer 42 away from the gate 22, and the third barrier layer 43 can completely cover the first titanium layer and the second titanium layer, preventing the gate metal trace 51 from contacting the first titanium layer or the second titanium layer.

[0075] The gate metal trace 51 may include an aluminum-copper (AlCu) gate metal trace. In order to avoid the problem of titanium and aluminum fusing together, which would cause the surface of the barrier layer 4 to be rough and affect the filling of the gate metal trace 51, this embodiment of the invention provides a third barrier layer 43 on the side of the second titanium layer away from the gate 22. The third barrier layer 43 can completely cover the first titanium layer and the second titanium layer, thereby preventing the gate metal trace 51 from contacting the first titanium layer or the second titanium layer, thus effectively avoiding the problem of titanium and aluminum fusing together.

[0076] In the technical solution of this embodiment of the invention, the barrier layer 4 may include a first barrier layer 41, a second barrier layer 42, and a third barrier layer 43. The first barrier layer 41 and the second barrier layer 42 can effectively prevent aluminum atoms from diffusing into the gate 22, and the third barrier layer 43 can further physically block the diffusion of aluminum atoms. Due to the barrier layer 4, aluminum atoms in the metal gate trace 51 will not diffuse through the barrier layer 4 to the gate 22, thus avoiding the problem of aluminum and polysilicon intermingling.

[0077] S350: A gate metal trace is formed on the side of the barrier layer away from the gate.

[0078] Optionally, based on the above embodiments, such as Figure 8 As shown, the third barrier layer 43 may include a titanium nitride layer, which can be formed in an atmosphere of a mixture of argon and nitrogen using a magnetron sputtering process on the side of the second barrier layer 42 away from the gate 22. The proportion of nitrogen can be 70%-80%, the deposition temperature can be 50℃, and the deposition thickness can be 50nm.

[0079] The third barrier layer 43, made of titanium nitride, can block the contact between the first barrier layer 41 and the second barrier layer 42 and the metal gate trace 51, thus preventing the gate metal trace 51 from contacting the first barrier layer 41 or the second barrier layer 42, effectively avoiding the problem of titanium and aluminum interfacial fusion. Although the heterogeneous phase interface between titanium nitride and the second barrier layer 42, made of titanium, may have interface defects, forming diffusion paths for aluminum atoms, the double titanium layer effectively blocks the aluminum atoms. The first and second titanium layers are formed independently with a higher lattice dislocation than a single titanium layer. That is, the grain boundary dislocation between the first and second titanium layers makes the atomic transport path between the first and second titanium layers very tortuous and discontinuous, thus forming a diffusion path that hinders the diffusion of aluminum atoms, achieving physical blockage of aluminum atom diffusion. At the same time, the dangling bonds on the surface of the titanium layer can preferentially adsorb aluminum atoms, thereby further reducing the mobility of aluminum atoms.

[0080] Figure 14 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention, such as... Figure 14 As shown, the preparation method includes: S400: Provides a semiconductor body of a first conductivity type; the semiconductor body includes a first surface and a second surface disposed opposite to each other; the semiconductor body includes a core region and an edge region, the edge region surrounding the core region; the semiconductor body of the core region also includes at least one well region and a first region, the first region being configured with a first conductivity type and located on the first surface, the well region being configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type being different.

[0081] S410: A gate insulating layer is formed on the first surface, and the gate insulating layer on the first surface of the semiconductor body of the core region includes a second groove, the second groove exposing the first region.

[0082] S420: A gate is formed on the side of the gate insulating layer away from the semiconductor body.

[0083] S430: A first insulating layer is formed on the side of the gate away from the semiconductor body; the first insulating layer corresponding to the semiconductor body in the edge region includes a first groove, the first groove exposing a portion of the gate.

[0084] S440: A barrier layer is formed on the side of the first insulating layer corresponding to the semiconductor body in the edge region away from the semiconductor body, and on the bottom and sidewall of the first groove; the barrier layer includes a first barrier layer and a second barrier layer, the first barrier layer is located on the side of the first insulating layer away from the gate, and is located on the bottom and sidewall of the first groove, and the second barrier layer is located on the side of the first barrier layer away from the gate; the first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer includes a first grain boundary line, which extends from the side of the first barrier layer away from the gate to the side of the first barrier layer near the gate; the second barrier layer includes a second grain boundary line, which extends from the side of the second barrier layer away from the gate to the side of the second barrier layer near the gate; the first grain boundary line and the second grain boundary line are staggered along a direction parallel to the gate.

[0085] Specifically, such as Figure 10 As shown, during the formation of a semiconductor device, a barrier layer 4 can be formed on the side of the first insulating layer 3 corresponding to the semiconductor body 1 in the edge region 104 away from the semiconductor body 1, and on the bottom and sidewalls of the first groove 31. The barrier layer 4 includes a first barrier layer 41, a second barrier layer 42, and a third barrier layer 43. For example, both the first barrier layer 41 and the second barrier layer 42 can include a titanium layer. In this embodiment of the invention, a first barrier layer 41 and a second barrier layer 42 with the same lattice constant are used. The first barrier layer 41 can include a titanium layer, and the second barrier layer 42 can also include a titanium layer. There is no strong strain field and ultra-high density defects between the first barrier layer 41 and the second barrier layer 42. The defect density and energy state at the interface between the first barrier layer 41 and the second barrier layer 42 are much lower than those at the heterogeneous phase boundary between the Ti layer and the TiN layer, thus the diffusion pull on aluminum atoms is weaker. At the same time, the grain boundary misalignment between the first barrier layer 41 and the second barrier layer 42 causes the atomic transport path between the two barrier layers to become very tortuous and discontinuous, thereby forming a diffusion path that hinders the diffusion of aluminum atoms. The gate metal trace 51 is connected to the gate 22 through the barrier layer 4. The metal gate trace 51 may include an aluminum-copper (AlCu) gate metal trace. Under high temperature conditions, aluminum atoms in the metal gate trace 51 cannot diffuse through the barrier layer 4 to the gate 22.

[0086] S450: A gate metal trace is formed on the side of the barrier layer away from the semiconductor body.

[0087] S460: A source electrode is formed on the first surface of the semiconductor body in the core region, and on the side of the first insulating layer corresponding to the semiconductor body in the core region away from the semiconductor body; the source electrode is in contact with the first region; the gate metal trace surrounds the source electrode, and the source electrode and the gate metal trace are insulated and isolated from each other.

[0088] S470: Drain electrode is formed on the second surface.

[0089] This invention provides a power module, wherein the power module includes a substrate and at least one semiconductor device provided in any of the above embodiments of this invention, and the substrate is used to carry at least one semiconductor device provided in any of the above embodiments of this invention.

[0090] The power module provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0091] This invention provides a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction.

[0092] The power conversion circuit includes a circuit board and at least one semiconductor device provided in any of the above embodiments of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0093] The power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention and has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0094] This invention provides a vehicle, wherein the vehicle includes a load and a power conversion circuit provided in any of the above embodiments of the invention. The power conversion circuit is used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

[0095] The vehicle provided in any of the above embodiments of the present invention includes the power conversion circuit provided in any of the above embodiments of the present invention, and the power conversion circuit provided in any of the above embodiments of the present invention includes the semiconductor device provided in any of the above embodiments of the present invention. Therefore, the vehicle provided in any of the above embodiments of the present invention has the beneficial effects of the semiconductor device provided in any of the above embodiments of the present invention.

[0096] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0097] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate interconnect structure, characterized by, The application relates to a semiconductor device, which comprises: a gate electrode; a first insulating layer located on one side of the gate electrode, wherein the first insulating layer comprises a first groove which exposes part of the gate electrode; a barrier layer comprising a first barrier layer and a second barrier layer, wherein the first barrier layer is located on the side of the first insulating layer away from the gate electrode and on the bottom and sidewall of the first groove, the second barrier layer is located on the side of the first barrier layer away from the gate electrode, the lattice constant of the first barrier layer is the same as that of the second barrier layer, the first barrier layer comprises a first grain boundary line extending from the side of the first barrier layer away from the gate electrode to the side of the first barrier layer close to the gate electrode, the second barrier layer comprises a second grain boundary line extending from the side of the second barrier layer away from the gate electrode to the side of the second barrier layer close to the gate electrode, and the first grain boundary line and the second grain boundary line are arranged in a staggered mode in the direction parallel to the gate electrode; a gate metal trace located on the side of the barrier layer away from the gate electrode.

2. The gate interconnect structure of claim 1, wherein, The first barrier layer comprises a first titanium layer, and the second barrier layer comprises a second titanium layer; the first titanium layer and the second titanium layer are independently formed.

3. The gate interconnect structure of claim 1, wherein, The thickness of the first barrier layer is 90-100 nm, and the thickness of the second barrier layer is 90-100 nm.

4. The gate interconnect structure of claim 1, wherein, The barrier layer further comprises a third barrier layer. The third barrier layer is located on the side of the second barrier layer away from the gate electrode, the vertical projection of the third barrier layer on the gate electrode covers the vertical projection of the first barrier layer and the second barrier layer on the gate electrode, and the third barrier layer is used for isolating the gate metal trace from the second barrier layer and the first barrier layer.

5. The gate interconnect structure of claim 4, wherein, The third barrier layer comprises a titanium nitride layer, and the thickness of the third barrier layer is 50 nm.

6. The gate interconnect structure of claim 1, wherein, The gate metal trace comprises an aluminum-copper alloy trace.

7. A semiconductor device, characterized by The application relates to a semiconductor device, which comprises: a semiconductor body provided with a first conductive type, wherein the semiconductor body comprises oppositely arranged first and second surfaces, the semiconductor body comprises a core region and an edge region surrounding the core region, the semiconductor body of the core region further comprises at least one well region and a first region provided with the first conductive type and located on the side of the first region away from the first surface, and the well region is provided with a second conductive type and located on the side of the first region away from the first surface, wherein the first conductive type is different from the second conductive type; a gate insulating layer located on the first surface, wherein the gate insulating layer of the first surface of the semiconductor body of the core region comprises a second groove which exposes the first region; a gate electrode located on the side of the gate insulating layer away from the semiconductor body; a first insulating layer located on the side of the gate electrode away from the semiconductor body, wherein the first insulating layer of the semiconductor body of the edge region comprises a first groove which exposes part of the gate electrode. The barrier layer is located on the side of the first insulating layer corresponding to the semiconductor body of the edge region away from the semiconductor body, and the bottom and sidewall of the first recess; the barrier layer comprises a first barrier layer and a second barrier layer, the first barrier layer is located on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess, and the second barrier layer is located on the side of the first barrier layer away from the gate; the first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer comprises a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer close to the gate; the second barrier layer comprises a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer close to the gate; the first grain boundary line and the second grain boundary line are arranged in a staggered manner along the direction parallel to the gate; The gate metal wire is located on the side of the barrier layer away from the semiconductor body; The source is located on the first surface of the semiconductor body of the core region and on the side of the first insulating layer corresponding to the semiconductor body of the core region away from the semiconductor body; the source is in contact with the first region; the gate metal wire surrounds the source, and the source and the gate metal wire are arranged in an insulating and isolated manner; The drain is located on the second surface.

8. A method of fabricating a gate interconnect structure, comprising: Comprise: Providing a gate; Forming a first insulating layer on one side of the gate; The first insulating layer comprises a first recess, and the first recess exposes part of the gate; Forming a barrier layer on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess; the barrier layer comprises a first barrier layer and a second barrier layer, the first barrier layer is located on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess, and the second barrier layer is located on the side of the first barrier layer away from the gate; the first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer comprises a first grain boundary line extending from the side of the first barrier layer away from the gate to the side of the first barrier layer close to the gate; the second barrier layer comprises a second grain boundary line extending from the side of the second barrier layer away from the gate to the side of the second barrier layer close to the gate; the first grain boundary line and the second grain boundary line are arranged in a staggered manner along the direction parallel to the gate; Forming a gate metal wire on the side of the barrier layer away from the gate.

9. The method of claim 8, wherein Forming a barrier layer on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess, comprising: Forming a first titanium layer on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess by a physical vapor deposition process; After a first interval in a vacuum environment, forming a second titanium layer on the side of the first titanium layer away from the gate by a physical vapor deposition process.

10. The method of claim 8, wherein A barrier layer is formed on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess, and further comprising: A third barrier layer is formed on the side of the second barrier layer away from the gate; the vertical projection of the third barrier layer on the gate covers the vertical projection of the first barrier layer on the gate and the vertical projection of the second barrier layer on the gate; the third barrier layer is used to isolate the gate metal trace from the second barrier layer and the first barrier layer.

11. The method of claim 10, wherein A third barrier layer is formed on the side of the second barrier layer away from the gate, comprising: A titanium nitride layer is formed on the side of the second barrier layer away from the gate by using a magnetron sputtering process in an atmosphere of a mixed gas of argon and nitrogen.

12. A method of manufacturing a semiconductor device, characterized by, Comprising: A semiconductor body of a first conductive type is provided; the semiconductor body comprises oppositely arranged first and second surfaces; the semiconductor body comprises a core region and an edge region surrounding the core region; the semiconductor body of the core region further comprises at least one well region and a first region, the first region is arranged to be of a first conductive type and is located on the first surface, the well region is arranged to be of a second conductive type and is located on the side of the first region away from the first surface, the first conductive type and the second conductive type are different; A gate insulating layer is formed on the first surface, and the gate insulating layer on the first surface of the semiconductor body of the core region comprises a second recess, the second recess exposes the first region; A gate is formed on the side of the gate insulating layer away from the semiconductor body; A first insulating layer is formed on the side of the gate away from the semiconductor body; the first insulating layer corresponding to the semiconductor body of the edge region comprises a first recess, and the first recess exposes part of the gate; A barrier layer is formed on the side of the first insulating layer corresponding to the semiconductor body of the edge region away from the semiconductor body and on the bottom and sidewall of the first recess; the barrier layer comprises a first barrier layer and a second barrier layer, the first barrier layer is located on the side of the first insulating layer away from the gate and on the bottom and sidewall of the first recess, and the second barrier layer is located on the side of the first barrier layer away from the gate; the first barrier layer and the second barrier layer have the same lattice constant; the first barrier layer comprises a first grain boundary line, the first grain boundary line extends from the side of the first barrier layer away from the gate to the side of the first barrier layer close to the gate; the second barrier layer comprises a second grain boundary line, the second grain boundary line extends from the side of the second barrier layer away from the gate to the side of the second barrier layer close to the gate; the first grain boundary line and the second grain boundary line are arranged in a staggered manner in a direction parallel to the gate; A gate metal trace is formed on the side of the barrier layer away from the semiconductor body; A source is formed on the first surface of the semiconductor body of the core region and on the side of the first insulating layer corresponding to the semiconductor body of the core region away from the semiconductor body. The source is in contact with the first region; the gate metal wire surrounds the source, and the source and the gate metal wire are insulated and separated; A drain is formed on the second surface.

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