Chip-and-chip three-dimensional layered interconnect packaging structure

Abstract

This invention relates to the field of semiconductor packaging technology, specifically to a chip-level three-dimensional layered interconnect packaging structure suitable for the Chiplet architecture. This invention provides a chip-level three-dimensional layered interconnect packaging structure. This structure arranges chips in three dimensions along the package thickness direction, setting intra-layer interconnect structures within different chip layers and inter-layer interconnect structures between adjacent chip layers. This constructs a multi-level interconnect system composed of intra-layer and inter-layer interconnects, forming three-dimensional interconnect paths distributed along the package thickness direction between chips. In this structure, each chip layer can contain one or more chips, and different chip layers can be configured hierarchically according to the chip's functional type. This achieves layered organization of the interconnect structure based on three-dimensional chip integration, providing a more flexible structural basis for the packaging integration of multi-chip systems.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and more specifically to a chip-level three-dimensional layered interconnect packaging structure suitable for the Chiplet architecture. Background Technology

[0002] As integrated circuit manufacturing processes continue to evolve, single-chip systems are gradually facing bottlenecks in transistor size, manufacturing cost, and yield control. To reduce design complexity, improve system integration flexibility, and enhance manufacturing economics, the Chiplet architecture, which decomposes complex system functions into multiple relatively independent chips and integrates them at the system level, is gradually becoming an important development direction in the semiconductor field.

[0003] In existing technologies, the main integration and packaging methods for Chiplet include the following categories: One type is a 2.5D packaging structure based on an interposer, which interconnects multiple chips in the same plane through a silicon interposer or an organic interposer. Another type is a three-dimensional packaging structure that stacks multiple chips vertically, and vertical electrical connections are usually achieved through through-hole structures, micro-bumps, etc.

[0004] However, the existing packaging structures still have certain limitations in practical applications.

[0005] For 2.5D packaging structures, interconnection between chips is mainly achieved through planar wiring. The interconnection path is relatively long, and the wiring complexity increases significantly with the increase in the number of chips and interconnection density, which places higher demands on the package area and interconnection resources.

[0006] For simple three-dimensional stacked structures, although the interconnection distance between cores can be shortened to some extent, problems such as interconnection concentration, interlayer stress superposition, and difficulty in thermal management can easily occur when the number of cores increases or the functional complexity increases.

[0007] Furthermore, in the Chiplet architecture, different chips often perform different functions, such as computing, storage, or interfaces, and they differ significantly in terms of power consumption, heat dissipation characteristics, and interconnect requirements. Existing packaging solutions typically employ a relatively uniform stacking or interconnection method, making it difficult to design differentiated layered layouts and interconnect structures for different functional chips. This limits the system integration density, structural stability, and overall package reliability.

[0008] Therefore, how to achieve high-density chip integration in chiplet packaging while rationally arranging the chips in three-dimensional layers, and how to construct a more flexible and stable interconnect structure system through the coordinated setting of intra-layer and inter-layer interconnect structures, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0009] To address the limitations of existing chiplet packaging structures in chiplet integration, such as restricted interconnect path organization, insufficient packaging flexibility, and difficulty in maintaining structural stability under multi-chiplet integration conditions, this invention provides a three-dimensional layered interconnect packaging structure. This structure arranges chips in three dimensions along the package thickness direction, incorporating intra-layer interconnect structures within different chiplet layers and inter-layer interconnect structures between adjacent chiplet layers. This creates a multi-level interconnect system composed of intra-layer and inter-layer interconnects, forming three-dimensional interconnect paths distributed along the package thickness direction between chips. In this structure, each chiplet layer can contain one or more chips, and different chiplet layers can be configured hierarchically according to chiplet function types. This achieves layered organization of the interconnect structure based on three-dimensional chiplet integration, providing a more flexible structural foundation for the packaging integration of multi-chiplet systems.

[0010] The technical solution of this invention is as follows: A chip-and-chip three-dimensional layered interconnect packaging structure includes: Packaging substrate; At least two core layers, wherein the core layers are arranged in a three-dimensional layered manner along the thickness direction of the package; Core particles are disposed in each core particle layer, and each core particle layer has one or more core particles. An intralayer interconnect structure is disposed within the same core layer to realize electrical connection between core particles within the core layer; Interlayer interconnection structures are disposed between adjacent core layers to enable electrical connections between different core layers; in, The intra-layer interconnect structure and the inter-layer interconnect structure together constitute a multi-level interconnect system. The multi-level interconnect system includes at least one level of intra-layer interconnect and at least one level of inter-layer interconnect, so that the chip particles form a three-dimensional interconnect path distributed along the package thickness direction.

[0011] Preferably, the number of core layers is two, three, or more.

[0012] Preferably, the cores set in different core layers are cores of different functional types, and the cores of different functional types include at least one or more of computing cores, storage cores, and interface cores.

[0013] Preferably, the intralayer interconnect structure includes at least one of a metal wiring layer, a rewiring layer, or a micro interconnect channel disposed within the same core layer.

[0014] Preferably, the interlayer interconnect structure includes a vertical interconnect structure, which is at least one of a through-hole structure, a vertical post, or a micro-bump interconnect structure.

[0015] Preferably, the intra-layer interconnect structure is mainly distributed along the package plane direction, and the inter-layer interconnect structure is mainly distributed along the package thickness direction, forming spatially separated interconnect paths.

[0016] Preferably, a buffer layer or intermediate support structure is provided between adjacent core layers, located around the interlayer interconnect structure.

[0017] Preferably, a heat dissipation structure is provided on the outer side of at least one core layer, and the heat dissipation structure is thermally connected to the corresponding core layer.

[0018] Preferably, the packaging substrate is a multilayer substrate structure, and at least some of the intralayer interconnect structures are disposed inside the packaging substrate.

[0019] Preferably, the packaging structure is a system-in-package structure or a packaging structure suitable for multi-chip integration.

[0020] Compared with the prior art, the chip-based three-dimensional layered interconnect packaging structure provided by the present invention has at least the following technical advantages: (a) Technical effects of three-dimensional layered arrangement of core particles This invention provides a three-dimensional arrangement of the core particles by setting at least two core particle layers in the thickness direction of the package. Compared with the traditional planar arrangement, this method is beneficial to achieve a higher core particle integration within a limited package area.

[0021] This three-dimensional layered arrangement provides more spatial organization dimensions for the interconnection paths between core particles, and provides a structural basis for the rational layout of subsequent interconnection structures.

[0022] (II) Technical advantages of placing core particles within the core layer One or more chips are set in each chip layer, so that the number and layout of chips can be flexibly configured according to system integration requirements, thereby avoiding excessive constraints on the overall packaging structure due to changes in the number of chips.

[0023] This configuration improves the adaptability of the packaging structure to different core combination forms, which is beneficial for the integration of multi-core systems.

[0024] (III) Technical effects of the intralayer interconnection structure By setting up an intralayer interconnect structure within the same core layer, the electrical connections between cores in the same layer are mainly completed in the package plane direction, which is beneficial for the centralized organization and management of the interconnection relationship between cores in the same layer.

[0025] This structure helps reduce the resource consumption of interlayer interconnects by the same-layer core interconnects, thereby improving the organizational efficiency of the interconnect structure.

[0026] (iv) Technical effects of interlayer interconnection structure By setting up interlayer interconnect structures between adjacent core layers, electrical connections between different core layers can be achieved along the package thickness direction, which helps to shorten the cross-layer interconnect path and reduce the extension of the interconnect path in the package plane.

[0027] This structure provides a clear and independent interconnection channel for signal transmission between different core layers, which helps to achieve an orderly organization of interlayer interconnections.

[0028] (v) The technical effects of intra-layer interconnection and inter-layer interconnection forming a multi-level interconnection system By coordinating the intra-layer interconnection structure and the inter-layer interconnection structure, a multi-level interconnection system is formed, including at least one level of intra-layer interconnection and at least one level of inter-layer interconnection, so that the interconnection paths between the core particles can be distributed at different spatial levels.

[0029] This multi-level interconnection system helps avoid over-concentration of interconnection paths at a single level, thereby improving the organizational rationality and overall stability of interconnection paths from a structural perspective.

[0030] (vi) Technical effects of layered configuration of different functional cores By setting different functional types of core particles in different core particle layers, core particles that perform different functions can be spatially distributed in layers, which is beneficial for targeted design of core particle layout and interconnection method according to functional differences.

[0031] This layered configuration provides a more flexible structural implementation path for the packaging and integration of multifunctional core systems.

[0032] (vii) The technical effects of setting up a buffer layer or intermediate support structure Placing buffer layers or intermediate support structures between adjacent core layers and around the interlayer interconnect structure helps to provide structural support for the interlayer interconnect region, thereby alleviating the problem of mechanical stress concentration in local areas during the stacking of multiple core layers.

[0033] This structure helps improve the structural stability of multi-layer packaging structures during long-term use.

[0034] (viii) The technical effects of the heat dissipation structure A heat dissipation structure is provided on the outside of at least one core layer, and it is thermally connected to the corresponding core layer, which helps to conduct the heat generated by the core during operation to the outside of the package.

[0035] This structure provides an effective structural basis for thermal management under multi-core stereo packaging conditions.

[0036] (ix) Technical advantages of a multilayer substrate structure for packaging By employing a multilayer packaging substrate structure and placing at least some of the intralayer interconnect structures inside the packaging substrate, it is beneficial to increase the density of interconnect structures and enhance the integration capability of the packaging structure without increasing the package size.

[0037] (x) The combined technical effects (unexpected effects) resulting from the synergy of technical features By employing a three-dimensional layered arrangement of chip components, a multi-level interconnect system, and a coordinated design of buffer layers and heat dissipation structures, chip component integration, interconnect path organization, and structural support are integrated within the same packaging structure. This approach improves packaging integration while ensuring the rationality of interconnect path organization and structural stability.

[0038] This overall effect is not achieved by a single structural feature alone, but by the cooperation of multiple structural features, demonstrating the synergistic advantage of the packaging structure of this invention at the overall design level. Attached Figure Description

[0039] To more clearly illustrate the technical solution of the present invention, the present invention will be further described below with reference to the accompanying drawings. It should be understood that the accompanying drawings are for illustrative purposes only and do not constitute a limitation on the scope of protection of the present invention.

[0040] Figure 1 Overall structure; Figure 2 : Three-dimensional layering; Figure 3 : Schematic diagram of intra-layer / inter-layer interconnection merging.

[0041] In the diagram: 1: Heat dissipation structure; 2: Core layer 2; 3: Interlayer interconnect structure; 4: Intralayer interconnect structure; 5: Core layer 1; 6: Packaging substrate. Detailed Implementation

[0042] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be understood that the following embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made by those skilled in the art to the embodiments without departing from the technical concept of the present invention should all fall within the scope of protection of the present invention.

[0043] In the following embodiments, the structures shown are merely schematic and are used to illustrate the interrelationships between various technical features. The specific structural form, size ratio, and arrangement can be adjusted according to actual packaging requirements. Example

[0044] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings. This embodiment is used to illustrate the overall structure and basic arrangement of the chip-based three-dimensional layered interconnect packaging structure of the present invention, but it does not constitute a limitation on the scope of protection of the present invention.

[0045] like Figure 1 and Figure 2 As shown, this embodiment provides a three-dimensional layered interconnect packaging structure for core components, including a packaging substrate 6 and at least two core component layers disposed on the packaging substrate 6: core component layer 2 (5) and core component layer 3 (2). The core component layers are arranged in a three-dimensional layered manner along the packaging thickness direction, and adjacent core component layers are spaced apart from each other in the packaging thickness direction.

[0046] Each core layer contains one or more cores. Each core can be fixedly positioned in its corresponding core layer according to the packaging design requirements, and the cores in different core layers are distributed vertically along the packaging thickness direction. Through this three-dimensional layered arrangement, multiple cores are no longer limited to being arranged within the same packaging plane, but rather form a multi-layer structure along the packaging thickness direction.

[0047] In the three-dimensional layered interconnection packaging structure of the core particles, an intralayer interconnection structure 4 is provided within the same core particle layer to realize the electrical connection between the core particles within the core particle layer; an interlayer interconnection structure 3 is provided between adjacent core particle layers to realize the electrical connection between different core particle layers.

[0048] The intra-layer interconnect structure 4 and the inter-layer interconnect structure 3 cooperate with each other to form a multi-level interconnect system, wherein the multi-level interconnect system includes at least one level of intra-layer interconnect and at least one level of inter-layer interconnect, so that the chip particles form a three-dimensional interconnect path distributed along the package thickness direction.

[0049] In this embodiment, the packaging substrate 6 can be a multilayer substrate structure, with the core layer and related interconnect structures disposed on or integrated with the packaging substrate, thereby forming a complete core-layer three-dimensional interconnect packaging structure.

[0050] With the above structural configuration, the chip three-dimensional layered interconnection packaging structure of this embodiment can organize the chips in layers in the packaging thickness direction, and realize the three-dimensional interconnection between chips through the intra-layer interconnection structure and the inter-layer interconnection structure, providing a basic structural form for the packaging integration of multi-chip systems. Example

[0051] Based on the core-particle three-dimensional layered interconnect packaging structure described in Example 1, this example further explains the arrangement of the intra-layer interconnect structure and the inter-layer interconnect structure and their mutual cooperation relationship.

[0052] like Figure 3 As shown, in this embodiment, an intra-layer interconnect structure 4 is provided within the same core layer. The intra-layer interconnect structure 4 is used to realize the electrical connection between one or more cores within the core layer. The intra-layer interconnect structure 4 can be arranged along the packaging plane, so that the cores within the same core layer are electrically connected through relatively concentrated planar interconnect paths.

[0053] An interlayer interconnect structure 3 is provided between adjacent core layers to achieve electrical connection between different core layers. The interlayer interconnect structure 3 is mainly arranged along the package thickness direction, so that core particles located in different core layers can establish electrical connection paths in the vertical direction.

[0054] In this embodiment, the intra-layer interconnection structure 4 and the inter-layer interconnection structure 3 are spatially distinguished: Intra-layer interconnect structures 4 are mainly distributed in the planar regions within each core layer, while inter-layer interconnect structures 3 are mainly distributed in the vertical connection regions between adjacent core layers. Through this arrangement, different types of interconnect paths occupy different spatial directions in the package structure, thereby forming a spatially separated interconnect path structure.

[0055] By simultaneously incorporating intra-layer interconnect structures and inter-layer interconnect structures within a three-dimensional layered packaging structure, a multi-level interconnect system is formed. This multi-level interconnect system includes at least one level of intra-layer interconnect and at least one level of inter-layer interconnect, ensuring that the electrical connections between chips are no longer concentrated in a single plane or layer, but are hierarchically organized along both the package thickness direction and the package plane direction.

[0056] In this embodiment, the intra-layer interconnect structure may include at least one of a metal wiring layer, a rewiring layer, or a micro interconnect channel; the inter-layer interconnect structure may include at least one of a via structure, a vertical through-pillar, or a micro-bump interconnect structure. It should be understood that the above interconnect structure forms are merely examples and do not constitute a limitation of the present invention. Those skilled in the art can select other equivalent interconnect structure forms according to specific packaging requirements.

[0057] Through the above structural setup, the multi-level interconnection system described in this embodiment can realize the hierarchical organization of different interconnection paths in the core-particle three-dimensional layered packaging structure, providing a clear and orderly structural foundation for the realization of complex interconnection relationships in multi-core-particle systems. Example

[0058] Based on the three-dimensional layered interconnection packaging structure of the chip particles described in Examples 1 and 2, this example further describes the layered arrangement of different functional chips particles and the setting of the buffer layer and heat dissipation structure 1.

[0059] In this embodiment, the chips arranged in different chip layers are chips of different functional types. Specifically, at least one chip layer contains a computing chip, at least one chip layer contains a storage chip, or at least one chip layer contains an interface chip. By arranging chips of different functional types in different chip layers, a layered distribution relationship is formed between the various chips in the package thickness direction, thereby facilitating the rational arrangement of their positions according to the characteristics of different functional chips.

[0060] A buffer layer or intermediate support structure is provided between adjacent core layers and around the interlayer interconnect structure. The buffer layer or intermediate support structure can be disposed in the area surrounding the interlayer interconnect structure to provide support and buffering. This arrangement ensures good structural stability of the interlayer interconnect region under multi-layer core stacking conditions.

[0061] In addition, a heat dissipation structure 1 is provided on the outer side of at least one core layer. The heat dissipation structure 1 forms a thermal connection with the corresponding core layer to conduct the heat generated by the core in the core layer during operation to the outside of the package. The heat dissipation structure can be provided on the upper side, lower side or side area of ​​the package structure according to the specific arrangement of the core layers.

[0062] In this embodiment, the functional chip layer arrangement, buffer layer or intermediate support structure, and heat dissipation structure can be combined and configured according to different packaging application requirements. It should be understood that the above configuration is only a preferred embodiment, and the present invention does not limit the specific number, position, or form of each functional chip layer, buffer layer, and heat dissipation structure.

[0063] Through the above structural configuration, the three-dimensional layered interconnection packaging structure of the chip particles described in this embodiment can achieve three-dimensional integration of multiple chips particles, while providing relatively independent arrangement space for different functional chips particles, and providing structural support and thermal management conditions in the interlayer interconnection area, thereby further improving the adaptability and stability of the packaging structure.

Claims

1. A three-dimensional layered interconnect packaging structure for chip components, characterized in that, include: Packaging substrate; At least two core layers, wherein the core layers are arranged in a three-dimensional layered manner along the thickness direction of the package; Core particles are disposed in each core particle layer, and each core particle layer has one or more core particles. An intralayer interconnect structure is disposed within the same core layer to realize electrical connection between core particles within the core layer; Interlayer interconnection structures are disposed between adjacent core layers to enable electrical connections between different core layers; The intra-layer interconnect structure and the inter-layer interconnect structure together constitute a multi-level interconnect system. The multi-level interconnect system includes at least one level of intra-layer interconnect and at least one level of inter-layer interconnect, so that the chip particles form a three-dimensional interconnect path distributed along the package thickness direction.

2. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, The number of core layers is two, three, or more.

3. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, The cores set in different core layers are cores of different functional types, and the cores of different functional types include at least one or more of computing cores, storage cores and interface cores.

4. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, The intralayer interconnect structure includes at least one of a metal wiring layer, a rewiring layer, or a micro interconnect channel disposed within the same core layer.

5. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, The interlayer interconnect structure includes a vertical interconnect structure, which is at least one of a via structure, a vertical through post, or a micro-bump interconnect structure.

6. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, The intralayer interconnect structure is mainly distributed along the package plane direction, and the interlayer interconnect structure is mainly distributed along the package thickness direction, forming spatially separated interconnect paths.

7. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, A buffer layer or intermediate support structure is provided between adjacent core layers, located around the interlayer interconnect structure.

8. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, A heat dissipation structure is provided on the outside of at least one core layer, and the heat dissipation structure is thermally connected to the corresponding core layer.

9. The chip-based three-dimensional layered interconnect packaging structure according to claim 1, characterized in that, The packaging substrate has a multilayer substrate structure, and at least some of the intralayer interconnect structures are disposed inside the packaging substrate.

10. The chip-based three-dimensional layered interconnect packaging structure according to any one of claims 1 to 9, characterized in that, The packaging structure is a system-level packaging structure, or a packaging structure suitable for multi-chip integration.

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