Unit library representation

Abstract

A method and data processing system for characterizing logic cells in an integrated circuit are provided. The method includes: identifying the input and output pins of the cell as selected input and output pins; evaluating a model of the logic cell for each input signal pair from a set including input signal pairs; identifying a subset of the set based on the evaluation; and determining the propagation delay for each pair in the subset.

Description

Technical Field

[0001] This disclosure relates to methods and systems for testing integrated circuits. Aspects of this disclosure can be used for cell library characterization and test pattern generation. Background Technology

[0002] In recent years, the destructive impact of silent data errors (SDEs) (also known as silent data corruption (SDCs)) in data centers has garnered increasing attention within the semiconductor industry. SDEs are elusive and difficult to detect until they impact a specific application. Detection may occur days or months after integrated circuits (ICs) have been deployed in the field. Furthermore, it has been observed that most devices in such setups fail at a very early stage of their deployment, raising questions about the reliability and quality of manufacturing testing.

[0003] While the causes of SDEs can be multifaceted, ranging from test omissions and design margins to design defects, the consensus across the industry is that these causes can be traced back to timing delay issues. Transistor performance can vary depending on software workloads and different operating and environmental conditions (known as the process, voltage, and temperature (PVT) corners), causing some defective behaviors to be captured only under certain conditions. Defective behaviors can also occur later in the chip's lifespan. In this case, silicon degradation due to aging effects manifests as additional delay-related failures. For example, aging effects caused by negative bias temperature instability (NBTI) and hot carrier injection (HCI) degrade circuit performance and cause reliability issues. Furthermore, the effects of aging on transistors are not uniform, making SDE screening more difficult.

[0004] Research into the root causes of SDE, such as isolating defective cores and reverse engineering, is complex and costly. Therefore, there is an urgent need for improved test generation and design-for-testability (DFT) techniques to enable the detection of timing-dependent defects leading to SDE before defective chips are shipped and deployed. The impact of different environmental conditions and lifetime degradation on cell propagation delays should also be considered during test generation.

[0005] Timing-related defects can exist in at least two ways. The first type of test generation program detects small-latency defects by propagating transitions through the fault location using the longest possible path. For example, Timing-Aware Unit-Aware Testing (TA CAT) Automated Test Pattern Generation (ATPG) generates tests for small-latency defects by propagating transitions through long paths with minimum relaxation. The second type of test generation program uses various criteria to directly select a subset of longest-path delay faults as the target for test generation. Summary of the Invention

[0006] One object of this disclosure is to provide a method for characterizing a cell library using single-input switching stimuli and multi-input switching stimuli.

[0007] The foregoing and other objectives are achieved by the features of the independent claim. Other implementations are apparent from the dependent claims, the description, and the drawings.

[0008] A method is provided for a computer implementation of characterizing logic cells in an integrated circuit based on propagation delay to address delay defects in the integrated circuit. The method includes: a) identifying input pins and output pins as selected input pins and output pins; b) evaluating a model of the logic cell for each input signal pair from a set comprising input signal pairs, each input signal including an input value for each input pin, the evaluation including: evaluating the logic cell based on a first input signal of the input signal pair in a first loop of two loops, and evaluating the logic cell based on a second input signal of the input signal pair in a second loop of two loops; c) identifying a subset of the set based on the evaluation; and d) determining a propagation delay for each pair in the subset. For each pair in the subset, the output value for the selected output pin jumps from a first value at the beginning of the first loop to a second value at the end of the second loop, the second value being different from the first value; and the jump of the input value for the selected input pin from the first value to the second value different from the first value is propagated to the selected output pin during the first loop or the second loop, such that the output value at the end of the second loop depends on the jump of the input value.

[0009] The method according to the first aspect enables the identification of propagation delays for each double-loop stimulus that propagates a transition from the on-path input to the output without masking the input. The method according to the first aspect also provides improved detection of timing-dependent defects.

[0010] In a first implementation, the method includes normalizing the propagation delay for each pair by using the minimum propagation delay for the selected input pin and the selected output pin.

[0011] In a second implementation, the method includes determining the maximum propagation delay of a logic cell based on the maximum propagation delay for one or more pairs of input and output pins.

[0012] In the third implementation, at least one input signal pair in the set includes a first input signal having an input value that is different from the input value of a second input signal for at least one input pin that is not the selected input pin.

[0013] In the fourth implementation, the propagation delay includes the time it takes for the transition of the input value for the selected input pin to propagate to the selected output pin.

[0014] These and other aspects of this disclosure are apparent from the embodiments described below. Attached Figure Description

[0015] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0016] Figure 1 A schematic diagram of a circuit based on an example is shown.

[0017] Figure 2 A flowchart of a method 200 for determining propagation delay in a logic unit, based on an example, is shown.

[0018] Figure 3 A schematic diagram of a circuit based on an example is shown.

[0019] Figure 4 A flowchart illustrating a method for generating a composite database for a cell library, based on an example, is shown.

[0020] Figure 5 A flowchart is shown, based on an example, of a method for extracting the path with the longest delay through an integrated circuit.

[0021] Figure 6 A flowchart is shown illustrating a method for generating timing verification tests based on an example.

[0022] Figure 7 A schematic diagram of a circuit based on an example is shown.

[0023] Figure 8 A flowchart of a method for generating automated test patterns, based on an example, is shown.

[0024] Figure 9 This is a schematic representation of a data processing system suitable for implementing embodiments of the present disclosure. Detailed Implementation

[0025] Example embodiments are described below in sufficient detail to enable those skilled in the art to embody and implement the systems and processes described herein. It is important to understand that embodiments may be provided in many alternative forms and should not be construed as limited to the examples set forth herein.

[0026] Therefore, while embodiments may be modified in various ways and take various alternative forms, specific embodiments thereof are shown in the accompanying drawings and described in detail below by way of example. There is no intention to limit oneself to the particular forms disclosed. Rather, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Throughout the drawings and detailed description, elements of the exemplary embodiments are consistently indicated by the same reference numerals as needed.

[0027] The terminology used to describe embodiments herein is not intended to be limiting. The articles “a,” “an,” and “the” are singular because they refer to a single thing; however, their use in the singular form herein should not preclude the existence of more than one thing. In other words, unless the context clearly indicates otherwise, an element referred to as singular may be one or more. The terms “comprising,” “including,” “containing,” and / or “comprising” as used herein specify the presence of the said feature, item, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0028] The reference to "design" in this document encompasses data describing microdevices, such as integrated circuit devices or system-on-a-chip (SoC) devices. However, "design" can also refer to an individual layer or portion of a layer of, for example, an integrated circuit device. The reference to "cell" or "logic cell" in this document refers to logic circuitry within a design. "Input mode" or "stimulus" includes input signals to a cell, where the signals include input values ​​for each input pin of the cell. The term "cell library" refers to a collection of logic cells used in a design. "Cell instance" refers to a specific instance of a logic cell in an actual integrated circuit. "Propagation delay" refers to a measure of the time it takes for a change in the input value at a target input pin of a cell to propagate to a target output pin of the cell.

[0029] Unless otherwise specified, all terms used herein, including technical and scientific terms, shall be interpreted in accordance with the conventions of the field. Unless expressly stated otherwise, commonly used terms shall also be interpreted in accordance with the conventions of the relevant field, rather than in an idealized or overly formal sense.

[0030] The methods and systems described in this paper provide a approach to test generation for timing-dependent defects, referred to as timing verification test generation. Timing verification test generation offers versatility, allowing the ATPG tool to consider cell and interconnect delays (collectively referred to herein as PVTA combinations) under different PVT corners and aging effects, targeting delay defects via the longest path under single-input switching (SIS) or multiple-input switching (MIS) conditions. This versatility ensures that the timing of the critical path is tested under every condition.

[0031] The timing verification test generation has several components. Characterization of the library cells used in the design is performed under different operating conditions and aging effects. For each cell, the cell characterization procedure exhaustively analyzes all double-loop input stimuli to find the stimuli that can propagate the transition through the cell, and their propagation delay. This ensures that timing information is available to support test generation with the maximum path delay.

[0032] The library characterizes the database and combines timing information obtained from a second source of timing information, such as a Standard Delay Format (SDF) file. An SDF file is a data file that includes timing information specific to the design. The SDF file provides the timing behavior and interconnect delays for the cell instances used in the design. In an SDF, two instances of the same cell can have different timing information, depending on design characteristics such as load capacitance. However, an SDF only considers single-input switching when characterizing delays. It does not account for the case where multiple inputs of a cell switch together within the same clock cycle.

[0033] Users who generate timing verification tests have the freedom to obtain one or more SDF files suitable for their applications. SDF files can be generated corresponding to each PVT corner. The program used for timing verification test generation utilizes timing information to enhance the SDF data, which is obtained by performing cell-level delay characterization against the standard cell library used in the design. The combined database includes timing information for cases where multiple inputs switch simultaneously, as well as the effects of operating conditions and aging.

[0034] In timing verification test generation, latency calculations are applied using a combined timing database to extract the path with the maximum latency. The path extraction process begins with dual-loop cell-aware defects, referred to as cell-aware test 2 timeframe defects or CAT-2TF defects. The CAT-2TF defect model is a model of latency defects occurring in silicon and is based on actual defects occurring inside transistors within standard cells. For each CAT-2TF defect, the longest path that can detect the CAT-2TF defect is obtained. This creates a superset of path latency faults, and a subset including the longest path is selected for test generation based on this superset.

[0035] Given the longest path associated with a CAT-2TF defect, a conventional test generation procedure is first used to generate a test cube that satisfies the basic propagation conditions for path-delay faults. The test cube includes a partially specified input vector, where the specified values ​​are sufficient to detect a specific fault or set of faults. The test cube is then expanded using a timing database to create one or more tests that maximize the path delay under different conditions. This involves optimizing the process to satisfy additional propagation conditions for cells along the path. The process preferentially selects the cells and their input stimuli that contribute the most to the path delay.

[0036] The method described in this paper can be used to enable the application of tests generated by the timing verification ATPG in addition to the standard 2-cycle mode. This allows for the evaluation of the impact of timing verification testing on the detection of additional timing-related defects that might be missed from other manufacturing tests. Library representation

[0037] According to the example described herein, library characterization is performed on each cell in the cell library to determine the propagation delay. In the first step, all valid double-cycle stimuli are identified for the target input / output pins of the cell. Double-cycle stimuli consist of two input modes to the cell. A stimulus is considered valid if it satisfies both of the following conditions relative to the target input and output pins:

[0038] Observation condition: There is a jump at the target output pin.

[0039] Propagation condition: A transition from the target input pin propagates to the output pin without being masked by a transition from any other input value.

[0040] In this paper, the target input pin is referred to as the on-path input, and other input pins are referred to as off-path inputs.

[0041] Effective stimuli are classified into two types: Single-Input Switching (SIS) and Multiple-Input Switching (MIS).

[0042] SIS (Single-Input Switching): Only inputs on the path carry the transition. Inputs outside the path retain a constant logic value. For one-sided and primitive gate types (such as AND / NAND, OR / NOR gates), the constant logic value is the same as its non-controllable value. As for complex units (such as And-Or-Inverters or XOR / XNOR), there is no fixed non-controllable value, and the constant logic value changes with the stimulus.

[0043] MIS (Multiple Input Switching): Inputs outside the path can change while simultaneously satisfying the propagation condition. To check if the propagation condition is satisfied, inputs on the path are held at their initial values, while other inputs are allowed to change. If the output does not change until an input on the path changes, the propagation condition is satisfied.

[0044] Figure 1 This is a circuit diagram illustrating a logic unit 100 according to an example. Unit 100 is an AND gate having three input pins 110, 120, and 130 and a single output pin 140. An input pattern, including input values ​​to each of the input pins 110, 120, and 130, can be applied to unit 100, and an output signal is observed at output pin 140. Figure 1 In the example shown, input pin 110 is an on-path input, and output pin 140 is an on-path output. Input pins 120 and 130 are off-path inputs.

[0045] Table 1 below illustrates the effective dual-cycle MIS excitation for cell 100. In Table 1, the first row shows the values ​​in the first cycle (referred to herein as the emit cycle), and the third row shows the values ​​in the second cycle (referred to herein as the capture cycle). The second row shows the values ​​when the off-path inputs 120 and 130 have changed, but the on-path input 110 has not changed. The rising transition of the on-path input 110 determines the transition at output 140. In other words, the rising transitions on the off-path inputs 120 and 130 do not affect the propagation path from the on-path input 110 to the output 140. Table 1

[0046] exist Figure 1 In the example shown, the propagation condition will not be met if the input signals to inputs 110, 120, and 130 undergo a falling transition. In this case, output 140 transitions after inputs 120 and 130 have changed, and the change in input 110 along the path does not propagate to output 140.

[0047] Figure 2 A flowchart of a method 200 for determining propagation delay in a cell is shown. Method 200 can be repeated for each input / output pin pair, treating each pair as an input and output on a path. Method 200 can be implemented in conjunction with other methods and systems described herein.

[0048] At block 210, method 200 includes identifying input pins and output pins as inputs and outputs on a path. At block 220, the method includes evaluating a model of a logic cell for each input pattern pair from a set comprising input pattern pairs. The model may be a representation of the circuit as an analog circuit simulation model. Each input pattern includes an input value for each input pin. The evaluation includes: evaluating the logic cell based on a first input pattern in a first loop of two loops, and evaluating the logic cell based on a second input pattern in the input pattern pair in a second loop of two loops.

[0049] At box 230, the method includes identifying a subset of the set of input patterns. For each pair in the subset, the output value for the output on the path jumps from a first value at the beginning of the first loop to a second value at the end of the second loop, thus satisfying the observation condition that the second value is different from the first value. Furthermore, for each pair in the subset, the jump of the input value for the input on the path from the first value to a second value different from the first value is propagated to the output on the path during either the first or second loop, such that the output value at the end of the second loop depends on the jump of the input value. Therefore, for each pair in the identified subset, the propagation condition is satisfied.

[0050] At box 240, the method includes determining the propagation delay for each input pattern pair in the subset. The propagation delay can be calculated using SPICE (Special Programming Interface) software or similar software. Method 200 may repeat the rising and falling transitions of the inputs along the path.

[0051] The maximum propagation delay of the effective double-cycle excitation for a cell can be determined by calculating the propagation delay according to method 200. This method can be applied to each cell in the cell library to obtain a complete library characterization.

[0052] Figure 3 A circuit diagram of a logic unit 300 according to an example is shown. Figure 3 The unit 300 shown in the diagram is an AND-OR-INVERTER, comprising two dual-input AND gates 310 and 320, followed by a NOR gate 330. Figure 3 In the diagram, the on-path input is pin 340 of the AND gate 310. The remaining input pins 350, 360, and 370 are off-path inputs, and the single output pin 380 is the on-path output.

[0053] Table 2 below shows all activators with a descent transition propagating from input 340 to output 380 along the path, sorted from maximum to minimum propagation delay. In Table 2, the propagation delay is normalized based on the minimum delay. Each activation in the second column of Table 2 is in the format... <abcd>This is indicated by the fact that each of A, B, C, and D corresponding to input pins 340, 350, 360, and 370 is F for a falling transition, R for a rising transition, or a constant 0 / 1 value. Table 2

[0054] Inspired by SIS <f100>Compared to the minimum case caused by MIS excitation <f1rf>The maximum propagation delay introduced was more than 40% higher. Significant delay differences also existed between different SIS stimuli; for example, the SIS stimuli ranked 4th... <f101>This can introduce a delay of approximately 35% more than the minimum delay. The results indicate that timing information related to MIS excitation should not be ignored, and relying on SIS information may not result in the maximum path delay.

[0055] In another test, the maximum propagation delay d for any stimulus was... max With minimum propagation delay d for any stimulus min percentage difference between p diff Measurements were taken for all NOR cells in the commercially available cell library, as well as all AND-OR-INVERTER and AND-OR cells. Considering all possible excitations and inputs and outputs along the path, MIS excitations were observed to cause the maximum propagation delay in NOR cells in 80% of cases, and the maximum delay was observed for NOR cells. p diff It is 5%. In AND-OR-INVERTER and AND-OR units, MIS excitation causes the maximum propagation delay in 81% of cases, and the maximum... p diff It is 60%. In addition, approximately 30% of the MIS excitation in the AND-OR-INVERTER and AND-OR cells causes a propagation delay that is 10% or longer than the minimum delay.

[0056] Considering all library characterization results, two trends were observed: First, the maximum delay difference is higher for more complex cells. Second, in most cases, MIS excitation leads to the maximum propagation delay.

[0057] Method 200 can be repeated for each cell in the cell library to obtain a library characterization. However, the timing information is the same for each instance of a cell in the actual design. The SDF file provides timing information for each instance of a cell in the design. Instances of the same cell from the same library may have different timing information in the SDF file based on instance-specific characteristics such as load capacitance and drive strength. However, the SDF file for the design has equal delays for different SIS stimuli associated with the inputs and outputs on the same path as the instance. Furthermore, as previously mentioned, the SDF file does not include MIS stimuli.

[0058] Figure 4 This is a block diagram illustrating method 400 for generating a combined database. The combined database utilizes both instance-related information from SDF files and extensive data provided by the cell library characterization. For each instance, all stimuli from both sources are considered. Method 400 can be used in conjunction with other methods described herein, and in particular method 200.

[0059] At box 410, method 400 includes accessing a cell library, which includes multiple cells for a design. At box 420, method 400 includes determining, for each cell in the cell library, the propagation delay for each pair of input and output pins for the cell. According to the example, the propagation delay can be determined using method 200 previously described. At box 430, the method includes accessing a Standard Delay Format (SDF) file for each instance of each cell, the SDF file including timing information for the instance. At box 440, method 400 includes combining the timing information from the SDF with the propagation delay for the cell to obtain a combined database. According to the example, combining the timing information with the propagation delay includes adjusting the propagation delay based on the timing information to obtain the propagation delay for the cell instance.

[0060] In some examples, a timing information value from the timing information values ​​in the SDF file can be used as a baseline, and the propagation delay from the library characterization is adjusted to the SDF baseline. When multiple SDF files are provided to cover different PVTA combinations, the adjustment can be repeated for each combination. This will be applied when there is no aging effect. In the case of aging effects in PVT combinations, the SDF file corresponding to the PVT corner can be used, and the cell characterization data for the PVTA combination can be combined with the data from the SDF files.

[0061] As in the example, the input and output pairs on each path of the cell are considered separately for tuning. Taking into account the propagation delay obtained from the cell characterization, all SIS and MIS stimuli are sorted from maximum propagation delay to minimum propagation delay: d 0 , d 1 , d 2 , ..., d n-1 Let the minimum SIS delay be... d i Considering the SDF file, let the corresponding delay for the same SIS stimulus be... r 0 When the minimum SIS stimulus is added to the SDF data, its latency is reduced by... r 0 / d i To adjust. The same adjustment can be applied to all stimuli. Therefore, d j use d j r 0 / d i To replace it.

[0062] Table 3 below illustrates examples for 3-input AND units (such as in...). Figure 1 The AND unit 100 shown in Table 3 is an adjustment of a 3-input AND unit with input 110 and output 140 on the path. The first column of Table 3 is an index number for the different stimuli considered. The second column indicates the stimuli. The third column indicates the type of stimuli, SIS or MIS. The fourth column provides the propagation delay (in arbitrary units) from the library representation. The fifth column includes the adjusted delay. Table 3

[0063] The third stimulus is the only SIS stimulus and is selected as the baseline SIS stimulus for performing delay adjustment. The timing information obtained from the SDF file for the SIS stimulus is... r 0 .for 1≤j≤4 , No. j The adjusted delay of the incentive is d j r 0 / d i The adjusted delay of the third incentive equals r 0 (Values ​​from the SDF file), and all other delays are adjusted based on the delay ratio. Longest path extraction

[0064] Figure 5 A block diagram of a method 500 for extracting the path with the longest delay time through an integrated circuit is shown. Method 500 can be used in conjunction with other methods and systems described herein.

[0065] At block 510, method 500 includes obtaining a dataset for the integrated circuit. The dataset includes the maximum arrival time and maximum propagation delay for each pin in the integrated circuit and is generated based on a static path delay calculation using data from a combination database (i.e., maximum propagation delay data for each cell), obtained from an evaluation of each cell for a dual-loop input stimulus. The static path delay can be determined by adding the maximum propagation delay for each cell in the design to the interconnect delay for the lines along the path. This calculation does not attempt to justify any value. Using the combination database, it uses the stimulus with the maximum propagation delay for each cell without checking whether the stimulus can be justified.

[0066] At block 520, method 500 includes selecting a logic cell in an integrated circuit. At block 530, method 500 includes identifying the longest reach path from a starting point in the integrated circuit to the output pin O of the selected logic cell, based on a dataset. The starting point can be a main input or a scan cell of the integrated circuit.

[0067] In the example, identifying the longest reach path starting from output pin O includes identifying the path from output pin O to input pin I1 of the selected logic unit, path a) will... Maximize, where It is an input pin. I 1 The maximum arrival time, and From I 1 The maximum propagation delay to O, and path b) is associated with a transition on output O. After an input pin is selected, the output pin that drives it is identified, and the process is repeated for the logic cell associated with that output pin. This is repeated until a scan cell or main input is reached.

[0068] At block 540, method 500 includes identifying the longest propagation path from the input pin I of the selected logic cell to the end point in the integrated circuit. The end point can be the main output or a scan cell of the integrated circuit.

[0069] In the example, identifying the longest propagation path starting from input pin I includes identifying the path from input pin I to the output pin O1 of the selected logic unit, path a) will... Maximize, where It is an input pin. I The maximum propagation time, and From I The maximum propagation delay to O1, and b) the output O1 is associated with a transition on input I. After the output pin that meets these conditions is identified, the process repeats until the scan cell or main output is reached. Depending on the cell type of the instance, both rising and falling transitions can be considered for the output to maximize the propagation delay.

[0070] At box 550, the longest path through the selected logic is extracted based on the identified longest arrival path and longest propagation path. Timing verification test generation

[0071] Figure 6 This is a block diagram of a method for generating timing verification tests based on an example. Method 600 can be implemented in conjunction with other methods and systems described herein. Method 600 depicts the generation of timing verification tests for a single PVTA combination.

[0072] At block 610, method 600 includes obtaining a design for an integrated circuit.

[0073] At box 620, method 600 includes, for example, using method 400 previously described, obtaining a combined database of propagation delays for each instance of each cell in the cell library of the design.

[0074] At box 630, the static path delay for each pin in the design is determined based on a combined database according to the maximum arrival time at the pin and the propagation delay from the pin.

[0075] At box 640, relaxed CAT-2TF defects below the user-defined threshold are identified and stored in a list. Relaxation refers to the difference between the actual clock cycle and the propagation delay of the path.

[0076] At box 650, the longest path through each CAT-2TF defect in the list is extracted, for example, using the previously described method 500. In some cases, two different CAT-2TF defects in the list may result in the same longest path. To avoid duplicate paths in the set of extracted paths, each newly extracted path can be compared with an earlier extracted path and checked to determine if the path has already been extracted. This check can be accelerated by associating a unique numeric identifier with each path.

[0077] At box 660, the temporal verification ATPG is applied to each extracted path for the CAT-2TF defect.

[0078] The temporal verification ATPG can be applied to each extracted path for the CAT-2TF defect. Given a path... p The path delay ATPG framework exports by targeting p The assignments required for the strong non-robust test begin. These assignments include transitions at the source of the path and non-control values ​​on each path's external input during the second clock cycle of the test. For p The assignment set is represented as A(p) Path delay ATPG is used to target p Generate satisfying A(p) The test cube is assigned values ​​in the model. Once the test cube is generated, arrival time analysis can be performed against on-path inputs and off-path inputs to determine, for each cell, whether only SIS stimulus or both SIS and MIS stimulus are required. This is followed by process optimization, which is applied to maximize the path delay. Additional values ​​are based on the values ​​along the path. p The input to its path has a cell with an unspecified value and is specified.

[0079] For each unit, search the combinational timing database for... A(p) The incentives are assigned consistent values. Incentives are sorted in descending order of their contribution to the path's delay. Taking into account the incentives in this order, the incentive at the top of the list is added. A(p) And the test generation attempt is based on A(p) To generate new test cubes.

[0080] Figure 7 The path through circuit 700 is depicted according to an example. p Circuit 700 includes a two-input OR gate 710, a two-input NAND gate 720, and two three-input AND gates 730. Path p Indicated by arrows. Figure 7 Depicting the path p The transition at the source and the non-control values ​​on each path external input in the second clock cycle. Satisfying these assignments leaves unspecified values ​​on the path external inputs at OR gate 710 and AND gate 730, as determined by... Figure 7 The variable X in the code indicates this. This determines the path. p possible assignment set A(p) With assignment set A(p) The cell excitations with consistent assignments are depicted in Table 4 below. For each cell, the excitations in Table 4 are shown in descending order of delay in the fourth column. Table 4

[0081] Even if unspecified values ​​are filled randomly, the AND gate 730 will still have a delay of 6 units—compared to... A(p) Consistent minimum delay. In Table 4, the fifth column indicates the minimum delay for each unit. A(p) Additional latency above the consistent minimum latency. Table 5 below shows a reordering of Table 4 based on the additional latency indicated in the fifth column of Table 4. Table 5

[0082] During test generation, the stimuli are ordered according to the sequence in Table 5. Therefore, the additional arguments will first target the possible MIS stimuli. <rrr>Consider the pathout input of the AND gate 730. It will then consider the input with excitation.<F F> OR Gate 710.

[0083] As the new test cube is calculated and A(p) Updated, with A(p) Consistent stimuli are found and ordered. Backtracking constraints are used for each stimulus and each unit to limit runtime. A(p) Test generation terminates when the list of consistent and unconsidered incentives is empty.

[0084] Figure 8 A method 800 for timing verification of ATPG is described according to an example. Method 800 can be used in conjunction with other methods and systems described herein.

[0085] At box 810, method 800 includes exporting the assignment collection. A(p) To be used to perform path-based operations p Strong non-robustness test.

[0086] At box 820, method 800 includes targeting A(p) Generate a test cube. If the test cube cannot be targeted... A (p) If generated, method 800 terminates. Let S Indicates and A(p) A consistent set of incentives.

[0087] At box 830, method 800 includes an excitation with the lowest latency for each cell identifier S. s 0 And for each excitation s of the cells in S i Determine incentives s i and s 0 The difference between x i .

[0088] At box 840, method 800 includes, based on the determined difference, ... S The incentives are sorted.

[0089] At box 850, method 800 includes repeating until the set is complete. S Empty: a) Select S Incentives at the top s i And from S Remove from s i b) will s i Add to A(p) ; and c) targeting A(p) Generate a new test cube. If a new test cube is generated, then from... S Remove from and A(p) All the incentives for conflict. Otherwise, from A(p) Remove from s i At the end of method 800, the resulting test cube is for the path. p The new test cube.

[0090] exist Figures 6 to 8 The timing verification test generation procedure described herein can be repeated for multiple PVTA combinations of a design to create a superset of timing verification test patterns, allowing the design to be tested more comprehensively. Each PVTA combination requires a separate SDF file and a library representation executed for that combination. Some patterns can be shared across different PVTA combinations. When the DUT (Device Under Test) is subjected to a specific PVTA combination on the ATE (Automatic Test Equipment), the corresponding subset of timing verification test patterns is applied to detect defects that might have been missed from other PVTA combinations.

[0091] The method described in this paper can be applied in conjunction with other manufacturing tests and unit-aware tests. Defects detected by timing verification tests are unique and cannot be detected by other tests. Units that fail timing verification tests can be analyzed for diagnostic purposes to determine the cause of the failure.

[0092] Figure 9 An example of a data processing system that can implement embodiments of the present disclosure to perform, for example, the methods of the embodiments described herein. The data processing system 900 includes a processor 910 connected to a local system bus 920. The local system bus connects the processor to main memory 930 and a graphics display adapter 940, which can be connected to a display 950. The data processing system can communicate with other systems via a wireless user interface adapter connected to the local system bus 920 or via a wired network, such as to a local area network. Additional memory 960 may also be connected via the local system bus 920.

[0093] Suitable adapters for other peripheral devices, such as keyboard 980 and mouse 990 or other pointing devices, such as wireless user interface adapter 970, allow the user to provide input to the data processing system. Other peripheral devices may include one or more I / O controllers, such as USB controllers, Bluetooth controllers, and / or dedicated audio controllers (connected to speakers and / or microphones). It should also be understood that various peripherals can be connected to the USB controller (via various USB ports), including input devices (e.g., keyboard, mouse, touchscreen, trackball, camera, microphone, scanner), output devices (e.g., printer, speaker), or any other type of device operable to provide input to the data processing system or receive output from the data processing system.

[0094] Furthermore, it should be understood that many devices referred to as input or output devices can both provide input and receive output in communication with the data processing system. Additionally, it should be understood that other peripheral hardware connected to the I / O controller can include any type of device, machine, or component configured to communicate with the data processing system.

[0095] The operating system included in the data processing system enables the output from the system to be displayed on a monitor to the user and allows the user to interact with the system. Examples of operating systems that can be used in a data processing system include Microsoft Windows. TM Linux TM UNIX TM iOS TM and Android TM operating system.

[0096] Furthermore, it should be understood that the data processing system 900 can be implemented in a network environment, a distributed system environment, a virtual machine in a virtual machine architecture, and / or a cloud environment. For example, the processor and associated components may correspond to a virtual machine running in a virtual machine environment on one or more servers. Examples of virtual machine architectures include VMware ESCi, Microsoft Hyper-V, Xen, and KVM.

[0097] Those skilled in the art will understand that the hardware depicted for the data processing system 900 can vary for a particular implementation. For example, the data processing system 900 in this example can correspond to a computer, workstation, and / or server. However, it should be understood that alternative embodiments of the data processing system can be configured with corresponding or alternative components, such as a mobile phone, tablet computer, controller board, or any other system operable to process data and perform the functions and features described herein associated with the operation of the data processing system, computer, processor, and / or controller discussed herein. The examples depicted are provided for illustrative purposes only and are not intended to imply any architectural limitations of this disclosure.

[0098] Data processing system 900 can be connected to a network (not part of data processing system 900), which can be any public or private data processing system network or combination of networks as known to those skilled in the art, including the Internet. Data processing system 900 can communicate via the network with one or more other data processing systems (again not part of data processing system 900), such as servers. However, alternative data processing systems can correspond to multiple data processing systems implemented as part of a distributed system, wherein processors associated with several data processing systems can communicate via one or more network connections and can collectively perform tasks described as being performed by a single data processing system. Therefore, it will be understood that, when referring to a data processing system, such a system can be implemented across several data processing systems organized within a distributed system that communicates with each other via a network.

[0099] The data processing system 900 is adapted to perform methods according to the embodiments described herein. For example, a keyboard 980 and a mouse 990 may serve as user input devices for receiving information from a user, a processor 910 may be adapted to perform the steps of the method, and a display 950 may be adapted to display a specific view to the user. A computer product including instructions may be provided that, when executed on a computer such as the data processing system 900, cause the computer to perform the steps of the methods of the embodiments described above.

[0100] This disclosure is based on flowcharts and / or block diagrams of methods, apparatus, and systems as exemplified by this disclosure. While the flowcharts described above illustrate a particular execution sequence, the execution sequence may differ from the depicted sequence. Boxes described in one flowchart may be combined with boxes from another flowchart. In some examples, some boxes in the flowcharts may not be required, and / or additional boxes may be added.

[0101] This disclosure may be embodied in other specific arrangements and / or methods. The described embodiments should be considered illustrative in all respects and not restrictive. In particular, the scope of this disclosure is indicated by the appended claims rather than by the description and drawings herein. All modifications falling within the meaning and equivalent scope of the claims should be covered within their scope.< / rrr> < / abcd>

Claims

1. A computer-implemented method for characterizing logic cells in an integrated circuit based on propagation delay to address delay defects in the integrated circuit, the logic cells comprising at least one input pin and at least one output pin, the computer-implemented method comprising: a) Identify the input pin and the output pin as the selected input pin and the selected output pin; b) Evaluate the model of the logic unit for each input signal pair from a set of input signal pairs, each input signal including an input value for each input pin, the evaluation comprising: in a first loop of two loops, evaluating the logic unit based on a first input signal of the input signal pair, and in a second loop of the two loops, evaluating the logic unit based on a second input signal of the input signal pair; c) Based on the evaluation, identify a subset of the set; and d) For each pair in the subset, determine the propagation delay; For each pair in the subset: The output value for the selected output pin jumps from a first value at the beginning of the first cycle to a second value at the end of the second cycle, the second value being different from the first value; and A transition of the input value to the selected input pin from a first value to a second value different from the first value is propagated to the selected output pin during either the first or the second cycle, such that the output value at the end of the second cycle depends on the transition of the input value.

2. The computer-implemented method according to claim 1 further includes: The propagation delay for each pair is normalized by the minimum propagation delay for the selected input pin and the selected output pin.

3. The computer-implemented method according to claim 1 further includes: The maximum propagation delay of the logic unit is determined based on the maximum propagation delay for one or more pairs of input and output pins.

4. The computer-implemented method of claim 1, wherein at least one input signal pair in the set of input signal pairs in the set includes a first input signal having an input value that is different from the input value of the second input signal for at least one input pin that is not the selected input pin.

5. The computer-implemented method of claim 1, wherein the propagation delay includes the time taken for the transition of the input value for the selected input pin to propagate to the selected output pin.

6. A computer-implemented method, comprising: Access the cell library, which includes multiple logic cells for integrated circuits. For each logic unit in the unit library, the propagation delay of one or more pairs of input pins and output pins for the logic unit is determined based on the method according to claim 1.

7. The computer-implemented method according to claim 6, further comprising: Access the stored data file, which includes interconnect delay information and timing information for instances of logic cells in the integrated circuit; as well as Based on the timing information, the propagation delay of one or more pairs of input pins and output pins of the logic unit is adjusted to obtain the propagation delay of each input pin and output pin of the instance.

8. The computer-implemented method of claim 7, wherein the timing information depends on the characteristics of the instance.

9. The computer-implemented method according to claim 8, wherein the characteristics include load capacitance and drive strength.

10. The computer-implemented method of claim 9, wherein the stored file is associated with a set of operating parameters and environmental parameters for the integrated circuit.

11. The computer-implemented method of claim 10, wherein each of the operating parameters or environmental parameters in the set of operating parameters and environmental parameters includes process, voltage, temperature, or aging parameters.

12. The computer-implemented method according to claim 7, further comprising: Determine the minimum and maximum propagation delays for the given instance.

13. A data processing system, comprising: processor; as well as memory, The memory includes instructions that, when executed by the processor, cause the processor to perform the method according to any one of claims 1 to 12.

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