Inductor reuse technology for amplifiers

Abstract

Certain aspects of this disclosure provide an amplifier. The amplifier typically includes: an active path coupled between an input node and an output node of the amplifier, wherein the active path includes a first transistor coupled to the input node of the amplifier and a first inductor coupled between the first transistor and the output node; and a bypass path coupled between the input node and the output node of the amplifier, the bypass path also including the first inductor.

Description

Cross-reference to related applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 499,682, filed November 1, 2023, entitled “Inductor Reuse Technique for Amplifier,” which has been assigned to the assignee of this application and whose entire contents are incorporated herein by reference. Technical Field

[0002] Certain aspects of this disclosure relate generally to electronic circuits, and more specifically to techniques and apparatus for signal amplification. Background Technology

[0003] Wireless communication devices are widely deployed to provide a variety of communication services, such as telephone, video, data, messaging, broadcasting, and so on. These wireless communication devices can transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including but not limited to 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobile Communications (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, and Wireless Local Area Network (WLAN) RATs (e.g., WiFi).

[0004] A wireless communication network may include multiple base stations capable of supporting communication with multiple mobile stations. A mobile station (MS) may communicate with a base station (BS) via downlink and uplink. A downlink (or forward link) refers to the communication link from the base station to the mobile station, while an uplink (or reverse link) refers to the communication link from the mobile station to the base station. The base station may transmit data and control information to the mobile station on the downlink and / or receive data and control information from the mobile station on the uplink. The base station and / or mobile station may include one or more amplifiers. For example, the base station or mobile station may include a low-noise amplifier (LNA) that amplifies signals received via one or more antennas. Summary of the Invention

[0005] The systems, methods, and apparatuses of this disclosure each have several aspects, none of which are solely responsible for their desired properties. Without limiting the scope of this disclosure as set forth in the following claims, some features will now be briefly discussed. Upon consideration of this discussion, and especially after reading the section entitled “Detailed Description,” it will be understood how the features of this disclosure provide advantages including reduced amplifier area loss and cost.

[0006] Certain aspects of this disclosure provide an amplifier. The amplifier typically includes: an active path coupled between an input node and an output node of the amplifier, wherein the active path includes a first transistor coupled to the input node of the amplifier and a first inductor coupled between the first transistor and the output node; and a bypass path coupled between the input node and the output node of the amplifier, the bypass path including the first inductor.

[0007] Certain aspects of this disclosure provide a method for signal amplification. The method typically includes: receiving a signal at an input node of an amplifier for amplification via the amplifier; amplifying the signal via an active path coupled between the input node and an output node of the amplifier, wherein the active path includes a first transistor coupled to the input node of the amplifier and a first inductor coupled between the first transistor and the output node; and activating a bypass path coupled between the input node and the output node of the amplifier, the bypass path including the first inductor.

[0008] Certain aspects of this disclosure provide a wireless device. The wireless device typically includes one or more antennas; and a low-noise amplifier (LNA) having an input node coupled to the one or more antennas, the LNA including: an active path coupled between the input node and an output node of the LNA, wherein the active path includes a transistor coupled to the input node and an inductor coupled between the transistor and the output node; and a bypass path coupled between the input node and the output node, the bypass path including the inductor.

[0009] To achieve the foregoing and related objectives, one or more aspects include the features fully described below and specifically pointed out in the claims. The following description and drawings illustrate some exemplary features of one or more aspects in detail. However, these features indicate only some of the various ways in which the principles of the various aspects may be employed, and this description is intended to include all such aspects and their equivalents. Attached Figure Description

[0010] To gain a more detailed understanding of the foregoing features of this disclosure, a more specific description, which has been briefly summarized above, can be obtained by referring to various aspects, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and are therefore not to be construed as limiting its scope, as other equally valid aspects may be acknowledged in this description.

[0011] Figure 1This is a diagram of an example wireless communication network in which various aspects of the present disclosure can be practiced.

[0012] Figure 2 It is a block diagram conceptually illustrating the design of an example base station (BS) and user equipment (UE) in which various aspects of this disclosure can be practiced.

[0013] Figure 3 This is a block diagram of an example radio frequency (RF) transceiver in which various aspects of the present disclosure can be practiced.

[0014] Figure 4 An example low-noise amplifier (LNA) is shown.

[0015] Figure 5 An example LNA is illustrated according to certain aspects of this disclosure, wherein at least a portion of the LNA's active path and bypass path are shared.

[0016] Figure 6 An example LNA, comprising a bypass path inductor element magnetically coupled to an active path inductor element, is illustrated according to certain aspects of this disclosure.

[0017] Figure 7A and Figure 7B An inductor structure for implementing an inductor element according to certain aspects of this disclosure is illustrated.

[0018] Figure 8 An inductor structure implemented on two layers of an integrated circuit (IC) according to certain aspects of this disclosure is illustrated.

[0019] Figure 9 This is a flowchart of an example operation for signal amplification based on certain aspects of this disclosure.

[0020] For ease of understanding, the same reference numerals have been used where possible to denote common elements in the figures. It is conceivable that elements disclosed in one aspect may be usefully applied to other aspects without specific description. Detailed Implementation

[0021] Some aspects of this disclosure relate to an amplifier having an active path for signal amplification and a bypass path for bypassing the amplifier. Some aspects involve sharing inductor elements between the active and bypass paths, thereby allowing for reductions in amplifier area losses and cost. In some aspects, the inductor elements of the bypass path may be magnetically coupled to the inductor elements of the active path, thereby allowing for further reductions in bypass path inductance. The inductor elements of the active and bypass paths can be implemented using an inductor element structure located on two layers of an integrated circuit (IC). In some aspects, the amplifier may be a low-noise amplifier (LNA). This disclosure provides an LNA design in which inductor elements for the active LNA path (e.g., providing amplification gain) and the bypass path are incorporated into a single integrated inductor structure. Tuning capacitor elements may also be shared for the active and bypass paths. The inductor element structure saves area by providing an integrated structure for the bypass and active paths while maintaining performance superior to other LNA implementations.

[0022] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be embodied in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided to make this disclosure thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the disclosure herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Furthermore, the scope of this disclosure is intended to cover such apparatus or methods practiced using structures, functionalities, or structures and functionalities other than or different from the various aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of the claims.

[0023] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as preferred or superior to other aspects.

[0024] As used herein, the term “connected to” in various tenses of the verb “connect” can mean that element A is directly connected to element B or that other elements can be connected between element A and element B (i.e., element A and element B are indirectly connected). In the context of electronic components, the term “connected to” can also be used herein to mean that a conductor, trace, or other conductive material is used to electrically connect element A and element B (and any components electrically connected between them).

[0025] Example wireless system

[0026] Figure 1 Example wireless communication network 100 is illustrated in which various aspects of this disclosure may be practiced. For example, wireless communication network 100 may be a new radio (NR) system (e.g., a fifth-generation (5G) NR network), an evolved universal terrestrial radio access (E-UTRA) system (e.g., a fourth-generation (4G) network), a universal mobile telecommunications system (UMTS) (e.g., a second-generation / third-generation (2G / 3G) network), or a code division multiple access (CDMA) system (e.g., a 2G / 3G network), or may be configured to communicate according to IEEE standards such as one or more standards in the 802.11 standard.

[0027] like Figure 1 As illustrated, the wireless communication network 100 may include multiple base stations (BS) 110a-110z (each individually referred to herein as "BS 110" or collectively as "BS 110") and other network entities. BS may also be referred to as access point (AP), evolved Node B (eNodeB or eNB), next-generation Node B (gNodeB or gNB), or some other terminology.

[0028] BS 110 can provide communication coverage for a specific geographic area (sometimes referred to as a "cell"), which can be stationary or mobile depending on the location of the mobile BS. In some examples, BS 110 can use any suitable transport network, interconnected with each other through various types of backhaul interfaces (e.g., direct physical connection, wireless connection, virtual network, etc.) and / or connected to one or more other BSs or network nodes (not shown) in the wireless communication network 100. Figure 1 In the example shown, BS 110a, 110b, and 110c can be macro BSs for macro cells 102a, 102b, and 102c, respectively. BS 110x can be a pico BS for pico cell 102x. BS 110y and 110z can be femto BSs for femto cells 102y and 102z, respectively. A BS can support one or more cells.

[0029] BS 110 communicates with one or more user equipment (UEs) 120a to 120y (each individually referred to herein as "UE 120" or collectively as "UE 120") in the wireless communication network 100. The UE can be fixed or mobile and can also be referred to as a user terminal (UT), mobile station (MS), access terminal, station (STA), client, wireless device, mobile device, or some other term. The user terminal can be a wireless device such as a cellular phone, smartphone, personal digital assistant (PDA), handheld device, wearable device, wireless modem, laptop computer, tablet computer, personal computer, etc.

[0030] BS 110 is considered a transmitting entity for downlink and a receiving entity for uplink. UE 120 is considered a transmitting entity for uplink and a receiving entity for downlink. As used herein, a “transmitting entity” is an independently operating apparatus or device capable of transmitting data via a frequency channel, and a “receiving entity” is an independently operating apparatus or device capable of receiving data via a frequency channel. In the following description, the subscript “dn” denotes downlink, and the subscript “up” denotes uplink. N can be selected. up One UE is used for simultaneous transmission on the uplink, and N UEs can be selected. dn Each UE is used for simultaneous transmission on the downlink. N up It can be equal to or not equal to N dn And N up and N dn It can be a static value or it can be changed for each scheduling interval. Beam control or some other spatial processing techniques can be used at BS 110 and UE 120.

[0031] UEs 120 (e.g., 120x, 120y, etc.) may be distributed throughout the wireless communication network 100, and each UE 120 may be stationary or mobile. The wireless communication network 100 may also include relay stations (e.g., relay station 110r) (also referred to as repeaters, etc.) that receive transmissions of data and / or other information from upstream stations (e.g., BS 110a or UE 120r) and transmit the transmissions of data and / or other information to downstream stations (e.g., UE 120 or BS 110), or relay transmissions between UEs 120 to facilitate communication between devices.

[0032] BS 110 can communicate with one or more UE 120s on both the downlink and uplink at any given time. The downlink (i.e., the forward link) is the communication link from BS 110 to UE 120, while the uplink (i.e., the reverse link) is the communication link from UE 120 to BS 110. UE 120 can also communicate peer-to-peer with another UE 120.

[0033] The wireless communication network 100 can use multiple transmit antennas and multiple receive antennas to transmit data on the downlink and uplink. BS 110 can be equipped with several (N) ap (N) antennas are used to achieve transmit diversity for downlink transmission and / or receive diversity for uplink transmission. A group (N) u Each UE 120 can receive downlink transmissions and send uplink transmissions. Each UE 120 can send user-specific data to and / or receive user-specific data from the BS 110. Typically, each UE 120 may be equipped with one or more antennas. u Each UE 120 can have the same or different number of antennas.

[0034] The wireless communication network 100 can be a time-division duplex (TDD) system or a frequency-division duplex (FDD) system. In a TDD system, the downlink and uplink share the same frequency band. In an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 can also utilize a single carrier or multiple carriers for transmission. Each UE 120 can be equipped with a single antenna (e.g., to reduce cost) or multiple antennas (e.g., where additional cost can be supported).

[0035] Network controller 130 (sometimes referred to as a "system controller") can communicate with a group of BS 110s and provide coordination and control (e.g., via backhaul) for these BS 110s. In some cases (e.g., in a 5G NR system), network controller 130 may include centralized units (CUs) and / or distributed units (DUs). In some aspects, network controller 130 can communicate with core network 132 (e.g., a 5G core network (5GC)) that provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, unified data management, application functions, network openness functions, network repository functions, network slice selection functions, etc.

[0036] In certain aspects of this disclosure, BS 110 and / or UE 120 may include a low-noise amplifier (LNA) implemented using active and bypass paths with shared inductance elements, as described in more detail herein.

[0037] Figure 2 Examples are given of aspects in which this disclosure may be implemented (e.g., from...). Figure 1 Example components of wireless communication network 100 (BS 110a and UE 120a).

[0038] On the downlink, at BS 110a, the transmitting processor 220 can receive data from data source 212, control information from controller / processor 240, and / or other data (e.g., from scheduler 244). Various types of data can be transmitted on different transport channels. For example, control information can be designated for the Physical Broadcast Channel (PBCH), Physical Control Format Indicator Channel (PCFICH), Physical Hybrid Automatic Repeat Request (HARQ) Indicator Channel (PHICH), Physical Downlink Control Channel (PDCCH), Group Common PDCCH (GC PDCCH), etc. Data can be designated for the Physical Downlink Shared Channel (PDSCH), etc. The Media Access Control (MAC)-Control Element (MAC-CE) is a MAC layer communication structure that can be used for exchanging control commands between wireless nodes. The MAC-CE can be carried in shared channels such as PDSCH, Physical Uplink Shared Channel (PUSCH), or Physical Sidelink Shared Channel (PSSCH).

[0039] Processor 220 can process (e.g., encode and symbol map) data and control information to obtain data symbols and control symbols, respectively. Transmitter processor 220 can also generate reference symbols such as those for primary synchronization signal (PSS), secondary synchronization signal (SSS), PBCH demodulation reference signal (DMRS), and channel state information reference signal (CSI-RS).

[0040] The transmit (TX) multiple-input multiple-output (MIMO) processor 230 can perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, and / or reference symbols where applicable, and can provide the output symbol stream to the modulators (MODs) in transceivers 232a-232t. Each modulator 232a-232t in the transceivers can process its own output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each transceiver 232a-232t can further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The downlink signal from transceivers 232a-232t can be transmitted via antennas 234a-234t respectively.

[0041] At UE 120a, antennas 252a-252r can receive downlink signals from BS 110a and can provide the received signals to transceivers 254a-254r respectively. Transceivers 254a-254r can adjust (e.g., filter, amplify, downconvert, and digitize) the corresponding received signals to obtain input samples. Each demodulator (DEMOD) in transceivers 232a-232t can further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. MIMO detector 256 can obtain the received symbols from all demodulators in transceivers 254a-254r, perform MIMO detection on the received symbols (where applicable), and provide the detected symbols. Receiver processor 258 can process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide the decoded data for UE 120a to data sink 260, and provide the decoded control information to controller / processor 280.

[0042] On the uplink, at UE 120a, the transmit processor 264 can receive and process data from data source 262 (e.g., for the Physical Uplink Shared Channel (PUSCH)) and control information from controller / processor 280 (e.g., for the Physical Uplink Control Channel (PUCCH)). The transmit processor 264 can also generate reference symbols for reference signals (e.g., for the Sounding Reference Signal (SRS)). Symbols from the transmit processor 264 can be pre-decoded (if applicable) by the TX MIMO processor 266, further processed by modulators (MODs) in transceivers 254a to 254r (e.g., for Single Carrier Frequency Division Multiplexing (SC-FDM), etc.), and transmitted to BS 110a. At BS 110a, the uplink signal from UE 120a can be received by antenna 234, processed by demodulators in transceivers 232a to 232t, detected by MIMO detector 236 (if applicable), and further processed by receiver processor 238 to obtain decoded data and control information transmitted by UE 120a. Receiver processor 238 can provide the decoded data to data sink 239 and the decoded control information to controller / processor 240.

[0043] Memory 242 and 282 can store data and program code for BS 110a and UE 120a, respectively. Memory 242 and 282 can also interface with controller / processor 240 and 280, respectively. Scheduler 244 can schedule UEs for data transmission on the downlink and / or uplink.

[0044] In some aspects of this disclosure, transceiver 232 and / or transceiver 254 may include a low-noise amplifier (LNA) implemented using active and bypass paths with shared inductance elements, as described in more detail herein.

[0045] NR can use Orthogonal Frequency Division Multiplexing (OFDM) with a cyclic prefix (CP) on both the uplink and downlink. NR can use Time Division Duplex (TDD) to support half-duplex operation. OFDM and Single-Carrier Frequency Division Multiplexing (SC-FDM) divide the system bandwidth into multiple orthogonal subcarriers, which are often referred to as tones, frequency bands, etc. Each subcarrier can be modulated with data. Modulation symbols can be transmitted in the frequency domain using OFDM and in the time domain using SC-FDM. The spacing between adjacent subcarriers can be fixed, and the total number of subcarriers can depend on the system bandwidth. The system bandwidth can also be divided into subbands. For example, a subband can cover multiple resource blocks (RBs).

[0046] Example RF transceiver

[0047] Figure 3 This is a block diagram of an example radio frequency (RF) transceiver circuit 300 according to certain aspects of this disclosure. The RF transceiver circuit 300 includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas 306 and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via antenna 306. When the TX path 302 and RX path 304 share antenna 306, these paths can be connected to the antenna via an interface 308, which may include any of a variety of suitable RF devices, such as switches, duplexers, double-ended converters, multiplexers, etc.

[0048] Receiving in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, mixer 314, DA 316, and PA 318 may be included in a radio frequency integrated circuit (RFIC). In some respects, the PA 318 may be external to the RFIC.

[0049] BBF 312 filters the baseband signal received from DAC 310, and mixer 314 mixes the filtered baseband signal with the transmit local oscillator (LO) signal to convert the baseband signal of interest to a different frequency (e.g., up-convert from baseband to RF). This frequency conversion process produces a sum and difference frequency between the LO frequency and the frequency of the baseband signal of interest. This sum and difference frequency is referred to as the "beat frequency". The beat frequency is typically in the RF range, such that the signal output from mixer 314 is typically an RF signal, which can be amplified by DA 316 and / or PA 318 before being transmitted by antenna 306. When one mixer 314 is exemplified, several mixers can be used to up-convert the filtered baseband signal to one or more intermediate frequencies and subsequently up-convert the intermediate frequency (IF) signal to the frequency used for transmission.

[0050] The RX path 304 may include a low-noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. In some aspects, the LNA 324 may be implemented using active and bypass paths with shared inductor elements, as described in more detail herein. The LNA 324, mixer 326, and BBF 328 may be included in one or more RFICs, which may be the same RFIC as the RFIC including the TX path components, or may not be the same RFIC as the RFIC including the TX path components. The RF signal received via antenna 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a received local oscillator (LO) signal to convert the RF signal of interest to a different baseband frequency (e.g., down-conversion). The baseband signal output from the mixer 326 may be filtered by the BBF 328 before being converted into digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0051] Some transceivers may employ a frequency synthesizer with a variable-frequency oscillator (e.g., a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a specific tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by amplifier 322 before being mixed with the baseband signal in mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by amplifier 334 before being mixed with the RF signal in mixer 326. In some aspects, a single frequency synthesizer may be used for both TX path 302 and RX path 304. In some aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier (such as a doubler) driven by an oscillator (e.g., a VCO) in the frequency synthesizer.

[0052] Controller 336 (e.g., Figure 2 The controller / processor 280 in the controller 336 can direct the operation of the RF transceiver circuitry 300A, such as transmitting signals via TX path 302 and / or receiving signals via RX path 304. The controller 336 can be a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The memory 338 (e.g., ...) Figure 2 The memory 282 in the memory can store data and / or program code for operating the RF transceiver circuit 300. The controller 336 and / or the memory 338 may include control logic (e.g., complementary metal-oxide-semiconductor (CMOS) logic).

[0053] Although Figures 1 to 3 Wireless communication is provided as an example application in which certain aspects of this disclosure can be implemented to facilitate understanding, but certain aspects described herein can be used in any of a variety of other suitable systems (e.g., amplifiers or other electronic systems).

[0054] Example Low Noise Amplifier (LNA)

[0055] For radio frequency integrated circuit (RFIC) designs, on-chip inductors can be used to implement impedance matching for low-noise amplifiers (LNAs). On-chip inductors can consume a large area. A multi-gain mode LNA may have one inductor for impedance matching of the active path used for the LNA and another inductor for impedance matching of the bypass path used for the LNA. The active path of the LNA can be active for amplification, or the LNA can be bypassed by activating the bypass path. Therefore, the two inductors used for the active and bypass paths may not be turned on simultaneously. Some aspects of this disclosure relate to using the same inductor for both the bypass and active paths, thereby reducing the number of on-chip inductors used for the LNA, saving area and cost. Some aspects provide circuit topologies for multi-gain mode LNAs and coil topologies for highly coupled (e.g., high coupling factor K), high quality factor (Q), and two-tap inductors.

[0056] Figure 4An LNA 400 is illustrated, having an inductor 402 (e.g., an off-chip surface mount device (SMD) inductor) coupled between an input node (e.g., labeled "LNA_IN") and the gate of transistor 404. As shown, the source of transistor 404 can be coupled to a reference potential node (e.g., ground) via inductor 422. The drain of transistor 404 can be coupled to the source of transistor 406. When LNA 400 is active, transistor 406 can be biased using a bias voltage.

[0057] The drain of transistor 406 can be coupled to an active path impedance matching circuit having an inductor 410 connected in parallel with a variable capacitor 408. As shown, each of the inductor 410 and capacitor 408 is coupled between a supply voltage (VDD) node and transistor 406. As shown, a tap (e.g., a center tap) of inductor 410 can be coupled to a first terminal of an AC-coupled capacitor 412 (e.g., a variable capacitor). A second terminal of capacitor 412 can be selectively coupled to the output node of the LNA (labeled "LNA_out") via switch 420. Switch 420 can be closed when the active LNA path 450 is enabled and open when the active LNA path 450 is disabled. Switch 418 can be coupled between the second terminal of capacitor 412 and a reference potential node (e.g., ground). Switch 418 can be closed when switch 420 is open.

[0058] LNA 400 also includes a bypass path 498 implemented via switch 424, which is coupled between the gate of transistor 404 and a bypass path impedance matching circuit having an inductor element 428 and a variable capacitor element 426. As shown, capacitor element 426 can be shunt-coupled between switch 424 and a reference potential node (e.g., ground), and inductor element 428 can be coupled in series between switch 424 and switch 416. As shown, switch 414 can be shunt-coupled between inductor element 428 and the reference potential node (ground). Switch 416 selectively couples inductor element 428 to the output node of LNA 400 (labeled "LNA_OUT"), as shown. When the LNA is in bypass mode, switches 416 and 424 can be closed. When the active LNA path 450 is enabled, switches 416 and 424 can be open and switch 414 can be closed.

[0059] As described, the active path of the LNA can be active for amplification, or the LNA can be bypassed by activating a bypass path. In some aspects of this disclosure, at least a portion of the active path and the bypass path can be shared, thereby reducing the area loss and cost of the LNA. In some aspects, instead of using two separate inductor elements 410, 428 for the respective active and bypass paths, the same inductor element can be used, thereby reducing the area loss and cost of the LNA. In some aspects, the gain of the LNA can be adjusted by adjusting a resistive element (not shown) that can be coupled in parallel with the inductor element 410.

[0060] Figure 5 An LNA 500 according to certain aspects of this disclosure is illustrated, wherein at least a portion of its active path and bypass path are shared. As shown, bypass path 520 may include series switches 506, 510 coupled between the gate of transistor 404 and variable capacitor element 504. Bypass path 520 may also include inductor element 502 coupled between capacitor element 504 and inductor element 410. During bypass mode, switches 506, 510 are closed. Switch 508 may be shunt-coupled between a reference potential node (electric ground) and a node 509 located between switches 506, 510. Switch 508 may be closed in active mode (e.g., when switches 506, 510 are open to ground node 509 located between switches 506, 510). As shown, bypass path 520 can start from gate transistor 404, across capacitor element 504, across inductor element 502, across a portion of inductor element 410 to tap 460, and across capacitor element 412 to the output node. Therefore, a portion of bypass path 520 can be shared with active path 450 (e.g., a portion of inductor element 410 is shared by both the active and bypass paths). Capacitor element 504 acts as a DC blocking capacitor. In bypass mode, the LNA input node can be at zero volts. For DC, inductors 502 and 410 act as short circuits. Therefore, when capacitor element 504 is not blocking DC (e.g., at zero volts), the LNA input node will be coupled to the supply voltage VDD.

[0061] Compared to the LNA 400, the LNA 500 uses fewer switches and does not use bypass capacitor element 426. Although the LNA 500 includes capacitor element 504, capacitor element 504 can be smaller than capacitor element 426. Therefore, the LNA 500 has a smaller size than the LNA 400.

[0062] Figure 6An LNA 500, comprising a bypass inductor magnetically coupled to an active inductor element, is illustrated according to certain aspects of this disclosure. Figure 602 shows inductor elements 410-1 and 410-2, where inductor element 410-2 represents the portion of inductor element 410 from the supply voltage node to tap 460, and inductor element 410-1 represents the portion of inductor element 410 from tap 460 to inductor element 502. In some aspects, inductor elements 410-1 and 410-2 may be magnetically coupled, as shown.

[0063] In some implementations, inductor 502 may be a standalone inductor (e.g., not magnetically coupled to inductor 410). In this case, inductor 410-1 may be an 8nH inductor, inductor 410-2 may be a 1.5nH inductor, and inductor 502 may be a 4.7nH inductor. In some aspects, as shown in Figure 604, inductor 502 may be magnetically coupled to each of inductors 410-1 and 410-2, thereby allowing the inductance of inductor 502 to be reduced from 4.7nH to 2.3nH, thereby further reducing the area loss of the LNA. Inductors 502, 410-1, and 410-2 may be implemented using a single inductor structure having a first tap 460 between inductors 410-1 and 410-2 and a second tap 640 between inductors 410-1 and 502.

[0064] Figure 7A and Figure 7B An inductor element structure 750 for implementing inductor elements 410, 502 according to certain aspects of this disclosure is illustrated. For example... Figure 7A As shown, inductor element 410-2 can be coupled to a first node (labeled "node 1") and a first tap (e.g., tap 460, in...). Figure 7A The inductor element 410-1 may be coupled between tap 1 and the second tap (e.g., tap 640, in the middle). The inductor element 410-2 may include an inductor element portion 702 implemented on a first layer (labeled "layer 1") of the integrated circuit (IC) and an inductor element portion 704 implemented on a second layer (labeled "layer 2") of the IC. Figure 7AThe inductor element 410-1 may include an inductor element portion 708 implemented on layer 1 and an inductor element portion 706 implemented on layer 2. Inductor element 502 includes an inductor element portion 710 implemented on layer 1 and an inductor element portion 712 implemented on layer 2. As shown, inductor element portions 702 and 708 may be implemented using interleaved coils, and inductor element portions 704 and 706 may be implemented using interleaved coils. Inductor element portions 702 and 706 may be magnetically coupled (e.g., having mutual inductance), and inductor element portions 704 and 708 may be magnetically coupled (e.g., having mutual inductance). Figure 7B As shown, inductor elements 410 and 502 can be implemented using a two-layer inductor element structure 750 spanning an integrated circuit (IC).

[0065] Figure 8 An inductor structure 750 implemented on two layers of an IC according to certain aspects of this disclosure is illustrated. As shown, the coil for the inductor 410-2 can be routed from node 1 on layer 1 to via 802 from layer 1 to layer 2, thereby realizing [the following information is missing from the original text]. Figure 7A The described inductor element portion 702. The coil for inductor element 410-2 continues from via 802 on layer 2 to via 804 (e.g., tap 1) from layer 2 to layer 1, thus realizing inductor element portion 704. The coil for inductor element 410-1 can extend from via 804 (tap 1) on layer 1 to via 806 from layer 1 to layer 2, thus realizing... Figure 7A The described inductor element portion 708. The coil for inductor element 410-2 continues from via 806 on layer 2 to via 808 (e.g., tap 2) from layer 2 to layer 1, thus realizing inductor element portion 706. The coil for inductor element 502 can extend from via 808 (tap 2) on layer 1 to via 810 from layer 1 to layer 2, thus realizing... Figure 7A The described inductor element portion 710. The coil for the inductor element 502 continues from the via 810 on layer 2 to node 2, thereby realizing the inductor element portion 712, as shown.

[0066] Example zoom-in operation

[0067] Figure 9 This is a flowchart of an example operation 900 for signal amplification according to certain aspects of this disclosure. Operation 900 may be performed, for example, by an amplifier (such as an LNA 500).

[0068] At box 902, the amplifier can be located at the amplifier's input node (e.g., Figure 5The signal for amplification via the amplifier is received at LNA_IN (as shown). At block 904, the amplifier is coupled to the amplifier's output node (e.g., LNA_IN) via amplifier coupling. Figure 5 The source path between (e.g., LNA_OUT) shown Figure 5 The amplification is performed via path 450. The active path may include a first transistor (e.g., transistor 404) coupled to the input node of the amplifier and a first inductor (e.g., [insert inductor name here]) coupled between the first transistor and the output node. Figure 6 (See inductor element 410-1). The amplified signal may include a second transistor (e.g., transistor 406) biased and coupled to the first transistor via a common source and cascode, wherein the first inductor element is coupled between the second transistor and the output node. In some aspects, the amplifier may adjust the capacitance of a capacitive element (e.g., capacitor element 412) coupled between the first inductor element and the output node in the active path. The amplifier may also include a second inductor element (e.g., inductor element 402) coupled between the input node and the gate of the first transistor.

[0069] At block 906, the amplifier activates a bypass path (e.g., path 520) between the input and output nodes, which also includes a first inductor. The amplifier may include a second inductor (e.g., inductor 410-2) coupled to the first inductor. A tap located between the first and second inductors may be coupled to the output node. The amplifier may also include a capacitor (e.g., capacitor 408) coupled in parallel to the series combination of the first and second inductors. The capacitor may be a variable capacitor. The variable capacitor, the first inductor, and the second inductor may form an impedance matching circuit for the active path. The amplifier can tune the impedance matching circuit by adjusting the capacitance of the variable capacitor. In some aspects, the bypass path may include a third inductor (e.g., ...) coupled to the first inductor. Figure 5The bypass path may include a capacitor element (e.g., capacitor element 504) coupled between the gate of the first transistor and the second inductor element. Activating the bypass path may include closing the bypass path by a first switch (e.g., switch 506) coupled between the gate of the first transistor and the capacitor element. In some cases, activating the bypass path may also include closing the bypass path by a second switch (e.g., switch 510) coupled between the first switch and the capacitor element, and disconnecting the bypass path by a third switch (e.g., switch 508) coupled between a reference potential node and a node located between the first and second switches (e.g., node 509). The third inductor element may be magnetically coupled to each of the first and second inductor elements. In some aspects, a first portion of the first inductor element may be interleaved with a first portion of the second inductor element, and a second portion of the first inductor element may be interleaved with a second portion of the second inductor element. The first portions of the first inductor element and the first portions of the second inductor element may be on the first layer of an integrated circuit (IC) (e.g., Figure 8 On layer 1 shown, and the second portion of the first inductor and the second portion of the second inductor are on the second layer of the IC (e.g., layer 1), and the second portion of the first inductor and the second portion of the second inductor are on the second layer of the IC (e.g., layer 2). Figure 8 On layer 2 shown.

[0070] Example

[0071] In addition to the various aspects described above, specific combinations of these aspects are also within the scope of this disclosure, some of which are detailed below:

[0072] Aspect 1: An amplifier comprising: an active path coupled between an input node and an output node of the amplifier, wherein the active path includes a first transistor coupled to the input node of the amplifier and a first inductor coupled between the first transistor and the output node; and a bypass path coupled between the input node and the output node of the amplifier, the bypass path including the first inductor.

[0073] Aspect 2: The amplifier according to aspect 1, wherein the active path further includes a second transistor coupled to the first transistor via a common source and common gate, and wherein the first inductor is coupled between the second transistor and the output node.

[0074] Aspect 3: The amplifier according to aspect 1 or 2 further includes: a second inductor coupled to the first inductor, wherein a tap located between the first inductor and the second inductor is coupled to the output node.

[0075] Aspect 4: According to aspect 3, the amplifier further includes a capacitor element, which is coupled in parallel to the series combination of the first inductor element and the second inductor element.

[0076] Aspect 5: The amplifier according to aspect 4, wherein the capacitor element is a variable capacitor element, and wherein the variable capacitor element, the first inductor element and the second inductor element form an impedance matching circuit for the active path.

[0077] Aspect 6: The amplifier according to any one of Aspects 3 to 5, wherein the bypass path further includes a third inductor coupled to the first inductor.

[0078] Aspect 7: The amplifier according to aspect 6, wherein the bypass path further includes a capacitor element coupled between the gate of the first transistor and the second inductor element.

[0079] Aspect 8: The amplifier according to aspect 7, wherein the bypass path further includes a first switch coupled between the gate of the first transistor and the capacitor element.

[0080] Aspect 9: The amplifier according to aspect 8, wherein: the bypass path further includes a second switch coupled between the first switch and the capacitor element; and the amplifier further includes: a third switch coupled between a reference potential node and a node located between the first switch and the second switch.

[0081] Aspect 10: An amplifier according to any one of Aspects 6 to 9, wherein the third inductor is magnetically coupled to each of the first inductor and the second inductor.

[0082] Aspect 11: The amplifier according to aspect 10, wherein a first portion of the first inductor element is interwoven with a first portion of the second inductor element, and wherein a second portion of the first inductor element is interwoven with a second portion of the second inductor element.

[0083] Aspect 12: The amplifier according to aspect 11, wherein the first portion of the first inductor and the first portion of the second inductor are on a first layer of an integrated circuit (IC), and wherein the second portion of the first inductor and the second portion of the second inductor are on a second layer of the IC.

[0084] Aspect 13: An amplifier according to any one of Aspects 1 to 12, wherein the active path includes a capacitive element coupled between the first inductive element and the output node.

[0085] Aspect 14: The amplifier according to any one of Aspects 1 to 13, the amplifier further comprising: a second inductor element coupled between the input node and the gate of the first transistor.

[0086] Aspect 15: A method for signal amplification, the method comprising: receiving a signal for amplification via the amplifier at an input node of an amplifier; amplifying the signal via an active path coupled to the amplifier between the input node and an output node of the amplifier, wherein the active path includes a first transistor coupled to the input node of the amplifier and a first inductor coupled between the first transistor and the output node; and activating a bypass path coupled to the amplifier between the input node and the output node, the bypass path including the first inductor.

[0087] Aspect 16: According to the method of aspect 15, amplifying the signal includes: biasing a second transistor coupled to the first transistor via a common source and common gate, and wherein the first inductor is coupled between the second transistor and the output node.

[0088] Aspect 17: The method according to aspect 15 or 16, wherein the amplifier includes a second inductor coupled to the first inductor, and wherein a tap located between the first inductor and the second inductor is coupled to the output node.

[0089] Aspect 18: According to the method of aspect 17, the amplifier further includes a capacitor element coupled in parallel with a series combination of the first inductor element and the second inductor element.

[0090] Aspect 19: The method according to aspect 18, wherein the capacitor element is a variable capacitor element, wherein the variable capacitor element, the first inductor element and the second inductor element form an impedance matching circuit for the active path, and wherein the method further comprises: tuning the impedance matching circuit by adjusting the capacitance of the variable capacitor element.

[0091] Aspect 20: The method according to any one of aspects 17 to 19, wherein the bypass path further includes a third inductor coupled to the first inductor.

[0092] Aspect 21: According to the method of aspect 20, the bypass path further includes a capacitor element coupled between the gate of the first transistor and the second inductor element.

[0093] Aspect 22: According to the method of aspect 21, activating the bypass path includes: closing a first switch of the bypass path coupled between the gate of the first transistor and the capacitor element.

[0094] Aspect 23: According to the method of aspect 22, activating the bypass path further includes: closing the second switch coupled between the first switch and the capacitor element; and disconnecting the third switch coupled between the reference potential node and the node located between the first switch and the second switch.

[0095] Aspect 24: The method according to any one of Aspects 20 to 23, wherein the third inductor is magnetically coupled to each of the first inductor and the second inductor.

[0096] Aspect 25: According to the method of aspect 24, wherein a first portion of the first inductor element is interwoven with a first portion of the second inductor element, and wherein a second portion of the first inductor element is interwoven with a second portion of the second inductor element.

[0097] Aspect 26: According to the method of aspect 25, the first portion of the first inductor and the first portion of the second inductor are on a first layer of an integrated circuit (IC), and the second portion of the first inductor and the second portion of the second inductor are on a second layer of the IC.

[0098] Aspect 27: The method according to any one of Aspects 15 to 26, the method further comprising: adjusting the capacitance of the capacitive element of the active path coupled between the first inductive element and the output node.

[0099] Aspect 28: The method according to any one of Aspects 15 to 27, wherein the amplifier further comprises a second inductor coupled between the input node and the gate of the first transistor.

[0100] Aspect 29: A wireless device comprising: one or more antennas; and a low-noise amplifier (LNA) having an input node coupled to the one or more antennas, the LNA comprising: an active path coupled between the input node and an output node of the LNA, wherein the active path includes a transistor coupled to the input node and an inductor coupled between the transistor and the output node; and a bypass path coupled between the input node and the output node, the bypass path including the inductor.

[0101] The above description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the elements discussed without departing from the scope of this disclosure. Various processes or components may be omitted, substituted, or added as appropriate in various examples. For example, the described method may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined in other examples. For example, any number of aspects set forth herein may be used to implement an apparatus or practice. Moreover, the scope of this disclosure is intended to cover such apparatus or methods practiced using structures, functionalities, or structures and functionalities other than or different from the various aspects of this disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be embodied by one or more elements of these claims.

[0102] The various operations of the methods described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or software components and / or modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Generally, in the presence of operations illustrated in the accompanying drawings, these operations can have corresponding components plus functional elements.

[0103] As used in this article, the phrase “at least one of” in a list of items refers to any combination of these entries, including a single member. As an example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbb, cc, and ccc, or any other ordering of a, b, and c).

[0104] The methods disclosed herein include one or more steps or actions for implementing the described methods. The steps and / or actions of the methods may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of a particular step and / or action may be modified without departing from the scope of the claims.

[0105] It should be understood that the claims are not limited to the precise configurations and components illustrated above. Various modifications, variations, and alterations may be made to the arrangement, operation, and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. An amplifier, the amplifier comprising: an active path coupled between an input node of the amplifier and an output node of the amplifier, wherein the active path includes a first transistor coupled to the input node of the amplifier and a first inductive element coupled between the first transistor and the output node; and a bypass path coupled between the input node of the amplifier and the output node of the amplifier, the bypass path including the first inductive element.

2. The amplifier of claim 1, wherein the active path further includes a second transistor coupled in a common-source common-gate configuration with the first transistor, and wherein the first inductive element is coupled between the second transistor and the output node. a second inductive element coupled to the first inductive element, wherein a tap between the first inductive element and the second inductive element is coupled to the output node.

3. The amplifier of claim 1, further comprising: a capacitive element coupled in parallel with a series combination of the first inductive element and the second inductive element.

4. The amplifier of claim 3, further comprising:

5. The amplifier of claim 4, wherein the capacitive element is a variable capacitive element, and wherein the variable capacitive element, the first inductive element, and the second inductive element form an impedance matching circuit for the active path.

6. The amplifier of claim 3, wherein the bypass path further includes a third inductive element coupled to the first inductive element.

7. The amplifier of claim 6, wherein the bypass path further includes a capacitive element coupled between a gate of the first transistor and the second inductive element.

8. The amplifier of claim 7, wherein the bypass path further includes a first switch coupled between the gate of the first transistor and the capacitive element.

9. The amplifier of claim 8, wherein: the bypass path further includes a second switch coupled between the first switch and the capacitive element; and the amplifier further includes a third switch coupled between a reference potential node and a node between the first switch and the second switch.

10. The amplifier of claim 6, wherein the third inductive element is magnetically coupled with each of the first inductive element and the second inductive element.

11. The amplifier of claim 10, wherein a first portion of the first inductive element is interleaved with a first portion of the second inductive element, and wherein a second portion of the first inductive element is interleaved with a second portion of the second inductive element.

12. The amplifier of claim 11, wherein the first portion of the first inductive element and the first portion of the second inductive element are on a first layer of an integrated circuit (IC), and wherein the second portion of the first inductive element and the second portion of the second inductive element are on a second layer of the IC. ​ 13. The amplifier of claim 1, wherein the active path comprises a capacitive element coupled between the first inductive element and the output node.

14. The amplifier of claim 1, further comprising: a second inductive element coupled between the input node and a gate of the first transistor.

15. A method for signal amplification, the method comprising: receiving, at an input node of an amplifier, a signal for amplification via the amplifier; amplifying via an active path of the amplifier coupled between the input node and an output node of the amplifier, wherein the active path comprises a first transistor coupled to the input node of the amplifier and a first inductive element coupled between the first transistor and the output node; and activating a bypass path of the amplifier coupled between the input node and the output node, the bypass path comprising the first inductive element.

16. The method of claim 15, wherein amplifying the signal comprises biasing a second transistor coupled in a common-source common-gate configuration with the first transistor, and wherein the first inductive element is coupled between the second transistor and the output node.

17. The method of claim 15, wherein the amplifier comprises a second inductive element coupled to the first inductive element, and wherein a tap between the first inductive element and the second inductive element is coupled to the output node. a capacitive element coupled in parallel with a series combination of the first inductive element and the second inductive element.

18. The method of claim 17, wherein the amplifier further comprises: tuning the impedance matching circuit by adjusting a capacitance of the variable capacitive element.

19. The method of claim 18, wherein the capacitive element is a variable capacitive element, wherein the variable capacitive element, the first inductive element, and the second inductive element form an impedance matching circuit for the active path, and wherein the method further comprises:

20. The method of claim 17, wherein the bypass path further comprises a third inductive element coupled to the first inductive element.

21. The method of claim 20, wherein the bypass path further comprises a capacitive element coupled between a gate of the first transistor and the second inductive element. closing a first switch of the bypass path coupled between the gate of the first transistor and the capacitive element.

22. The method of claim 21, wherein activating the bypass path comprises:

23. The method of claim 22, wherein activating the bypass path further comprises: closing a second switch of the bypass path coupled between the first switch and the capacitive element; and opening a third switch coupled between a reference potential node and a node between the first switch and the second switch.

24. The method of claim 20, wherein the third inductive element is magnetically coupled to each of the first inductive element and the second inductive element.

25. The method of claim 24, wherein a first portion of the first inductive element is interleaved with a first portion of the second inductive element, and wherein a second portion of the first inductive element is interleaved with a second portion of the second inductive element. ​ ​ 26. The method of claim 25, wherein the first portion of the first inductive element and the first portion of the second inductive element are on a first layer of an integrated circuit (IC), and wherein the second portion of the first inductive element and the second portion of the second inductive element are on a second layer of the IC.

27. The method of claim 15, further comprising: adjusting a capacitance of a capacitance element coupled between the first inductive element and the output node.

28. The method of claim 15, wherein the amplifier further comprises: a second inductive element coupled between the input node and a gate of the first transistor.

29. A wireless device, the wireless device comprising: one or more antennas; and a low noise amplifier (LNA) having an input node coupled to the one or more antennas, the LNA comprising: an active path coupled between the input node of the LNA and an output node of the LNA, wherein the active path includes a transistor coupled to the input node and an inductive element coupled between the transistor and the output node; and a bypass path coupled between the input node and the output node, the bypass path including the inductive element.

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