A three-dimensional stacked chip testing method based on multi-interface cooperation and parallel broadcasting

Abstract

The application discloses a three-dimensional stacked chip testing method based on multi-interface cooperation and parallel broadcasting, and relates to the technical field of integrated circuit testing.The method sets a USB controller on a master control chip layer to preload 116 bit testing instruction streams to a PRO_RAM on the chip;the states of each layer are configured by issuing instructions through JTAG;then, a coordinator FSM runs in a three-stage pipeline mode of instruction fetching, broadcasting and executing, instruction parameters are synchronously distributed to BIST controllers of target layers by using a source fan-out broadcasting bus;by introducing physically isolated shadow registers and active registers in the BIST controllers, the next group of instructions are prefetched and loaded in the background while the current task scanning and shifting are performed, and zero-bubble task switching is achieved;the application effectively reduces the transmission amount of repeated instructions, eliminates the time domain coupling of configuration and execution in the traditional architecture, and significantly improves the testing efficiency of the heterogeneous stacked chip.

Description

Technical Field

[0001] This invention relates to the technical field of integrated circuit testing, and more specifically, to a three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting. Background Technology

[0002] With the rapid development of 3D-SIC technology, chips are stacked with multiple dies using vertical interconnect technologies (such as TSV), achieving integration density and performance far exceeding that of traditional 2D chips. However, this vertical integration structure also presents severe technical challenges to chip testing, diagnostics, and yield improvement. Traditional testing methods and architectures are no longer sufficient to meet its complex testing requirements.

[0003] The current mainstream 3D-SIC testing methods and architectures primarily follow the IEEE Std 1838-2019 standard (Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits). This standard provides a test access architecture including a Serial Control Mechanism (SCM), a Chip Package Register (DWR), and an optional Flexible Parallel Port (FPP). Although IEEE 1838 provides a standardized access channel, existing test systems based on this standard still have core limitations. The SCM in the IEEE 1838 standard typically uses the traditional JTAG (IEEE 1149.1) interface for test command loading and control. However, the inherently low bandwidth of the JTAG interface (typically in the 10Mbps to 30Mbps range) becomes a significant performance bottleneck when transmitting large-scale test stimuli (TestStimuli / Seed) and unloading test responses. According to authoritative research in the field of integrated circuit testing, in the production testing of multi-layer stacked chips, test seed loading time can account for more than 60% of the total test time, severely restricting test efficiency. Existing test procedures, including those utilizing the high-speed data transmission scheme of IEEE 1838 FPP, essentially still employ a serial "load, execute, unload" mode driven by an external ATE. While FPP provides a high-speed path, it requires a continuous and synchronous clock and data stream from an external ATE, and the next set of test data cannot be pre-loaded using FPP during the test execution phase. This external and serial dependency leads to pipeline interruptions, with core resources idle during the loading phase and data ports idle during the execution phase, generating numerous "pipeline bubbles." In 3D-SIC, different dies (single-chip layers) may have different test requirements (different test stimuli, each layer requiring different test input signals), scan chain lengths, and failure modes (i.e., heterogeneity). Existing technologies often rely on globally unified test instructions for configuration, and when multiple dies require the same stimuli, they lack efficient on-chip data broadcasting and sharing mechanisms, still requiring serial or repetitive loading paths—that is, repeatedly loading each layer serially, loading data layer by layer via JTAG, and unable to send it all at once. This repetitive, serial configuration and loading process creates redundancy in test data transmission; the same data is repeatedly sent and loaded, occupying the JTAG interface multiple times, wasting time and reducing test efficiency. While a single JTAG interface can provide precise control, its extremely low speed cannot meet the needs of large-scale configuration; and while high-speed interfaces are fast, they lack the ability to fine-grained control over test logic.

[0004] Therefore, the industry urgently needs a comprehensive test solution that can integrate external high-speed data preloading, on-chip precise control, and parallel broadcasting mechanisms to overcome the bandwidth limitations of a single interface, achieve parallel pipelined operation of loading and execution, and support autonomous and efficient testing of 3D-SIC. Summary of the Invention

[0005] The purpose of this invention is to solve the problems of limited JTAG interface bandwidth, low testing efficiency, and severe pipeline bubbles in existing 3D-SIC (3D-Semiconductor Chip) testing. This invention proposes an autonomous comprehensive testing solution based on multi-interface collaboration and a parallel broadcast pipeline. This method completely breaks the bandwidth bottleneck of JTAG by integrating high-speed interfaces such as USB 2.0 for parallel preloading of large-scale test data. Simultaneously, an on-chip parallel broadcast pipeline architecture is constructed to achieve parallel operation of test data prefetching and core test execution, thereby eliminating "pipeline bubbles" caused by serial dependencies and significantly improving test resource utilization. Furthermore, this invention retains the precise control capabilities of JTAG for test configuration. By constructing a source-side fan-out physical broadcast bus, it achieves one-to-many concurrent distribution of test loads for multiple target chips. This mode compresses the distribution complexity of configuration instructions from a linear increase of O(N) to a constant delay of O(1), ultimately achieving a significant reduction in the total 3D-SIC testing time and a decrease in testing costs.

[0006] The technical solution of this invention is as follows: A three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting is provided. The main control chip layer in the stacked chip integrates a program memory (PRO_RAM), a test coordinator (FSM), and a USB controller. Each chip layer achieves vertical signal interconnection through vertical through-silicon vias (TSVs). Each chip layer is equipped with a BIST controller containing a shadow register and an active register. The method includes:

[0007] Step 1: Load the required 116-bit format test command stream into the PRO_RAM of the main control chip layer in batches via the USB controller;

[0008] Step 2: Send configuration data through the TAG interface and cascaded TSV path to complete the initialization of each chip layer, including configuring the scan insertion bit SIB and broadcast control bit BCB to activate the hardware broadcast path and select the target scan chain.

[0009] Step 3: Use FSM to read test instructions from PRO_RAM and construct a dynamic test group. Broadcast the key information of each instruction in the group to the BIST controller of the corresponding target chip layer. Each BIST controller executes the test and capture tasks according to the key information. At the same time, FSM continues to read the next dynamic test group and broadcast it. After the current test task is completed, each BIST controller continues to execute the next test and capture task. The key information includes scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected feature signature. The test process is as follows:

[0010] Step 31: The BIST controller reads the corresponding control bit from the polynomial read-only memory Poly_Rom using the polynomial configuration as the index, and uses the control bit to configure the reconfigurable feedback network RP-FN to change the feedback loop structure of the linear feedback shift register LFSR.

[0011] Step 32: The BIST controller loads the LFSR seed into the LFSR. The LFSR generates a test sequence starting from the seed. The test sequence enters the test circuit for testing through the selected scan chain.

[0012] Step 33: The Multi-Input Feature Register (MISR) receives the feedback response from the test circuit and generates the actual feature signature. The BIST controller compares and processes the actual feature signature based on the result comparison enable to obtain the test result.

[0013] The beneficial effects of this invention are:

[0014] First, the technical solution of this invention sets up a USB control module in the main control chip layer to build a high-speed test data interface, separating the data transmission function from the traditional JTAG interface. The USB control module is used to preload large-scale test instructions, LFSR seeds, and polynomial configuration parameters at high speed, while the JTAG interface is only used to send control instructions such as starting the test, configuring the broadcast path, and querying the test status. The technical solution of this invention decouples the test data transmission from the test process control, which can make full use of the high bandwidth advantage of the USB interface to achieve rapid batch loading of test data, while using the JTAG interface to achieve precise control. This effectively breaks through the performance bottleneck caused by the limited bandwidth of the traditional JTAG interface, significantly reduces the test data loading time, and improves the overall efficiency of the three-dimensional stacked chip test system.

[0015] Secondly, the technical solution of this invention sets up a scan insertion bit (SIB) and a broadcast control bit (BCB) structure inside each chip layer, and configures them through the JTAG interface before the test begins. The scan insertion bit is used to flexibly select and connect the scan chain inside the chip to achieve selective testing of the target circuit module. The broadcast control bit is used to establish a test data broadcast path between different chip layers, so that the test data can be directly transmitted and distributed efficiently along the established path during subsequent testing, thereby reducing the repeated loading process, improving the test data distribution efficiency, and enhancing the flexibility of testing different chip modules.

[0016] Third, the technical solution of this invention innovatively designs a dynamically organized test instruction format. It introduces a Die mask instruction and a continue flag into the test instructions. The Die mask instruction specifies the target chip layer, and the continue flag is used to organize multiple test instructions into a dynamic test group, thereby achieving flexible test flow control. Through the combination of the Die mask and the continue flag, the target chip layer can be selected in the spatial dimension, and test groups can be dynamically constructed in the temporal dimension. Simultaneously, in conjunction with the established hardware broadcast path, test parameters can be broadcast and distributed across multiple chip layers at once, avoiding repeated loading of the same test data and significantly reducing the amount of test data transmitted. This invention also sets input and output masks in the test instructions, utilizing fine-grained control of the scan path to achieve the selection of sub-scan chains and shield the X-state diffusion of irrelevant regions, preventing irrelevant data from moving into the MISR and affecting the test results, thus improving test accuracy. Furthermore, this invention introduces a test instruction pre-fetching and pipelined execution mechanism into the test flow, enabling the test execution phase and the reading and broadcasting phases of the next test group to proceed in parallel, thereby effectively eliminating the pipeline bubble problem in traditional test flows and further improving the overall test throughput.

[0017] Fourth, the technical solution of this invention sets a polynomial configuration index field in the test instruction. The BIST controller can read the corresponding control bit from the polynomial read-only memory Poly_Rom based on this index, and use this control bit to configure the reconfigurable feedback network RP-FN. This dynamically changes the feedback loop structure of the linear feedback shift register LFSR at the hardware level, realizing real-time reconfiguration of the feedback polynomial. In this way, the same test hardware platform can select different feedback polynomials according to different test tasks, thereby generating pseudo-random test sequences with different statistical characteristics, significantly improving the diversity of test vectors and fault coverage capability, while avoiding the design of multiple test circuits for different test requirements, improving the flexibility and resource utilization efficiency of the test system. Attached Figure Description

[0018] The advantages of the above and additional aspects of the present invention will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0019] Figure 1 This is an overall architecture diagram of a 3D-SIC testing device according to an embodiment of the present invention;

[0020] Figure 2 This is a structural diagram of a layered test instruction format according to an embodiment of the present invention;

[0021] Figure 3 This is an internal structural diagram of a PTAP controller according to an embodiment of the present invention;

[0022] Figure 4 This is a microarchitecture diagram of a three-stage pipeline based on a circular buffer, according to an embodiment of the present invention;

[0023] Figure 5 This is a timing diagram of a three-stage pipelined concurrent execution according to an embodiment of the present invention;

[0024] Figure 6 This is a diagram of a reconfigurable LFSR and RP-FN reconfiguration feedback network structure according to an embodiment of the present invention. Detailed Implementation

[0025] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0026] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0027] like Figures 1 to 6 As shown, this embodiment provides a three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting. This method is used to broadcast test data and perform parallel testing on a three-dimensional stack containing multiple chip layers. Each chip layer is interconnected with signals through vertical through-silicon vias (TSVs), and each chip layer is equipped with a BIST controller that includes a shadow register and an active register.

[0028] First, it needs to be explained that, such as Figure 1As shown, the physical basis of the test device of this invention is an N-layer vertically stacked chip assembly (Die1, Die2, Die3, ..., DieN). This architecture is finely divided at the logical and physical levels into a "master control chip layer (Die 1)" that assumes global management responsibilities and "execution under test layers (Die 2 to Die n)" that serve as distributed execution nodes. Each Die is vertically interconnected with JTAG control signals, broadcast data signals, and status feedback signals through vertical through-silicon vias (TSVs). The master control chip layer serves as the instruction brain and scheduling hub of the entire 3D stack, and it integrates a memory (PRO_RAM), a test coordinator (implemented as a finite state machine FSM), and a USB controller (USB_Controller).

[0029] The USB_Controller module works in conjunction with the external physical layer PHY chip to fully utilize its high-speed physical bandwidth, preloading large-scale test instruction streams generated offline onto the chip at high speed. This achieves deep decoupling and physical isolation between the external communication time domain and the on-chip test logic time domain. PRO_RAM, as an on-chip cache, adopts a static random access memory (SRAM) architecture to store complete test programs and instructions pre-compiled and pre-loaded by the host computer. This ensures that subsequent pipeline execution at each stage does not require real-time timing alignment from external ATE (Automatic Test Equipment), supporting the chip's "autonomous testing" technology from the hardware level. The Test Coordinator (FSM), acting as the three-level pipeline manager at the system scheduling center, is responsible for coordinating the step synchronization of the instruction fetch, broadcast, and execution phases. Its core logic relies on the physical isolation and double buffering mechanism of shadow registers and active registers within each chip layer. This allows the instruction fetch and broadcast stages to complete the silent pre-distribution and background loading of the next set of instruction payloads in parallel within the long time window during which the execution stage drives the current test batch to perform scan shifting. This eliminates pipeline bubbles caused by waiting for configuration data in traditional architectures and ensures the continuous saturation operation of the test engine when heterogeneous tasks alternate.

[0030] Each die also features fully symmetrical test access and execution hardware, including: a 3D stacked test access port (PTAP) compliant with the IEEE 1149.1 standard, a standard test access port (STAP) extended based on the IEEE 1838 standard, and a fully functional Built-In Self-Test (BIST) subsystem. The STAPs and PTAPs in each die are chained together via TSVs, enabling seamless access and control of chip layers at any depth within the stack via external JTAG interfaces. Furthermore, each die's corresponding BIST subsystem integrates configurable broadcast control bits (BCB) and scan insertion bits (SIB). The BCB manages the broadcast enable and routing of test data from this layer to other layers, while the SIB flexibly connects and selects multiple scan chains within the layer. This is the fundamental hardware mechanism supporting targeted testing of different modules within the chip (i.e., heterogeneous testing).

[0031] Regarding inter-layer interconnect topology, this invention achieves a complete replacement of the traditional cascaded daisy-chain architecture by fanning out a broadcast bus from the source end. This bus is physically led out from the Die 1 master control layer and synchronously fans out through the vertical TSV link to all layers from Die 2 to Die n. This design has the significant advantage of constant-level compression of distribution latency, successfully compressing the time complexity of instruction distribution from the traditional linear growth of O(N) to a constant latency of O(1), meaning that no matter how many chip stack layers increase, the time for instructions to reach the top-level chip remains consistent. This fundamentally solves the inherent contradiction between vertical bandwidth utilization and control logic flexibility of a single interface, significantly improving the bus saturation of the three-dimensional stacked system when test tasks are intensively deployed.

[0032] A three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting specifically includes:

[0033] Step 1, High-speed preloading and time-domain decoupling: The 116-bit format test instruction stream required for testing is loaded in batches into the PRO_RAM of the main control chip layer through the USB controller, so as to establish an on-chip instruction reservoir and realize the complete time-domain decoupling of external slow communication and internal high-speed test logic.

[0034] Specifically, the USB controller serves as the test data interface. It employs a USB 2.0 controller (USB_Controller) integrated within the host control chip layer, working in conjunction with a necessary external USB physical layer (PHY) chip to form a high-speed data preloading channel between the host control chip layer and the host computer. Before the test sequence officially starts, the USB controller uses burst mode to preload the large-scale test command stream generated offline by the host computer into the PRO_RAM of the host control chip layer (the host control chip layer can refer to Die1 in the stack) at a rate of up to 480Mbps.

[0035] It should be noted that this invention adopts a "multi-interface collaborative working mode" in testing, giving full play to the inherent advantages of different interfaces to form a synergy. That is, two external interfaces with clear division of labor and capable of working together are set at the main control chip layer, namely the test data interface and the test control interface. The test data interface module adopts a USB 2.0 controller (USB_Controller) integrated inside the chip, which can realize "data preloading" and preload test data into PRO_RAM. The test control interface adopts the mature and precise JTAG interface, strictly following relevant international standards. The JTAG interface only acts as a lightweight and precise controller, responsible for sending simple control commands and status queries such as "Start Test", "Configure specific broadcast path", "Query test status", and "Read final signature". The combination of the test data interface and the test control interface completely decouples the most time-consuming data transfer stage from the core test stimulus application and response analysis stage in the traditional test process. It also utilizes the high bandwidth of the USB interface to fundamentally avoid the performance bottleneck caused by transmitting large amounts of data through a low-speed serial interface during test execution. This avoids the contradiction between bandwidth and controllability of a single interface and optimizes the overall efficiency of the system.

[0036] Step 2, Inter-layer state initialization: Configuration data is sent through the TAG interface and cascaded TSV path to complete the static initialization of each chip layer, including the configuration of scan insertion bit SIB and broadcast control bit BCB, so as to activate the hardware broadcast path, select the target scan chain, and enable each chip layer to enter the ready state to respond to the subsequent instruction stream.

[0037] Specifically, static initialization is an overall process used to bring the test hardware of each chip layer into a working state. It includes resetting the test control register and loading default parameters, resetting the BIST control module, initializing the basic path of the scan chain, establishing inter-layer test communication links, and configuring the scan insertion bit SIB and broadcast control bit BCB. Among them, resetting the test control register and loading default parameters are used to clear the state left over from the previous test cycle and load the default test parameters. Resetting the BIST control module is used to put the built-in self-test controller into standby state. These are common initialization and configuration operations in the test system and will not be described in detail here.

[0038] Each chip layer in the 3D stack is equipped with a Test Access Port (PTAP) and a Standard Test Access Port (STAP). The PTAPs and STAPs of each chip layer are vertically interconnected via TSVs. External test equipment (ATE / host computer) is connected to the PTAP of the main control chip layer. The SIBs of each chip layer are configured, specifically including:

[0039] The external test equipment first sends JTAG signals (including test clock TCK, test mode selection TMS, and test data input TDI) to the PTAP of the master control chip layer. The PTAP of the master control chip layer forwards the received JTAG signals sequentially to the STAPs of each target chip layer through the inter-layer cascaded TSV path. The STAP of each target chip layer directly transmits the received JTAG signals to the TAP controller inside its own chip layer, so that the TAP controllers of each target chip layer run the JTAG state machine synchronously under the same JTAG clock TCK. In the configuration start phase, the external test equipment controls the TAP controller to enter the Shift-IR state through the TMS and serially inputs the BCB register access instruction through the TDI port. This instruction is shifted into the instruction register of each chip layer sequentially through the PTAP and the cascaded STAP path (i.e., the inter-layer cascaded TSV path). After the instruction shift is completed, the external test equipment controls the TAP controller to enter the Update-IR state through the TMS. At this time, the TAP controllers of each target chip layer decode the instructions in the instruction register. Based on the decoding results, each SIB register is selected as the currently accessed data register. Subsequently, the external test equipment controls the TAP controller to enter the Shift-DR state via TMS and serially inputs SIB configuration data through the TDI port. This configuration data is shifted sequentially into the shift units of the corresponding SIB registers of each chip layer via the PTAP and cascaded STAP paths. For SIBs that need to be selected, their configuration data is set to 1 to enable the scan chain segment to access the test circuit; for SIBs that are not selected, their configuration data is set to 0 to shield the corresponding scan chain segment, thereby achieving selective access and configuration of the scan chain. After the configuration data shift is completed, the external test equipment controls the TAP controller to enter the Update-DR state via TMS. The SIB registers of each chip layer latch the data in the shift unit to the configuration latch, thereby completing the configuration of the SIB registers and realizing the pre-construction of the inter-layer static test environment. When the configuration data corresponding to each target chip layer is the same, it is configured uniformly under the same clock; when the configuration data corresponding to each target chip layer is different, it needs to be configured separately.

[0040] It should be noted that the Scan Insertion Bit (SIB) module in the BIST subsystem provides another layer of flexibility. The SIB allows a large global scan chain to be physically divided into multiple shorter, independent subchains. By configuring the SIB registers through the JTAG interface, one or more subchains can be dynamically selected for testing while keeping the other subchains stationary.

[0041] The configuration method for BCB is the same as that for SIB; the configuration data for BCB includes broadcast sender characters and broadcast receiver characters, which are used to identify the role configuration of each chip layer during the test broadcast process; this will not be elaborated here.

[0042] Step 3, three-level pipeline scheduling (the coordinator FSM operates in a three-level asynchronous decoupled mode of instruction fetch, broadcast, and execution, achieving overlap between configuration and execution); the FSM reads test instructions from PRO_RAM and constructs dynamic test groups, broadcasting the key information of each instruction in the dynamic test group to the BIST controller of the corresponding target chip layer. Each BIST controller executes the test and capture tasks according to the key information. At the same time, the FSM continues to read the next dynamic test group and broadcast it. After the current test task is completed, each BIST controller continues to execute the next test and capture task, and so on until all test tasks are completed; the key information includes scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected feature signature.

[0043] like Figure 2 As shown, in order to achieve deep collaboration between software and hardware in the autonomous testing process of three-dimensional stacked integrated circuits, this invention defines an ultra-long test instruction (VLIW) with a total width of 116 bits, which includes a 3-bit die mask, a 2-bit test mode, a 9-bit scan chain length, a 1-bit result comparison enable, a 4-bit input mask, a 56-bit LFSR seed, a 4-bit output mask, a 4-bit polynomial configuration, a 32-bit expected feature signature, and a 1-bit continuation flag.

[0044] The test instruction is divided into three macroscopic functional areas in its microarchitecture design. Through fine-grained bit-level definitions of ten key fields in the underlying hardware, seamless scheduling and parallel distribution of complex test tasks across multiple cores are ensured. The high 5 bits of the instruction are defined as the target selection control area, its core consisting of a 3-bit die mask and a 2-bit test mode field. The 3-bit die mask establishes a direct mapping relationship with the chip layer, with each logical state corresponding to the activation and enable of a specific level core. This design forms the logical basis for the invention's implementation of "multicast" and "source-side fan-out parallel broadcast," allowing the coordinator FSM to accurately locate the target test node within a single bus cycle. The corresponding 2-bit test mode field defines the instruction execution logic, differentiating between a completely new startup mode (executing a new test group from scratch), a vector flow mode (continuing to send test vectors), and a breakpoint resume mode (continuing testing from the interrupted position). This supports multiple timing collaboration mechanisms in a three-dimensional integrated environment, enabling the multi-core system to flexibly organize the test process according to different test stages. The following 10 bits are designated as the "Test Parameter Configuration Area," consisting of a 9-bit scan chain length field and a 1-bit result comparison enable field. The scan chain length, as the precise counting boundary of the physical shift cycle, directly constrains the number of toggles the hardware counter makes during the scan shift phase. Within this area, the 1-bit result comparison enable bit acts as a switch for on-chip self-diagnostic logic. When this bit is active, the BIST controller automatically activates the hardware comparator after capture, enabling localized determination of the test result within the chip. This significantly reduces the bandwidth dependence on external ATE (ATE) response data (e.g., when set to 1, the hardware automatically compares the captured actual signature with the preset expected signature after the test and directly generates a pass / fail flag; when set to 0, only the signature is captured without automatic comparison). The remaining 101 bits constitute the core instruction set area, integrating core functions such as path control, stimulus generation, and result verification. The 4-bit input and output mask fields respectively demonstrate the invention's fine-grained control over the scan path, enabling the selection of sub-scan chains and shielding the X-state diffusion and irrelevant data shifting into the MISR in irrelevant regions. The mathematical starting point of the excitation source is provided by a 56-bit deep LFSR seed field, ensuring that the pseudo-random sequence covers ultra-large-scale fault requirements. The accompanying 4-bit polynomial configuration field acts as an index to the polynomial read-only memory (Poly_Rom), guiding the BIST controller to switch the feedback polynomial in real time through the reconfigured feedback network (RP-FN) (i.e., selecting one of 16 preset LFSR feedback polynomials from the polynomial read-only memory (Poly_Rom) on this layer of the chip, dynamically changing the statistical characteristics of the test vector).This area also includes a 32-bit expected polynomial field (i.e., signature) as a comparison benchmark (a standard output signature pre-calculated by the Automatic Test Vector Generation (ATPG) tool, corresponding to this test vector set under fault-free circuit conditions, used to ultimately verify whether the test response is correct). The last bit of the instruction set is defined as the Die mask instruction field (i.e., the Continue Flag). This field gives the test stream a linked list organization capability. Based on the level state of this bit, the master control layer can logically aggregate discrete instructions into "dynamic test groups". When the master control layer recognizes that this bit is valid, it will continue to prefetch subsequent instruction payloads until it encounters an instruction whose flag is cleared. All instructions in the same test group occupy consecutive address blocks in PRO_RAM (e.g., test group A occupies addresses 0x00~0x02, test group B occupies addresses 0x03~0x05, with no address gaps). This finely controlled architecture based on a 116-bit instruction set, combined with the atomic switching mechanism between shadow registers and active registers, supports the "zero-bubble" operation of the three-stage pipeline from the hardware level, achieving the optimal match between test bandwidth and execution efficiency.

[0045] It should be noted that this invention innovatively proposes a dynamically configurable hierarchical test instruction format based on a linked list structure, such as... Figure 2 As shown, this instruction format is an improvement on the traditional fixed-length, fixed-field instruction structure. Each test instruction has a total width of 116 bits, and its fields are carefully designed for flexibility and high efficiency. This linked-list organizational structure gives test programs unprecedented flexibility: test programs can be stored non-contiguously in PRO_RAM (here, "non-contiguous" means that different test groups can be stored non-contiguously, i.e., test group A and test group B do not need to be adjacent in PRO_RAM. In other words, the storage space of PRO_RAM can be flexibly allocated, saving idle resources, but the instructions within each test group are still stored contiguously). The instruction group length can be dynamically determined according to the logical relationship of the test content, no longer bound by the fixed frame format. Combined with the space selection capability provided by the Die mask instruction, this instruction system achieves dual dynamic configurability in both the "spatial dimension" (which dies to select) and the "temporal dimension" (how long the instruction group is), allowing almost all on-chip storage and bus transmission resources to be devoted to data directly related to the actual test task.

[0046] like Figure 3As shown, the PTAP controller, as the core access gateway, consists of a microarchitecture comprised of a synchronous front-end subsystem jtag_sync (JTAG synchronization unit), an instruction decoding engine, and a hierarchical status register group including an IFSR data register (instruction feedback shift register) and a MISR data register (multi-input signature register). This architecture aims to address the bottlenecks in 3D-SIC testing from three dimensions: physical layer, protocol layer, and data layer. Addressing the TSV parasitic effect in deep 3D-IC stacking environments, the traditional JTAG architecture, which directly utilizes an external TCK to drive the scan chain, is prone to clock skew and duty cycle distortion, leading to metastability risks in cross-clock domain transmission. Therefore, this design constructs a single-cycle pulse-based synchronous retiming interface jtag_sync at the PTAP front-end. This interface utilizes the on-chip high-speed system clock System... The CLK performs multi-stage oversampling and edge detection on asynchronous input JTAG signals, decoupling the edge-triggered behavior in the protocol into single-cycle level enable signals tck_rise and tck_fall within the system clock domain. This completely decouples the internal instruction decoding and data shifting logic from the external TCK quality, ensuring that signal toggles occur at the rising edge of the system clock. This eliminates the timing violation risk of cross-layer transmission and provides a solid physical guarantee for the stable operation of the subsequent three-stage pipeline under high-speed clocks. The PTAP controller's side facing external test equipment includes the test clock TCK, test mode selection TMS, and other functions. The device includes test input ports such as TDI (Test Data Input) and test output ports such as TDO (Test Data Output). The on-chip side includes extended eTDI / eTDO test data input / output ports, eTCK / eTMS extended test clock / mode selection ports, and control and feedback ports consisting of the Start_Test signal, Start_Pulse_Out signal, Session_Complete_Ack signal, and RTI_or_TLR_Sn signal indicating test / idle or test logic reset status.

[0047] To efficiently coordinate the autonomous operation of the external test equipment (ATE) and the on-chip BIST engine, this invention proposes a session-granular closed-loop handshake communication protocol. It employs a "request-response" state machine mechanism to dynamically manage the test process. The specific process is as follows: The FSM reads test instructions from the PRO_RAM and constructs a dynamic test group. Key information from each instruction in the dynamic test group is broadcast to the corresponding target chip layer's BIST controller. Specifically, this includes:

[0048] A ring buffer is set in the main control chip layer. After the system containing the 3D stack is powered on or reset, the FSM is in the IDLE state, waiting for the test start command from the JTAG interface. When the main control chip layer PTAP receives the start command from the external test device and decodes the INST_START_TEST instruction, it generates a single-cycle Start_Test pulse and sends it to the FSM (activating the internal three-stage pipeline of instruction fetch, broadcast, and execution to enter parallel execution state). The FSM immediately enters the FETCH_INSTR state (instruction read state). In this state, the FSM reads the first test instruction from the specified starting address of PRO_RAM, and at the same time parses the test instruction to obtain its corresponding Die mask instruction, test mode, scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, expected feature signature, and continuation flag. It checks the continuation flag of the instruction. If the continuation flag is valid (e.g., flag is 1), it continues to read subsequent instructions and repeats the execution. The process continues until a test instruction with an invalid continuation flag (0) is read, thus logically constructing a complete dynamic test group. The parsed scheduling metadata corresponding to this dynamic test group is then pushed into the circular buffer. The master control chip layer, acting as the source, leads out a broadcast bus that penetrates the vertical TSV link and synchronously fans out to other chip layers. After reading, the FSM enters the BROADCAST state (broadcast distribution state). In this state, the FSM strictly follows the target chip layer indicated by the die mask of each instruction. Through the broadcast bus fanned out from the master control chip layer to each target chip layer, the FSM transmits the scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected signature of each instruction from the circular buffer to the shadow register of each corresponding target chip layer (that is, the shadow register of the BIST controller of all selected chip layers) in a one-to-many mode, using a serial bit stream. The system waits for all BIST controllers to have received the data.

[0049] In this embodiment, the FSM can function as an instruction fetch unit, interacting directly with the on-chip memory PRO_RAM through the core state machine. It can prefetch a 116-bit very long instruction stream from PRO_RAM. Utilizing the continuation flag at the end of the 116-bit instruction, the FSM can perceive the logical relationships between instructions in real time. When the flag is active, the FSM automatically encapsulates multiple consecutive tasks targeting different chip layers into dynamic batches and pushes the parsed scheduling metadata into a circular buffer. This step achieves seamless integration between offline task organization and on-chip real-time scheduling, providing highly regularized data input for subsequent parallel distribution. It should also be noted that the transmission content for the one-to-many broadcast mode in the BROADCAST state is optimized. It mainly transmits parameters necessary for test execution, including scan chain length, result comparison enable, LFSR seed, polynomial configuration, and expected signature. Fields like the Die mask, which are only used for routing control in test mode, end their purpose after parsing by the top-level FSM and do not need to be broadcast downwards, further saving broadcast time.

[0050] While each BIST controller executes its current test task, the FSM performs a forward-looking operation to check whether the starting address data of the next test group in PRO_RAM is ready (i.e., check the status of the prefetch buffer). If the next test group is not yet ready, the FSM will enter the normal BIST_RUN state (BIST execution waiting state) to wait for the instruction to prefetch the next test group. After the reading and broadcasting are completed, the FSM will enter the BIST_RUN_PARALLEL state (BIST parallel execution state). If the next test group is ready (i.e., the data of the next test group has been prefetched into the on-chip buffer and is available), the FSM will directly read and broadcast, and then enter the BIST_RUN_PARALLEL state.

[0051] In the BIST_RUN_PARALLEL state, the FSM continuously monitors the Test_Done status signal (high level indicates completion) fed back by all target chip layers. If the Test_Done of all target chip layers is high (i.e. all are valid), the MISR of each layer has latched the compressed data into the actual feature signature (i.e. capture is complete), and the shadow registers of each target chip layer corresponding to the next test group have been loaded, the FSM transmits a globally synchronized parallel_load_pulse loading pulse. Driven by this pulse, the parameters of the next batch (scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, expected feature signature) pre-stored in each shadow register will be instantly moved to the corresponding active register within a single clock cycle, thereby triggering the next batch of test tasks to start immediately without any bus waiting, so as to achieve zero-interval task replacement.

[0052] In this embodiment, the FSM can act as a broadcast unit to drive the source fan-out broadcast bus on the physical layer to transmit key information. Its working mechanism reflects the deep optimization of the 3D interconnect topology of this invention. When the BIST controller is in the "idle time slot" of long-time scan shift, the FSM will distribute the key test loads such as LFSR seed, polynomial configuration and scan chain length in the buffer to the shadow register inside each target chip through a single bus transaction, according to the parsed Die mask field. This configuration background loading mechanism compresses the physical delay of instruction distribution from the traditional O(N) cascade growth to a constant O(1), and the entire loading process is completely transparent to the currently running test execution, completely eliminating the scan chain pause caused by waiting for configuration data.

[0053] It should be noted that the MISR (Multiple Input Signature Register) is a response compression circuit commonly used in Built-in Self-Test (BIST) architectures. It uses a linear feedback shift register structure to compress and accumulate the large amount of response data generated by the circuit under test (DUT) cycle by cycle, ultimately forming a fixed-length signature. At the end of the test, the register state in the MISR serves as the final signature for that test, used to compare with the expected signature to determine if a fault exists in the circuit. This MISR-based response compression and signature generation method has been widely used in the field of integrated circuit testing; its specific implementation process will not be elaborated here.

[0054] After the capture is complete, the FSM enters the SESSION_COMPLETE state (test session completed state) and sends a session completion request (Session_Complete_Req) ​​to the host computer. The host computer reads the final feature signatures of each layer through the JTAG interface for subsequent detailed analysis and sends back a response (Session_Complete_Ack). Upon receiving the response from the host computer, the FSM intelligently jumps according to the global test progress: if all test groups have been completed, it returns to the IDLE state; if all test groups have not been completed, it continues execution. This series of state transitions and parallel operations constitutes an efficient, smooth, and non-blocking test pipeline.

[0055] It should be noted that in the BIST_RUN_PARALLEL state, the FSM waits for the test tasks corresponding to the current test group to complete, achieving true task-level parallelism. The test tasks corresponding to the current test group are independently executed by the BIST controller of each target chip layer according to their own heterogeneous characteristics (such as scan chain length and fault mode differences), including controlling scan chain shifting, applying LFSR test vectors, and capturing circuit responses to the multi-input feature register (MISR). Meanwhile, in the BIST_RUN_PARALLEL state, the FSM continuously monitors the Test_Done signal of all target dies, referring to... Figure 5 It can be seen that the timing of "current test execution" and "next test group prefetch / broadcast" overlaps at this stage, and the synchronization logic of the Test_Done signal is the key to avoiding pipeline bubbles.

[0056] Specifically, the process of the BIST controller executing test tasks includes:

[0057] Step 31: The BIST controller uses the polynomial configuration in the key information as an index to read the corresponding control bit from the polynomial read-only memory Poly_Rom, and uses the control bit to configure the reconfigurable feedback network RP-FN, thereby physically changing the feedback loop structure of the LFSR in real time and realizing the dynamic reconfiguration of the feedback polynomial.

[0058] Specifically, once all target chip layer shadow registers have confirmed receipt (via the broadcast_done=1 signal), the FSM enters the BIST_START state (test start state) and sends a globally synchronized parallel_load_pulse load pulse signal to all target chip layers participating in the current test group. Driven by this pulse, the scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected signature pre-stored in the shadow registers are instantaneously shifted to the active register within a single clock cycle, triggering the BIST_START state of each layer. The IST controller begins operation (i.e., executes the test task corresponding to the current test group). The BIST controller, indexed by the value of the polynomial configuration field, reads a set of pre-defined control bits from the local polynomial read-only memory (Poly_Rom) and uses these control bits to precisely configure the closed and open states of each switch in the RP-FN. This changes the feedback loop structure of the LFSR, achieving dynamic reconfiguration of the feedback polynomial. Specifically, the RP-FN is an array of programmable switches (such as transmission gates or multiplexers), and the linear feedback shift register (LFSR) is an array of flip-flops (DFFs). Figure 6 As shown, for a single switch, if it is set to the closed state, the output of the corresponding D flip-flop DFF in the linear feedback shift register LFSR is connected to the feedback network of LFSR and participates in the feedback operation; if it is set to the open state, the corresponding D flip-flop DFF in the linear feedback shift register LFSR does not participate in the feedback operation.

[0059] In this embodiment, a reconfigurable test pattern generator, which is the core of the BIST subsystem, is used within each chip layer, and its structure is as follows: Figure 6 As shown, traditional BIST typically uses a fixed feedback polynomial LFSR, which limits the diversity of test modes. This invention, however, sets a reconfigurable feedback network (RP-FN) at the front end of the linear feedback shift register (LFSR) and pre-defines a polynomial configuration as an index in the test instructions. Before generating a pseudo-random test sequence, the control bit corresponding to the current test task is read from the Poly_Rom using this index. The control bit is then used to configure the RP-FN to reconstruct the feedback loop structure of the LFSR, enabling it to generate a pseudo-random test sequence according to the preset feedback polynomial, thus completing the test task. This allows the same hardware to generate pseudo-random test sequences with different random characteristics and fault detection capabilities according to different test requirements, greatly enhancing the completeness and flexibility of the test.

[0060] Step 32: The BIST controller loads the LFSR seed from the key information into the LFSR. The LFSR uses the seed as the starting point for sequence generation to generate a test sequence. The test sequence enters the test circuit for testing through the gated target scan chain.

[0061] Key information also includes the LFSR seed and scan chain length. The BIST controller determines the selected scan chain and masks irrelevant scan chains based on the input mask. The received LFSR seed is loaded in parallel into the corresponding D flip-flop (DFF) array in the LFSR as the starting point for sequence generation. In test mode, the LFSR generates a test sequence based on the scan chain length. Specifically, a shift update is performed in each scan clock cycle. The outputs on its multiple DFFs are processed by a phase shifter to reduce inter-bit correlation. Then, the test sequences corresponding to each scan chain are driven in parallel to the test circuit for testing.

[0062] Step 33: The test circuit feedback response to the Multiple Input Feature Register (MISR) generates the actual feature signature corresponding to the current test task. The BIST controller performs comparison processing on the actual feature signature based on the result comparison enable in the key information to obtain the test result.

[0063] Specifically, the BIST controller sends the output of the selected scan chain to the Multi-Input Feature Register (MISR) (masking irrelevant scan chains) according to the output mask. During the test, the MISR continuously receives test response data and compresses the response data stream into a unique, fixed-length actual feature signature. The FSM continuously monitors the Test_Done status signal (high level indicates completion) fed back by all target chip layers. After the test, if the Test_Done of all target chip layers is high (fault-free die waiting for slow execution die to complete), the FSM enters the MISR_CAPTURE state (MISR response capture state) after a delay of 1 TCK clock cycle. If the Test_Done signal of some chip layers exceeds the preset timeout threshold (which can be checked via J... The TAG configuration (default value is twice the maximum scan chain shift period) remains low throughout the test. The FSM automatically marks the target chip layer as a test timeout fault and forces its Test_Done to high to avoid global blocking. Simultaneously, it records the ID of the timeout chip layer to the on-chip fault status register (Fault_Status_Reg). Then, it enters the MISR_CAPTURE state (the current test group has completed execution, including timeout processing; i.e., Test_Done for each target chip layer is high), and issues a globally synchronized MISR_Latch capture signal. The MISR of each target chip layer solidifies the compressed response data into the final feature signature. The signature of the timeout fault chip layer is marked as "invalid" and does not participate in subsequent result comparisons. The BIST controller reads the result comparison enable bit. If the result comparison enable bit is valid (e.g., 1 for valid, 0 for invalid), it compares the expected feature signature in the actual feature signature key information in the local MISR using a hardware comparator to generate the localized test result for that chip layer. If the result comparison enable bit is invalid, no comparison is performed.

[0064] It should be noted that the test sequence is shifted and loaded into the flip-flops or logic units inside the test circuit through a scan chain. This is used to apply test stimuli to the circuit under test and drive the circuit to generate a corresponding response signal under the action of the test clock. This test process of applying a test vector to the test circuit and obtaining the circuit response is a common method, and the specific implementation process will not be described in detail here.

[0065] As the test progresses, when the FSM detects that all test batches in the current session have been completed, it actively pulls the session_req signal high to initiate a completion request. During the test, the ATE polls this status bit by periodically sending INST_SESS_REQ instructions. Once the request is detected, it confirms that the on-chip task is completed and enters the result processing stage. Finally, it generates a Session_Complete_Ack pulse by sending an INST_SESS_ACK instruction to clear the internal status and release bus control, thus achieving seamless connection between sessions.

[0066] To further alleviate the bandwidth bottleneck caused by reading massive test data from 3D-ICs, this invention integrates a hierarchical diagnostic mechanism in the backend, implementing a "state-priority screening, data-on-demand diagnosis" strategy. First, a first-level state screening is performed, utilizing the IFSR DR register maintained by PTAP to collect the Done and Pass / Fail flags for each chip layer in real time. The ATE prioritizes reading the extremely low-width IFSR DR via the JTAG interface. If all flags show a pass, the test is directly considered successful, and subsequent data reading is skipped, significantly reducing the testing time for good chips. Only when the IFSR DR indicates a fault at a specific level does the ATE activate the second-level on-demand diagnostic mechanism. The ATE sends an INST_MISR_READ instruction to switch the data path to the wide-width MISR DR register. At this point, the system serially shifts out the 32-bit complete signature data accumulated at the fault layer. This hierarchical strategy minimizes invalid data throughput. While ensuring fault location accuracy, it significantly improves the effective utilization of the test bus and the overall system throughput in conjunction with the parallel scheduling of the three-level pipeline.

[0067] The invention innovatively provides an intelligent data sharing and broadcasting test mechanism for homogeneous IP (corresponding to step 2), illustrated using three stacked chips as an example. This mechanism fully utilizes the hardware redundancy characteristics present in the stacked chips, such as... Figure 1As shown, multiple chip layers in the stack (e.g., Die1, Die2, Die3) integrate identical hardware intellectual property (IP) modules (such as the same processor core, cache, or interface controller). During the test configuration phase, the host computer first programs the broadcast control bit (BCB) registers of the relevant chip layers through a precise JTAG interface. For example, the BCB of Die1 is configured as a "broadcast sender," while the BCBs of Die2 and Die3 are configured as "broadcast receivers." This configuration operation physically establishes a dedicated test data broadcast path from Die1 to Die2 and Die3. Subsequently, only one copy of the test instructions and LFSR seed data for this common IP module needs to be stored in PRO_RAM. When the test coordinator FSM processes this instruction, because its Die mask is set to 001 (input to the first layer), the test mode field is set to 01 (the current Die acts as a broadcast source to send data to other layers), and the BCB path has been pre-established, the test parameters in this instruction (especially the LFSR seed) are automatically and synchronously transmitted to the corresponding BIST subsystems of Die2 and Die3 through the activated hardware broadcast path, while being read from PRO_RAM and prepared for application to Die1's own BIST engine. Simultaneously, the scan insertion bits (SIBs) of Die1, Die2, and Die3 are independently configured via the JTAG interface, ensuring that each chip layer selects only the scan chain directly connected to the common IP module, while masking scan chains connected to other logic modules. After configuration, the three chip layers use identical LFSR seeds and feedback polynomial configurations to drive IP modules with identical internal circuit structures, executing completely identical test sequences in parallel. Storage efficiency has been optimized. Vector seeds for testing the same IP only need to be stored once in the stack, saving (N-1) / N storage space (N is the number of layers containing the same IP). At the same time, the amount of configuration data transmitted has been greatly reduced, replacing multiple separate loads with a single broadcast.

[0068] It should also be noted that, since the test stimulus and the logic under test are completely identical at the hardware level, assuming no manufacturing defects, the three chip layers should generate completely identical test response signatures. By comparing the signatures generated by each layer for the same test, faults introduced by manufacturing process deviations of specific chip layers can be identified and located very efficiently. This is of great value for yield analysis, fault diagnosis, and reliability improvement of 3D-SIC. This invention constructs a complete solution from test data injection, dynamic instruction organization, parallel process scheduling, to flexible test engine configuration and intelligent data sharing, providing a highly efficient, flexible, resource-saving, and autonomous testing method for 3D stacked chips.

[0069] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0070] The units in the device of the present invention can be merged, divided, or reduced according to actual needs.

[0071] In this invention, the terms "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; "linking" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of these terms in this invention according to the specific circumstances.

[0072] The shapes of the components in the accompanying drawings are schematic and may differ from their actual shapes. The drawings are only used to illustrate the principles of the present invention and are not intended to limit the present invention.

[0073] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various modifications, alterations, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. A three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting, characterized in that, The master control chip layer in the stacked chips integrates a program memory (PRO_RAM), a test coordinator (FSM), and a USB controller. Each chip layer is vertically interconnected via through-silicon vias (TSVs). Each chip layer is equipped with a BIST controller containing a shadow register and an active register. The method includes: Step 1: Load the required 116-bit format test command stream into the PRO_RAM of the main control chip layer in batches via the USB controller; Step 2: Send configuration data through the TAG interface and cascaded TSV path to complete the initialization of each chip layer, including configuring the scan insertion bit SIB and broadcast control bit BCB to activate the hardware broadcast path and select the target scan chain. Step 3: Use FSM to read test instructions from PRO_RAM and construct a dynamic test group. Broadcast the key information of each instruction in the group to the BIST controller of the corresponding target chip layer. Each BIST controller executes the test and capture tasks according to the key information. At the same time, FSM continues to read the next dynamic test group and broadcast it. After the current test task is completed, each BIST controller continues to execute the next test and capture task. The key information includes scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected feature signature. The test process is as follows: Step 31: The BIST controller reads the corresponding control bit from the polynomial read-only memory Poly_Rom using the polynomial configuration as the index, and uses the control bit to configure the reconfigurable feedback network RP-FN to change the feedback loop structure of the linear feedback shift register LFSR. Step 32: The BIST controller loads the LFSR seed into the LFSR. The LFSR generates a test sequence starting from the seed. The test sequence enters the test circuit for testing through the selected scan chain. Step 33: The Multi-Input Feature Register (MISR) receives the feedback response from the test circuit and generates the actual feature signature. The BIST controller compares and processes the actual feature signature based on the result comparison enable to obtain the test result.

2. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 1, characterized in that, Step 3 specifically includes: A circular buffer is set up in the main control chip layer. After the system is powered on or reset, the FSM is in the IDLE state. When the PTAP of the main control chip layer receives the start command issued by the external test device and decodes the INST_START_TEST instruction, a single-cycle Start_Test pulse is generated, and the FSM enters the FETCH_INSTR state. In this state, the FSM reads the first test instruction from the specified starting address of PRO_RAM. At the same time, it parses the test instruction to obtain its corresponding Die mask instruction, test mode, scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, expected feature signature, and continuation flag. It checks the continuation flag of the instruction. If the continuation flag is valid, it continues to read subsequent instructions until a test instruction with an invalid continuation flag is read, thus constructing a complete dynamic test group. The parsed data corresponding to the dynamic test group is pushed into the circular buffer. The master control chip layer leads out a broadcast bus as the source end. This broadcast bus penetrates the vertical TSV link and synchronously fans out to other chip layers. The FSM enters the BROADCAST state. In this state, the FSM addresses the target chip layer according to the die mask of each instruction. It also synchronously sends the scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected signature of each instruction from the ring buffer to the shadow register of the corresponding target chip layer through the broadcast bus fanned out from the master control chip layer to each target chip layer.

3. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 2, characterized in that, Step 3 also includes: While each BIST controller is executing the current test task, the FSM checks whether the starting address data of the next test group in PRO_RAM is ready. If not, it enters the normal BIST_RUN state and waits for the instruction to fetch the next test group. After the reading and broadcasting are completed, the FSM will enter the BIST_RUN_PARALLEL state. If it is ready, it will directly read and broadcast, and then enter the BIST_RUN_PARALLEL state.

4. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 3, characterized in that, Step 3 also includes: In the BIST_RUN_PARALLEL state, the FSM continuously monitors the Test_Done status signals fed back by all target chip layers. When the Test_Done of all target chip layers is high, the actual feature signature is latched by the MISR of each layer, and the shadow registers corresponding to the next test group are loaded, the FSM transmits a globally synchronized parallel_load_pulse loading pulse. Under the drive of this pulse, the data corresponding to the next test group pre-stored in each shadow register will be instantly moved to the corresponding active register within a single clock cycle, thereby triggering the start of the next test task. After the MISR latches the actual feature signature, the BIST controllers at each layer execute the test and capture tasks corresponding to the next test group. At the same time, the FSM enters the SESSION_COMPLETE state and sends a session completion request to the host computer. The host computer reads the actual feature signature of each layer through the JTAG interface and sends back a response. After receiving the response from the host computer, if all test groups have been completed, the FSM returns to the IDLE state; if all test groups have not been completed, execution continues.

5. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 2, characterized in that, Step 31 specifically includes: Once all target chip layer shadow registers have been received, the FSM enters the BIST_START state and sends a globally synchronized parallel_load_pulse load pulse signal to all target chip layers participating in the current test group. Driven by this pulse, the scan chain length, result comparison enable, input mask, LFSR seed, output mask, polynomial configuration, and expected signature pre-stored in the shadow registers are instantaneously moved to the active register within a single clock cycle, triggering the BIST controllers of each layer to begin operation. The BIST controllers use the value of the polynomial configuration field as an index to retrieve data from their local polynomial registers. The corresponding set of pre-set control bits is read from the Poly_Rom memory, and these control bits are used to precisely configure the closed and open states of each switch in the RP-FN to change the feedback loop structure of the LFSR. Specifically, the RP-FN is an array of programmable switches, and the linear feedback shift register LFSR is an array of flip-flops (DFFs). For a single switch, if it is set to the closed state, the output of the corresponding flip-flop (DFF) in the LFSR participates in the feedback operation; if it is set to the open state, the output of the corresponding flip-flop (DFF) in the LFSR does not participate in the feedback operation.

6. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 5, characterized in that, Step 32 specifically includes: The BIST controller determines the selected scan chain based on the input mask and masks irrelevant scan chains. It loads the received LFSR seed into the corresponding DFF array in the LFSR in parallel as the starting point for sequence generation. In test mode, the LFSR generates a test sequence based on the scan chain length and performs shift updates in each scan clock cycle. The outputs on its multiple DFFs are processed by a phase isolator to reduce inter-bit correlation. Then, the test sequences corresponding to each scan chain are driven in parallel to be input to the test circuit for testing.

7. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 6, characterized in that, Step 33 specifically includes: The BIST controller sends the output of the selected scan chain to the Multi-Input Feature Register (MISR) based on the output mask. During the test, the MISR continuously receives test response data and compresses the response data stream into a unique, fixed-length actual feature signature. The FSM continuously monitors the Test_Done status signals fed back by all target chip layers. If the Test_Done signals of all target chip layers are high, the FSM enters the MISR_CAPTURE state after a one-TCK clock delay. If the Test_Done signals of some chip layers remain low within a preset timeout threshold, the FSM automatically marks that target chip layer as having timed out. The system detects a fault and forces its Test_Done value to high to avoid global blocking. Simultaneously, it records the ID of the timed-out chip layer to the on-chip fault status register, then enters the MISR_CAPTURE state and issues a globally synchronized MISR_Latch capture signal. The MISRs of each target chip layer solidify the compressed response data into the final feature signature. The BIST controller reads the result comparison enable bit. If the result comparison enable bit is valid, it compares the expected feature signature in the key information of the actual feature signature in the local MISR using a hardware comparator to generate the localized test result for that chip layer. If the result comparison enable bit is invalid, no comparison is performed.

8. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 1, characterized in that, Each chip layer in the three-dimensional stack is equipped with a Test Access Port (PTAP) and a Secondary Test Access Port (STAP) conforming to the IEEE 1838 standard. The PTAP and STAP of each chip layer are cascaded and coupled through TSV to achieve debugging path, and the PTAP of the master control chip layer is connected to the external test equipment as the only physical access window.

9. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 1, characterized in that, Step 2 specifically includes: The external test equipment first sends a JTAG signal to the PTAP of the main control chip layer. The PTAP of the main control chip layer forwards the signal sequentially to the STAP of each target chip layer through the inter-layer cascaded TSV path. The STAP of each target chip layer transmits the received JTAG signal to the TAP controller inside its own chip layer, so that the TAP controllers of each target chip layer run the JTAG state machine synchronously under the same JTAG clock TCK. In the configuration start phase, the external test equipment controls the TAP controller to enter the Shift-IR state through the TMS and serially inputs the BCB register access instruction through the TDI port. This instruction is shifted into the instruction register of each chip layer sequentially through the PTAP and cascaded STAP paths. The external test equipment controls the TAP controller. The device enters the Update-IR state. Each layer of the TAP controller decodes the instructions in the instruction register and selects each SIB register as the currently accessed data register based on the decoding result. Then, the external test equipment controls the TAP controller to enter the Shift-DR state and serially inputs the SIB configuration data through the TDI port. The data is then shifted sequentially into the shift units of the corresponding SIB registers of each chip layer through the PTAP and cascaded STAP paths. For SIBs that need to be selected, the configuration data is set to 1, and for SIBs that are not selected, the configuration data is set to 0. After completion, the external test equipment controls the TAP controller to enter the Update-DR state. Each chip layer's SIB register latches the data in the shift unit to the configuration latch, completing the configuration.

10. The three-dimensional stacked chip testing method based on multi-interface collaboration and parallel broadcasting as described in claim 9, characterized in that, Step 1 specifically includes: The USB controller is connected to the host computer through an external USB physical layer chip to form a high-speed data preloading channel. Before the test sequence is officially started, the USB controller uses burst mode to preload the host computer with a large-scale test instruction stream generated offline into the PRO_RAM of the main control chip layer at high speed and in batches through this channel.

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