Current mirror, gate driver and method for controlling output current

Abstract

Disclosed herein are current mirrors, gate drivers, and methods for controlling output current. A current mirror circuit includes a first current source to provide a first reference current, a first transistor having a control terminal, a first current terminal coupled to receive the first reference current, and a second current terminal coupled to a reference potential, a second transistor having a control terminal coupled to the control terminal of the first transistor, a first current terminal coupled to an output node of the current mirror circuit, and a second current terminal coupled to the reference potential, and a matching circuitry having an input coupled to the output node of the current mirror circuit and an output coupled to the first current terminal of the first transistor, the matching circuitry configured to provide a replica voltage at the first current terminal of the first transistor corresponding to a voltage at the output node of the current mirror circuit.

Description

Technical Field

[0001] This disclosure relates to a current mirror, a gate driver including the current mirror, and a method for controlling an output current. Background Technology

[0002] Due to the existence of both high-current mirrors capable of supplying currents of 1.2 A and above, and cascode structures, implementing high-current and high-precision current mirrors typically requires a large area. In conventional current mirrors, cascode structures can be used to provide the necessary robustness against VDS modulation (drain-source voltage modulation) to deliver currents on the order of several amperes while maintaining good accuracy.

[0003] In high-voltage (HV) applications, cascode structures can be implemented using high-rated MOS transistors to protect the underlying low-voltage mirror, where VDS (drain-source voltage) can be as high as, for example, 36 V. However, in some cost-competitive technologies (such as junction isolation), the maximum voltage difference between the source / body and the substrate is limited to 300 mV, meaning that HV devices with the necessary rated voltage for use as cascode structures are unavailable. Therefore, it is not possible to implement HV mirrors with cascode structures in such technologies without using voltage extensions based on complex and expensive techniques. Implementing conventional HV current mirrors without cascode structures can result in a significant performance degradation. Summary of the Invention

[0004] The features of the invention are set forth in the appended claims.

[0005] According to a first aspect of this disclosure, a current mirror circuit is provided, comprising: a first current source for providing a first reference current; a first transistor having a control terminal, a first current terminal coupled to receive the first reference current, and a second current terminal coupled to a reference potential; a second transistor having a control terminal coupled to the control terminal of the first transistor, a first current terminal coupled to an output node of the current mirror circuit, and a second current terminal coupled to the reference potential; and a matching circuit system having an input coupled to the output node of the current mirror circuit and an output coupled to the first current terminal of the first transistor, the matching circuit system being configured to provide a replicated voltage at the first current terminal of the first transistor corresponding to the voltage at the output node of the current mirror circuit.

[0006] By replicating the voltage at the first current terminal of the second transistor at the first current terminal of the first transistor, the matching circuit system can mitigate the VDS modulation effect in the current mirror circuit. Therefore, the current mirror circuit of this disclosure can implement a non-cascode current mirror with performance comparable to that of a conventional cascode low-voltage (LV) current mirror. Furthermore, the current mirror of this disclosure provides higher headroom than the cascode current mirror circuit. Advantageously, this disclosure can be applied to any conventional current mirror, regardless of its specific application.

[0007] In some embodiments, each of the first transistor and the second transistor is a high-voltage transistor.

[0008] When applied to high-voltage applications, significant area savings can be achieved because the present invention enables the implementation of a non-cascode high-voltage (HV) current mirror with performance comparable to that of a conventional cascode low-voltage (LV) current mirror.

[0009] In some embodiments, the replicated voltage is a 1:1 copy of the voltage at the output node of the current mirror circuit.

[0010] In some embodiments, the control terminal of the first transistor is coupled to the first current terminal of the first transistor via a switch.

[0011] When the switch is closed, the current mirror circuit can operate as a simple current mirror. Therefore, the switch allows the current mirror to be selectively reconfigured between a simple current mirror mode and a precise current mirror mode.

[0012] In some embodiments, the first current terminal of the second transistor is directly connected to the output node of the current mirror circuit.

[0013] In some embodiments, the matching circuit system includes: a third transistor having a control terminal, a first current terminal, and a second current terminal, the first current terminal being coupled to the control terminal of the third transistor; a fourth transistor having a control terminal, a first current terminal, and a second current terminal, the control terminal being coupled to the control terminal of the third transistor; a second current source configured to control a second reference current between the first current terminal and the second current terminal of the third transistor; and a third current source configured to control a third reference current between the first current terminal and the second current terminal of the fourth transistor; wherein the second current terminal of the fourth transistor is coupled to the first current terminal of the first transistor.

[0014] The input of the matching circuit system can be coupled to the second current terminal of the third transistor. The output of the matching circuit system can be coupled to the second current terminal of the fourth transistor.

[0015] Advantageously, the matching circuit system provides open-loop matching between the voltage at the first current terminal of the second transistor and the voltage at the first current terminal of the first transistor, thereby enabling the current mirror circuit to perform real-time VDS modulation compensation.

[0016] In some embodiments, the matching circuit system further includes: a fourth current source configured to provide a fourth reference current to a second current terminal of the third transistor, wherein the fourth reference current is equal to the second reference current; and a fifth current source configured to provide a fifth reference current to the second current terminal of the fourth transistor, wherein the fifth reference current is equal to the third reference current.

[0017] Including a fourth and fifth current source in the matching circuit system helps prevent the third and fourth transistors from drawing current from the output node and the first current source, respectively.

[0018] In some embodiments, the first reference current is equal to the second reference current.

[0019] In some embodiments, the first current terminal of the fourth transistor is coupled to the control terminal of the first transistor.

[0020] This feature helps to provide a charging / discharging path for the control terminal of the first transistor without adversely affecting the operation of the matching circuit system.

[0021] In some embodiments, the first and second transistors are NMOS transistors, and the third and fourth transistors are PMOS transistors.

[0022] In some embodiments, the first and second transistors are PMOS transistors, and the third and fourth transistors are NMOS transistors.

[0023] In embodiments where the first, second, third, and fourth transistors are MOS transistors, the control terminal, first current terminal, and second current terminal of a corresponding transistor may correspond to the gate, drain, and source of the corresponding transistor, respectively.

[0024] In some embodiments, the first and second transistors are NPN transistors, and the third and fourth transistors are PNP transistors.

[0025] In some embodiments, the first and second transistors are PNP transistors, and the third and fourth transistors are NPN transistors.

[0026] In embodiments where the first, second, third, and fourth transistors are bipolar junction transistors, the control terminal, first current terminal, and second current terminal of a corresponding transistor may correspond to the base, collector, and emitter of the corresponding transistor, respectively.

[0027] According to a second aspect of this disclosure, a gate driver is provided, which includes a current mirror circuit according to the first aspect defined above.

[0028] In some embodiments, the output node of the current driver circuit is coupled to the gate of the power transistor.

[0029] The gate driver can be a high-voltage gate driver.

[0030] The gate driver can be configured to implement controlled shutdown.

[0031] According to a third aspect of this disclosure, a method for generating an output current is provided, the method comprising: providing a first reference current between a first current terminal and a second current terminal of a first transistor; generating an output current between a first current terminal and a second current terminal of a second transistor, wherein a control terminal of the second transistor is coupled to a control terminal of the first transistor; and providing a voltage at the first current terminal of the first transistor corresponding to a voltage at the first current terminal of the second transistor.

[0032] In some embodiments, the step of providing a voltage at a first current terminal of a first transistor corresponding to the voltage at a first current terminal of a second transistor includes: controlling a second reference current between a first current terminal and a second current terminal of a third transistor, wherein the first current terminal of the third transistor is coupled to a control terminal of the third transistor, and wherein the second current terminal of the third transistor is coupled to the first current terminal of the second transistor; controlling a third reference current between a first current terminal and a second current terminal of a fourth transistor, wherein the control terminal of the fourth transistor is coupled to the control terminal of the third transistor; wherein the second current terminal of the fourth transistor is coupled to the first current terminal of the first transistor.

[0033] In some embodiments, the second reference current is equal to the third reference current.

[0034] In some embodiments, a first current terminal of the second transistor is coupled to the gate terminal of the power transistor, and the method further includes controlling the output current to cause the voltage at the gate terminal of the power transistor to discharge stably. Attached Figure Description

[0035] A more complete understanding of the subject matter can be derived by referring to the following figures, with reference to the specific embodiments and claims. The same appendage marks are used throughout the figures to refer to similar elements.

[0036] Figure 1 An example common-source cascode current mirror circuit is schematically shown;

[0037] Figure 2 A non-cascode current mirror circuit according to an exemplary embodiment of the present disclosure is schematically shown;

[0038] Figure 3 A non-cascode current mirror circuit according to another exemplary embodiment of the present disclosure is schematically shown;

[0039] Figure 4 This illustration schematically shows example embodiments of the present disclosure including... Figure 2 The voltage gate driver of the non-cascode current mirror circuit; and

[0040] Figure 5 A method for controlling the output current according to an exemplary embodiment of the present invention is shown. Detailed Implementation

[0041] The following detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the terms "exemplary" and "example" mean "serving as an example, instance, or illustration." Any embodiment described herein as exemplary or illustrative is not to be construed as preferred or advantageous over other embodiments. Furthermore, one is not to be bound by any express or implied theory presented in the foregoing technical field, background art, or the appended specific embodiments.

[0042] Figure 1 An example cascode current mirror circuit 100 is schematically shown, which includes a low-voltage (LV) current mirror 102 and a high-voltage (HV) cascode structure 104.

[0043] The LV current mirror 102 includes a first NMOS transistor 122 and a second NMOS transistor 124.

[0044] The gate 126 of the first NMOS transistor 122 and the gate 128 of the second NMOS transistor 124 are coupled to each other and to the drain 130 of the first NMOS transistor 122. The LV current mirror 102 is biased by a current source 106 coupled between the positive power supply potential VCC and the drain 130 of the first NMOS transistor 122. The drain 132 of the second NMOS transistor 124 is coupled to the HV cascode structure 104. The sources 134 of the first transistor 122 and 136 of the second transistor 124 are coupled to the negative power supply potential VEE. The current source 106 is configured to output a constant current IB1 such that the drain-source current of the first NMOS transistor 122 has a value of IB1 when it is turned on in its "on" state. The current mirror ratio of the LV current mirror 102 is 1:K, such that the drain-source current of the second NMOS transistor 124 has a value of IB1xK when it is turned on in its "on" state.

[0045] The HV cascode structure 104 includes an HV cascode transistor 142 in the form of an NMOS transistor 142, the source 144 of which is coupled to the drain 132 of a second NMOS transistor 124 of the LV current mirror 102. The gate 146 of the HV cascode transistor 142 is coupled to a control signal for switching the drain-source current of the HV cascode transistor 142. The drain 148 of the HV cascode transistor 142 is coupled to a node GL 108, which is charged or discharged by a constant current. For example, node GL 108 may be coupled to the gate of an external device, such that the cascode current mirror circuit 100 acts as a gate driver for the external device.

[0046] As an example, node GL 108 might need to discharge from up to 25 V to -10 V with a constant current. The HV cascode structure / switch 104, 142 allows the LV current mirror 102 to have a nearly constant drain-source voltage VDS throughout this transition. For example, the HV cascode structure 104, 142 can keep the current stable near the correct value (e.g., 1.2 A) during transitions. In a gate driver, this can be used to implement controlled shutdown in the event of a fault condition.

[0047] However, the HV cascode structures 104 and 142 need to be very large to ensure headroom for the LV current mirror 102 throughout the transition between its initial and final voltages when discharging at node GL 108. In some techniques, such as junction isolation, there is no HV NMOS available with a sufficient voltage rating for use in a cascode configuration.

[0048] Figure 2A non-cascode current mirror circuit 200 according to an example embodiment of the present disclosure is schematically shown. The non-cascode current mirror circuit 200 includes a high-voltage (HV) current mirror 202, a first current source 206, and a matching circuit system 300, wherein the first current source 206 is configured to output a first reference current IB1.

[0049] The HV current mirror 202 includes a first transistor M1 222 and a second transistor M2 224. In this embodiment, both the first transistor M1 222 and the second transistor M2 224 are NMOS transistors. The first (NMOS) transistor M1 222 includes a control terminal 226 in the form of a gate 226, a first current terminal 228 in the form of a drain 228, and a second current terminal 230 in the form of a source 230. The second (NMOS) transistor M2 224 also includes a control terminal 232 in the form of a gate 232, a first current terminal 234 in the form of a drain 234, and a second current terminal 236 in the form of a source 236. The drain 228 of the first transistor M1 222 is coupled to receive a first reference current IB1 from the first current source 206. The source 230 of the first (NMOS) transistor M1 222 and the source 236 of the second (NMOS) transistor M2 224 are coupled to a reference potential in the form of a negative power supply potential VEE. The gate 226 of the first (NMOS) transistor M1 222 and the gate 232 of the second (NMOS) transistor M2 224 are coupled to each other. The drain 234 of the second (NMOS) transistor M2 224 is coupled to the output node GL 208 of the current mirror circuit 200.

[0050] The gate 226 of the first (NMOS) transistor M1 222 can be selectively coupled to the drain 228 of the first (NMOS) transistor M1 222 via switch SW1 237. Closing switch SW1 237 allows the current mirror circuit 200 to be reconfigured as a simple current mirror. However, when the current mirror circuit 200 is operating as a precision current mirror, switch SW1 237 is open.

[0051] The HV current mirror 202 is biased by a first current source 206 coupled between the positive power supply potential VCC and the drain 228 of the first (NMOS) transistor M1 222. The current source 206 is configured to output a current IB1 such that the drain-source current of the first (NMOS) transistor M1 222 has a value IB1 when it is turned on in its "on" state. The matching circuit system 300 includes an input 302 coupled to the output node GL 208 of the current mirror circuit 200 and an output 304 coupled to the first drain 228 of the first (NMOS) transistor M1 222. The matching circuit system 300 is configured to provide a replica voltage GL_copy at the first drain 228 of the first transistor M1 222, corresponding to the voltage GL at the output node GL 208 of the current mirror circuit 200. Therefore, the current through the second transistor M2 224 mirrors the current through the first transistor M1 222. The current mirror ratio of the HV current mirror 202 (determined by the relative specifications of the first transistor M1 222 and the second transistor M2 224) is 1:K, such that the drain-source current of the second (NMOS) transistor M2 224 has a value IB1xK when it is turned on in its "on" state.

[0052] The matching circuit system 300 further includes a third transistor M3 322, a fourth transistor M4 324, and a second current source 332, a third current source 334, a fourth current source 336 and a fifth current source 338.

[0053] In this embodiment, both the third transistor M3 322 and the fourth transistor M4 324 are PMOS transistors. The third transistor M3 322 includes a control terminal 326 in the form of a gate 326, a first current terminal 328 in the form of a drain 328, and a second current terminal 330 in the form of a source 330. The input 302 of the matching circuit system 300, which is coupled to the output node GL 208 of the current mirror circuit 200, is also coupled to the source 330 of the third transistor M3 322. The gate 326 and drain 328 of the third transistor M3 322 are coupled together. The fourth transistor M4 324 includes a control terminal 332 in the form of a gate 332, a first current terminal 334 in the form of a drain 334, and a second current terminal 336 in the form of a source 336. The gate 332 of the fourth transistor M4 324 is coupled to the gate 326 of the third transistor M3 322. The source 336 of the fourth transistor M4 324 is coupled to the output 304 of the matching circuit system 300, and the output 304 itself is coupled to the drain 228 of the first transistor M1 222.

[0054] A second current source 332 is coupled between the drain 328 of the third transistor M3 322 and the negative power supply potential VEE, and is configured to output a second reference current IB2. A third current source 334 is coupled between the drain 334 of the fourth transistor M4 324 and the negative power supply potential VEE, and is configured to provide a third reference current IB2. A fourth current source 336 is coupled between the positive power supply potential VCC and the source 330 of the third transistor M3 322, and is configured to provide a fourth reference current IB2. A fifth current source 338 is coupled between the positive power supply potential VCC and the source 336 of the fourth transistor M4 324, and is configured to provide a fifth reference current IB2. In this embodiment, each of the second, third, fourth, and fifth reference currents provided by the second current source 332, the third current source 334, the fourth current source 336, and the fifth current source 338 has the same value IB2.

[0055] With switch SW1 237 in the "OFF" state, the matching circuit system 300 generates a copy of the voltage at output node GL 208 at its output 304. The voltage at the gate 326 of the third transistor M3 322 is shifted downward by an amount Vgs relative to the voltage at output node GL 208, where Vgs is the gate-source voltage of the third transistor M3 322. Because the gate 326 and drain 328 of the third transistor M3 322 are coupled together, the value of the shifted Vgs is effectively fixed by the drain-source current of the third transistor M3 322, which is controlled by the second current source 332 to the value IB2. The voltage at the source 336 of the fourth transistor M4 324 is shifted upward by the same amount Vgs relative to the voltage at the gate 332 of the fourth transistor M4 324, where Vgs is the gate-source voltage of the fourth transistor M4 324. In this example embodiment, the gate-source voltage Vgs of the third transistor M3 322 and the fourth transistor M4 324 are the same because they are matched devices with the same gate voltage and are biased using the same current IB2. Therefore, the voltage at the output 304 of the matched circuit system 300, and consequently the voltage at the drain 228 of the first (NMOS) transistor M1 222, is a 1:1 copy of the voltage at node GL 208. While a 1:1 ratio is preferred, a small mismatch between the values ​​will only have a second-order effect on the output current of the current mirror circuit.

[0056] In this embodiment, the presence of a third current source 336, which provides a reference current IB2 equal to the reference current provided by the first current source 332, ensures that the third transistor M3 322 does not draw current from the output node GL 208. However, in other embodiments, the third current source 336 may be omitted. Similarly, the presence of a fourth current source 338, which provides a reference current IB2 equal to the reference current provided by the second current source 334, ensures that the fourth transistor M4 324 does not draw current from the first current source 206. However, in other embodiments, the fourth current source 338 may be omitted, or the fourth current source 338 may be effectively combined with the first current source 206.

[0057] With switch SW1 237 open, the gate 226 of the first transistor M1 222 must adjust itself to allow current IB1 to flow through the first transistor M1 222. The coupling from the gate 226 of the first transistor M1 222 to the drain 334 of the fourth transistor M4324 provides a suitable path for charging / discharging the gate 226 as needed. However, in other embodiments, different paths may be provided.

[0058] Therefore, the HV mirror 202 of the current mirror circuit 200, including the first transistor M1 222 and the second transistor M2 224, will accurately mirror the current IB1xK at the output node 208 of the current mirror circuit 200, wherein the first transistor M1 222 is biased by the current IB1 and its drain-source voltage Vds is matched with the voltage at the output node GL 208. The output current IB1xK is regulated by open-loop control to avoid causing delay.

[0059] In some embodiments, the current mirror circuit 200 may be programmable or adjustable, for example, to control the values ​​of IB1, IB2, and / or K. In some applications, the values ​​of IB1, IB2, and / or K may be kept constant.

[0060] By mitigating the VDS modulation effect, the current mirror circuit 200 is able to implement a non-cascode high-voltage (HV) current mirror with performance comparable to that of a conventional cascode low-voltage (LV) current mirror.

[0061] The current mirror circuit 200 provides real-time sensing and scaling of the voltage at the output node GL 208 by matching the drain-source voltage of the first transistor M1 222 with the drain-source voltage of the second transistor M2 224 (i.e., the voltage at the output node GL 208 of the current mirror circuit 200). Therefore, the current mirror circuit 200 is capable of performing real-time VDS modulation compensation.

[0062] Figure 2 The configuration of the non-cascode current mirror circuit 200 also ensures that... Figure 1The cascode current mirror circuit 100 provides higher headroom. This enables linear voltage transition behavior to be maintained over a wider voltage range when a constant current is discharged from the main capacitive external gate node coupled to the output node GL 208.

[0063] The absence of an HV cascode transistor allows for the implementation of a current mirror circuit 200 using cost-saving techniques such as junction isolation, which do not provide an HV MOS that can be used in a cascode configuration due to the maximum voltage drop between its source and substrate voltages.

[0064] When switch SW1 237 is closed, the non-cascode current mirror 200 is effectively configured as a simple current mirror. By opening switch SW1 237, the non-cascode current mirror 200 is reconfigured as a precise current mirror due to the presence of the matching circuit system 300. Therefore, the matching circuit system 300 can improve the performance of any simple current mirror.

[0065] The non-cascode current mirror circuit 200 does not require a cascode structure, and thus enables a significant reduction in die area while maintaining the same performance as the cascode structure.

[0066] Although the HV mirror 202 is configured for high-voltage applications in this example embodiment, those skilled in the art will understand that the HV mirror 202 can be made from an LV mirror (e.g., Figure 1 The LV mirror 102 is replaced for applications where the voltage at node GL 108 changes between low voltages.

[0067] In the embodiment of the current mirror circuit 200 described above, the first and second transistors are NMOS transistors, the third and fourth transistors are PMOS transistors, and the control terminal, first current terminal, and second current terminal of each transistor correspond to its gate terminal, drain terminal, and source terminal, respectively. Those skilled in the art will understand that in other embodiments of the current mirror circuit, the first and second transistors may be PMOS transistors, and the third and fourth transistors may be NMOS transistors, with the control terminal, first current terminal, and second current terminal of each transistor similarly corresponding to their respective gate terminal, drain terminal, and source terminal. In such embodiments, the reference potential defined in the claims will correspond to a high power supply voltage rail. Those skilled in the art will further understand that other embodiments exist, wherein (i) the first and second transistors are NPN transistors, and the third and fourth transistors are PNP transistors, or (ii) the first and second transistors are PNP transistors, and the third and fourth transistors are NPN transistors. In such embodiments, the control terminal, first current terminal, and second current terminal of each transistor will correspond to their respective base terminal, collector terminal, and emitter terminal.

[0068] As an example Figure 3 Another current mirror circuit 200' according to an alternative exemplary embodiment of the present disclosure is schematically shown. Features of the current mirror circuit 200' corresponding to those of the current mirror circuit 200 are labeled using similar reference numerals (with apostrophes). The non-cascode current mirror circuit 200' includes a high-voltage (HV) current mirror 202', a first current source 206', and a matching circuit system 300', wherein the first current source 206' is configured to output a first reference current IB1.

[0069] The HV current mirror 202' includes a first transistor M1' 222' and a second transistor M2' 224'. In this embodiment, both the first transistor M1' 222' and the second transistor M2' 224' are PMOS transistors. The first (PMOS) transistor M1' 222' includes a control terminal 226' in the form of a gate 226', a first current terminal 228' in the form of a drain 228', and a second current terminal 230' in the form of a source 230'. The second (PMOS) transistor M2' 224' also includes a control terminal 232' in the form of a gate 232', a first current terminal 234' in the form of a drain 234', and a second current terminal 236' in the form of a source 236'. The drain 228' of the first transistor M1' 222' is coupled to receive a first reference current IB1 from the first current source 206'. The source 230' of the first (PMOS) transistor M1'222' and the source 236' of the second (PMOS) transistor M2'224' are coupled to a reference potential in the form of a positive power supply potential VCC. The gate 226' of the first (PMOS) transistor M1'222' and the gate 232' of the second (PMOS) transistor M2'224' are coupled to each other. The drain 234' of the second (PMOS) transistor M2'224' is coupled to the output node GL 208' of the current mirror circuit 200'. As in the previous embodiment, the gate 226' of the first (PMOS) transistor M1'222' can be selectively coupled to the drain 228' of the first (PMOS) transistor M1'222' via switch SW1'237'.

[0070] A first current source 206' is coupled between the negative power supply potential VEE and the drain 228' of the first (PMOS) transistor M1' 222', and provides a current IB1 through the first transistor M1' 222'. A matching circuit system 300' coupled between the output node GL208' of the current mirror circuit 200' and the first drain 228' of the first (PMOS) transistor M1' 222' is configured to provide a replica voltage GL_copy at the first drain 228' of the first transistor M1' 222', corresponding to the voltage GL at the output node GL 208' of the current mirror circuit 200'. Therefore, the current through the second transistor M2' 224' is IB1xK, mirroring the current through the first transistor M1' 222' with a current mirror ratio of 1:K.

[0071] The matching circuit system 300' further includes a third transistor M3' 322', a fourth transistor M4' 324', and a second current source 332', a third current source 334', a fourth current source 336', and a fifth current source 338'.

[0072] In this embodiment, both the third transistor M3' 322' and the fourth transistor M4' 324' are NMOS transistors. The third (NMOS) transistor M3' 322' includes a control terminal 326' in the form of a gate 326', a first current terminal 328' in the form of a drain 328', and a second current terminal 330' in the form of a source 330'. The input 302' of the matching circuit system 300', coupled to the output node GL 208' of the current mirror circuit 200', is also coupled to the source 330' of the third transistor M3' 322'. The gate 326' and drain 328' of the third (NMOS) transistor M3' 322' are coupled together. The fourth (NMOS) transistor M4' 324' includes a control terminal 332' in the form of a gate 332', a first current terminal 334' in the form of a drain 334', and a second current terminal 336' in the form of a source 336'. The gate 332' of the fourth (NMOS) transistor M4' 324' is coupled to the gate 326' of the third (NMOS) transistor M3' 322'. The source 336' of the fourth transistor M4' 324' is coupled to the output 304' of the matching circuit system 300', and the output 304' itself is coupled to the drain 228' of the first transistor M1' 222'.

[0073] A second current source 332' is coupled between the drain 328' of the third transistor M3' 322' and the positive power supply potential VCC, and is configured to output a second reference current IB2. A third current source 334' is coupled between the drain 334' of the fourth transistor M4' 324' and the positive power supply potential VCC, and is configured to provide a third reference current IB2. A fourth current source 336' is coupled between the negative power supply potential VEE and the source 330' of the third transistor M3' 322', and is configured to provide a fourth reference current IB2. A fifth current source 338' is coupled between the negative power supply potential VEE and the source 336' of the fourth transistor M4' 324', and is configured to provide a fifth reference current IB2. As in the previous embodiments, each of the second reference current, third reference current, fourth reference current and fifth reference current provided by the second current source 332', third current source 334', fourth current source 336' and fifth current source 338' may have the same value IB2.

[0074] based on Figure 2 The description of the current mirror circuit 200 will make it clear to those skilled in the art. Figure 3 The operation of the current mirror circuit 200'.

[0075] Figure 4The application of the above-described non-cascode current mirror circuit 200 in the form of a (high) voltage gate driver 500 according to an exemplary embodiment of the present disclosure is illustrated schematically. In this exemplary embodiment, the gate driver 500 is used to drive the gate of a power transistor 600. The power transistor 600 may be any suitable power switch that needs to be driven by the voltage gate driver 500, for example, by means of non-exhaustive examples, an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The gate driver 500 includes a current source 510 in the form of a non-cascode current mirror circuit 200, which serves as an optional current generator. The output node GL 208 of the current mirror circuit 200 may be connected to the gate of the power transistor 600 via the output node 520 of the gate driver 500. The gate driver 500 includes other blocks, such as an operational amplifier circuit 530 for controlling the voltage at the output node 520 during a regulation mode, and a pull switch circuit 540 for pulling the voltage at the output node 520 to a reference voltage 550 during a pull mode. Each of the current mirror circuit 510, operational amplifier circuit 530, and pull-switch circuit 540 is coupled to the same output node 520. Specifically, the non-cascode current mirror circuits 200 and 510 provide a soft-shutdown mode that provides safe shutdown of the power transistor in the event of a fault condition. For example, during soft shutdown, the voltage at the output node 520 of the gate driver 500 can be pulled to a reference voltage in a controlled manner by steadily reducing the gate voltage at the output node 520 of the voltage gate driver 500. This avoids high voltage spikes that might otherwise be caused by a sudden cut-off of the gate voltage. The soft-shutdown mode may also be beneficial under other fault conditions. Using the current mirror circuit 200 for soft shutdown mode reduces the die area occupied by the soft shutdown feature. The current mirror circuit 200 can be used to steadily reduce the voltage at the output node 520 of the gate driver 500 to a reference voltage in the form of a low-voltage power rail VEE by means of a constant current. This can be achieved by maintaining the reference current IB1 at a constant value.

[0076] Figure 5A method 700 according to an example embodiment of the present disclosure is illustrated. Method 700 includes a step 702 of providing a first reference current IB1 between a first current terminal 228 and a second current terminal 230 of a first transistor M1 222. Method 700 further includes a step 704 of generating an output current between a first current terminal 234 and a second current terminal 236 of a second transistor M2 224, wherein a control terminal 232 of the second transistor M2 224 is coupled to a control terminal 226 of the first transistor M1 222. Method 700 further includes a step 706 of providing a voltage GL_copy at the first current terminal 228 of the first transistor M1 222 corresponding to the voltage GL at the first current terminal 234 of the second transistor M2 224.

[0077] Step 706, which provides a voltage GL_copy at the first current terminal 228 of the first transistor M1 222 corresponding to the voltage GL at the first current terminal 234 of the second transistor M2 224, may include driving a second reference current IB2 between the first current terminal 328 and the second current terminal 330 of the third transistor M3 322, wherein the first current terminal 328 of the third transistor M3 322 is coupled to the control terminal 326 of the third transistor M3 322, and wherein the second current terminal 330 of the third transistor M3 322 is coupled to the first current terminal 234 of the second transistor M2 224. Step 706 may further include driving a third reference current IB2 between the first current terminal 334 and the second current terminal 336 of the fourth transistor M4 324, wherein the control terminal 332 of the fourth transistor M4 324 is coupled to the control terminal 326 of the third transistor M3 322. The second current terminal 336 of the fourth transistor M4 324 may be coupled to the first current terminal 228 of the first transistor M1 222.

[0078] In method 700, the second reference current IB2 may be equal to the third reference current IB2.

[0079] Although the above examples have been described for use in gate drivers, the current mirror described herein can be used in any suitable system or application.

[0080] It will be readily understood that the components of the embodiments generally described herein and illustrated in the accompanying drawings can be arranged and designed in a wide variety of different configurations. Therefore, the more detailed descriptions of the various embodiments illustrated below are not intended to limit the scope of this disclosure, but merely to illustrate various embodiments. Although various aspects of the embodiments are presented in the drawings, the drawings are not necessarily drawn to scale.

[0081] It should be understood that any components that are alleged to be coupled may be directly or indirectly coupled or connected. In the case of indirect coupling, an additional component may be placed between the two components that are alleged to be coupled.

[0082] The invention may be implemented in other specific forms without departing from its spirit or essential characteristics. The described embodiments are to be considered in all respects merely illustrative and not restrictive. Therefore, the scope of the invention is indicated by the appended claims rather than by the detailed description herein. All variations that appear within the meaning and scope of the equivalents of the claims are included within its scope.

[0083] References to features, advantages, or similar language throughout this specification do not imply that all features and advantages achievable through the invention should be included in or in any single embodiment of the invention. In fact, language relating to features and advantages should be understood to mean that a specific feature, advantage, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, throughout this specification, discussions of features and advantages, as well as similar language, may, but do not necessarily, refer to the same embodiments.

[0084] Furthermore, the features, advantages, and characteristics described in this invention can be combined in any suitable manner in one or more embodiments. Those skilled in the art will recognize that, in view of the description herein, the invention can be practiced without having one or more specific features or advantages of a particular embodiment. In other instances, additional features and advantages that may not be present in all embodiments of the invention may be appreciated in certain embodiments.

Claims

1. A current mirror circuit, characterized in that, include: A first current source is used to provide a first reference current; The first transistor has a control terminal, a first current terminal coupled to receive the first reference current, and a second current terminal coupled to a reference potential. The second transistor has a control terminal coupled to the control terminal of the first transistor, a first current terminal coupled to the output node of the current mirror circuit, and a second current terminal coupled to the reference potential. as well as A matching circuit system having an input coupled to the output node of the current mirror circuit and an output coupled to the first current terminal of the first transistor, the matching circuit system being configured to provide a replicated voltage at the first current terminal of the first transistor corresponding to the voltage at the output node of the current mirror circuit.

2. The current mirror circuit according to claim 1, characterized in that, Each of the first transistor and the second transistor is a high-voltage transistor.

3. The current mirror circuit according to claim 1 or claim 2, characterized in that, The replicated voltage is a 1:1 copy of the voltage at the output node of the current mirror circuit.

4. The current mirror circuit according to any one of the preceding claims, characterized in that, The control terminal of the first transistor is coupled to the first current terminal of the first transistor via a switch.

5. The current mirror circuit according to any one of the preceding claims, characterized in that, The first current terminal of the second transistor is directly connected to the output node of the current mirror circuit.

6. The current mirror circuit according to any one of the preceding claims, characterized in that, The matching circuit system includes: A third transistor has a control terminal, a first current terminal, and a second current terminal, wherein the first current terminal is coupled to the control terminal of the third transistor. The fourth transistor has a control terminal, a first current terminal, and a second current terminal, the control terminal being coupled to the control terminal of the third transistor; A second current source is configured to control a second reference current between the first current terminal and the second current terminal of the third transistor; and A third current source is configured to control a third reference current between the first current terminal and the second current terminal of the fourth transistor. The input of the matching circuit system is coupled to the second current terminal of the third transistor; The output of the matching circuit system is coupled to the second current terminal of the fourth transistor.

7. The current mirror circuit according to claim 6, characterized in that, The matching circuit system further includes: A fourth current source, configured to provide a fourth reference current to the second current terminal of the third transistor, wherein the fourth reference current is equal to the second reference current; and A fifth current source is configured to provide a fifth reference current to the second current terminal of the fourth transistor, wherein the fifth reference current is equal to the third reference current.

8. A gate driver, characterized in that, Includes the current mirror circuit according to any of the preceding claims.

9. The gate driver circuit according to claim 8, characterized in that, The output node of the current driver circuit is coupled to the gate of the power transistor.

10. A method for controlling output current, characterized in that, The method includes: A first reference current is provided between the first current terminal and the second current terminal of the first transistor; An output current is generated between the first current terminal and the second current terminal of the second transistor, and the control terminal of the second transistor is coupled to the control terminal of the first transistor; and A voltage corresponding to the voltage at the first current terminal of the second transistor is provided at the first current terminal of the first transistor.

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