Floating point add round off tail bits processing apparatus and method based on hardware replication

Abstract

The application discloses a hardware-multiplexing-based floating-point addition and rounding off tail bit processing device and method, relates to the technical field of microprocessor design, and comprises: a scale shift multiplexing circuit, which is used for performing an exponent alignment operation on a first floating-point operand and a second floating-point operand, performing tail number right shift processing on the smaller floating-point operand in the aligned first floating-point operand and the aligned second floating-point operand, and extracting a target tail bit discarded in the tail number right shift processing process; a sign exponent splicing circuit, which is used for obtaining a target sign bit and a target exponent output by a main operation unit, splicing the target sign bit, the target exponent and a target tail bit, and generating an intermediate floating-point number; and a normalization multiplexing circuit, which is used for taking the intermediate floating-point number as a third floating-point operand, constructing a virtual operand as a fourth floating-point operand, performing a floating-point addition operation on the third floating-point operand and the fourth floating-point operand, and outputting a normalized floating-point number. High-precision intermediate results in iterative calculation are obtained.

Description

Technical Field

[0001] This invention relates to the field of microprocessor design technology, and in particular to a floating-point addition mantissa discarding processing device and method based on hardware reuse. Background Technology

[0002] Floating-point adders have a wide range of applications, such as climate simulation, fluid dynamics calculations, gradient calculations in deep learning, and matrix operations. However, floating-point addition operations discard some mantissa bits in scenarios involving rounding, exponent alignment, overflow, and underflow, resulting in a certain loss of precision. In high-precision computation scenarios, rounding errors can lead to deviations in results; in gradient calculations and matrix operations in deep learning (such as FP16 / FP32 mixed-precision training), the loss of low-order mantissa bits can also lead to vanishing gradients or parameter update deviations. Furthermore, floating-point adders are highly complex; achieving higher precision requires more logic gates and more complex circuit designs, which will result in longer computation delays.

[0003] In summary, how to provide higher precision intermediate results in high-precision computing scenarios, improve the overall reliability of simulation, without affecting the latency and performance of the original floating-point addition module, and achieve a balance between CPU performance and computational accuracy is a technical problem that needs to be solved in this field. Summary of the Invention

[0004] In view of this, the purpose of this invention is to provide a hardware-reused floating-point addition mantissa discarding device and method, which can provide higher precision intermediate results in high-precision computing scenarios, improve the overall simulation reliability, and not affect the latency and performance of the original floating-point addition module, thus achieving the goal of balancing CPU performance and computational accuracy. The specific solution is as follows:

[0005] In a first aspect, this application discloses a floating-point addition mantissa discarding processing device based on hardware multiplexing, including an alignment shift multiplexing circuit, a sign exponent concatenation circuit, and a normalization multiplexing circuit, wherein the alignment shift multiplexing circuit is an alignment shift circuit of a multiplexed floating-point adder, and the normalization multiplexing circuit is a normalization circuit of a multiplexed floating-point adder.

[0006] The alignment shift multiplexing circuit is used to perform an exponential alignment operation on the received first floating-point operand and second floating-point operand, and to right-shift the mantissa of the smaller floating-point operand in the aligned first floating-point operand and second floating-point operand, and to extract the target mantissa bits discarded during the right-shift process.

[0007] The sign-exponent concatenation circuit is used to obtain the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and to concatenate the target sign bit, the target exponent and the target mantissa bit to generate an intermediate floating-point number.

[0008] The normalized multiplexing circuit is used to take the intermediate floating-point number as the third floating-point operand, construct the corresponding virtual operand as the fourth floating-point operand, and then perform a floating-point addition operation on the third floating-point operand and the fourth floating-point operand to output a normalized floating-point number.

[0009] Optionally, the virtual operand is an operand with a negative sign bit, the same exponent as the third floating-point operand, and all mantissa bits are zero.

[0010] Optionally, the alignment shift multiplexing circuit includes:

[0011] The shift register is used to perform a right shift of the mantissa of the smaller of the first and second aligned floating-point operands.

[0012] The mantissa truncation circuit is used to determine the number of mantissa bits to be truncated based on the floating-point numerical precision mode of the smaller floating-point operand, so as to truncate the target mantissa bits to be discarded.

[0013] A buffer storage array is used to store the target mantissa bits.

[0014] Optionally, the normalized multiplexing circuit includes:

[0015] The sign bit generator generates a virtual operand sign bit with a negative sign based on the normal control signal;

[0016] A zero-value mantissa generator generates all-zero mantissa bits based on the bit width of the third floating-point operand;

[0017] A combiner is used to combine the sign bit of the virtual operand, the all-zero mantissa bit, and the exponent of the third floating-point operand into a virtual operand.

[0018] Optionally, the floating-point addition mantissa discarding processing device based on hardware multiplexing further includes:

[0019] An anomaly detection circuit is used to detect whether the first floating-point operand and the second floating-point operand are abnormal operands, wherein the abnormal operands include denormalized operands, infinity, or NaN;

[0020] An abnormal signal generation unit is used to generate an abnormal control signal and activate the bypass logic of the processing device if the detection result is that the first floating-point operand and the second floating-point operand are abnormal operands.

[0021] A normal signal generation unit is used to jump to the execution step of the alignment shift multiplexing circuit if the detection result indicates that the first floating-point operand and the second floating-point operand are normal operands.

[0022] Optionally, the abnormal signal generation unit includes:

[0023] The first bypass processing unit is configured to generate an exception control signal if the detection result indicates that the first floating-point operand and the second floating-point operand are denormalized operands, activate the main arithmetic unit of the floating-point adder for floating-point addition logic of the denormalized operands, then disable the right shift processing of the mantissa of the alignment shift multiplexing circuit, and directly output the corresponding calculation result.

[0024] Optionally, the abnormal signal generation unit includes:

[0025] The second bypass processing unit is used to generate an abnormal control signal if the detection result is that the first floating-point operand and the second floating-point operand are infinity or NaN, and to activate the sign bit combinational logic circuit and NaN generator, disable the parallel shift multiplexing circuit, and directly output the special floating-point result corresponding to the preset floating-point number representation format standard.

[0026] Secondly, this application discloses a floating-point addition method for discarding mantissas based on hardware multiplexing, including:

[0027] Perform an exponential alignment operation on the received first and second floating-point operands, and right-shift the mantissa of the smaller of the aligned first and second floating-point operands, and extract the target mantissa bits discarded during the right-shift process.

[0028] Obtain the target sign bit and target exponent from the main arithmetic unit of the floating-point adder, and then concatenate the target sign bit, the target exponent and the target mantissa bit to generate an intermediate floating-point number.

[0029] The intermediate floating-point number is used as the third floating-point operand, and a corresponding virtual operand is constructed as the fourth floating-point operand. Then, a floating-point addition operation is performed on the third floating-point operand and the fourth floating-point operand, and a normalized floating-point number is output.

[0030] Optionally, before performing the exponent alignment operation on the received first and second floating-point operands, the method further includes:

[0031] Detect whether the first floating-point operand and the second floating-point operand are abnormal operands, wherein the abnormal operands include denormalized operands, infinity, or NaN;

[0032] If the detection result indicates that the first floating-point operand and the second floating-point operand are abnormal operands, an abnormal control signal is generated and the bypass logic of the processing device is activated.

[0033] If the detection result indicates that the first floating-point operand and the second floating-point operand are normal operands, then the process jumps to the execution step of the parallel shift multiplexing circuit.

[0034] Optionally, if the detection result indicates that the first floating-point operand and the second floating-point operand are abnormal operands, an abnormal control signal is generated, and the bypass logic of the processing device is activated, including:

[0035] If the detection result indicates that the first floating-point operand and the second floating-point operand are denormalized operands, an abnormal control signal is generated, and the main arithmetic unit of the floating-point adder is activated to perform floating-point addition operations on the denormalized operands. Then, the right shift processing of the mantissa of the alignment shift multiplexing circuit is turned off, and the corresponding operation result is directly output.

[0036] If the detection result indicates that the first floating-point operand and the second floating-point operand are infinity or NaN, an abnormal control signal is generated, and the sign bit combinational logic circuit and NaN generator are activated, the alignment shift multiplexing circuit is turned off, and the special floating-point result corresponding to the preset floating-point representation format standard is directly output.

[0037] Thirdly, this application discloses an electronic device, comprising:

[0038] Memory, used to store computer programs;

[0039] A processor is configured to execute the computer program to implement the steps of the aforementioned hardware-reused floating-point addition method for discarding mantissa digits.

[0040] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned hardware-reused floating-point addition method for discarding mantissa digits.

[0041] As can be seen, this application discloses a floating-point addition mantissa discarding processing device based on hardware multiplexing, including an alignment shift multiplexing circuit, a sign exponent concatenation circuit, and a normalization multiplexing circuit. The alignment shift multiplexing circuit is an alignment shift circuit of a multiplexed floating-point adder, and the normalization multiplexing circuit is a normalization circuit of a multiplexed floating-point adder. The alignment shift multiplexing circuit is used to perform an exponent alignment operation on the received first and second floating-point operands, and to right-shift the mantissa of the smaller of the aligned first and second floating-point operands. The system extracts the target mantissa bits discarded during the right shift process; the sign-exponent concatenation circuit obtains the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and concatenates the target sign bit, target exponent, and target mantissa bits to generate an intermediate floating-point number; the normalization multiplexing circuit uses the intermediate floating-point number as the third floating-point operand, constructs a corresponding virtual operand as the fourth floating-point operand, and then performs a floating-point addition operation on the third floating-point operand and the fourth floating-point operand to output a normalized floating-point number. Therefore, by reusing the structure of the floating-point adder, redirecting the mantissa overflow signal in the order shift multiplexing circuit, and dynamically switching the operation mode of the normalization multiplexing circuit, the hardware resources are reused in time and space with zero increase in chip area. The mantissa shifted out during the order shifting process of floating-point addition is retained and output as a normalized floating-point number to obtain a high-precision intermediate floating-point number, reducing iterative calculation errors. Furthermore, the main arithmetic unit and the mantissa processing are processed in parallel, and the main arithmetic unit has zero delay penalty, thus realizing the self-iterative optimization of the floating-point adder. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0043] Figure 1 This is a schematic diagram of a floating-point addition mantissa processing device based on hardware multiplexing disclosed in this application.

[0044] Figure 2 A diagram showing the discard mantissa structure of a specific double-precision floating-point adder disclosed in this application;

[0045] Figure 3 This application discloses a flowchart of a floating-point addition method for discarding mantissa based on hardware multiplexing.

[0046] Figure 4This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0048] Floating-point numbers have a large dynamic range, capable of representing very large and very small values. High-precision floating-point calculations are often required in fields such as scientific computing, graphics processing, and machine learning. In high-performance CPU design, the precision of floating-point addition has a significant impact on the accuracy of calculations. Higher precision in floating-point adders reduces rounding errors, resulting in more reliable results.

[0049] Floating-point adders have a wide range of applications, such as climate simulation, fluid dynamics calculations, gradient calculations in deep learning, and matrix operations. However, floating-point addition operations discard some mantissa bits in scenarios involving rounding, exponent alignment, overflow, and underflow, resulting in a certain loss of precision. In high-precision computation scenarios, rounding errors can lead to deviations in results; in gradient calculations and matrix operations in deep learning (such as FP16 / FP32 mixed-precision training), the loss of low-order mantissa bits can also lead to gradient vanishing or parameter update deviations. Furthermore, floating-point adders are highly complex; achieving higher precision requires more logic gates and more complex circuit designs, resulting in longer computation delays. This invention proposes a floating-point adder design method to retain mantissa bits during exponent alignment, and through normalization, outputs higher-precision intermediate results, reducing the precision loss caused by exponent alignment in floating-point addition operations. This invention can provide higher-precision intermediate results in high-precision computation scenarios, improving the overall reliability of simulations.

[0050] In floating-point addition, the exponents of two floating-point numbers need to be aligned (i.e., aligned exponents). This is typically done by right-shifting the mantissa of the smaller number to match the exponent of the larger number. During this right shift, the lower-order bits of the smaller number's mantissa may be discarded, resulting in a loss of precision.

[0051] To address this, the present invention provides a hardware-reused floating-point addition mantissa discarding processing scheme, which can provide higher precision intermediate results in high-precision computing scenarios, improve the overall simulation reliability, and not affect the latency and performance of the original floating-point addition module, thereby achieving the goal of balancing CPU performance and calculation accuracy.

[0052] Reference Figure 1As shown, this embodiment of the invention discloses a floating-point addition mantissa discarding processing device based on hardware multiplexing, including an alignment shift multiplexing circuit 11, a sign exponent concatenation circuit 12, and a normalization multiplexing circuit 13. The alignment shift multiplexing circuit 11 is an alignment shift circuit for a multiplexed floating-point adder, and the normalization multiplexing circuit 13 is a normalization circuit for a multiplexed floating-point adder.

[0053] The alignment shift multiplexing circuit 11 is used to perform an exponential alignment operation on the received first floating-point operand and second floating-point operand, and to right-shift the mantissa of the smaller floating-point operand in the aligned first floating-point operand and the aligned second floating-point operand, and to extract the target mantissa bits discarded during the right-shift process.

[0054] The sign-exponent concatenation circuit 12 is used to obtain the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and to concatenate the target sign bit, the target exponent and the target mantissa bit to generate an intermediate floating-point number.

[0055] The normalized multiplexing circuit 13 is used to take the intermediate floating-point number as the third floating-point operand, construct the corresponding virtual operand as the fourth floating-point operand, and then perform a floating-point addition operation on the third floating-point operand and the fourth floating-point operand to output a normalized floating-point number.

[0056] The virtual operand is an operand with a negative sign bit, the same exponent as the third floating-point operand, and all zero mantissa bits.

[0057] It is understandable that if the computation scenario is a high-precision computation scenario such as typhoon path prediction, in the process of predicting the typhoon path waypoints, multiple iterative floating-point operations based on typhoon information and geographical environment information need to be performed. Among them, the rounding error (intermediate result error) of each floating-point addition based on the waypoint prediction requirement causes the final path to deviate from the actual trajectory by tens of kilometers. Therefore, when the computation scenario is a high-precision computation scenario such as typhoon path prediction, the corresponding typhoon path prediction is generated, and the corresponding original floating-point operation data information is determined based on typhoon information and geographical environment information, and then input into the device of the present invention.

[0058] If the computation scenario is a deep learning training scenario, during the deep learning training process of the model, there is gradient update. For example, in mixed precision training, the loss of low-order mantissas during alignment can cause gradient values ​​to be truncated (e.g., the gradient value is set to zero when it is less than 1e-4), leading to gradient vanishing. Specifically, in ResNet-50 training, traditional floating-point addition may cause the gradient update error rate after the 50th layer to reach 15%, resulting in a 30% decrease in model convergence speed. Therefore, in the deep learning training scenario, the loss value is calculated based on the training data information of the current training scenario (the predicted value and the true value of the training set during the model training process). Then, in the process of calculating the gradient of each layer of the model based on the loss value, the floating-point adder is also needed to iteratively calculate the relevant gradient information based on the loss value. During this process, the corresponding floating-point operands are generated based on the loss value information and input into the device of this invention.

[0059] The floating-point addition mantissa discarding device comprises two parts. The first part, called FADDR (alignment shift multiplexing circuit 11 + sign exponent concatenation circuit 12), is mainly responsible for extracting the mantissa shifted out by the alignment shift in floating-point addition. The second part, called FADDN (normalization multiplexing circuit 13), normalizes the mantissa extracted by FADDR and outputs a normalized floating-point number conforming to the standard floating-point format. The structure of the FADDR partially multiplexed floating-point adder proposed in this invention retains the mantissa portion that should have been discarded before rounding after the alignment shift operation of the two input floating-point operands srca and srcb, and concatenates it with the sign bit and exponent of the original floating-point addition result to form an intermediate floating-point number; the structure of the FADDR partially multiplexed floating-point adder takes the output result of FADDR (intermediate floating-point number) as the new srca, and simultaneously constructs a new srcb, which consists of a negative sign bit, the same exponent bit as the new srca, and all-zero mantissa bits. The FADDN section can normalize the FADDR result, outputting a standard floating-point number. This enables addition with operands within the normal range as input, performing an order shift, discarding the mantissa, and outputting a standard floating-point number. It's important to note that the entire processing flow described above applies to normalization when both the first and second floating-point operands are normal operands.

[0060] The alignment shift multiplexing circuit 11 includes:

[0061] The shift register is used to perform a right shift of the mantissa of the smaller of the first and second aligned floating-point operands.

[0062] The mantissa truncation circuit is used to determine the number of mantissa bits to be truncated based on the floating-point numerical precision mode of the smaller floating-point operand, so as to truncate the target mantissa bits to be discarded.

[0063] A buffer storage array is used to store the target mantissa bits.

[0064] The standardized multiplexing circuit 13 includes:

[0065] The sign bit generator generates a virtual operand sign bit with a negative sign based on the normal control signal;

[0066] A zero-value mantissa generator generates all-zero mantissa bits based on the bit width of the third floating-point operand;

[0067] A combiner is used to combine the sign bit of the virtual operand, the all-zero mantissa bit, and the exponent of the third floating-point operand into a virtual operand.

[0068] It is understandable that the multiplexing circuit 11 multiplexes the mantissa-aligned shifter (including the exponent comparison circuit and the barrel shifter) of the standard floating-point adder, i.e., the shift register. Then, a mantissa truncation circuit and a buffer storage array are added. The mantissa truncation circuit is connected to the overflow terminal of the barrel shifter. When the mantissa of the smaller operand is shifted right, bits 53 to 104 of the barrel shifter output are truncated, and the truncated target mantissa bits are then stored in the buffer storage array. The normalization multiplexing circuit 13 multiplexes the normalization shifter (processing the shift logic for leading zeros) and the rounder (performing rules such as nearest-neighbor rounding). The multiplexing control logic reconfigures the normalization circuit of the main adder to perform srca+(-0) operations (equivalent absolute value normalization). The added hardware includes a combiner, a sign bit generator, and a zero-value mantissa generator. The usage of each added hardware component is described above and will not be repeated here.

[0069] The normalization process for cases where abnormal operands exist in the first and second floating-point operands is as follows:

[0070] The aforementioned hardware-reused floating-point addition mantissa discarding processing device further includes:

[0071] An anomaly detection circuit 14 is used to detect whether the first floating-point operand and the second floating-point operand are abnormal operands, wherein the abnormal operands include denormalized operands, infinity, or NaN;

[0072] An abnormal signal generation unit 15 is used to generate an abnormal control signal and activate the bypass logic of the processing device if the detection result is that the first floating-point operand and the second floating-point operand are abnormal operands.

[0073] The normal signal generation unit 16 is used to jump to the execution step of the alignment shift multiplexing circuit if the detection result is that the first floating-point operand and the second floating-point operand are normal operands.

[0074] The abnormal signal generation unit 15 includes:

[0075] The first bypass processing unit is configured to generate an exception control signal if the detection result indicates that the first floating-point operand and the second floating-point operand are denormalized operands, activate the main arithmetic unit of the floating-point adder for floating-point addition logic of the denormalized operands, then disable the right shift processing of the mantissa of the alignment shift multiplexing circuit, and directly output the corresponding calculation result.

[0076] The abnormal signal generation unit 15 includes:

[0077] The second bypass processing unit is used to generate an abnormal control signal if the detection result is that the first floating-point operand and the second floating-point operand are infinity or NaN, and to activate the sign bit combinational logic circuit and NaN generator, disable the parallel shift multiplexing circuit, and directly output the special floating-point result corresponding to the preset floating-point number representation format standard.

[0078] Understandably, before the floating-point operand input alignment shift multiplexing circuit 11, the anomaly detection circuit 14 performs state detection on the received floating-point operand. If any one or more of the following are present in the first or second floating-point operand: a denormalized operand, infinity, or NaN, the anomaly detection circuit 14 determines them to be anomalies, generates a corresponding anomaly control signal, and then activates bypass logic for processing. Specifically, when the result is that the floating-point operand is a denormalized operand, the corresponding bypass logic is the floating-point addition logic for the denormalized operand, and then the right shift processing of the mantissa of the alignment shift multiplexing circuit is turned off, directly outputting the corresponding operation result. When the result is infinity or NaN, anomaly control signal is generated, and the corresponding bypass logic is to activate the sign bit combinational logic circuit and the NaN generator, turn off the alignment shift multiplexing circuit, and directly output the special floating-point result corresponding to the preset floating-point number representation format standard, where the preset floating-point number representation format standard is IEEE 754-2019 Clause 7. As can be seen, it can handle cases where the input operands are outside the normal range, i.e., the input operands are zero, NOT, or infinity, and the output is overflow or infinity. It outputs the corresponding floating-point number according to the special number handling rules for floating-point addition. It can also handle floating-point numbers that are outside the normal range, aligning with the handling method for floating-point addition.

[0079] like Figure 2 The diagram illustrates the structure of a floating-point adder for discarding mantissas, demonstrating how the original floating-point addition unit is reused to complete the retrieval process. V1 to V4 represent the addition execution stack, with numbers 0 to 1 representing different operations within the stack. `srca` and `srcb` are the input floating-point operands. The specific processing flow is as follows:

[0080] STEP 1: Perform FADDR processing on the floating-point numbers srca and srcb. After the operands of the input floating-point addition unit complete the exponentiation operation, the mantissa bits are not retained before rounding. For example, when performing floating-point double-precision addition, the 52-bit mantissa after the 52nd bit shift is retained, and then concatenated with the sign bit and exponent of the original floating-point addition result to form a pseudo-floating-point number. That is, the format of this floating-point number does not meet the standard floating-point format requirements.

[0081] STEP2: Use the output of FADDR as the input operand srca for the FADDN operation, and construct a corresponding srcb based on srca. The sign of srcb is negative, the exponent is the same as the output of FADDR, and the mantissa is all 0.

[0082] STEP3: Reuse the structure of the floating-point adder to perform floating-point addition on srca and srcb of FADDN, thereby normalizing the output of FADDR result, that is, outputting a floating-point number in a standard floating-point format.

[0083] In this way, by redirecting the mantissa overflow signal in the alignment shift multiplexing circuit and dynamically switching the operation mode of the normalization multiplexing circuit, spatiotemporal multiplexing of hardware resources is achieved. The multiplexing circuit reduces the increase in area and power consumption of the microprocessor chip where the device resides. Furthermore, in the dedicated computation unit required for mantissa extraction, the delay only increases by one cycle to ensure the acquisition of high-precision intermediate results (normalized floating-point numbers) during computation. Moreover, hardware detection replaces software judgment, eliminating the risk of standard compatibility issues. The detection of abnormal states avoids the activation of invalid circuits, eliminating redundant operations such as alignment / shifting / normalization, and preventing error propagation.

[0084] As can be seen, this application discloses a floating-point addition mantissa discarding processing device based on hardware multiplexing, including an alignment shift multiplexing circuit, a sign exponent concatenation circuit, and a normalization multiplexing circuit. The alignment shift multiplexing circuit is an alignment shift circuit of a multiplexed floating-point adder, and the normalization multiplexing circuit is a normalization circuit of a multiplexed floating-point adder. The alignment shift multiplexing circuit is used to perform an exponent alignment operation on the received first and second floating-point operands, and to right-shift the mantissa of the smaller of the aligned first and second floating-point operands. The system extracts the target mantissa bits discarded during the right shift process; the sign-exponent concatenation circuit obtains the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and concatenates the target sign bit, target exponent, and target mantissa bits to generate an intermediate floating-point number; the normalization multiplexing circuit uses the intermediate floating-point number as the third floating-point operand, constructs a corresponding virtual operand as the fourth floating-point operand, and then performs a floating-point addition operation on the third floating-point operand and the fourth floating-point operand to output a normalized floating-point number. Therefore, by reusing the structure of the floating-point adder, redirecting the mantissa overflow signal in the order shift multiplexing circuit, and dynamically switching the operation mode of the normalization multiplexing circuit, the hardware resources are reused in time and space with zero increase in chip area. The mantissa shifted out during the order shifting process of floating-point addition is retained and output as a normalized floating-point number to obtain a high-precision intermediate floating-point number, reducing iterative calculation errors. Furthermore, the main arithmetic unit and the mantissa processing are processed in parallel, and the main arithmetic unit has zero delay penalty, thus realizing the self-iterative optimization of the floating-point adder.

[0085] Reference Figure 3 As shown, the present invention discloses a floating-point addition method for discarding mantissas based on hardware multiplexing, comprising:

[0086] Step S11: Perform an exponent alignment operation on the received first and second floating-point operands, and right-shift the mantissa of the smaller floating-point operand between the aligned first and second floating-point operands, and extract the target mantissa bits discarded during the right-shift process.

[0087] Step S12: Obtain the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and concatenate the target sign bit, the target exponent, and the target mantissa bit to generate an intermediate floating-point number.

[0088] Step S13: Use the intermediate floating-point number as the third floating-point operand, construct the corresponding virtual operand as the fourth floating-point operand, and then perform a floating-point addition operation on the third floating-point operand and the fourth floating-point operand to output a normalized floating-point number.

[0089] Before performing the exponent alignment operation on the received first and second floating-point operands, the method further includes:

[0090] Detect whether the first floating-point operand and the second floating-point operand are abnormal operands, wherein the abnormal operands include denormalized operands, infinity, or NaN;

[0091] If the detection result indicates that the first floating-point operand and the second floating-point operand are abnormal operands, an abnormal control signal is generated and the bypass logic of the processing device is activated.

[0092] If the detection result indicates that the first floating-point operand and the second floating-point operand are normal operands, then the process jumps to the execution step of the parallel shift multiplexing circuit.

[0093] If the detection result indicates that the first floating-point operand and the second floating-point operand are denormalized operands, an abnormal control signal is generated, and the main arithmetic unit of the floating-point adder is activated to perform floating-point addition operations on the denormalized operands. Then, the right shift processing of the mantissa of the alignment shift multiplexing circuit is turned off, and the corresponding operation result is directly output.

[0094] If the detection result indicates that the first floating-point operand and the second floating-point operand are infinity or NaN, an abnormal control signal is generated, and the sign bit combinational logic circuit and NaN generator are activated, the alignment shift multiplexing circuit is turned off, and the special floating-point result corresponding to the preset floating-point representation format standard is directly output.

[0095] As can be seen, this application discloses performing an exponent alignment operation on the received first and second floating-point operands, right-shifting the mantissa of the smaller of the aligned first and second floating-point operands, and extracting the target mantissa bits discarded during the right-shifting process; obtaining the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and bit-concatenating the target sign bit, the target exponent, and the target mantissa bits to generate an intermediate floating-point number; using the intermediate floating-point number as the third floating-point operand, constructing a corresponding virtual operand as the fourth floating-point operand, and then performing a floating-point addition operation on the third and fourth floating-point operands to output a normalized floating-point number. Therefore, by reusing the structure of the floating-point adder, redirecting the mantissa overflow signal in the order shift multiplexing circuit, and dynamically switching the operation mode of the normalization multiplexing circuit, the hardware resources are reused in time and space with zero increase in chip area. The mantissa shifted out during the order shifting process of floating-point addition is retained and output as a normalized floating-point number to obtain a high-precision intermediate floating-point number, reducing iterative calculation errors. Furthermore, the main arithmetic unit and the mantissa processing are processed in parallel, and the main arithmetic unit has zero delay penalty, thus realizing the self-iterative optimization of the floating-point adder.

[0096] Furthermore, embodiments of this application also disclose an electronic device, Figure 4 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content of the diagram should not be construed as limiting the scope of this application.

[0097] Figure 4 This is a schematic diagram of the structure of an electronic device 20 provided in an embodiment of this application. Specifically, the electronic device 20 may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the floating-point addition discarding mantissa processing method based on hardware multiplexing disclosed in any of the foregoing embodiments. Furthermore, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0098] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0099] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0100] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored thereon can include operating system 221, computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0101] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the electronic device 20 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows Server, Netware, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the hardware-reused floating-point addition and mantissa discarding method disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0102] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the aforementioned hardware-multiplexed floating-point addition method for discarding mantissas. Specific steps of this method can be found in the corresponding content disclosed in the foregoing embodiments, and will not be repeated here.

[0103] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0104] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. The software module may be located in random access memory (RAM), memory, read-only memory (ROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, removable disks, CD-ROMs (Compact Disc-Read Only Memory), or any other form of storage medium known in the art.

[0105] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0106] The solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A floating-point addition mantissa discarding processing device based on hardware multiplexing, characterized in that, It includes an order-shifting multiplexing circuit, a sign exponent concatenation circuit, and a normalization multiplexing circuit. The order-shifting multiplexing circuit is an order-shifting circuit for a multiplexed floating-point adder, and the normalization multiplexing circuit is a normalization circuit for a multiplexed floating-point adder. The alignment shift multiplexing circuit is used to perform an exponential alignment operation on the received first floating-point operand and second floating-point operand, and to right-shift the mantissa of the smaller floating-point operand in the aligned first floating-point operand and second floating-point operand, and to extract the target mantissa bits discarded during the right-shift process. The sign-exponent concatenation circuit is used to obtain the target sign bit and target exponent output by the main arithmetic unit of the floating-point adder, and to concatenate the target sign bit, the target exponent and the target mantissa bit to generate an intermediate floating-point number. The normalized multiplexing circuit is used to take the intermediate floating-point number as the third floating-point operand, construct the corresponding virtual operand as the fourth floating-point operand, and then perform a floating-point addition operation on the third floating-point operand and the fourth floating-point operand to output a normalized floating-point number.

2. The floating-point addition mantissa discarding processing device based on hardware multiplexing according to claim 1, characterized in that, The virtual operand is an operand with a negative sign bit, the same exponent as the third floating-point operand, and all zero mantissa bits.

3. The floating-point addition mantissa discarding processing device based on hardware multiplexing according to claim 1, characterized in that, The order-shift multiplexing circuit includes: The shift register is used to perform a right shift of the mantissa of the smaller of the first and second aligned floating-point operands. The mantissa truncation circuit is used to determine the number of mantissa bits to be truncated based on the floating-point numerical precision mode of the smaller floating-point operand, so as to truncate the target mantissa bits to be discarded. A buffer storage array is used to store the target mantissa bits.

4. The floating-point addition mantissa discarding processing device based on hardware multiplexing according to claim 1, characterized in that, The standardized multiplexing circuit includes: The sign bit generator generates a virtual operand sign bit with a negative sign based on the normal control signal; A zero-value mantissa generator generates all-zero mantissa bits based on the bit width of the third floating-point operand; A combiner is used to combine the sign bit of the virtual operand, the all-zero mantissa bit, and the exponent of the third floating-point operand into a virtual operand.

5. The floating-point addition mantissa discarding processing device based on hardware multiplexing according to claim 1, characterized in that, Also includes: An anomaly detection circuit is used to detect whether the first floating-point operand and the second floating-point operand are abnormal operands, wherein the abnormal operands include denormalized operands, infinity, or NaN; An abnormal signal generation unit is used to generate an abnormal control signal and activate the bypass logic of the processing device if the detection result is that the first floating-point operand and the second floating-point operand are abnormal operands. A normal signal generation unit is used to jump to the execution step of the alignment shift multiplexing circuit if the detection result indicates that the first floating-point operand and the second floating-point operand are normal operands.

6. The floating-point addition mantissa discarding processing device based on hardware multiplexing according to claim 5, characterized in that, The abnormal signal generation unit includes: The first bypass processing unit is configured to generate an exception control signal if the detection result indicates that the first floating-point operand and the second floating-point operand are denormalized operands, activate the main arithmetic unit of the floating-point adder for floating-point addition logic of the denormalized operands, then disable the right shift processing of the mantissa of the alignment shift multiplexing circuit, and directly output the corresponding calculation result.

7. The floating-point addition mantissa discarding processing device based on hardware multiplexing according to claim 5, characterized in that, The abnormal signal generation unit includes: The second bypass processing unit is used to generate an abnormal control signal if the detection result is that the first floating-point operand and the second floating-point operand are infinity or NaN, and to activate the sign bit combinational logic circuit and NaN generator, disable the parallel shift multiplexing circuit, and directly output the special floating-point result corresponding to the preset floating-point number representation format standard.

8. A floating-point addition method for discarding mantissas based on hardware multiplexing, characterized in that, include: Perform an exponential alignment operation on the received first and second floating-point operands, and right-shift the mantissa of the smaller of the aligned first and second floating-point operands, and extract the target mantissa bits discarded during the right-shift process. Obtain the target sign bit and target exponent from the main arithmetic unit of the floating-point adder, and then concatenate the target sign bit, the target exponent and the target mantissa bit to generate an intermediate floating-point number. The intermediate floating-point number is used as the third floating-point operand, and a corresponding virtual operand is constructed as the fourth floating-point operand. Then, a floating-point addition operation is performed on the third floating-point operand and the fourth floating-point operand, and a normalized floating-point number is output.

9. The floating-point addition method for discarding mantissas based on hardware multiplexing according to claim 8, characterized in that, Before performing the exponent alignment operation on the received first and second floating-point operands, the method further includes: Detect whether the first floating-point operand and the second floating-point operand are abnormal operands, wherein the abnormal operands include denormalized operands, infinity, or NaN; If the detection result indicates that the first floating-point operand and the second floating-point operand are abnormal operands, an abnormal control signal is generated and the bypass logic of the processing device is activated. If the detection result indicates that the first floating-point operand and the second floating-point operand are normal operands, then the process jumps to the execution step of the parallel shift multiplexing circuit.

10. The floating-point addition method for discarding mantissas based on hardware multiplexing according to claim 9, characterized in that, If the detection result indicates that both the first floating-point operand and the second floating-point operand are abnormal operands, then an abnormal control signal is generated, and the bypass logic of the processing device is activated, including: If the detection result indicates that the first floating-point operand and the second floating-point operand are denormalized operands, an abnormal control signal is generated, and the main arithmetic unit of the floating-point adder is activated to perform floating-point addition operations on the denormalized operands. Then, the right shift processing of the mantissa of the alignment shift multiplexing circuit is turned off, and the corresponding operation result is directly output. If the detection result indicates that the first floating-point operand and the second floating-point operand are infinity or NaN, an abnormal control signal is generated, and the sign bit combinational logic circuit and NaN generator are activated, the alignment shift multiplexing circuit is turned off, and the special floating-point result corresponding to the preset floating-point representation format standard is directly output.

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