Fpga simulation use case batch regression execution method and system
By combining randomization and batch regression FPGA simulation methods with the UVM simulation platform, the problem of low efficiency in FPGA network card problem localization is solved, and efficient batch regression execution of FPGA simulation test cases is achieved, improving the probability of problem reproduction and coverage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING QUANXIN CABLE TECH
- Filing Date
- 2025-12-15
- Publication Date
- 2026-05-29
Smart Images
Figure CN122111769A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of FPGA simulation and verification technology, and more specifically to a method and system for batch regression execution of FPGA simulation test cases. Background Technology
[0002] When issues arise with the DPU network interface card (NIC) implemented on an FPGA, there are currently two troubleshooting methods: reading registers and capturing waveform samples. Currently, reading registers via the PCIe interface can lead to PCIe errors and unreadable registers. Furthermore, due to resource constraints, the information obtainable from registers is limited, often failing to pinpoint the exact problem. Waveform capture requires redesigning the interface, but due to cost considerations and limited FPGA resources, adding waveform capture signals can worsen timing and introduce additional problems. Additionally, given the current complexity of DPU NICs, generating waveform capture versions is time-consuming and inefficient. The limited waveform range that an FPGA can capture means that many problems originate early, far from the trigger point, leading to capture failures. This necessitates careful selection of the trigger point.
[0003] Given the aforementioned shortcomings, a UVM-based FPGA simulation and verification platform has been introduced. By reproducing the problem and obtaining the complete waveform signal, the problem can be reproduced on the simulation platform, allowing for rapid problem localization and bug fixing. However, due to the significant difference in operating efficiency between the simulation platform and the FPGA, simulating only a single test case cannot quickly reproduce the problem on the FPGA. Summary of the Invention
[0004] The purpose of this invention is to provide a batch regression execution method for FPGA simulation test cases. By combining the randomization and batch regression of the simulation platform, batch regression execution of FPGA simulation test cases can be achieved 24 / 7, which improves the reproducibility of FPGA board problems, shortens the problem-solving cycle, and expands the coverage of simulation.
[0005] According to a first aspect of the present invention, a method for batch regression execution of FPGA simulation test cases is proposed, comprising the following steps: Step 1: Read the test case file of the preset FPGA simulation test cases and parse the key attributes of each test case line by line. Calculate the weight sorting based on priority weight and time factor to generate the test case execution queue. Step 2: Calculate the time base seed using a hash function based on the system timestamp; Step 3: Generate enhancement seeds based on historical execution records and coverage data; Step 4: For each test case, generate a random seed based on the fusion of the time-based seed and the enhanced seed to obtain the seed package for each test case; Step 5: Start parallel simulation in batches, allocate seeds from the seed package to each test case in the test case execution queue in sequence, execute the simulation in seed order and monitor the execution progress and status of each test case in real time, and synchronize to the real-time status library. Step 6: Extract the execution results of all use cases from the real-time state database, extract key indicators, and then perform problem pattern recognition and coverage analysis; Step 7: Calculate the seed effectiveness score based on the test case execution results, and add the seed validity mark, test case failure record, and coverage data to the historical knowledge base; Step 8: Based on the updated historical knowledge base, dynamically update the seed generation parameters and test case execution parameters, automatically start the next round of test case execution, and realize the batch continuous execution of dynamically self-optimized FPGA simulation test cases.
[0006] According to a second aspect of the present invention, a batch regression execution system for FPGA simulation test cases is proposed, which is applicable to the aforementioned batch regression execution system method for FPGA simulation test cases. The system includes a test case management module, a random seed generation module, a UVM simulation platform, a DPU network card, a result analysis module, and an iterative optimization module. The test case management module is used to manage the test case files of FPGA simulation test cases; The random seed generation module is used to generate a random seed for each test case based on the fusion of the time-based seed and the enhanced seed, and obtain a seed package for each test case. The batch execution control module is used to control the UVM simulation platform to start multi-threaded parallel execution according to the configured number of parallel executions and the execution plan; The UVM simulation platform is used to read test case seed packages and priorities, generate simulation stimuli in batch order, convert them into DUT interface form and inject them into the DPU network card. Each batch starts and executes several tasks in parallel, and monitors the execution progress and status of each test case in real time, and synchronizes them to the real-time status library. The DPU network card is configured through logic code, and test cases are called and executed in its simulation module; The results analysis module is used to extract the execution results of all test cases from the real-time status database, extract key indicators, perform problem pattern recognition and coverage analysis, calculate seed effect score, and add seed validity markers, test case failure records, and coverage data to the historical knowledge base. The iterative optimization module is used to dynamically update the iteration seed generation parameters and test case execution parameters based on the updated historical knowledge base, and automatically start the next round of test case execution to achieve batch continuous execution of dynamically self-optimized FPGA simulation test cases.
[0007] The implementation of the FPGA simulation test case batch regression execution system and method in the above embodiments of the present invention, through an intelligent seed generation mechanism that combines time-based, history-enhanced, and coverage-oriented approaches, avoids the problem that traditional reliance on simple timestamps is insufficient to cover complex scenarios, resulting in low probability of problem discovery and failure to trigger a large number of potential design defects. The method of the present invention can improve the triggering probability of complex scenarios and potential defects, thereby improving the defect detection capability of FPGA simulation. At the same time, by focusing on coverage gaps through coverage-oriented seed generation, and combining coverage growth assessment and targeted optimization suggestions, the coverage can be accurately improved, avoiding blind testing and maximizing resource utilization.
[0008] In terms of test execution strategy, execution batches are dynamically planned based on test case attributes, and parallelism and execution priority are adjusted according to real-time resource load. Effective / ineffective seeds are distinguished to avoid wasting test resources in low-value test scenarios and reduce resource conflicts and waste. Combined with the self-optimization strategy formed by seed effect quantitative evaluation, automatic problem pattern identification, and dynamic parameter optimization during the testing process, the test strategy can be improved without manual intervention. It is adapted to 24 / 7 full-process continuous iterative test operation, which improves test efficiency and problem discovery capabilities, and enhances the targeting, efficiency and continuous optimization capabilities of testing.
[0009] It should be understood that all combinations of the foregoing concepts and the additional concepts described in more detail below may be considered part of the inventive subject matter of this disclosure, provided that such concepts do not contradict each other. Furthermore, all combinations of the claimed subject matter are considered part of the inventive subject matter of this disclosure.
[0010] The foregoing and other aspects, embodiments, and features of the teachings of the present invention will be more fully understood from the following description in conjunction with the accompanying drawings. Other additional aspects of the invention, such as features and / or beneficial effects of exemplary embodiments, will become apparent from the following description or may be learned through practice of specific embodiments according to the teachings of the present invention. Attached Figure Description
[0011] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical or nearly identical component shown in the various figures may be denoted by the same reference numeral. For clarity, not every component is labeled in each figure. Embodiments of various aspects of the invention will now be described by way of example and with reference to the accompanying drawings.
[0012] Figure 1 This is a flowchart of a batch regression execution method for FPGA simulation test cases according to an embodiment of the present invention.
[0013] Figure 2This is a schematic diagram of the principle of the FPGA simulation test case batch regression execution system according to an embodiment of the present invention. Detailed Implementation
[0014] To better understand the technical content of the present invention, specific embodiments are described below in conjunction with the accompanying drawings.
[0015] Various aspects of the invention are described in this disclosure with reference to the accompanying drawings, which illustrate numerous illustrative embodiments. The embodiments of this disclosure are not necessarily intended to encompass all aspects of the invention. It should be understood that the various concepts and embodiments described above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed herein are not limited to any particular implementation. Furthermore, some aspects of the invention disclosed may be used alone or in any suitable combination with other aspects of the invention disclosed.
[0016] Combination Figure 1 , Figure 2 As shown, the FPGA simulation test case batch regression execution method according to an embodiment of the present invention includes the following steps: Step 1: Read the test case file of the preset FPGA simulation test cases and parse the key attributes of each test case line by line. Calculate the weight sorting based on priority weight and time factor to generate the test case execution queue. Step 2: Calculate the time base seed using a hash function based on the system timestamp; Step 3: Generate enhancement seeds based on historical execution records and coverage data; Step 4: For each test case, generate a random seed based on the fusion of the time-based seed and the enhanced seed to obtain the seed package for each test case; Step 5: Start parallel simulation in batches, allocate seeds from the seed package to each test case in the test case execution queue in sequence, execute the simulation in seed order and monitor the execution progress and status of each test case in real time, and synchronize to the real-time status library. Step 6: Extract the execution results of all use cases from the real-time state database, extract key indicators, and then perform problem pattern recognition and coverage analysis; Step 7: Calculate the seed effectiveness score based on the test case execution results, and add the seed validity mark, test case failure record, and coverage data to the historical knowledge base; Step 8: Based on the updated historical knowledge base, dynamically update the seed generation parameters and test case execution parameters, automatically start the next round of test case execution, and realize the batch continuous execution of dynamically self-optimized FPGA simulation test cases.
[0017] As an optional embodiment, in step 1, by reading the test case file file_lst, the test case name, module, estimated execution time and priority of each test case are extracted, and the past success rate, historical problem type and best seed list of the test cases are read from the historical knowledge base to construct a test case information structure (testcase_info) containing basic attributes and historical features. Then, based on the priority weight multiplied by the time factor, a sorting weight is calculated to generate a test case execution queue; The priority weights include three levels: HIGH, MEDIUM, and LOW, configured as follows: HIGH-100, MEDIUM-50, LOW-10; time factor = 1.0 / log. 10 , is used to indicate the estimated execution time.
[0018] Simultaneously, the execution environment initialization is completed, including reading toolchain version requirements, resource thresholds, and other configurations from the policy configuration library, and checking the availability and compatibility of the UVM and IP libraries; compiling the RTL code and verifying that there are no syntax errors; creating a working directory named after a timestamp and subdirectories named logs, results, waveforms, config, and temp, and setting read and write permissions; initializing the execution status tracking table and associating it with the real-time status library.
[0019] Further, in step 2, based on the system timestamp, a base seed is calculated using a hash function, including: Obtain the system timestamp at the millisecond level, generate a time base seed through a hash function, and ensure that the seed is unique for different use cases at the same time: The base seed is calculated as hash(timestamp + test case name) mod 2³².
[0020] Further, in step 3, an enhancement seed is generated based on historical execution records and coverage data, including: Data of use cases with historical execution records is extracted from the historical knowledge base. n historical seeds for the historical triggering issues of the use cases are extracted, and a mutation enhancement seed set is generated through mutation operations. These mutation operations include bit flipping, offset addition / subtraction, and golden ratio number operations. For example, a simple bit flipping mutation operation is as follows: Mutant seed = Success seed XOR (1 << (current minute mod 16))), generating 2 mutation seeds. The golden ratio number mutation operation is as follows: Mutant seed = (Success seed × Golden ratio number) mod 2³¹. The offset addition / subtraction mutation operation is as follows: Mutant seed = Success seed + Round number × Prime number. Extract coverage data from the historical knowledge base and identify low-coverage modules with a coverage rate of less than 80%: module signature = CRC32(module name) mod 65536; then generate a targeted seed by XORing the time-based seed with the module signature to focus on the uncovered code area.
[0021] In a further embodiment, the seed can be adjusted over time using a round factor (execution round number × the fractional part of the golden ratio), with the formula: final seed = base seed × (1 + round factor) mod 2³³, to ensure seed differences for different execution rounds.
[0022] Further, in step 4, for each test case, a random seed is generated based on the fusion of the time-based seed and the enhanced seed to obtain a seed package for each test case, including: Based on the test case execution queue from step 1, each test case is assigned a time base seed and at least one enhancement seed, wherein: For use cases with historical execution records, seed packages for use cases are assembled based on time-based seeds and historical enhanced seed sets; For test cases whose modules have coverage data and coverage is <80%, seed packages for test cases are assembled based on time-based seeds and targeted seeds; For use cases without historical data or coverage data, select a time-based seed to assemble the seed package for the use case.
[0023] This enables seed-use case binding, allocating a seed package containing n seeds to each use case (n is greater than or equal to 1, or 1 if there is no historical data or coverage data), obtaining the seed package (seed allocation table) corresponding to each use case, and a seed generation log recording the seed generation method and parameters for each seed, while also generating a seed generation strategy record.
[0024] Further, in step 5, based on the configured number of parallel executions, the number of test cases in each batch is calculated and the test case queue is divided into multiple batches. The number of test cases in each batch = min(number of parallel executions × 2, total number of test cases / 4). A JSON format execution plan file is created for each batch, including the test case name, seed package, timeout threshold, and priority. The file is saved to the config directory and synchronized to the real-time status database. The system initiates multi-threaded parallel execution based on the execution plan, reads test case seed packages and priorities from the real-time state database, executes them in batches, and executes several tasks in parallel in each batch. The system also monitors the execution progress and status of each test case in real time and synchronizes them to the real-time state database.
[0025] As mentioned above, the priority weights are configured as follows for different priorities: HIGH=100, MEDIUM=50, LOW=10.
[0026] The time factor is 1.0 / log. 10 This indicates the estimated execution time.
[0027] Therefore, by planning the batch execution of test cases, it is ensured that test cases of different modules within a batch are mixed and executed at similar times, balancing diversity and execution efficiency. Considering the dependencies between test cases, the batch execution order is planned and an execution plan file in JSON format is generated. In the subsequent parallel execution scheduling, multi-threaded execution of each batch of test cases is started based on the execution plan, and a corresponding seed package is allocated according to each test case, and the simulation is executed in seed order.
[0028] Furthermore, it can simultaneously monitor the utilization of resources such as CPU and memory in real time, as well as the execution progress and status of each use case.
[0029] As an optional implementation, the execution progress and status of each use case are monitored in real time, including: Regularly scan the simulation logs, extract the simulation time field to calculate the progress percentage: current simulation time / expected execution time × 100%, and synchronize it to the real-time state database; The detection includes keywords such as ERROR, FATAL, TIMEOUT, and failed, records the exception type, the seed involved, and the failed module, and synchronizes them to the real-time status database and exception record list; For timeout test cases where the runtime is greater than the timeout threshold, the test will be retried a maximum of 2 times using the unexecuted backup seed in the seed package. If it still fails, it will be marked as a failure and synchronized to the real-time state library. After each test case is completed, the execution status (PASS / FAIL), actual execution time, coverage data, and error information are collected, saved in JSON format to the results directory, a list of completed results is maintained, and synchronized to the real-time status database.
[0030] It should be understood that if the execution time of a use case scheduling task exceeds the timeout threshold, a termination signal is sent and the timeout information is recorded; if the task has not been attempted more than 3 times, it is re-added to the queue with a new seed, otherwise it is marked as "TIMEOUT_FAILED".
[0031] Furthermore, in step 6, the execution results of all use cases are extracted from the real-time state database. After extracting key metrics, problem pattern recognition and coverage analysis are performed, including: Extract all test case execution results from the real-time state database, and statistically analyze key parameters such as total number of test cases, number of executed test cases, number of pass / fail test cases, success rate, total simulation time, average execution time, and distribution of failed modules. At the same time, further cluster analysis can be performed on failed test cases to extract failure features such as error message patterns, failure time points, involved modules, and seed features. Cluster analysis is performed based on the distribution of failed test cases, and seed information corresponding to the failed test cases is associated. Specifically: if ≥3 test cases fail in the same module, it is identified as a module-level problem; if the same error message appears ≥2 times, it is identified as a function-level problem. At the same time, the severity of the problem can be calculated by combining the impact factor (number of failed test cases / total number of test cases involving the module). Merge coverage data, perform coverage analysis, identify coverage gaps based on the standard of areas with coverage less than 80% of the target value, and calculate coverage growth; Furthermore, use case failure records and coverage data are added to the historical knowledge base.
[0032] Simultaneously, in step 7, the seed effect score is calculated synchronously based on the use case execution results, and the seed validity is marked, including: Seed effectiveness scores are calculated based on execution data. Valid and invalid seeds are distinguished according to the seed effectiveness scores. Valid seeds are marked as reusable, and invalid seeds are marked as avoidable. Seed effectiveness marks are then synchronized to the historical database.
[0033] Furthermore, in step 8, the iterative seed generation parameters and test case execution parameters can be dynamically updated based on the updated historical knowledge base, automatically initiating the next round of test case execution, thereby achieving dynamic self-optimization of FPGA simulation test cases through batch continuous execution, including: Based on the seed performance score, if the proportion of effective seeds is less than or equal to 20%, the mutation intensity will be increased; if the proportion of ineffective seeds is greater than or equal to 50%, the mutation intensity will be decreased and updated to the strategy configuration library to optimize the random seed generation in subsequent rounds. Based on the test case failure records, synchronously generate test case optimization execution strategies: test cases that fail ≥ 2 times will undergo code review; test cases whose execution time exceeds twice the estimated time will be split into test cases. Based on the distribution of timeout test cases, if more than 10% of test cases are completed near the 90% threshold, the timeout threshold will be adjusted and increased, and the policy configuration library will be updated. Adjust the parallelism of test case execution based on resource utilization: if resource utilization is <70%, decrease the parallelism by -1; if utilization is >90% and the failure rate does not increase, increase the parallelism by +1.
[0034] In an optional embodiment, for multiple rounds of execution, the number, start and end time, decision result, parameters used, and result summary of each round can be recorded and saved to the round history database.
[0035] Therefore, by calculating the hash value of the basic seed for the next round, hash(current round basic seed + round number + current timestamp), the continuity of seeds between rounds is ensured and duplication is avoided.
[0036] Combination Figure 2 As shown, according to the present invention, a batch regression execution system for FPGA simulation test cases is also proposed, which is applicable to the aforementioned batch regression execution method for FPGA simulation test cases. The system includes a test case management module, a random seed generation module, a UVM simulation platform, a DPU network card, a result analysis module, and an iterative optimization module.
[0037] The test case management module is used to manage the test case files of FPGA simulation test cases.
[0038] The random seed generation module is used to generate a random seed for each test case based on the fusion of the time-based seed and the enhanced seed, thereby obtaining a seed package for each test case.
[0039] The batch execution control module is used to control the UVM simulation platform to start multi-threaded parallel execution according to the configured number of parallel executions and the execution plan.
[0040] The UVM simulation platform is used to read test case seed packets and priorities, generate simulation stimuli in batches, convert them into DUT interface format, and feed them into the DPU network card. Each batch starts and executes several tasks in parallel, and the execution progress and status of each test case are monitored in real time and synchronized to the real-time state database. The signals output by the DUT are converted into message format, compared with the input stimuli, and the simulation results are output.
[0041] The DPU network card is configured through logic code and executed as test cases in its simulation module, outputting in DUT format.
[0042] The results analysis module is used to extract the execution results of all use cases from the real-time state database, extract key indicators, perform problem pattern recognition and coverage analysis, calculate seed effect scores, and add seed validity markers, use case failure records, and coverage data to the historical knowledge base.
[0043] The iterative optimization module is used to dynamically update the iteration seed generation parameters and test case execution parameters based on the updated historical knowledge base, and automatically start the next round of test case execution to achieve batch continuous execution of dynamically self-optimized FPGA simulation test cases.
[0044] Therefore, the FPGA simulation test case batch regression execution method of the above embodiments of the present invention can realize full-process, self-optimizing FPGA batch simulation testing, improve the efficiency of problem discovery and coverage growth rate, and adapt to the continuous testing needs of large-scale FPGA designs.
[0045] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the claims.
Claims
1. A method for batch regression execution of FPGA simulation test cases, characterized in that, Includes the following processes: Step 1: Read the test case file of the preset FPGA simulation test cases and parse the key attributes of each test case line by line. Calculate the weight sorting based on priority weight and time factor to generate the test case execution queue. Step 2: Calculate the time base seed using a hash function based on the system timestamp; Step 3: Generate enhancement seeds based on historical execution records and coverage data; Step 4: For each test case, generate a random seed based on the fusion of the time-based seed and the enhanced seed to obtain the seed package for each test case; Step 5: Start parallel simulation in batches, allocate seeds from the seed package to each test case in the test case execution queue in sequence, execute the simulation in seed order and monitor the execution progress and status of each test case in real time, and synchronize to the real-time status library. Step 6: Extract the execution results of all use cases from the real-time state database, extract key indicators, and then perform problem pattern recognition and coverage analysis; Step 7: Calculate the seed effectiveness score based on the test case execution results, and add the seed validity mark, test case failure record, and coverage data to the historical knowledge base; Step 8: Based on the updated historical knowledge base, dynamically update the seed generation parameters and test case execution parameters, automatically start the next round of test case execution, and realize the batch continuous execution of dynamically self-optimized FPGA simulation test cases.
2. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 1, the test case file file_lst is read to extract the test case name, module, estimated execution time, and priority of each test case. The historical success rate, historical problem type, and best seed list of the test cases are read from the historical knowledge base to construct a test case information structure containing basic attributes and historical features. Then, based on the priority weight multiplied by the time factor, a sorting weight is calculated to generate a test case execution queue; The priority weights include three levels: HIGH, MEDIUM, and LOW, configured as follows: HIGH-100, MEDIUM-50, LOW-10; time factor = 1.0 / log. 10 , is used to indicate the estimated execution time.
3. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 2, the basic seed is calculated using a hash function based on the system timestamp, including: Obtain the system timestamp at the millisecond level, generate a time base seed through a hash function, and ensure that the seed is unique for different use cases at the same time: The base seed is calculated as hash(timestamp + test case name) mod 2³².
4. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 3, an enhancement seed is generated based on historical execution records and coverage data, including: Extract data of use cases with historical execution records from the historical knowledge base, extract n historical seeds of historical triggering issues of the use cases, and generate a mutation generation history enhancement seed set through mutation operations, wherein the mutation operations include one of bit flipping, adding or subtracting offsets, and golden ratio operations; Extract coverage data from the historical knowledge base and identify low-coverage modules with a coverage rate of less than 80%: module signature = CRC32(module name) mod 65536; then generate a targeted seed by XORing the time-based seed with the module signature to focus on the uncovered code area.
5. The FPGA simulation test case batch regression execution method according to claim 4, characterized in that, In step 4, for each test case, a random seed is generated based on the fusion of the time-based seed and the enhanced seed to obtain the seed package for each test case, including: Based on the test case execution queue from step 1, each test case is assigned a time base seed and at least one enhancement seed, wherein: For use cases with historical execution records, seed packages for use cases are assembled based on time-based seeds and historical enhanced seed sets; For test cases whose modules have coverage data and coverage is <80%, seed packages for test cases are assembled based on time-based seeds and targeted seeds; For use cases without historical data or coverage data, select a time-based seed to assemble the seed package for the use case.
6. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 5, based on the configured number of parallel executions, the number of test cases in each batch is calculated and the test case queue is divided into multiple batches. The number of test cases in each batch = min(number of parallel executions × 2, total number of test cases / 4). A JSON format execution plan file is created for each batch, including the test case name, seed package, timeout threshold, and priority. The plan is saved to the config directory and synchronized to the real-time status database. The system initiates multi-threaded parallel execution based on the execution plan, reads test case seed packages and priorities from the real-time state database, executes them in batches, and executes several tasks in parallel in each batch. The system also monitors the execution progress and status of each test case in real time and synchronizes them to the real-time state database.
7. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 5, the real-time monitoring of the execution progress and status of each use case includes: Regularly scan the simulation logs, extract the simulationtime field to calculate the progress percentage: current simulation time / expected execution time × 100%, and synchronize it to the real-time status database; The detection includes keywords such as ERROR, FATAL, TIMEOUT, and failed, records the exception type, the seed involved, and the failed module, and synchronizes them to the real-time status database and exception record list; For timeout test cases where the runtime is greater than the timeout threshold, the test will be retried a maximum of 2 times using the unexecuted backup seed in the seed package. If it still fails, it will be marked as a failure and synchronized to the real-time state library. After a test case is completed, the execution status (PASS / FAIL), actual execution time, coverage data, and error information are collected, saved in JSON format to the results directory, and synchronized to the real-time status database.
8. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 6, the execution results of all use cases are extracted from the real-time state database. After extracting key metrics, problem pattern recognition and coverage analysis are performed, including: Extract all test case execution results from the real-time state database, and statistically analyze the total number of test cases, pass rate, average execution time, and distribution of failed modules; Cluster analysis was performed based on the distribution of failed test cases, and seed information corresponding to the failed test cases was associated. Specifically, for ≥3 failed test cases in the same module, module-level problems were located, and for the same error message appearing ≥2 times, function-level problems were located. Merge coverage data, perform coverage analysis, identify coverage gaps based on the standard of areas with coverage less than 80% of the target value, and calculate coverage growth.
9. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 7, a seed performance score is calculated based on the test case execution results, and seed validity markers, test case failure records, and coverage data are added to the historical knowledge base, including: Seed effectiveness scores are calculated based on execution data. Effective and ineffective seeds are distinguished according to these scores. Effective seeds are marked for reuse, while ineffective seeds are marked for avoidance. These seed effectiveness markings are then synchronized to the historical database. Record failed test cases and coverage data in the historical knowledge base.
10. The FPGA simulation test case batch regression execution method according to claim 1, characterized in that, In step 8, the step of dynamically updating the iteration seed generation parameters and test case execution parameters based on the updated historical knowledge base, and automatically starting the next round of test case execution to achieve dynamic self-optimization of FPGA simulation test cases in batches and continuous execution includes: Based on the seed performance score, if the proportion of effective seeds is less than or equal to 20%, the mutation intensity will be increased; if the proportion of ineffective seeds is greater than or equal to 50%, the mutation intensity will be decreased and updated to the strategy configuration library to optimize the generation of random seeds in subsequent rounds. Based on the test case failure records, synchronously generate test case optimization execution strategies: test cases that fail ≥ 2 times will undergo code review; test cases whose execution time exceeds twice the estimated time will be split into test cases. Based on the distribution of timeout test cases, if more than 10% of test cases are completed near the 90% threshold, the timeout threshold will be adjusted and increased, and the policy configuration library will be updated. Adjust the parallelism of test case execution based on resource utilization: if resource utilization is <70%, decrease the parallelism by -1; if utilization is >90% and the failure rate does not increase, increase the parallelism by +1.
11. A batch regression execution system for FPGA simulation test cases, characterized in that, It includes a test case management module, a random seed generation module, a UVM simulation platform, a DPU network interface card, a results analysis module, and an iterative optimization module; The test case management module is used to manage the test case files of FPGA simulation test cases; The random seed generation module is used to generate a random seed for each test case based on the fusion of the time-based seed and the enhanced seed, and obtain a seed package for each test case. The batch execution control module is used to control the UVM simulation platform to start multi-threaded parallel execution according to the configured number of parallel executions and the execution plan; The UVM simulation platform is used to read test case seed packages and priorities, generate simulation stimuli in batch order, convert them into DUT interface form and inject them into the DPU network card. Each batch starts and executes several tasks in parallel, and monitors the execution progress and status of each test case in real time, and synchronizes them to the real-time status library. The DPU network card is configured through logic code, and test cases are called and executed in its simulation module; The results analysis module is used to extract the execution results of all test cases from the real-time status database, extract key indicators, perform problem pattern recognition and coverage analysis, calculate seed effect score, and add seed validity markers, test case failure records, and coverage data to the historical knowledge base. The iterative optimization module is used to dynamically update the iteration seed generation parameters and test case execution parameters based on the updated historical knowledge base, and automatically start the next round of test case execution to achieve batch continuous execution of dynamically self-optimized FPGA simulation test cases.