Data recording method, device, computer equipment, storage medium and program product
By configuring a chip with hardware breakpoint functionality, access-related information can be acquired and recorded, solving the problem of high cost in recording chip register access sequence information in existing technologies, and achieving efficient recording of access sequence information.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SPREADTRUM COMMUNICATION (SHANGHAI) CO LTD
- Filing Date
- 2026-03-10
- Publication Date
- 2026-05-29
AI Technical Summary
Recording chip register access sequence information in existing technologies is costly, increasing chip area and additional costs.
By configuring a chip with hardware breakpoint functionality, the chip's operating status can be obtained, the source address and general-purpose register values in the program counter can be read, access-related information can be recorded, and access sequence information can be constructed, thus avoiding the need to add additional monitoring modules.
This reduces the cost of recording access sequence information and eliminates the need to modify the chip's internal program or add a monitoring module, thus achieving efficient access sequence information recording.
Smart Images
Figure CN122111827A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of chip control, and in particular to a data recording method, apparatus, computer equipment, storage medium, and program product. Background Technology
[0002] In related technologies, mainstream SoC (System on a Chip) chip control is implemented through software access (read / write) of register mapping addresses. Chip stability issues are often related to configuration errors. Access sequence information contains details of register accesses by each instruction within a functional module. Therefore, when testing functional modules within a chip to pinpoint stability problems, obtaining the register access sequence information for that functional module can help developers / testers quickly locate the issue.
[0003] In related technologies, the common way to record the access sequence information of registers is to add a monitoring module to the chip bus to monitor register access and store each monitored access information in a dedicated RAM (Random Access Memory). However, adding a monitoring module will also increase the chip area, which will increase additional costs.
[0004] Therefore, how to reduce the cost of recording access sequence information is an urgent problem to be solved. Summary of the Invention
[0005] Therefore, it is necessary to provide a data recording method, apparatus, computer equipment, storage medium, and program product that can reduce the cost of recording access sequence information in order to address the above-mentioned technical problems.
[0006] In a first aspect, this application provides a data recording method, the method being applied to a computer device, the computer device communicating with a chip having a hardware breakpoint function, the method comprising:
[0007] During each instruction of the target module executed by the chip, the operating status of the chip is acquired; wherein, the instruction address corresponding to each instruction of the target module is configured as a read / write breakpoint.
[0008] When the running state is stopped, the source address stored in the program counter is read, and the source address is the instruction address of the target instruction currently being executed by the chip;
[0009] Read the runtime data and read the target instruction from the source address; the runtime data includes the values of various general-purpose registers within the chip;
[0010] The chip is controlled to execute the next instruction, and the target instruction, the source address, and the running data are used as access-related information of the target instruction, and the access-related information is recorded; wherein, the access-related information corresponding to each instruction of the target module is used to construct the access sequence information of the target module to the registers.
[0011] In one embodiment, the method further includes, before reading the runtime data:
[0012] Determine whether the source address is a program breakpoint; the program breakpoint is any address after the instruction address corresponding to the end instruction of the target module;
[0013] If it is determined that the source address is not the program breakpoint, then the running data is read.
[0014] In one embodiment, reading the target instruction from the source address includes:
[0015] Read the instruction code that identifies the target instruction from the source address;
[0016] The target instruction is determined based on the instruction code.
[0017] In one embodiment, the method further includes:
[0018] After generating the access-related information, the access-related information is parsed to obtain access details information;
[0019] Based on the access details, the access sequence information of the target module to the register is constructed.
[0020] In one embodiment, the method further includes:
[0021] After determining that the source address is a program breakpoint, the access-related information is parsed for each access-related information to obtain access details information;
[0022] Based on the access details, the access sequence information of the target module to the register is constructed.
[0023] In one embodiment, parsing the access-related information to obtain access details includes:
[0024] Parse the target instruction in the access-related information to obtain the operation action, operation object, and operation address;
[0025] Based on the operation object and the running data, determine the task data;
[0026] Based on the target instruction, the source address, the operation object, the operation action, the task data, and the operation address, construct the access details information of the target instruction.
[0027] Secondly, this application also provides a data recording device, which includes a status monitoring module, an address reading module, a data reading module, and a recording module, wherein:
[0028] The status monitoring module is used to acquire the operating status of the chip during each instruction of the target module; wherein, the instruction address corresponding to each instruction of the target module is configured as a read / write breakpoint.
[0029] The address reading module is used to read the source address stored in the program counter when the running state is stopped. The source address is the instruction address of the target instruction currently being executed by the chip.
[0030] The data reading module is used to read running data and read the target instruction from the source address; the running data includes the values of various general-purpose registers within the chip;
[0031] The recording module is used to control the chip to execute the next instruction and record the access-related information as the target instruction, the source address, and the running data as access-related information of the target instruction; wherein, the access-related information corresponding to each instruction of the target module is used to construct the access sequence information of the target module to the registers.
[0032] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the data recording method as described in any one of the first aspects above.
[0033] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the data recording method as described in any one of the first aspects above.
[0034] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the data recording method as described in any one of the first aspects above.
[0035] In the aforementioned data recording method, apparatus, computer equipment, storage medium, and program product, since the instruction addresses corresponding to each instruction of the target module are configured as read / write breakpoints, the CPU in the chip will stop execution and enter a break state after executing each instruction of the target module. At this time, the source addresses in the general-purpose registers and program counter are preserved. The running data in the general-purpose registers, the source addresses in the program counter, and the target instructions that the CPU has finished executing, obtained from the source addresses, are all recorded as access-related information of the target instructions. Furthermore, the computer equipment controls the CPU of the chip to execute the next instruction of the target module, and then obtains the access-related information of the next instruction after the execution of the next instruction. Finally, after all the instructions of the target module have been executed, the access-related information of each instruction in the target module can be obtained.
[0036] The access-related information represents the instruction's identity, storage location, and specific details of its register access. After obtaining the access-related information for each instruction in the target module through the above steps, the access sequence information for registers in the target module can be constructed based on this information. Furthermore, since hardware breakpoints are configured, there is no need to modify the internal program of the chip or add additional monitoring modules. The computer device only needs to be configured once and can be reused multiple times, thereby reducing the cost of recording access sequence information. Attached Figure Description
[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0038] Figure 1 This is a flowchart illustrating a data recording method in one embodiment;
[0039] Figure 2 This is a flowchart illustrating the process of reading target instructions in one embodiment;
[0040] Figure 3 This is a schematic diagram illustrating the process of constructing access sequence information in one embodiment;
[0041] Figure 4 This is a flowchart illustrating the process of parsing and accessing relevant information in one embodiment;
[0042] Figure 5 This is a logical schematic diagram of a data recording method in another embodiment;
[0043] Figure 6 This is a logical diagram illustrating the parsing of access-related information in another embodiment;
[0044] Figure 7 This is a schematic diagram illustrating the correspondence in one embodiment;
[0045] Figure 8 This is a structural block diagram of a data recording device in one embodiment;
[0046] Figure 9 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0048] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.
[0049] In related technologies, mainstream SoC (System on a Chip) chip control is implemented through software access (read / write) of register mapping addresses. Chip stability issues are often related to configuration errors. Access sequence information contains details of register accesses by each instruction within a functional module; specifically, the access details for a single instruction include: the instruction, the instruction address (source address) storing the instruction, the accessed register, the read and / or write operations, the task data, and the destination address.
[0050] Therefore, when testing functional modules in a chip to locate stability issues, obtaining the access sequence information of the registers of that functional module can help developers / testers quickly locate the problem.
[0051] The data recording method provided in this application can be applied to application environments where computer devices communicate and interact with SOC chips. The computer device communicates with the SOC (System on a Chip) chip; the SOC chip includes a CPU (Central Processing Unit), general-purpose registers, a PC register, and multiple IPs (Intellectual Property).
[0052] The PC register, also known as the program counter, stores the address of the next instruction to be executed after the current instruction has finished executing. The CPU directly reads the address of the instruction to be executed from the PC register, loads the instruction from the address, and executes it. The program counter directly determines the CPU's execution path. Chip IP refers to pre-developed and verified functional modules in integrated circuit design, which can be directly used in chip design to shorten the development cycle and reduce costs.
[0053] Computer equipment can include, but is not limited to, various personal computers, laptops, smartphones, tablets, drones, low-altitude aircraft, IoT devices, and portable wearable devices. IoT devices can include smart speakers, smart TVs, smart air conditioners, smart in-vehicle devices, projection equipment, etc. Portable wearable devices can include smartwatches, smart bracelets, head-mounted displays, etc. Head-mounted displays can include virtual reality (VR) devices, augmented reality (AR) devices, smart glasses, etc. Servers can be independent physical servers, server clusters or distributed systems composed of multiple physical servers, or cloud servers providing cloud computing services.
[0054] In an exemplary embodiment, a data recording method is provided, taking the application of the method to a computer device as an example; the data recording method provided in this application embodiment is applicable to SOC chips with hardware breakpoint function; wherein, the hardware breakpoint function of the SOC is a debugging function provided by the CPU, which allows developers to set breakpoints during program execution. When the program executes to a specific address or meets a specific condition, the CPU will stop the program execution and enter the break state (debug state), and instead execute the debug exception handling program, thereby facilitating debugging by developers.
[0055] Hardware breakpoints are controlled by the CPU's internal debug registers. They can be set to three trigger conditions: Execute breakpoint: triggered when the CPU executes an instruction at a specified address; Write breakpoint: triggered when the program writes data to a specified address; Read / Write breakpoint: triggered when the program reads data from or writes data to a specified address. By setting hardware breakpoints, breakpoints can be set without modifying the internal code of the System-on-a-Chip (SoC).
[0056] like Figure 1 As shown, the data recording method provided in this application embodiment includes the following steps 10-40, wherein:
[0057] Step 10: During each instruction of the target module executed by the chip, obtain the chip's operating status.
[0058] For the embodiments of this application, before the data recording process, environmental preparation work needs to be performed; wherein, the environmental preparation work includes: determining the target module for which data recording needs to be performed, and determining the instruction address of each instruction in the target module; setting the instruction address of each instruction in the target module as a read / write breakpoint; the environmental preparation work is completed.
[0059] After completing the environmental preparation, the computer equipment, through a debugger, controls the CPU in the SOC chip to execute each instruction in the target module sequentially. Specifically, the process of the CPU executing each instruction includes: the program counter loading the instruction addresses of each instruction sequentially according to the instruction order of the target module; the CPU directly reading the address of the instruction to be executed from the program counter; and executing the instruction after loading it from the instruction address.
[0060] Because the instruction addresses corresponding to each instruction in the target module are configured as read / write breakpoints, the CPU will stop execution and enter a break state after executing each instruction of the target module. Computer devices monitor the CPU's running state in the SoC through debuggers or other components. One possible implementation is to use debuggers such as Trace32 or J-Link, or to manipulate the running state of the controlled CPU in the SoC by running a small core independent of the controlled CPU.
[0061] Step 20: When the running state is stopped, read the source address stored in the program counter. The source address is the instruction address of the target instruction currently being executed by the chip.
[0062] In the embodiments of this application, when the computer device determines that the running state is a stopped state (break state), it determines that the current target instruction has been completed. At this time, the program counter (PC register) still stores the source address (instruction address) of the target instruction that has been completed. At this time, the computer device reads the source address (instruction address) of the target instruction stored in the program counter, and can determine the instruction that the CPU has finished executing through the source address.
[0063] Step 30: Read the execution data and read the target instruction from the source address; the execution data includes the values of various general-purpose registers in the chip.
[0064] In the embodiments of this application, the computer device reads the target instruction based on the source address (instruction address) read from the program counter; and the target instruction that has been executed has been accessed and read and / or written at least one of the general-purpose registers in the SOC as the operation object; however, which general-purpose register is the operation object needs to be further parsed according to the target instruction; therefore, at this time, it is necessary to record each general-purpose register and the value in each general-purpose register as the execution data of the target instruction.
[0065] Step 40: The control chip executes the next instruction and records the target instruction, source address, and running data as access-related information of the target instruction. Among them, the access-related information corresponding to each instruction of the target module is used to construct the access sequence information of the target module to the registers.
[0066] In this embodiment of the application, after acquiring the runtime data and reading the target instruction, the data recording of the target instruction is completed. At this point, the computer device, through a debugger, controls the CPU in the SOC chip to continue executing the next instruction of the target module. Further, the target instruction read by the computer device, along with its source address and runtime data, are constructed into an array for storage. This array represents the access-related information of the target instruction. The access-related information characterizes the identity of the target instruction, its storage location, and the specific details of its access to registers. After obtaining the access-related information of each instruction in the target module through the above steps, the access sequence information of the target module for registers can be constructed based on the access-related information of each instruction.
[0067] In the above data recording method, since the instruction addresses corresponding to each instruction of the target module are all configured as read / write breakpoints, the CPU in the chip will stop execution and enter a break state after executing each instruction of the target module. At this time, the source addresses in the general-purpose registers and the program counter will be preserved. The running data in the general-purpose registers, the source addresses in the program counter, and the target instructions that the CPU has finished executing, obtained from the source addresses, are all recorded as access-related information of the target instructions. Furthermore, the computer device controls the CPU of the chip to execute the next instruction of the target module, and then obtains the access-related information of the next instruction after the execution of the next instruction. Finally, after all the instructions of the target module have been executed, the access-related information of each instruction in the target module can be obtained.
[0068] The access-related information represents the instruction's identity, storage location, and specific details of its register access. After obtaining the access-related information for each instruction in the target module through the above steps, the access sequence information for registers in the target module can be constructed based on this information. Furthermore, since hardware breakpoints are configured, there is no need to modify the internal program of the chip or add additional monitoring modules. The computer device only needs to be configured once and can be reused multiple times, thereby reducing the cost of recording access sequence information.
[0069] Since the purpose of this solution is to record the access sequence information of the target module to the registers, program breakpoints are set in this embodiment to ensure that the CPU in the SOC chip can stop after executing all instructions of the target module. The program breakpoint is any address after the instruction address corresponding to the end instruction of the target module.
[0070] Therefore, when a computer device determines that the CPU in the SOC is in a stopped state, and before reading the running data, it also includes: determining whether the source address is a program breakpoint; the program breakpoint is any address after the instruction address corresponding to the end instruction of the target module; if it determines that the source address is not a program breakpoint, then the running data is read.
[0071] In other words, when the CPU is determined to be in a stopped state, the source address stored in the program counter is read, and it is determined whether this source address is a program breakpoint. If the source address read from the program counter is a program breakpoint, it means that all instructions in the target module have been executed, and there is no need to continue executing subsequent instructions; the computer device further controls the CPU to stop through the debugger to prevent it from executing subsequent instructions. If the source address read from the program counter is not a program breakpoint, it means that there are still unexecuted instructions in the target module; at this time, the computer device reads the running data and target instructions and records access-related information; after recording the access-related information, the computer device further controls the CPU in the SOC chip through the debugger to execute the next instruction in the target module.
[0072] In one embodiment, the instruction address may store the instruction itself; that is, in step 30, the computer device may directly read the target instruction from the source address.
[0073] In one embodiment, such as Figure 2 As shown, in step 30, the target instruction is read from the source address, which may specifically include steps 31 and 32, wherein:
[0074] Step 31: Read the instruction code that identifies the target instruction from the source address;
[0075] Step 32: Determine the target instruction based on the instruction code.
[0076] Specifically, each instruction address may store a unique identifier for the instruction, such as an identification code. The computer device then accesses the source address, reads the instruction code of the target instruction, and further retrieves the target instruction based on the instruction code.
[0077] As explained above, although the access-related information for each target instruction indicates that the target instruction accessed at least one of the general-purpose registers in the SOC as the operand, and performed a read and / or write operation, the specific general-purpose register that was the operand needs further analysis based on the target instruction. The following details the steps for constructing access sequence information based on the access-related information of each instruction.
[0078] In one embodiment, such as Figure 3 As shown, the data recording method further includes steps 50 and 60, which construct access sequence information based on access-related information of each instruction, wherein:
[0079] Step 50: After generating access-related information, parse the access-related information to obtain access details.
[0080] Specifically, the access details include: the instruction, the instruction address (source address) storing the instruction, the accessed register, the read and / or write operations, the task data, and the target address. However, the access information for each instruction only includes the target instruction and the source address storing the target instruction; therefore, for the target instruction and the execution data, it is necessary to further determine the accessed registers, the read and / or write operations, the task data, and the target address to obtain the complete access details.
[0081] Step 60: Based on each access detail information, construct the access sequence information of the target module to the registers.
[0082] Specifically, after parsing the access details of each instruction, the access details are arranged according to the execution order of the instructions, thereby constructing the access sequence information of the target module to the registers.
[0083] In one embodiment, such as Figure 4 As shown, in step 50, the access-related information is parsed to obtain access details, which may specifically include steps 51-53, wherein:
[0084] Step 51: Parse the target instruction in the access information to obtain the operation action, operation object, and operation address;
[0085] Step 52: Determine the task data based on the operation object and the running data;
[0086] Step 53: Construct access details information for the target instruction based on the target instruction, source address, operation object, operation action, task data, and operation address.
[0087] Specifically, for each target instruction, the computer device parses the relevant access information to obtain the corresponding operation (read / write / read+write), the operation object (at least one general-purpose register), and the operation address (to read data from or write data to that address). Further, from the execution data, the general-purpose register corresponding to the operation object is determined, and the value stored in that general-purpose register is read as the task data.
[0088] Furthermore, the computer device arranges the target instruction, source address, operation object, operation action, task data, and operation address in a preset order and converts them into a preset data format, thereby constructing access details information of the target instruction.
[0089] It should be noted that, in the embodiments of this application, after obtaining each access-related information, the access-related information can be parsed to obtain access details. Alternatively, after determining that the source address is a program breakpoint, that is, after determining that all instructions of the target module have been executed and obtaining the access-related information of each instruction, the access-related information can be parsed sequentially to obtain the access details of each access-related information.
[0090] The above describes a method for recording the access sequence information of registers by the target module. The following is a more specific embodiment to illustrate the detailed implementation process of this data recording method.
[0091] In one embodiment, the control register (instruction address) range of a certain IP (target module) is 0x30000000-0x3FFFFFFF, and it is desired to monitor all read and write operations of this IP on the register; if the program end address is set to 0x90000000, the control script (or program) flow is as follows:
[0092] The logic of the data recording method is as follows: Figure 5 As shown; where,
[0093] 1: Set the end address 0x90000000 as a program breakpoint; when the CPU executes an instruction at address 0x90000000, the CPU will terminate execution.
[0094] 2: Set all instruction addresses in the range 0x30000000 to 0x3FFFFFFF as read / write breakpoints.
[0095] 3: Control the CPU to execute (running).
[0096] 4: Read the CPU's running status and determine whether it is in running or break (debug) state.
[0097] 5: If the CPU is running, return to step 4 to continue reading.
[0098] 6: If the CPU is in a break state, read the source address (instruction address) stored in the PC register (program counter).
[0099] 7: Determine if the source address read is equal to the end address 0x90000000. If so, control the CPU to end execution; otherwise, read the values from all general-purpose registers X0-X30 as the running data.
[0100] 8: Access the source address read from the PC register to obtain the binary instruction code.
[0101] 9: Construct an array based on the source address, runtime data, instruction code, and / or (target instruction determined by the instruction code) as access-related information.
[0102] 10: Record access-related information in array index+1.
[0103] 11: Return to step 3 and continue execution.
[0104] Furthermore, in this embodiment, after obtaining the access-related information of each instruction in the target module, the access-related information is then parsed. The logic for parsing the access-related information is as follows: Figure 6 As shown, where:
[0105] 1: At the start of the parsing process, access-related information is parsed sequentially according to the execution order of instructions in the target module; the next access-related information to be parsed is then found.
[0106] 2: Based on the instruction code in the access information, determine the target instruction, parse the target instruction, and obtain the operation action (Load, Store, and Load+Store), the operation object (which general-purpose registers), and the offset address;
[0107] 3: Read the value in the register corresponding to the operation object as the task data; calculate based on the offset address and CPU register address to determine the actual target address for reading and writing; output the parsing results: target address, task data, and operation action.
[0108] 4: Determine if this is the last piece of data; if yes, end the parsing; if no, return to step 1 and continue execution.
[0109] Explanation of the principle: The assembly instructions corresponding to the Load / Store action contain the CPU register (source address) and the offset address. By adding the CPU register address and the offset address, the target address for reading and writing can be obtained.
[0110] like Figure 7 The diagram shows the correspondence between instruction address (source address), instruction code, and instruction.
[0111] by Figure 7 The selected area in the middle is an example. BF26DEEC is the source address read from the PC register, and A93E27AA is the instruction code: "stpx10, x9, [x29, #-0X20]; x10, x9, [x29, #-32]" is the step of the target instruction. The target instruction's function is to write the values in the x10 and x9 registers to the positions x29-0x20 and x29-0x20+0x8 respectively.
[0112] Parsing the target instruction reveals the operation is "store," targeting the general-purpose registers x10, x20, and x29, with an offset address of -0x20. From the task data, we find the corresponding values x10=0x100, x9=0x200, and x29=0x30000020. Calculating these values with the offset address yields the target address: 0x30000000 and 0x30000008. The instruction's purpose is to write 0x100 to 0x30000000 and 0x200 to 0x30000008. Specifically, 0xBF26DEEC: Write 0x100 -> 0x30000000; 0xBF26DEEC: Write 0x200 -> 0x30000008.
[0113] The above summarizes the execution logic of the data recording method in this application embodiment. The data recording method provided in this application embodiment relies on the CPU's hardware breakpoint functionality, such as ARM and RISC-V architecture CPUs, and has the following requirements for the CPU or SOC:
[0114] The CPU supports setting program breakpoints, which can be used to set the PC breakpoint at the end position.
[0115] The CPU supports setting read / write breakpoints for a data range.
[0116] The tool or independent small core can control the CPU to enter break and running states through the jtag or swd interface.
[0117] The tool or a separate small core can read whether the CPU is currently in a running or broken state.
[0118] In the break state, the tool or independent small core can read the CPU registers such as pc, r0, r1, etc.
[0119] In break state, the tool or independent small core can read the binary instruction data at the address where the pc is located.
[0120] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.
[0121] Based on the same inventive concept, this application also provides a data recording apparatus for implementing the data recording method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data recording apparatus embodiments provided below can be found in the limitations of the data recording method described above, and will not be repeated here.
[0122] In one exemplary embodiment, such as Figure 8 As shown, a data recording device 800 is provided. The device 800 includes a status monitoring module 801, an address reading module 802, a data reading module 803, and a recording module 804, wherein:
[0123] The status monitoring module 701 is used to acquire the chip's operating status during each instruction of the target module; wherein, the instruction addresses corresponding to each instruction of the target module are configured as read / write breakpoints.
[0124] The address reading module 802 is used to read the source address stored in the program counter when the running state is stopped. The source address is the instruction address of the target instruction currently being executed by the chip.
[0125] The data reading module 803 is used to read runtime data and read the target instruction from the source address; the runtime data includes the values of various general-purpose registers within the chip;
[0126] The recording module 804 is used to control the chip to execute the next instruction and to record the target instruction, source address and running data as access-related information of the target instruction. Among them, the access-related information corresponding to each instruction of the target module is used to construct the access sequence information of the target module to the registers.
[0127] In the aforementioned data recording device 800, since the instruction addresses corresponding to each instruction of the target module are configured as read / write breakpoints, the CPU in the chip will stop execution and enter a break state after executing each instruction of the target module. At this time, the source addresses in the general-purpose registers and the program counter will be retained. The running data in the general-purpose registers, the source addresses in the program counter, and the target instructions that the CPU has finished executing based on the source addresses will all be recorded as access-related information of the target instructions. Furthermore, the computer device controls the CPU of the chip to execute the next instruction of the target module, and then obtains the access-related information of the next instruction after the execution of the next instruction. Finally, after all the instructions of the target module have been executed, the access-related information of each instruction in the target module can be obtained.
[0128] The access-related information represents the instruction's identity, storage location, and specific details of its register access. After obtaining the access-related information for each instruction in the target module through the above steps, the access sequence information for registers in the target module can be constructed based on this information. Furthermore, since hardware breakpoints are configured, there is no need to modify the internal program of the chip or add additional monitoring modules. The computer device only needs to be configured once and can be reused multiple times, thereby reducing the cost of recording access sequence information.
[0129] In one embodiment, the data recording device 800 further includes a verification module, specifically used for:
[0130] Determine if the source address is a program breakpoint; a program breakpoint is any address after the address of the instruction corresponding to the end instruction of the target module.
[0131] If the source address is determined not to be a program breakpoint, then read the runtime data.
[0132] In one embodiment, the data reading module 803 is specifically used to: read instruction codes that represent the identity of the target instruction from the source address;
[0133] Determine the target instruction based on the instruction code.
[0134] In one embodiment, the data recording device 800 further includes a parsing module, wherein the parsing module is specifically used for:
[0135] After generating access-related information, the access-related information is parsed to obtain access details;
[0136] Based on the access details, construct the access sequence information of the target module to the registers.
[0137] In one embodiment, the parsing module is specifically used for:
[0138] After determining the source address as the program breakpoint, the access-related information is parsed for each access-related information to obtain access details;
[0139] Based on the access details, construct the access sequence information of the target module to the registers.
[0140] In one embodiment, the parsing module is specifically used for:
[0141] Parse the target instruction in the access information to obtain the operation action, operation object and operation address;
[0142] Determine the task data based on the target of the operation and the running data;
[0143] Based on the target instruction, source address, operation object, operation action, task data, and operation address, construct the access details information of the target instruction.
[0144] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.
[0145] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 9 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When the computer program is executed by the processor, it implements a data recording method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.
[0146] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0147] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the data recording method as described in any of the above-described data recording method embodiments.
[0148] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the data recording method as described in any of the above-described data recording method embodiments.
[0149] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of a data recording method as described in any of the above-described data recording method embodiments.
[0150] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.
[0151] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.
[0152] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.
[0153] The above embodiments merely illustrate several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.
Claims
1. A data recording method, characterized in that, The method is applied to a computer device that communicates with a chip equipped with hardware breakpoint functionality, and the method includes: During each instruction of the target module executed by the chip, the operating status of the chip is acquired; wherein, the instruction address corresponding to each instruction of the target module is configured as a read / write breakpoint. When the running state is stopped, the source address stored in the program counter is read, and the source address is the instruction address of the target instruction currently being executed by the chip; Read the runtime data and read the target instruction from the source address; the runtime data includes the values of various general-purpose registers within the chip; The chip is controlled to execute the next instruction, and the target instruction, the source address, and the running data are used as access-related information of the target instruction, and the access-related information is recorded; wherein, the access-related information corresponding to each instruction of the target module is used to construct the access sequence information of the target module to the registers.
2. The method according to claim 1, characterized in that, Before reading the runtime data, the method further includes: Determine whether the source address is a program breakpoint; the program breakpoint is any address after the instruction address corresponding to the end instruction of the target module; If it is determined that the source address is not the program breakpoint, then the running data is read.
3. The method according to claim 2, characterized in that, The step of reading the target instruction from the source address includes: Read the instruction code that identifies the target instruction from the source address; The target instruction is determined based on the instruction code.
4. The method according to claim 3, characterized in that, The method further includes: After generating the access-related information, the access-related information is parsed to obtain access details information; Based on the access details, the access sequence information of the target module to the register is constructed.
5. The method according to claim 3, characterized in that, The method further includes: After determining that the source address is a program breakpoint, the access-related information is parsed for each access-related information to obtain access details information; Based on the access details, the access sequence information of the target module to the register is constructed.
6. The method according to claim 4 or 5, characterized in that, The step of parsing the access-related information to obtain access details includes: Parse the target instruction in the access-related information to obtain the operation action, operation object, and operation address; Based on the operation object and the running data, determine the task data; Based on the target instruction, the source address, the operation object, the operation action, the task data, and the operation address, construct the access details information of the target instruction.
7. A data recording device, characterized in that, The device includes a status monitoring module, an address reading module, a data reading module, and a recording module, wherein: The status monitoring module is used to acquire the operating status of the chip during each instruction of the target module; wherein, the instruction address corresponding to each instruction of the target module is configured as a read / write breakpoint. The address reading module is used to read the source address stored in the program counter when the running state is stopped. The source address is the instruction address of the target instruction currently being executed by the chip. The data reading module is used to read running data and read the target instruction from the source address; the running data includes the values of various general-purpose registers within the chip; The recording module is used to control the chip to execute the next instruction and record the target instruction, the source address, and the running data as access-related information of the target instruction; wherein, the access-related information corresponding to each instruction of the target module is used to construct the access sequence information of the target module to the registers.
8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.
10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.