Power failure protection method and device for solid state disk

Abstract

The application provides a self-adaptive solid state disk power failure protection method and device. The method comprises the following steps: after triggering power failure, firstly, the physical address of the data to be persisted in the volatile cache is directly determined by calculation based on a pre-stored linear mapping relationship, so as to eliminate the energy consumption and delay of traditional traversal search; secondly, the real-time available energy of the energy storage array is obtained and compared with a preset energy demand threshold; the energy demand threshold is obtained based on load prediction; if the energy is insufficient, part of the data subset is abandoned to be written according to the dynamically generated data priority order; finally, the selected data subset is written into the non-volatile storage medium according to the calculated physical address. The application significantly improves the power failure protection success rate and system energy efficiency.

Description

Technical Field

[0001] This invention relates to the field of data storage technology, and specifically to a method and apparatus for power-loss protection of a solid-state drive. Background Technology

[0002] In enterprise-level data storage, to compensate for the slow write speed of non-volatile storage media (such as flash memory), volatile memory (such as dynamic random access memory) is typically used as a high-speed write cache. Data written by the host is first quickly stored in the volatile cache, acknowledged by the main controller, and then written in batches to the non-volatile storage media in the background, thus greatly improving the system's write performance and response speed. However, an inherent drawback of volatile memory is its data loss after power failure. Therefore, to prevent data loss due to unexpected power outages, storage devices must be equipped with power-loss protection circuits, typically composed of capacitors or supercapacitor arrays. These circuits provide emergency power within milliseconds after a mains power interruption, enabling the main controller to safely transfer the "data to be persisted" (i.e., data received but not yet written to the non-volatile media) and critical system metadata (such as logical-physical address mapping tables) from the cache to the non-volatile storage media, thus completing the persistent storage of data.

[0003] Current mainstream power-loss protection solutions generally adopt a worst-case "static maximization" configuration strategy. That is, during the hardware design phase, it is assumed that a power outage will occur in the most extreme case: at this point, the volatile cache is completely full, and all the data within is critical data that must be saved. Based on this assumption, engineers calculate the required energy and configure a corresponding large-capacity capacitor array. However, this strategy faces a serious but often overlooked systemic timing contradiction in practice. This contradiction is rooted in the inherent data organization and management methods of computer systems, rather than a simple problem of insufficient total energy.

[0004] The Mixed and Unordered Nature of Data in the Cache: A volatile cache is not a simple, ordered queue of data. To efficiently manage storage space and accelerate read and write operations, two types of data coexist in the cache: (a) data to be persisted: new data that needs to be protected; and (b) cache copies of already persisted data: old data copies that have been written to flash memory and temporarily retained to accelerate subsequent reads. In the event of a power failure, the system must precisely distinguish between the two and write only the former to flash memory. However, this data is not stored contiguously in the physical cache space, but rather distributed according to the available space at any given time.

[0005] Locating the data is a necessary prerequisite for persistence: writing data from the cache to flash memory is not simply a matter of copying the entire cache memory space. The main controller must perform two key pre-processing operations: First, location: it needs to find the specific physical address in the cache where each piece of data to be persisted is stored. Second, addressing: it needs to obtain the host logical address corresponding to each data block so that the global address mapping table can be correctly updated after writing to flash memory, ensuring that the data can be found after a system restart. This location and addressing information is typically managed using dynamic data structures such as linked lists, hash tables, or B+ trees, which are themselves stored in the volatile cache.

[0006] The high cost of traditional lookup processes in crisis situations: When a power outage occurs, the main controller, within the limited time window provided by the capacitor, must first traverse the aforementioned dynamic data structure, performing one or more scans and queries of the cache range to complete the location and addressing. This lookup process itself consumes a considerable number of processor clock cycles and corresponding power. However, in critical moments when the capacitor voltage decays exponentially (typically only tens of milliseconds), traditional linked list traversal or tree structure lookup operations may occupy precious milliseconds or even longer.

[0007] This leads to an awkward technical dilemma: a significant portion of the limited emergency energy is consumed in data processing overhead, specifically "finding which data needs to be saved and where it is," rather than being used entirely for the data saving operation of "physically writing the data to the storage medium." This ineffective energy loss due to data management (searching, sorting) severely restricts the actual effective data writing time and energy, often resulting in the loss of data that should have been saved in the cache due to power depletion at the last minute.

[0008] While existing technologies can extend power supply time by optimizing capacitor materials and increasing capacity, they fail to fundamentally resolve the timing and energy consumption contradictions introduced by data management methods. Summary of the Invention

[0009] To address the aforementioned technical problems, this invention proposes a solid-state drive power-loss protection method and device, aiming to eliminate data addressing overhead after power failure and achieve refined on-demand energy allocation and adaptive management throughout the entire lifecycle.

[0010] According to one aspect of the present invention, a power-loss protection method for a solid-state drive (SSD) is provided. The SSD includes a main controller, a volatile write cache, a non-volatile storage medium, and an energy storage array composed of multiple independently controllable capacitor units. After the main controller detects a power-loss trigger signal, the following steps are performed: In response to the power failure trigger signal, the physical offset address corresponding to all data to be persisted in the volatile write cache is determined by calculation based on the pre-established and maintained mapping relationship between logical addresses and physical offsets in the volatile write cache. Obtain parameters characterizing the current energy storage state of the energy storage array, and calculate the real-time available energy that can be used for data writing based on these parameters; The real-time available energy is compared with a preset energy demand threshold; the energy demand threshold is associated with the estimated energy required to write all the data to be persisted to the non-volatile storage medium. When the real-time available energy is lower than the energy demand threshold, a data subset is selected from all the data to be persisted according to a predetermined data priority order, such that the energy estimate required to write the data subset to the non-volatile storage medium does not exceed the real-time available energy. Based on the physical offset address determined in the above steps, the data in the data subset is persisted to the non-volatile storage medium.

[0011] Furthermore, the mapping relationship is implemented as follows: a linear storage area is allocated in the cache to centrally store the data to be written; a mapping function from logical address to physical offset is established for data in different logical address ranges; and the function parameters are recorded in a lookup table. The address determination process is as follows: the function parameters and error range are obtained by querying the lookup table; the predicted address is obtained by substituting them into the function; and the precise address is obtained by searching within the error range near the predicted address.

[0012] Furthermore, the energy demand threshold is dynamically calculated and updated by continuously analyzing the write command sequence, predicting future data increments, and combining flash memory write energy efficiency parameters.

[0013] Furthermore, the data priority order is formed by tracking the access attributes of the data and dynamically calculating priority scores according to rules, with system management data having the highest priority.

[0014] Furthermore, the state parameters of the energy storage array are obtained by measuring its terminal voltage and reading the effective capacity value that has been periodically calibrated.

[0015] Furthermore, during normal power supply, the number of capacitor cells in charging standby state is dynamically adjusted by controlling the switching devices on the capacitor cell branch based on the written load prediction results.

[0016] According to another aspect of the present invention, a power-loss protection device for a solid-state drive is provided. It includes: Main controller; A volatile write cache, connected to the main controller via a first data interface, is used to provide data to the main controller. Perform high-speed data access; A non-volatile storage medium is connected to the main controller via a second data interface; The energy storage array consists of multiple parallel capacitor units, with a controlled switch connected in series in the branch containing each capacitor unit. Device; the power output terminal of the energy storage array is coupled to the main controller and the non-volatile storage medium. A power supply network is used to provide emergency power during power outages; The power management unit is connected to the main controller via a control interface and to the energy storage array via a power management interface. A power link connection is used to manage the charging and discharging of the energy storage array according to the instructions of the main controller; The device is configured to perform the method described in the first aspect when triggered by a power failure.

[0017] Furthermore, the energy storage array is divided into a basic support group and a dynamic expansion group; the power management unit is configured to: during normal power supply, according to the instructions of the main controller, control the on / off state of the controlled switching devices in the dynamic expansion group, so as to selectively connect or isolate them to the charging circuit.

[0018] Furthermore, the device also includes a health monitoring circuit, the detection end of which is connected to the energy storage array, and its feedback end is communicatively connected to the main controller, for periodically detecting the electrical parameters of the energy storage array to assess its health status and calibrate the effective capacity value.

[0019] The beneficial effects of this application, compared to the prior art, are that it provides a method and installation method for power-loss protection of solid-state drives. The method includes: after the main controller detects a power-down trigger signal, in response to the power-down trigger signal, calculating and determining the physical address of all data to be persisted in the volatile write cache according to a pre-established and maintained mapping relationship between logical addresses and physical addresses; obtaining a parameter characterizing the current energy storage state of the energy storage array, and calculating the real-time available energy for data writing based on the parameter; comparing the real-time available energy with a preset energy demand threshold; the energy demand threshold is associated with the estimated energy required to write all data to be persisted to the non-volatile storage medium; when the real-time available energy is lower than the energy demand threshold, selecting a data subset from all data to be persisted according to a pre-determined data priority order, such that the estimated energy required to write the data subset to the non-volatile storage medium does not exceed the real-time available energy; and persisting the data in the data subset to the non-volatile storage medium according to the physical offset address determined in the previous step. This significantly improves the power-down protection success rate and system energy efficiency. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the architecture of a solid-state drive power-loss protection device provided in an embodiment of this application.

[0022] Figure 2 This is a flowchart illustrating a power-loss protection method for a solid-state drive provided in an embodiment of this application.

[0023] Figure 3 This is a flowchart illustrating the steps for calculating and determining the physical addresses of all data to be persisted in the volatile write cache according to an embodiment of this application.

[0024] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0026] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0027] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0028] In enterprise-grade and high-performance solid-state drives (SSDs), using volatile DRAM as a high-speed write cache has become a standard design for improving performance. However, the power-loss volatility of DRAM poses a risk of data loss, therefore a power-loss protection system consisting of a capacitor array must be provided to offer emergency power after an external power outage, enabling the main controller to safely write the data to be persisted from the cache to the non-volatile flash memory.

[0029] Traditional protection schemes generally employ static maximization configuration, assuming the worst-case scenario and configuring large-capacity capacitors. However, this scheme suffers from a system timing contradiction: after a power failure, the main controller first needs to traverse the complex dynamic data structures (such as linked lists and B+ trees) in the cache to locate which data needs to be saved and their specific locations. This addressing process itself consumes precious milliseconds of time and capacitor energy, severely compressing the effective window actually used for data writing. Furthermore, fixed-capacity capacitors cannot adapt to dynamically changing write loads, resulting in energy waste and additional heat generation under light loads, while under heavy loads or when capacitors age, insufficient energy may cause protection failure, exposing the device to risk.

[0030] To fundamentally resolve the aforementioned contradictions, this application proposes a method and device for power-loss protection of solid-state drives.

[0031] See Figure 1 , Figure 1 This is a schematic diagram of the architecture of a solid-state drive power-loss protection device provided in an embodiment of this application.

[0032] The device 100 protected in this application is a hardware entity specifically built to implement a power-loss protection method for solid-state drives. Its core lies in the specific connection relationship and functional configuration between various components, mainly including: a main controller 101, a volatile write cache 102, a non-volatile storage medium 103, an energy storage array 104, and a power management unit 105.

[0033] The device uses a main controller 101 as its core hub. The main controller 101 connects to a volatile write cache 102 (typically a DRAM chip) via a first data interface (e.g., a parallel bus compliant with the DDR standard). This interface provides a high-bandwidth, low-latency bidirectional data channel, enabling the main controller 101 to perform fast read and write operations on the cache, which is fundamental for data temporary storage and subsequent rapid location. Simultaneously, the main controller 101 connects to a non-volatile storage medium 103 (i.e., a NAND flash memory chipset) via a second data interface (e.g., a flash memory channel compliant with the ONFI or Toggle standard) for performing the final persistent data write and metadata management.

[0034] The core of this device's power supply is the energy storage array 104. This array is not a single capacitor, but rather composed of multiple capacitor units (which can be polymer capacitors, tantalum capacitors, or double-layer capacitors) connected in parallel. A key design feature is that a controlled switching device (such as a low-impedance MOSFET) is connected in series in the parallel branch containing each capacitor unit. This structure allows each or each group of capacitor units to be independently connected or disconnected. The power output of the energy storage array 104 is coupled (i.e., via wires, PCB traces, or a simple DC-DC converter) to the common power supply network of the main controller chip and the non-volatile memory chip's power input pins. This means that when the external main power supply fails, the energy storage array 104 becomes the direct emergency power source for these two critical chips, maintaining the voltage and current required for their continued operation. It is important to note that the volatile write cache (DRAM), due to its physical characteristics, cannot and does not need to be powered by the energy storage array for an extended period after a power outage. Its protection is achieved by transferring its contents to flash memory before the data is lost.

[0035] To intelligently manage the energy storage array 104, the device 100 is equipped with a power management unit 105 (typically a separate PMIC chip). This unit connects to the main controller 101 via a control interface (e.g., I²C, SPI, or GPIO) to receive various commands from the main controller 101. Simultaneously, it connects to the energy storage array via a power link (i.e., copper foil traces carrying large currents and possibly including power devices such as inductors) to execute specific charging and discharging control logic. The main controller 101 controls the on / off switching of various switching devices in the energy storage array 104 and adjusts charging parameters by sending commands to the power management unit 105.

[0036] Ultimately, the device 100 (as a whole) is configured to execute the method protected by this application upon power failure. This means that all the aforementioned hardware (main controller, cache, flash memory, array, PMIC) is organized through firmware or dedicated hardware logic circuits, enabling it to automatically and collaboratively complete a series of operations such as rapid data location, energy calculation and decision-making, and selective data writing after detecting a power failure signal.

[0037] In some embodiments, the main controller 101 or the system designer logically divides the capacitor units in the energy storage array 104 into two groups based on function: a basic protection group and a dynamic expansion group. The basic protection group typically consists of some capacitor units and is used to meet the basic power failure protection needs under normal light loads; the dynamic expansion group consists of the remaining capacitor units and serves as a supplementary energy reserve to cope with sudden heavy loads.

[0038] The specific implementation is as follows: the power output terminal of the power management unit 105 is connected to the two sets of capacitors through their respective independent switch control branches. During normal power supply, the load prediction logic (corresponding to the method claim) in the main controller 101 runs continuously. When a light load is predicted in the future, the main controller 101 sends a command to the power management unit 105 through the control interface, and the power management unit 105 keeps the switching devices of the branch where the dynamic expansion group is located in the open state accordingly. At this time, the dynamic expansion group is physically isolated from the main charging circuit, neither charging nor generating static leakage current, thereby significantly reducing the overall power consumption and heat generation of the system. When a surge in write load is predicted or detected, the main controller 101 immediately issues a command, and the power management unit 105 closes the switching devices of the dynamic expansion group, enabling it to quickly connect to the charging circuit and complete charging in a short time, thereby enabling the total energy reserve of the entire energy storage array 104 to reach a high standby level. This design realizes on-demand activation of energy reserves, optimizing energy efficiency and component life while ensuring protection capabilities.

[0039] In some embodiments, to ensure the reliability of device 100 throughout its entire lifecycle, this application also adds a health monitoring circuit. This circuit typically includes a high-precision analog-to-digital converter (ADC), a signal generator driver, and a communication interface with the main controller 101. Its detection end is connected to the energy storage array 104 via components such as precision sampling resistors to apply test signals and acquire responses; its feedback end is connected to the main controller via a communication link (such as an I²C bus shared with the PMIC).

[0040] The specific workflow is periodic: During the idle period of the solid-state drive (SSD), the main controller 101 instructs the health monitoring circuit to initiate a test. The circuit applies a small-amplitude test current pulse with a specific waveform, measured in microseconds, to the energy storage array, and simultaneously acquires the transient voltage response waveform across the energy storage array at high speed. The acquired raw data is sent to the main controller 101. The algorithm inside the main controller 101 analyzes this waveform and calculates key electrical parameters, such as the initial slope of the voltage drop (directly related to the equivalent series resistance ESR), the voltage recovery time constant (reflecting dielectric loss), and the self-discharge rate after rest. Using these parameters, the main controller 101 can assess the overall health status of the energy storage array 104 and quantify its capacity degradation ratio. Subsequently, the main controller 101 uses this health information to dynamically calibrate the "effective capacity value" used for energy calculation and may adjust control parameters such as the charging voltage threshold of the power management unit 105. This enables the device to sense hardware aging and proactively tighten policy boundaries, thereby providing deterministic core data protection even after capacitor performance deteriorates.

[0041] See Figure 2 , Figure 2 This is a flowchart illustrating a power-loss protection method for a solid-state drive provided in an embodiment of this application. The method includes the following steps: Step 10: In response to the power-down trigger signal, based on the pre-established and maintained logical address and physical address... The mapping relationship between addresses is used to calculate and determine the physical addresses of all data to be persisted in the volatile write cache.

[0042] This step aims to completely avoid time-consuming memory traversal after a power outage, obtaining the precise storage location of the data to be persisted through direct calculation and fine-tuning. Its implementation is based on an address mapping mechanism established and maintained during normal operation.

[0043] This mechanism is built upon the volatile write cache 102. During normal device operation, the main controller 101 allocates a contiguous physical memory space within the volatile write cache 102 as a centralized storage area for data to be persisted. When data is written to this area, it is not written in a tightly packed manner, but rather a certain proportion of free storage units are forcibly reserved within preset logical segments; these units constitute buffer intervals. The main controller 101 continuously monitors and analyzes the data stored in this area, accurately recording the correspondence between the logical block address of each data block and its actual physical offset within this contiguous space.

[0044] Based on the correspondence of these records, the main controller 101 performs background modeling for different logical address intervals. It uses mathematical fitting methods (such as least squares) to calculate a set of optimal parameters for each logical address interval, thereby constructing a linear mapping function in the form: Physical Offset = k × LBA + b. This function can approximate the mapping pattern from logical address to physical address within the interval with minimal error. During the fitting process, the main controller 101 simultaneously calculates the maximum prediction error range of this linear model under the current data distribution; this error value (denoted as ε) quantitatively characterizes the degree of approximation of the mapping.

[0045] All these computational results—namely, the linear function parameters (k, b) corresponding to each logical address interval and their associated error range ε—are integrated and stored in a structured lookup table within the on-chip static memory of the main controller 101, which can be directly accessed at high speed. This table serves as a "navigation directory" for the global address mapping, characterized by extremely fast access speed and near-zero static power consumption.

[0046] When the power failure trigger signal arrives and the emergency procedure is initiated, the main controller 101 immediately executes the process for each piece of data that needs to be saved and persisted. Figure 3 The defined operations, Figure 3 A flowchart illustrating the steps for calculating and determining the physical addresses of all data to be persisted in the volatile write cache according to an embodiment of this application includes: Step 11: For any data to be persisted, query the lookup table based on its logical address to obtain the corresponding... The linear function parameters and a preset positioning error range; Step 12: Substitute the logical address into the linear function to obtain the predicted physical address; Step 13: Perform the operation within the memory space defined by the predicted physical address and the positioning error range. Search to find the precise physical address.

[0047] First, the main controller uses the logical address of the data as the key to look up the lookup table in the on-chip SRAM. This operation is a deterministic, constant-time access, from which the main controller directly obtains the pre-calculated linear function coefficients (k, b) and the positioning error range ε ​​corresponding to the interval to which the logical address belongs.

[0048] Next, linear computation is performed. Using the acquired k and b, the main controller (or its dedicated arithmetic unit) performs a simple multiply-accumulate operation: Predicted physical address = k × LBA + b. This step transforms the "addressing" problem into a purely arithmetic problem, which can be completed in one or a few clock cycles, generating a predicted address pointing to the linear memory region of the cache.

[0049] Finally, a bounded local search is performed. Because of the reserved buffer intervals during data storage, the actual data page may not occupy the precisely predicted address. Therefore, the main controller 101 defines a very small, contiguous physical address search window in the volatile write cache, centered on the predicted physical address and with the error range ε ​​obtained from the lookup table as the radius. Subsequently, an efficient local search (such as a binary search) is performed within this window. Thanks to the error range ε ​​being strictly limited to a very small value (typically covering only a few adjacent memory units), this search requires only a very small number of memory accesses to locate the precise physical address of the data block within nanoseconds to microseconds.

[0050] Step 20: Obtain parameters characterizing the current energy storage state of the energy storage array, and calculate the real-time available energy that can be used for data writing based on these parameters.

[0051] This step aims to accurately quantify the total energy currently available from the energy storage array for data writing. The main controller 101, via circuitry connected to the power management unit 105 (PMIC), measures the total output voltage V of the energy storage array 104 (i.e., the entire array composed of multiple parallel capacitor cells, each with a series switch) in real time. Simultaneously, the main controller 101 reads an effective capacity value C. This value is not fixed but dynamically calibrated through a periodically executed probing procedure: when idle, the main controller 101 applies a microsecond-level test current pulse to the energy storage array 104 and acquires its voltage response waveform; by analyzing the voltage change characteristics, the equivalent series resistance and charge retention capability of the capacitors can be evaluated, thereby calculating their current effective capacity to offset the effects of aging.

[0052] Based on the measured real-time voltage V and the calibrated effective capacity C, the system calculates E using the formula E = 0.5 * C * V. ^2 The real-time available energy E is calculated, in joules. This energy value forms the basis for all subsequent decisions.

[0053] Step 30: Compare the real-time available energy with a preset energy demand threshold; the energy demand threshold is related to the estimated energy required to write all the data to be persisted to the non-volatile storage medium.

[0054] This step aims to determine whether the current energy is sufficient to complete the task of saving all the data to be persisted. The energy requirement threshold used by the main controller 101 for comparison is a dynamic value that is continuously calculated and updated during normal power supply. This value is calculated based on continuous analysis of the host write command stream: information such as the arrival time and data size of write commands is collected, and time series analysis methods (such as multi-scale decomposition) are used to predict the total amount of data to be persisted that is expected to accumulate in the volatile write cache within a preset protection time window (e.g., 50 milliseconds). Subsequently, this predicted data amount is multiplied by a known unit energy consumption coefficient related to the current write power consumption of the non-volatile storage medium 103 to convert it into the estimated energy value required to complete the writing of this data, which is the energy requirement threshold.

[0055] At the moment of power failure, the main controller 101 directly compares the real-time available energy calculated in step 20 with this dynamically updated energy demand threshold. The result of this comparison is a crucial judgment that determines the subsequent process.

[0056] Step 40: When the real-time available energy is lower than the energy demand threshold, select a data subset from all the data to be persisted according to a predetermined data priority order, such that the estimated energy required to write the data subset to the non-volatile storage medium does not exceed the real-time available energy.

[0057] When step 30 determines that the real-time available energy is lower than the demand threshold, step 40 is initiated, selectively saving a portion of the data to be persisted. This selection is based on a set of data priority rules dynamically maintained during operation. These rules continuously track the access history (e.g., access frequency, last access time) and data attributes (e.g., whether it is file system metadata, user file data, etc.) of each data block in the cache, calculating and updating a priority score for each data block in real time. Key metadata (such as address mapping tables) is always assigned the highest score.

[0058] When power is lost and energy is insufficient, the main controller 101 sorts all data to be persisted from highest to lowest priority score. Then, starting with the data with the highest score, it sequentially accumulates the estimated energy consumption required to write each data block until the accumulated value is about to exceed the real-time available energy obtained in step 20. At this point, the set of data blocks that have been accumulated constitutes the final selected data subset. The remaining data blocks in the sorting process are actively marked as not needing to be saved, and their corresponding buffer states are immediately updated, thus being skipped in subsequent write operations.

[0059] Step 50: Based on the physical offset address determined in the previous step, persist the data in the data subset to the non-volatile storage medium.

[0060] This step is the final write execution phase. For each data block in the subset of data selected in step 40, the main controller 101 again goes through the process of step 10 to obtain its precise physical address in the volatile write cache. Subsequently, the main controller 101 initiates the direct memory access (DMA) controller, reads the data block content and its necessary logical address information from the cache according to these addresses, and writes the data to the non-volatile storage medium (NAND flash memory) through the flash interface channel. At the same time, the system must update the address mapping table in the flash memory with the new physical location information of the data to ensure that the data can be accessed correctly after a restart. The entire write process will continue until all selected data blocks have been written, or the energy storage array voltage drops to a level that cannot sustain operation.

[0061] In summary, this application, through the aforementioned power-loss protection method and device, brings the following significant benefits: First, it achieves near-zero addressing energy consumption. By replacing the traditional time-consuming cache traversal with direct calculation based on linear mapping, valuable emergency energy is completely freed from the unnecessary consumption of "data searching" and concentrated entirely on effective data writing operations, effectively increasing available energy without increasing any capacitor hardware costs. Second, it provides deterministic protection capabilities with millisecond-level response. The system can clearly know how much data can be protected instantly upon power failure through accurate load prediction and real-time energy auditing, and execute the optimal "sacrifice a pawn to save the rook" strategy based on data value priority. This fundamentally eliminates the blindness and uncertainty of traditional solutions and greatly improves the system survivability under extreme conditions. Finally, adaptive reliability maintenance throughout the entire lifecycle is achieved. Through real-time monitoring and dynamic calibration of the health status of energy storage components, the system can sense its own functional decline like a living organism and actively adjust the energy budget and protection strategy. Thus, even after the equipment has been in service for many years and the capacitor performance has naturally degraded, the system can still ensure the absolute security of core metadata through the degradation mode, avoiding the precipitous drop in protection capability in traditional designs and ensuring the consistency and reliability of storage devices throughout their entire lifecycle from manufacturing to obsolescence.

[0062] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0063] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0064] The above are merely optional embodiments of this application and do not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A power-loss protection method for a solid-state drive (SSD), the SSD comprising a main controller, a volatile write cache, a non-volatile storage medium, and an energy storage array composed of multiple independently controllable capacitor units, characterized in that... After the main controller detects the power failure trigger signal, it performs the following steps: In response to the power failure trigger signal, the physical offset address corresponding to all data to be persisted in the volatile write cache is determined by calculation based on the pre-established and maintained mapping relationship between logical addresses and physical offsets in the volatile write cache. Obtain parameters characterizing the current energy storage state of the energy storage array, and calculate the real-time available energy that can be used for data writing based on these parameters; The real-time available energy is compared with a preset energy demand threshold. The energy requirement threshold is associated with the estimated energy required to write all the data to be persisted to the non-volatile storage medium. When the real-time available energy is lower than the energy demand threshold, a data subset is selected from all the data to be persisted according to a predetermined data priority order, such that the energy estimate required to write the data subset to the non-volatile storage medium does not exceed the real-time available energy. Based on the physical offset address determined in the above steps, the data in the data subset is persisted to the non-volatile storage medium.

2. The method according to claim 1, characterized in that, The pre-established and maintained mapping relationship is achieved through the following steps: In the volatile write cache, a contiguous physical memory space is allocated as a linear storage area to centrally store data to be persisted; For data stored in the linear storage area, a mapping function from logical address to physical offset is established for different logical address ranges based on the correspondence between its logical address and physical offset within the linear storage area. Each logical address range and its corresponding mapping function parameters are recorded in a lookup table.

3. The method according to claim 2, characterized in that, The step of calculating and determining the physical addresses of all data to be persisted in the volatile write cache includes: For any data to be persisted, query the lookup table based on its logical address to obtain the corresponding linear function. Numerical parameters and a preset positioning error range; Substituting the logical address into the linear function yields the predicted physical address; A search is performed within the memory space defined by the predicted physical address and the positioning error range. Find the precise physical address.

4. The method according to claim 1, characterized in that, The energy demand threshold is dynamically set in the following manner: During normal power supply to the SSD, the sequence of write commands from the host is continuously analyzed to predict future write commands. The expected increase in the amount of data to be persisted in the volatile write cache within a specified time period; Based on the predicted data volume and the write energy efficiency parameters of the non-volatile storage medium, the following calculations are obtained: Determine the energy demand threshold and keep it updated.

5. The method according to claim 1, characterized in that, The predetermined data priority order is achieved through the following steps: During the operation of the solid-state drive, the access status and attributes of data in the volatile write cache are tracked and recorded. Based on the access status and attributes, data is allocated and its priority is dynamically adjusted according to preset rules. The scores are assigned to system management data, which are given a constant highest priority.

6. The method according to claim 1, characterized in that, The step of obtaining parameters characterizing the current energy storage state of the energy storage array includes: measuring the terminal voltage of the energy storage array and reading an effective capacity value that has been periodically calibrated.

7. The method according to any one of claims 1 to 6, characterized in that, During normal power supply to the solid-state drive, the following steps are also performed: Based on the predicted write load, the number of capacitor cells in the charging standby state is changed by controlling the on / off state of the switching devices connected to the parallel branches of each capacitor cell in the energy storage array.

8. A solid-state drive power-loss protection device, characterized in that, include: Main controller; A volatile write cache, connected to the main controller via a first data interface, is used to provide data to the main controller. Perform high-speed data access; A non-volatile storage medium is connected to the main controller via a second data interface; The energy storage array consists of multiple parallel capacitor units, with a controlled switch connected in series in the branch containing each capacitor unit. Device; the power output terminal of the energy storage array is coupled to the main controller and the non-volatile storage medium. A power supply network is used to provide emergency power during power outages; The power management unit is connected to the main controller via a control interface and to the energy storage array via a power management interface. A power link connection is used to manage the charging and discharging of the energy storage array according to the instructions of the main controller; The device is configured to perform the method as described in any one of claims 1 to 7 when triggered by a power failure.

9. The apparatus according to claim 8, characterized in that, The energy storage array is divided into a basic protection The power management unit is configured to, during normal power supply, control the switching of controlled switching devices in the dynamic expansion group according to the instructions of the main controller, so as to selectively connect or isolate them from the charging circuit.

10. The apparatus according to claim 8 or 9, characterized in that, The device also includes health monitoring. The circuit, wherein the detection end of the health monitoring circuit is connected to the energy storage array, and its feedback end is communicatively connected to the main controller, is used to periodically detect the electrical parameters of the energy storage array to assess its health status and calibrate the effective capacity value.

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