Multi-mode single-ended transmitter based on power-optimized reception and data bus inversion

Abstract

An NRZ / PAM-3 / PAM-4 multi-mode transmitter comprises eight identical data channels and two identical differential feedforward clock channels, the differential feedforward clock channels generate two differential clock signals according to a half-rate differential clock and output to a receiving end, the data channels perform serialization, equalization and DBI encoding processing on a plurality of pseudo-random binary sequences (PRBS) according to a mode control word and a clock signal output by the differential feedforward clock channels, and output the DBI encoded data to the receiving end; through power optimal receiving end termination, clock embedded DBI and multi-mode architecture technology, the ability of low power consumption, high energy efficiency and high bandwidth transmission can be realized.

Description

Technical Field

[0001] This invention relates to a technology in the field of wired communication, specifically an NRZ / PAM-3 / PAM-4 multimode single-ended transmitter that combines optimal power receiver termination and clock-embedded data bus flip-flop technology. Background Technology

[0002] While existing NRZ / PAM-3 / PAM-4 single-ended transmitters lack complete analysis and implementation of optimal receiver termination for driver power, the additional DBI flag pins in existing PAM-4 and NRZ DBI technologies reduce transmitter pin efficiency, and existing PAM-3 pDBI technology embeds the DBI bit into the data path, reducing the effective data rate per pin. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes a multi-mode single-ended transmitter based on power-optimal reception and data bus switching. Through power-optimal receiver termination, clock-embedded DBI, and multi-mode architecture technology, it can achieve low power consumption, high energy efficiency, and high bandwidth transmission capabilities.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to a multi-mode single-ended transmitter based on power-optimal reception and data bus switching, comprising: eight identical data paths and two identical differential feedforward clock paths, wherein: the differential feedforward clock paths generate two differential clock signals according to a half-rate differential clock and output them to the receiver; the data paths, based on the mode control word and clock signal output by the differential feedforward clock paths, perform serialization, equalization, and DBI encoding processing on multiple pseudo-random binary sequences (PRBS), and output the DBI-encoded data to the receiver.

[0006] Each data path includes: a pseudo-random binary sequence (PRBS) generator, a multi-mode serializer, an encoder, a multi-mode DBI module, a retiming and phase shifter, a high-speed serializer, a main driver with a single-ended power isolation low-voltage swing termination logic (PI-LVSTL) structure, and a capacitively coupled feedforward equalizer (CC-FFE). Specifically: the 31st-order PRBS generator produces 48 data streams per channel, which are output to the multi-mode serializer of each channel; the multi-mode serializer operates in one of PAM-4 / PAM-3 / NRZ modes according to the mode control word output from the differential feedforward clock path, serializing the 48 parallel data streams to obtain 1 / 4 rate data before outputting it to the encoder; the encoder, according to the corresponding operating mode, encodes the 1 / 4 rate data... The code becomes the control signal for the driver and is output to the multi-mode DBI module; the multi-mode DBI module collects all the data from the eight data paths, performs selective DBI encoding, and outputs it to the retiming and phase shifter. After parallel data alignment and timing the data into four time-interleaved channels, it is output to the high-speed serializer; the high-speed serializer serializes the four time-interleaved 1 / 4 rate data into full rate data and outputs them to the main driver and CC-FFE respectively; the main driver uses the control data for the pull-up and pull-down branches to generate PAM-4 / PAM-3 / NRZ data corresponding to the mode. At the same time, the CC-FFE, based on capacitive coupling, only generates short pulses at the data edges and superimposes them with the data output by the main driver to accelerate edge switching. The superimposed data is sent to the receiver through the channel.

[0007] The selective DBI encoding refers to: collecting all data from eight data paths and counting the data in the same unit interval (UI). If the number of zeros exceeds half, the UI is DBI encoded in PAM-4 / PAM-3 mode, but NRZ data is passed directly without processing.

[0008] Each differential feedforward clock path includes: a clock buffer, a quadrature phase clock generator, a quadrature error correction and duty cycle correction module, a multimode divider, a clock DBI module, a clock high-speed serializer, a clock master driver, and a clock CC-FFE. Specifically: the clock buffer amplifies the externally input half-rate differential clock to full swing before outputting it to the quadrature phase clock generator; the quadrature phase clock generator divides the differential half-rate clock into four mutually orthogonal 1 / 4-rate clocks and outputs them to the quadrature error correction and duty cycle correction module to correct the phase difference and duty cycle between the four phases, and then outputs these corrections to the multimode divider, the clock DBI module, the clock high-speed serializer, and the data path retiming module. The circuit includes a phase shifter; a multi-mode divider divides the 1 / 4 rate clock into frequencies, and selects the corresponding rate clock signal to output to the multi-mode serializer and PRBS generator in the data path according to different operating modes; the clock DBI module modulates the clock amplitude according to the DBI flag generated by the multi-mode DBI module, and the clock high-speed serializer serializes it into a full-rate clock driver control signal, which is then output to the clock master driver and CC-FFE driver respectively; the clock master driver generates a corresponding differential clock signal at the output terminal according to the clock driver control signal, and the clock CC-FFE generates a short pulse at the edge through the coupling capacitor and superimposes the output signal with the clock signal generated by the master driver before sending it to the receiving end through the channel.

[0009] Technical effect

[0010] This invention is compatible with NRZ / PAM-3 / PAM-4 modes. Except for the multimode serializer and encoder in the data path and the multimode divider in the clock path, the remaining modules share a high degree of multimode single-ended voltage transmitter. Compared with the prior art, this invention significantly improves mode compatibility while minimizing hardware overhead, area overhead and power consumption. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of the present invention;

[0012] Figure 2 This is a schematic diagram illustrating the working principle of clock-embedded DBI technology.

[0013] Figure 3 A schematic diagram illustrating the working principle of the driver in three modes;

[0014] Figure 4 The termination curve is shown in the example.

[0015] In the figure: (a) are the curves of expected signaling current for PAM-3 and PAM-4 as a function of receiver termination; (b) are the curves of total expected signaling current for the three modes as a function of receiver termination.

[0016] Figure 5 A comparison chart of I / O bandwidth for clock-embedded DBI technology and PAM-4DBI and PAM-3pDBI technologies;

[0017] Figure 6 A schematic diagram of a majority voting system;

[0018] Figure 7 A schematic diagram of a DBI encoder;

[0019] Figure 8 This is a schematic diagram of the clock DBI module;

[0020] Figure 9 Timing diagrams generated for the PU_MSB_CLK_DBI and PU_LSB_CLK_DBI control signals;

[0021] Figure 10 This is a rendering of an example.

[0022] In the figure: (a) is the layout of the embodiment; (b) is the channel characteristics of the embodiment;

[0023] Figure 11 The following is a diagram of the rear eye in the embodiment;

[0024] Figure 12 The power consumption breakdown diagram is shown in the example. Detailed Implementation

[0025] like Figure 1 As shown in the embodiment, a multi-mode single-ended transmitter based on power-optimal reception and data bus flipping is provided, comprising: eight identical data paths and two differential feedforward clock paths. Each data path includes: a PRBS generator, a multi-mode serializer, an encoder, a multi-mode DBI module, a retiming and phase shifter, a high-speed serializer, and a parallel main driver and CC-FFE connected in sequence. Each differential feedforward clock path includes: a clock buffer, a quadrature phase clock generator, a quadrature error correction and duty cycle correction module, a multi-mode divider, a clock DBI module, a clock high-speed serializer, and a parallel clock main driver and clock CC-FFE.

[0026] The PRBS generator in the data path generates parallel data at a corresponding rate according to the mode control word and outputs it to the corresponding multimode serializer. The multimode serializer and encoder operate in the corresponding mode according to the mode control word.

[0027] The corresponding rates refer to the following: when operating in PAM-4 mode, each PRBS31 chip generates 667 Mbps of parallel data (48 bits); when operating in NRZ mode, each PRBS31 chip generates 333 Mbps of parallel data (48 bits); and when operating in PAM-3 mode, each PRBS31 chip generates 500 Mbps of parallel data (48 bits).

[0028] If operating in PAM-4 mode, the 48:24 serializer serializes 48-bit parallel data at a rate of 667 Mbps into 24-bit parallel data at a rate of 1.33 Gbps. The subsequent 24:8 serializer serializes the 24-bit parallel data at a rate of 1.33 Gbps into 8-bit parallel data at a rate of 4 Gbps. The PAM-4 encoder generates the corresponding 16-bit parallel driver control signal at a rate of 4 Gbps according to the encoding rules in Table 1.

[0029] Table 1

[0030] As shown in Table 1, the odd-numbered bits of the 8-bit input are used as the 2-bit MSB and the even-numbered bits are used as the LSB, for a total of 4 groups. If operating in NRZ mode, the 48:24 serializer serializes the 48-bit parallel data at a rate of 333Mbps into 24-bit parallel data at a rate of 667Mbps. The subsequent 24:8 serializer, shared by the PAM-4 mode, serializes the 24-bit parallel data at a rate of 667Mbps into 8-bit parallel data at a rate of 2Gbps. Finally, the 8:4 serializer serializes the 8-bit parallel data at a rate of 2Gbps into 4-bit parallel data at a rate of 4Gbps. The NRZ encoder encodes the input 4-bit parallel data at a rate of 4Gbps into a 16-bit 4Gbps driver control signal according to the rules in Table 2.

[0031] Table 2

[0032] If operating in PAM-3 mode, the 48:24 serializer shared with PAM-4 / NRZ mode serializes 48-bit 500Mbps parallel data into 24-bit 1Gbps parallel data. The subsequent 24:6 serializer serializes the 24-bit 1Gbps parallel data into 6-bit 4Gbps parallel data. The PAM-3 encoder encodes the 6-bit 4Gbps parallel data into 16-bit 4Gbps parallel driver control signals according to the rules in Table 3.

[0033] Table 3

[0034] As shown in Table 3, the input 6-bit data is divided into the first 3 bits and the last 3 bits. Each 3 bits is labeled A, B, and C from the least significant bit to the most significant bit. According to the 3-bit-2UI encoding rule, each 3 bits represents the full-speed data of the adjacent 2UI. Therefore, 6 bits correspond to the full-speed data of the adjacent 4UI.

[0035] The multi-mode DBI module statistically analyzes the data of the same UI output by each data path encoder. There are four multi-mode DBI modules to statistically analyze the data generated by the eight multi-mode encoders. DBI encoding is performed only on PAM-3 and PAM-4 signals, and not on NRZ signals, thus achieving selective DBI encoding. The module specifically includes a majority voter (MV) and a multi-mode DBI encoder. The majority voter counts the total number of 10 and 01 levels and the total number of H and L levels in PAM-4 and PAM-3 modes, respectively, based on the encoder data. If the count exceeds half of the number of data paths, the DBI_FLAG signal is output as 1 to the multi-mode DBI encoder to indicate that the data needs to be DBI encoded; otherwise, 0 is output to indicate that no encoding is required.

[0036] like Figure 6 As shown, the majority voting unit includes eight parallel decision circuits and a statistical circuit. The decision circuits, based on the data output from the eight data encoders, output 0 to the statistical circuit if the input data is 10 or 01 in PAM-4 mode, and 1 otherwise. In PAM-3 mode, if the input data is H or L, the decision circuit outputs 0 to the statistical circuit, and 1 otherwise. The statistical circuits, based on the eight indication messages output from the decision circuits, count the number of 0s. If the number exceeds half the number of data paths, the statistical circuit outputs DBI_FLAG as 1 to the multi-mode DBI encoder, indicating that DBI encoding is required; otherwise, it outputs DBI_FLAG as 0, indicating that DBI encoding is not required.

[0037] like Figure 7 As shown, the multi-mode DBI encoder includes a mode control word generator and a DBI mode selector. The mode control word generator generates a corresponding digital code based on the system's current operating mode control word and the DBI_FLAG signal. The DBI mode selector, in response to the four input driver control signals, outputs either the raw data or the DBI-encoded data to the subsequent circuitry, depending on the current operating mode and whether DBI encoding is required.

[0038] The eight decision circuits in the multi-mode voter receive the PU_MSB, PU_LSB, and PD_MSB signals of the same UI generated by eight encoders. When operating in PAM-4 mode, the PU_MSB and PU_LSB signals of each channel are XORed, which means that when a channel sends 10 or 01 data in this UI, it is judged as 0 and output to the subsequent statistical circuit. When operating in PAM-3 mode, the PU_MSB and PD_MSB signals of each channel are XORed, which means that when a channel sends H or L data in this UI, it is judged as 0 and output to the subsequent statistical circuit. The subsequent statistical circuit analyzes the eight decision results output from the preceding stage. If the number of zeros is greater than five, it indicates that the total number of 10 and 01 signals in the current UI of the eight PAM-4 signals is greater than five, or the total number of H and L signals in the current UI of the eight PAM-3 signals is greater than five. According to the DBI flip rule, the DBI_FLAG signal is output as 1 to the DBI encoder, indicating that DBI encoding of the input signal is required. If the number of zeros is less than or equal to four, it indicates that the total number of 10 and 01 signals in the same UI of PAM-4 is less than half, or the total number of H and L signals in the same UI of PAM-3 is less than half. In this case, DBI_FLAG is 0, indicating that DBI encoding of the input data is not required. The multi-mode DBI encoder determines the input signal based on the transmitter's current operating mode and the DBI_FLAG signal. The FLAG indicator signal selects the encoding of the control signals PU_MSB, PU_LSB, PD_MSB, and PD_LSB for each input channel of the same UI. The input data can be categorized into four cases: no encoding required when operating in NRZ mode; no encoding required when operating in PAM-3 or PAM-4 mode without triggering the DBI mechanism; encoding required when operating in PAM-3 mode with the DBI mechanism triggered; and encoding required when operating in PAM-4 mode with the DBI mechanism triggered. Therefore, by encoding the mode selection control word Mode_Sel<1:0> and the DBI flag bit DBI_FLAG and its inverted signal DBI_FLAG_b, a 2-bit DBI mode selection bit DBI_Sel<1:0> is generated, selecting one of the four output cases. As for the DBI encoding rules, according to... Figure 3 The current magnitude under different signaling levels can be determined according to the following rules: For PAM-4 mode, if the number of 10 and 01 levels with higher signaling current exceeds half of the number of channels, then 10 is converted to 11, 01 is converted to 00, and the original 11 and 00 are converted to 10 and 01 respectively, so that 11 and 00 with lower signaling current account for more than half of the total channel data, thereby reducing driver power consumption; For PAM-3 encoding, since the signaling current of H and L is higher than that of M, if the total number of H and L exceeds half of the number of channels, then H and L are converted to M, and M is converted to L.

[0039] like Figure 7As shown, when the data is in NRZ mode, the DBI_Sel<1:0> control word is 00, and all 4 control signals are output as is. When the data is in PAM-3 or PAM-4 mode but the DBI mechanism is not triggered, the DBI_Sel<1:0> control word is 01, and the input control data is also output as is. When the data is in PAM-3 mode and the DBI mechanism is triggered, DBI_Sel<1:0> is 10, and PU_MSB and PU_LSB are output with a 0 level, indicating that the conversion from H and L to M or M has not occurred. PU_LSB and PD_LSB are output with an XOR of PU_MSB and PD_MSB, indicating that M is converted to L. When the data is in PAM-4 mode and the DBI mechanism is triggered, PU_MSB and PD_MSB are output as is, and PU_LSB and PD_LSB are output after inversion, indicating the conversion between 11 and 10, and between 01 and 00.

[0040] The four-channel multi-mode DBI module outputs DBI-encoded PU_MSB, PU_LSB, PD_MSB, and PD_LSB control signals. Each control signal is 8 bits, representing the same UI from eight data channels. These data are returned to their original paths according to the original eight channels. Each channel consists of four consecutive UIs of DBI-encoded PU_MSB_DBI, PU_LSB_DBI, PD_MSB_DBI, and PD_LSB_DBI control signals. The 4-bit PU_MSB_DBI, PU_LSB_DBI, PD_MSB_DBI, and PD_LSB_DBI signals from each channel are processed by a retiming module to obtain edge-aligned 4×4-bit data. Then, a phase-shifting module is used to interleave the output control signals, ensuring a 90° phase difference between the same control signals from two adjacent UIs. A high-speed 4:1 serializer serializes the 4-bit signals interleaved in the same time to obtain 1-bit 16Gbps control signals PU_MSB_DBI, PU_LSB_DBI, PD_MSB_DBI, and PD_LSB_DBI. These four control signals are then simultaneously output to the main driver and CC-FFE driver of the data path, and superimposed at the output before being output to the channel.

[0041] The buffer in the clock path receives two externally input 8GHz differential clocks with impedance matching and amplifies them into full-swing differential clocks. The quadrature phase clock generator divides the two differential 8GHz clocks into four quadrature 4GHz clocks. The quadrature error correction and duty cycle correction modules correct the phase difference between the two sets of differential clocks to 90° and the duty cycle of each clock to 50%. The multimode divider first divides the 4GHz clock by 2 to 2GHz, providing output to an 8:4 serializer in NRZ mode or a 24:6 serializer in PAM-3 mode with a 12:6 serialization. Furthermore, the 4GHz clock before division and the 2GHz clock after division are selected by mode: in PAM-4 mode, the 4GHz clock is output to a 24:8 serializer; in NRZ mode, the 2GHz clock is output to a 24:8 serializer. The 2GHz clock is further divided by 2 to obtain a 1GHz clock, which is output to the 24:6 serializer in PAM-3 mode for 24:12 serialization. The 2GHz clock is further divided by 3 / 4 / 6 for 48:24 serialization in different modes. In PAM-4 mode, the 2GHz clock is divided by 3 to obtain a 667MHz clock for 48:24 serialization; in PAM-3 mode, the 2GHz clock is divided by 4 to obtain a 500MHz clock for 48:24 serialization; and in NRZ mode, the 2GHz clock is divided by 6 to obtain a 333MHz clock for 48:24 serialization. The clock generated by this selector, in addition to being used for 48:24 serialization, is also used by the PRBS31 generator to generate 48-bit parallel NRZ data at 333Mbps / 500Mbps / 667Mbps in NRZ / PAM-3 / PAM-4 modes.

[0042] like Figure 2 As shown, the clock DBI module adjusts the swing amplitude based on whether the data path is DBI encoded. Specifically, when a full-rate clock with a 50% duty cycle needs to be sent to the receiving end, the drive control signals PU_MSB_CLK_DBI and PD_LSB_CLK_DBI must be two full-rate, in-phase clocks with a 50% duty cycle. PD_MSB_CLK_DBI and PU_LSB_CLK_DBI then form another pair of in-phase clocks with a 50% duty cycle, but with a 180° phase difference from the first pair. When the output clock amplitude is modulated larger, PU_LSB_CLK_DBI and PD_LSB_CLK_DBI need to be toggled; therefore, the clock DBI encoder only encodes the PU_LSB_CLK and PD_LSB_CLK control signals.

[0043] like Figure 8As shown, the DBI encoders for PU_MSB_CLK and PD_MSB_CLK simply XOR the input signal with a 0 level, thus not changing the output logic value. However, the DBI encoders for PU_LSB_CLK and PD_LSB_CLK, which may require inversion, XOR the DBI_FLAG of each UI generated by the data path with the corresponding UI's input signal. If the data undergoes DBI encoding, the PU_LSB_CLK and PD_LSB_CLK of the clock path are inverted. Since PU_MSB_CLK_DBI and PD_LSB_CLK_DBI are in-phase clock signals with a 50% duty cycle when unencoded, the input signals of the DBI encoders for PU_MSB_CLK and PD_LSB_CLK before 4:1 serialization and the DBI encoder are sequential four-phase quadrature clocks at a rate of 4GHz. PU_LSB_CLK and PD_MSB_CLK are 50% duty cycle clock signals that are inverted from the previous clock group. Therefore, the input signals of the PU_LSB_CLK and PD_MSB_CLK clock DBI encoders are four-phase clocks that are inverted from the input clocks of the PU_MSB_CLK and PD_LSB_CLK DBI encoders, respectively. The high-speed 4:1 clock serializer serializes the continuous 4UI parallel 4GHz PU_MSB_CLK_DBI, PU_LSB_CLK_DBI, PD_MSB_CLK_DBI, and PD_LSB_CLK_DBI clocks into 1-bit 16GHz PU_MSB_CLK_DBI, PU_LSB_CLK_DBI, PD_MSB_CLK_DBI, and PD_LSB_CLK_DBI clocks, as shown below. Figure 9 As shown in (a), the full-rate signal of PU_MSB_CLK_DBI or PD_LSB_CLK_DBI can be generated by swapping the positions of the 90° quarter-rate clock and the 270° quarter-rate clock during high-speed serialization. Clock-embedded DBI, when DBI is enabled, XORs the DBI flag bit with the corresponding quadrature clock within the corresponding unit interval, toggling PU_LSB_CLK_DBI and PD_LSB_CLK_DBI, as shown below. Figure 9 As shown in (b), the full-speed data obtained from serialization is output to the main driver and the clock CC-FFE driver, and the summation at the output node is transmitted to the remote end through the channel.

[0044] Through specific experiments, the multi-mode single-ended transmitter based on power-optimal reception and data bus switching of this invention was realized using 40nm CMOS technology, with a core area of ​​0.447mm². 2 ,like Figure 10 As shown in (a), at an 8 GHz Nyquist bandwidth, the single-ended channel attenuation is 5.57 dB, as... Figure 10 As shown in (b). Under PRBS31 data, the transmitter's back-eye diagram is as follows: Figure 11 As shown.

[0045] like Figure 11 As shown in (a), the 16Gbps NRZ signal has an eye height of 231.57mV and an eye width of 54.74ps; Figure 11 (b)(c) reveals that after applying DBI, the eye height of the upper and lower eyes of the 24Gbps PAM-3 signal increases by approximately 20mV, and the eye width increases by approximately 3-4ps, verifying the improvement in signal integrity brought about by DBI. Furthermore, after applying DBI, the H and L level traces of the PAM-3 eye become thinner, while the M level trace becomes thicker, demonstrating that DBI increases the distribution probability of the M level and decreases the distribution probability of H and L, thereby helping to reduce the power consumption of the driver. Figure 11 (d)(e) revealed that the 32Gbps PAM-4 signal increased the eye height and eye width by about 17mV and 6ps, respectively, and the 11 and 00 levels were thicker, while the 10 and 01 levels were relatively thinner, verifying the effect of DBI on PAM-4. Figure 11 (f) and (g) respectively show the change of the feedforward clock from level 2 to level 4 before and after applying DBI in PAM-3 mode; Figure 11 (h)(i) indicates that in PAM-4 mode, the feedforward clock also changes from a 2-level to a 4-level before and after applying DBI, verifying the correct function of DBI in the clock path. Regarding power consumption, such as... Figure 12 As shown, the transmitter's eight data paths and two clock paths achieve energy efficiencies of 0.89 / 0.76 / 0.69 pJ / bit respectively after applying the clock embedded DBI technology in NRZ / PAM-3 / PAM-4 mode. Figure 12 (b)(c) The embedded DBI display clock optimizes the overall power consumption of the PAM-3 driver by 17.89%; Figure 12 (d)(e) The embedded DBI for displaying the clock optimizes the overall power consumption of the PAM-4 driver by 18.34%.

[0046] Compared to existing technologies, the 0.5VDDQ termination at the receiver reduces the power consumption of the driver in PAM-4 mode by 12.5% ​​compared to VSS and VDDQ. Clock-embedded DBI reduces the power consumption of the PAM-4 driver by 18.34%, which is better than the 16.3% power reduction of the PAM-4 DBI single-ended transmitter proposed by Seongcheol Kim et al. of Korea University and the 12.2% power reduction of the 50Gbps PAM-4 single-ended transmitter published by Yunseong Jo et al. of Hanyang University at ISSCC 2025. Furthermore, the transmitter's energy efficiency in PAM-4 mode is improved to 0.69 pJ / bit, surpassing the 1.04 pJ / bit efficiency of the 50 Gbps PAM-4 single-ended transmitter by Yunseong Jo et al. from Hanyang University, South Korea, and the 0.77 pJ / bit efficiency of the 40 Gbps single-ended hybrid DAC-based transmitter presented by Sanghyuk Seo et al. from Seoul National University at the 2024 ISCAS conference. Moreover, the clock-embedded DBI reduces the transmitter's energy efficiency in PAM-3 mode to 0.76 pJ / bit, surpassing the 0.86 pJ / bit efficiency of the PAM-3 transmitter in TCAS-I presented by Chanheum Han et al. from Kwangwoon University, South Korea, at the 2025 conference, and the 1.13 pJ / bit efficiency achieved by the NRZ / PAM-3 dual-mode transmitter combined with pDBI technology proposed by them in the 2025 JSSC journal. The clock-embedded DBI design significantly improves the transmitter's output bandwidth, enabling the multi-mode transmitter to operate at data rates of 16 / 24 / 32Gbps / pin in DBI applications, which is superior to the 14G / 25.2Gbps / pin rate of the dual-mode transmitter proposed by Chanheum Han et al. from Kwangwoon University, South Korea.

[0047] In summary, for the multi-mode architecture of this invention, the curve showing the sum of the expected signaling currents for the three modes as a function of the receiver termination is as follows: Figure 4 As shown in (b), the minimum value is also obtained at 0.5VDDQ. While the M level of PAM-3 mode has a minimum value when generated in the form of no short-circuit current, the present invention eliminates the additional required DBI flag bit pin and the flag bit inside the single data path and improves the pin efficiency of the transmitter to 100%, which is 6.25% and 12.5% ​​higher than the 1-bit and 2-bit DBI flag bit pin schemes, respectively. The effective data rate of a single pin is also increased to a maximum of 200%, which is 12.5% ​​higher than the pDBI technology of PAM-3, maximizing the output bandwidth of the transmitter.

[0048] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. An NRZ / PAM-3 / PAM-4 multimode transmitter, characterized in that, include: Eight identical data paths and two identical differential feedforward clock paths, wherein: the differential feedforward clock path generates two differential clock signals based on the half-rate differential clock and outputs them to the receiving end; the data path performs serialization, equalization, and DBI encoding processing on multiple pseudo-random binary sequences (PRBS) based on the mode control word and clock signal output by the differential feedforward clock path, and outputs the DBI-encoded data to the receiving end; Each data path includes: a pseudo-random binary sequence (PRBS) generator, a multimode serializer, an encoder, a multimode DBI module, a retiming and phase shifter, a high-speed serializer, a main driver with a single-ended power isolation low-voltage swing termination logic (PI-LVSTL) structure, and a capacitively coupled feedforward equalizer (CC-FFE). Each differential feedforward clock path includes: a clock buffer, a quadrature phase clock generator, a quadrature error correction and duty cycle correction module, a multimode divider, a clock DBI module, a clock high-speed serializer, a clock master driver, and a clock CC-FFE.

2. The NRZ / PAM-3 / PAM-4 multimode transmitter according to claim 1, characterized in that, The PRBS generator generates 48 data streams per channel, which are output to the multi-mode serializer of each channel. The multi-mode serializer operates in one of PAM-4 / PAM-3 / NRZ modes according to the mode control word output from the differential feedforward clock path, serializing the 48 parallel data streams to obtain 1 / 4 rate data before outputting it to the encoder. The encoder encodes the 1 / 4 rate data into a driver control signal according to the corresponding operating mode and outputs it to the multi-mode DBI module. The multi-mode DBI module aggregates all data from the eight data channels, performs selective DBI encoding, and outputs it to the reprocessor. The timing and phase shifter, after parallel data alignment and timing the data into four time-interleaved channels, outputs to the high-speed serializer; the high-speed serializer serializes the four time-interleaved 1 / 4 rate data into full rate data and outputs them to the main driver and CC-FFE respectively; the main driver uses the control data for the pull-up and pull-down branches to generate PAM-4 / PAM-3 / NRZ data corresponding to the mode, while the CC-FFE, based on capacitive coupling, generates short pulses only at the data edges and superimposes them with the data output by the main driver to accelerate edge switching, and the superimposed data is sent to the receiver through the channel.

3. The NRZ / PAM-3 / PAM-4 multimode transmitter according to claim 2, characterized in that, The selective DBI encoding refers to: collecting all data from eight data channels and statistically analyzing the data of the same UI. If the number of zeros exceeds half, the UI is encoded using PAM-4 / PAM-3 mode DBI encoding, but NRZ data is not processed and is passed directly.

4. The NRZ / PAM-3 / PAM-4 multimode transmitter according to claim 1, characterized in that, The clock buffer amplifies the externally input half-rate differential clock to full swing and outputs it to the quadrature phase clock generator. The quadrature phase clock generator divides the differential half-rate clock into four mutually orthogonal 1 / 4 rate clocks and outputs them to the quadrature error correction and duty cycle correction module to correct the phase difference and duty cycle between the four phase data and output them to the multi-mode divider, the clock DBI module, the clock high-speed serializer, and the retiming and phase shifter of the data path, respectively. The multi-mode divider divides the 1 / 4 rate clock and selects the corresponding rate clock signal to output to the multi-mode serializer and PRBS generator in the data path according to different operating modes. The clock DBI module modulates the clock amplitude according to the DBI flag generated by the multi-mode DBI module and serializes it into a full-rate clock driver control signal by the high-speed clock serializer, which is then output to the main clock driver and CC-FFE driver respectively. The main clock driver generates a corresponding differential clock signal at the output terminal according to the clock driver control signal. The CC-FFE generates a short pulse at the edge through the coupling capacitor and superimposes the output signal with the clock signal generated by the main driver before sending it to the receiving end through the channel.

5. The NRZ / PAM-3 / PAM-4 multimode transmitter according to claim 1, characterized in that, The selective DBI encoding refers to the following: the multi-mode DBI module counts the data of the same UI output by each data path encoder. There are four multi-mode DBI modules to count the data generated by eight multi-mode encoders. DBI encoding is performed only on PAM-3 and PAM-4 signals, and not on NRZ signals, thus achieving selective DBI encoding. This module specifically includes: a majority voter (MV) and a multi-mode DBI encoder. The majority voter counts the total number of 10 and 01 levels and the total number of H and L levels in PAM-4 and PAM-3 modes, respectively, based on the encoder data. If the count exceeds half of the number of data paths, the DBI_FLAG signal is output as 1 to the multi-mode DBI encoder to indicate that the data needs to be DBI encoded; otherwise, 0 is output to indicate that no encoding is required.

6. The NRZ / PAM-3 / PAM-4 multimode transmitter according to claim 5, characterized in that, The majority voter includes eight parallel decision circuits and statistical circuits. The decision circuits, based on the data output from the eight data encoders, output 0 to the statistical circuit if the input is 10 or 01 in PAM-4 mode, and 1 otherwise. In PAM-3 mode, if the input is H or L, the decision circuit outputs 0 to the statistical circuit, and 1 otherwise. The statistical circuits, based on the eight indication messages output from the decision circuits, count the number of 0s. If the number exceeds half the number of data paths, the statistical circuit outputs DBI_FLAG as 1 to the multi-mode DBI encoder, indicating that DBI encoding is required; otherwise, it outputs DBI_FLAG as 0, indicating that DBI encoding is not required.

7. The NRZ / PAM-3 / PAM-4 multimode transmitter according to claim 5, characterized in that, The multi-mode DBI encoder includes a mode control word generator and a DBI mode selector, wherein: the mode control word generator generates corresponding digital codes based on the current operating mode control word and the DBI_FLAG signal; the DBI mode selector, in response to the four input driver control signals, outputs the original data or the DBI-encoded data to the subsequent circuit according to the current operating mode and whether DBI encoding is required.

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