An embedded security subsystem and method for high-speed encryption and decryption

Abstract

The application discloses a high-speed encryption and decryption embedded security subsystem and method. The system comprises an SPI interface, a DMA module, an arithmetic core array, a CPU and a system bus; the SPI interface is additionally provided with a transmission ready TR and a receiving ready RR special handshake signal line; the DMA module is divided into a sending DMA and a receiving DMA; the arithmetic core array comprises at least three parallel arranged arithmetic cores. The sending DMA responds to the TR signal to move data into an idle arithmetic core and starts operation; the receiving DMA moves the result to the SPI interface after the operation of the arithmetic core is completed and triggers the RR signal. Through the double DMA cooperation and the multi-arithmetic core pipeline scheduling, the SPI interface realizes the full-duplex parallel transmission of the command issuing and the response uploading, the CPU is only responsible for the initialization and does not participate in the real-time data processing, so that the interface bandwidth utilization and the encryption and decryption throughput are greatly improved, and the system is suitable for high-bandwidth real-time security application scenarios.

Description

Technical Field

[0001] This invention relates to an embedded security subsystem for high-speed encryption and decryption, and also to a method for implementing high-speed encryption and decryption using the subsystem, belonging to the field of data processing technology. Background Technology

[0002] With the rapid development of high-bandwidth applications such as 5G / 6G communication, 8K ultra-high-definition video, and intelligent connected vehicles, data transmission rates are growing exponentially, placing unprecedented demands on the real-time performance and processing efficiency of information security. In key areas such as national defense, finance, and public safety, the real-time and secure interaction of massive amounts of data has become a rigid requirement. Against this backdrop, hardware-implemented cryptographic algorithm IP cores (referred to as computing cores) have become core components for ensuring data security due to their high performance and high security.

[0003] However, the performance of current embedded security modules faces significant bottlenecks. Firstly, at the physical interface level, although the SPI interface has the potential for full-duplex communication, in practical security applications, it is limited by the "command-response" type of blocking communication protocol, meaning its effective data transmission is actually in a half-duplex state. For example... Figure 1 As shown, in the traditional SPI transmission method, when MOSI sends a command, MISO needs to send back invalid data, and when MISO uploads a response, MOSI also needs to send back invalid data, which leads to a significant reduction in interface bandwidth utilization and becomes a key factor restricting system throughput.

[0004] Secondly, at the internal data processing level of the chip, traditional technical solutions heavily rely on the CPU for data transfer and scheduling. For example... Figure 2 As shown, data needs to be moved from the interface to a single computing core by the CPU, and after the calculation is completed, the CPU moves the result back. During this process, the CPU needs to continuously query or wait for interrupts. This not only consumes valuable CPU computing resources, but also introduces a large amount of serial waiting time in the data processing chain, making it difficult to meet the requirements of high concurrency and low latency for large data volumes and streaming encryption / decryption. In summary, existing technologies face the dual challenges of low interface utilization and high internal data processing latency in high-bandwidth application scenarios. This makes it difficult for the encryption and decryption performance of embedded security modules to keep pace with the ever-increasing data throughput demands, thus creating a system performance bottleneck. Therefore, there is an urgent need for a new system architecture and methodology to simultaneously overcome the limitations of both interface and internal processing efficiency, achieving truly high-speed encryption and decryption capabilities. Summary of the Invention

[0005] The primary technical problem to be solved by this invention is to provide a high-speed encryption and decryption embedded security subsystem.

[0006] Another technical problem to be solved by the present invention is to provide a high-speed encryption and decryption method.

[0007] To achieve the above-mentioned technical objectives, the present invention adopts the following technical solution: According to a first aspect of the present invention, a high-speed encryption / decryption embedded security subsystem is provided, comprising an SPI interface, a DMA module, a computing core array, a CPU, and a system bus; wherein, The SPI interface includes a TR signal line for notifying transmission readiness and an RR signal line for notifying reception readiness; the DMA module includes a transmit DMA and a receive DMA; the computing core array includes multiple computing cores configured in parallel; the DMA module, the computing core array, the CPU, and the Slave terminal are all connected to the system bus; The transmit DMA is used in response to the first state of the TR signal line to move the current data frame from the SPI interface to an idle computing core in the computing core array and start the computing core operation; the receive DMA is used in response to the second state of the completion of any computing core operation to move the processing result of the computing core to the SPI interface and control the RR signal line to notify that the data is ready.

[0008] Preferably, the transmitting DMA is configured to: while the receiving DMA is transferring the processing result from the first computing core, transfer subsequent data frames to a second computing core different from the first computing core, thereby enabling the multiple computing cores to work in a pipeline-like collaborative manner.

[0009] Preferably, the computing core array includes a first computing core, a second computing core, and a third computing core, and the transmit DMA is configured to cyclically schedule the loading of data frames in the order of the first computing core, the second computing core, and the third computing core.

[0010] Preferably, the transmitting DMA allocates the data frame with sequence number n to the ((n-1) mod 3+1)th computing core.

[0011] Preferably, the computational kernel is used to implement any one of the SM4, AES, SM1 or SM7 symmetric cryptographic algorithms.

[0012] Preferably, the Master end of the SPI interface is deployed on a host computer, and the Slave end is deployed on a security on-chip system.

[0013] According to a second aspect of the present invention, a high-speed encryption / decryption method is provided, comprising the following steps: Configure the DMA module and SPI interface, and complete the initialization; The Master end of the SPI interface sends the k-th frame of command data, and the Slave end of the SPI interface sends back invalid data. Once the command data transmission for the kth frame is complete, the Master terminal of the SPI interface sends a notification via the TR signal line. Send the DMA response to the notification, move the k-th frame data to the i-th computing core in the computing core array and start the operation; at the same time, the Master end of the SPI interface continues to send the (k+1)-th frame command data; When the i-th core completes its operation, the receiving DMA retrieves its result and notifies that the response is ready via the RR signal line. The Slave end of the SPI interface responds to the notification and starts uploading the k-th frame response data; at the same time, it sends a DMA to move the (k+1)-th frame data to the j-th computing core in the computing core array, where j≠i, and starts the operation; and the Master end of the SPI interface continues to send subsequent command data. Once a stable state is reached, command issuance, kernel computation, and response uploading form a parallel pipeline.

[0014] Preferably, the computing core array includes a first computing core, a second computing core, and a third computing core, and the transmit DMA cyclically selects the target computing core for data loading in the order of the first, second, and third computing cores.

[0015] Ideally, the data frame with sequence number n is assigned to the ((n-1) mod 3+1)th computational core for processing.

[0016] Compared with existing technologies, this invention introduces a dedicated TR / RR handshake signal line and a dual DMA collaborative mechanism to transform the traditional SPI interface from a "command-response" half-duplex blocking communication to application-layer full-duplex transmission, significantly improving the effective utilization of interface bandwidth. Simultaneously, by employing an array of at least three parallel computing cores, coupled with a DMA cyclic scheduling strategy, a deep pipeline is formed for data transfer, core computation, and result feedback, enabling parallel processing of multiple frames of data and completely eliminating the serial waiting overhead of the CPU in data transfer and scheduling. This system architecture effectively solves the dual bottlenecks of low interface utilization and high internal processing latency in traditional embedded security modules, enabling continuous, high-speed data encryption and decryption throughput in high-bandwidth application scenarios, significantly improving overall system performance and real-time performance. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of "command-response" data transmission in the existing SPI technology; Figure 2 This is a schematic diagram illustrating how a computing kernel processes encrypted and decrypted data in existing technologies. Figure 3 This is a schematic diagram of the structure of a high-speed encryption and decryption embedded security subsystem in the first embodiment of the present invention; Figure 4This is a schematic diagram of the workflow of the improved SPI full-duplex communication mechanism in the second embodiment of the present invention. Figure 5 This is a flowchart of a high-speed encryption / decryption method in the second embodiment of the present invention; Figure 6 This is a schematic diagram of the workflow of the three-core collaborative mechanism in the second embodiment of the present invention. Detailed Implementation

[0018] The technical content of the present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0019] First Embodiment like Figure 3 As shown, the first embodiment of the present invention provides a high-speed encryption and decryption embedded security subsystem. This subsystem mainly includes an SPI interface, a DMA module, a computing core array, a CPU, and a system bus connecting all the above modules.

[0020] In this subsystem, the Master side of the SPI interface is deployed on the host computer (master control chip), while the Slave side is deployed on the secure system-on-a-chip (secure SoC) as the slave device. Compared with the standard SPI interface, this embodiment of the invention adds two dedicated handshake signal lines in addition to the original four signal lines—Master Transmitter-Slave Receiver (MOSI), Master Receiver-Slave Transmitter (MISO), Clock (CLK), and Chip Select (CS): the Transmit Ready signal line TR and the Receive Ready signal line RR. This improvement is a key foundation for realizing subsequent high-speed full-duplex communication.

[0021] All core functional modules, including the DMA module, computing core array, CPU, and SPI Slave interface logic, are interconnected via a system bus. In one embodiment of the invention, this subsystem bus can be an AHB (Advanced High-performance Bus). The AHB bus is a member of the ARM AMBA protocol family, featuring high bandwidth and low latency, making it ideal for connecting high-performance components such as processors, DMA, and hardware acceleration modules.

[0022] It should be noted that the CPU's role in this subsystem has been simplified and optimized. Its main responsibility is limited to configuring necessary parameters for the DMA module and computing core array during the initialization phase after system power-on. Once initialization is complete, the CPU will no longer intervene in any real-time data transfer or computing core scheduling tasks in the subsequent actual data encryption and decryption process, thereby freeing up valuable processing resources.

[0023] The core of data transfer is handled by the DMA module. This module is further divided into two functionally independent sub-modules: Transmit DMA (TxDMA) and Receive DMA (RxDMA). TxDMA is mainly responsible for responding to the status of the TR signal line, transferring the data to be encrypted or decrypted (DataIN) from the SPI interface to the designated computing core in the computing core array, and triggering (enabling) the computing core to start operation. RxDMA is responsible for continuously monitoring the operation completion status of each computing core in the computing core array (for example, by detecting the "Done" signal output by the computing core). Once a computing core has completed its operation, RxDMA immediately removes its generated result data (DataOUT) from that computing core and transports it back to the transmit buffer of the SPI interface. At the same time, it notifies the host computer that the response data is ready to be read by setting the RR signal line.

[0024] The compute core array is key to the parallel processing capability of this subsystem. It consists of at least three identical compute cores connected in parallel to the system bus. Each compute core is an independent computing unit capable of executing one of the symmetric cryptographic algorithms such as SM4, AES, SM1, or SM7. The use of at least three compute cores is based on considerations of avoiding bus access conflicts and achieving smooth pipelined processing: while one compute core is being read by RxDMA, another can be performing computations, and the third can simultaneously be written with new data to be processed by TxDMA.

[0025] like Figure 4 As shown, one of the core improvements of this invention lies in introducing two dedicated handshake signal lines, TR (Transmit Ready) and RR (Receive Ready), and linking them with the transmit DMA (TxDMA) and receive DMA (RxDMA) respectively, thereby breaking the blocking mode of the traditional SPI communication "command-response". This design enables the SPI interface to achieve full-duplex transmission of effective application layer data on top of full-duplex physical layer. Specifically, the sending of command data and the uploading of response data can overlap in time, avoiding idle periods caused by waiting for the other party's response, and fundamentally solving the efficiency bottleneck of application layer data transmission being only half-duplex in traditional technical solutions.

[0026] Based on the above architecture, the workflow of this subsystem for processing large data streams can operate efficiently. After data is transmitted to the secure SoC via the SPI interface, when the TxDMA detects a valid TR signal, it sequentially and cyclically moves the data frame to different computing cores in the computing core array (e.g., sequentially using computing core 1, computing core 2, and computing core 3) according to a preset cyclic scheduling strategy, and starts the operation of the corresponding computing core. Each computing core independently and in parallel completes its assigned encryption and decryption tasks. When any computing core finishes its operation, the RxDMA detects its completion status, then moves the processing result of that computing core to the output side of the SPI interface and sets the RR signal line to notify the host computer to read the frame result data. Through the handshake coordination of TR and RR signals, and the cyclic and cross-scheduling of multiple computing cores by TxDMA and RxDMA, the command issuance and response upload of the SPI interface can achieve true application-layer full-duplex transmission (see Figure 4 The multiple computing cores also form an efficient pipeline operation, which significantly improves the overall encryption and decryption throughput.

[0027] Second Embodiment like Figure 5 As shown, the second embodiment of the present invention elaborates on a high-speed encryption / decryption method based on the aforementioned subsystem. This method begins with system startup and initialization and includes at least the following steps: S1: Execution from the Bootloader to the on-chip system, the CPU configures the DMA module and initializes the SPI interface.

[0028] In this step, after the system completes power-on boot, the CPU first configures the DMA module, clarifying the responsibilities and operating parameters of TxDMA and RxDMA. This includes setting the source address (SPI interface receive buffer), destination address (core array buffer), and triggering conditions for TxDMA (such as a valid TR signal); simultaneously, it sets the source address (core's operation result buffer), destination address (SPI interface transmit buffer), and triggering conditions (such as the operation completion signal sent by the core). Subsequently, the CPU initializes the SPI interface. Besides configuring standard communication rates, clock polarity, and phase parameters, the key step is defining the pin functions and initial levels of the newly added TR and RR signal lines, thus laying the foundation for full-duplex communication based on hardware handshake.

[0029] Specifically, the CPU accesses the DMA module's internal configuration registers via the system bus to set the following parameters: Configure transmit DMA (TxDMA): Source address: Set to the starting address of the SPI interface receive buffer (SPI_RX_BUF).

[0030] Destination address: Set to the circular base address of the input buffer of the core array, and associate it with the core index offset.

[0031] Transfer mode: Set to single or incremental burst transfer mode from peripheral to memory.

[0032] Triggering condition: Enable hardware triggering and bind it to the active level (such as rising edge) of the TR signal line.

[0033] Transmission length: Set according to the command data frame length specified in the security protocol.

[0034] Configure Receive DMA (RxDMA): Source address: Set to the address of the cache area (CORE_n_RESULT_BUF) of each computing core, and associate it with the completion status of the computing core.

[0035] Destination address: Set to the starting address of the SPI interface transmit buffer (SPI_TX_BUF).

[0036] Transfer mode: Set to single transfer mode from memory to peripheral.

[0037] Triggering conditions: Enable hardware triggering and bind it to the operation completion signal (such as CORE_DONE) output by each computing core.

[0038] Notification mechanism: Configure RxDMA to automatically set the RR signal line after each transmission is completed.

[0039] Configure the bus and arbitration: Configure the master device priority of TxDMA and RxDMA on the system bus (such as AHB) to avoid access conflicts.

[0040] Configure the compute core array cache as a non-cacheable and strongly-ordered storage area to ensure consistency between DMA and compute core access data.

[0041] The above configuration process is completed once during the system initialization phase, after which the CPU no longer intervenes in the real-time data stream.

[0042] S2: The SPI Master sends the first frame of command data under the MOSI line, while the SPI Slave sends back invalid data.

[0043] After initialization, the host computer (SPI Master) assembles frames according to application requirements and begins sending the first frame of command data through the MOSI line. To maintain the full-duplex timing of the SPI interface physical layer, the secure SoC (SPISlave) acting as the slave device will synchronously send back preset invalid data (such as all zeros or specific padding codes) on the MISO line.

[0044] S3: After the first frame of command data transmission is completed, the SPI Master notifies the SPI Slave and TxDMA via the TR line.

[0045] Once the last bit of the first frame of command data has been sent, the SPI Master sends a clear hardware handshake signal by setting the TR signal line to an active level (e.g., pulling it from low to high). This signal is simultaneously captured by the SPISlave and TxDMA, indicating that the entire frame of command data has been delivered to the interface buffer and is ready for subsequent processing.

[0046] S4: TxDMA uses a three-core collaborative mechanism to move the first frame command data from the SPI interface to the core for command processing.

[0047] Upon detecting a valid TR signal, TxDMA immediately initiates a data transfer operation. It transfers the first frame of command data buffered in the SPI interface to the currently scheduled target compute core (e.g., compute core 1) in the compute core array according to the three-core collaborative mechanism (its detailed sub-steps are S01-S09), sets the enable signal of that compute core, and starts its encryption / decryption operation.

[0048] S5: While executing step S4, the SPI Master sends the second frame of command data on the MOSI line, and the SPI Slave sends back invalid data.

[0049] This is a key point demonstrating full-duplex and pipelined parallelism. While the TxDMA is handling and processing the first frame of data, the SPI Master does not need to wait; instead, it immediately begins sending the second frame of command data via the MOSI line. At this time, since the response to the first frame has not yet been generated, the SPI Slave continues to send invalid data back on the MISO line.

[0050] S6: After the first frame of command data is processed, RxDMA moves the first frame of response data to the SPI port for uploading through the three-core collaborative mechanism, and notifies the SPI Slave and SPI Master through the RR line.

[0051] Once the target computing core (core 1) in the computing core array completes its computation on the first frame of data, it generates a computation completion status signal. RxDMA continuously monitors this status, and upon detecting the signal, it immediately starts, retrieving the processed first frame of response data from the core's internal buffer and writing it to the SPI interface's transmit buffer. Subsequently, RxDMA sends a "response data ready" notification to the SPI Slave and SPI Master by setting the RR signal line to an active level.

[0052] S7: While executing step S6, the SPI Slave stops sending back invalid data and starts uploading the first frame of response data.

[0053] This is another key aspect demonstrating full-duplex operation. After detecting a valid RR signal, the SPI Slave immediately switches the data source on the MISO line: it stops outputting invalid data and instead reads the first frame of response data from the SPI interface's transmit buffer, serializes it, and sends it to the SPI Master.

[0054] S8: On the MOSI line, the SPI Master sequentially sends the next nth frame of command data; on the MISO line, the SPISlave sequentially uploads the next nth frame of response data.

[0055] At this point, the system has entered a stable full-duplex pipeline state. The SPI Master continuously sends command data for frames 3, 4...n; simultaneously, the SPI Slave uploads response data for frames 2, 3...n. The command and response streams run in complete parallel on the SPI interface, achieving continuous high-throughput data transmission.

[0056] The specific scheduling and operation process of the three-core collaborative mechanism mentioned in steps S4 and S6 above is as follows: Figure 6 As shown, and defined in detail through the following sub-steps (S01~S09), the core of which is to put the three compute cores into pipeline operation: S01: TxDMA moves the first block of data to compute core 1 and starts the operation.

[0057] S02: Computation kernel 1 performs calculations and then notifies RxDMA after the processing is complete.

[0058] S03: RxDMA moves the processing result of computation core 1 to the SPI interface.

[0059] S04: While executing step S02, TxDMA moves the second block of data to computing core 2 and starts the operation.

[0060] S05: Computation kernel 2 performs calculations and then notifies RxDMA after the processing is complete.

[0061] S06: RxDMA moves the processing results of compute core 2 to the SPI interface.

[0062] S07: While executing step S05, TxDMA moves the third block of data to computing core 3 and starts the operation.

[0063] S08: Computation core 3 performs calculations and then notifies RxDMA after completion.

[0064] S09: RxDMA moves the processing results of computation core 3 to the SPI interface.

[0065] Subsequently, for subsequent data blocks, the system will repeat the sequence of steps S01 to S09. The mapping relationship between the data block number n and the core index i is determined by the formula i = ((n-1) mod 3) + 1, thereby ensuring that the three cores are cyclically and evenly scheduled to form an efficient pipeline.

[0066] The mapping relationship between data block number n and kernel index i is shown in the table below: This invention addresses the need for high-speed encryption and decryption of large datasets by creatively employing a multi-core array collaborative mechanism supported by Transmit DMA (TxDMA) and Receive DMA (RxDMA). Specifically, the core array consists of at least three identical cores, all mounted on a system bus (such as the AHB bus). The essence of their collaborative operation lies in forming a processing pipeline: while the first core (core 1) is performing computation, the second core (core 2) can receive new data, and the third core (core 3) may be idle or ready to proceed. This avoids the blocking phenomenon of "single core operation-waiting-transfer" in traditional solutions, achieving overlap between computation and data I / O.

[0067] It is important to emphasize that the number of compute cores in this collaborative mechanism should not be less than three. If there are only two compute cores, a situation may arise where the receiving DMA (RxDMA) is fetching results from one compute core while the sending DMA (TxDMA) needs to fetch new data into the same compute core, leading to read / write conflicts on the internal cache resources of that compute core, causing bus contention and memory access errors. On the other hand, the number of compute cores should not be excessive. In resource-constrained embedded subsystem designs, infinitely increasing the number of compute cores will drastically increase chip area and power consumption, and will also increase the complexity of the DMA module polling or managing the status of numerous compute cores, which is detrimental to the balance between cost and reliability. Therefore, using three compute cores is a preferred and effective design point between avoiding conflicts and controlling resource overhead.

[0068] Specifically, in step S5, the system begins to demonstrate its full-duplex and parallel processing potential. Specifically, at the same time that TxDMA initiates the data transfer operation for the first frame of command data, the SPI Master does not enter an idle waiting state. Instead, it immediately utilizes the full-duplex physical characteristics of the SPI interface to initiate the transmission of the second frame of command data on the MOSI line. At this time, the system bus, through its internal arbitration mechanism, rationally allocates bandwidth between the TxDMA data transfer request and the SPI Slave interface data reception request, ensuring that the two operate in parallel. The clock signal (CLK) continuously provides a synchronization clock, the chip select signal (CS) remains valid, and the TR signal line maintains its set state from step S3, all of which ensures the smooth transmission of the second frame of data. Simultaneously, since the processing of the first frame of data is not yet complete, the SPI Slave continues to send back invalid data in the same format as before on the MISO line to maintain link timing. This step clearly demonstrates that the SPI Master's data transmission, the TxDMA data transfer, and the data processing of core 1 are executed in parallel.

[0069] In step S6, after computation core 1 completes the operation on the first frame of command data (e.g., completes SM4 encryption), it generates an operation completion signal (e.g., Done). RxDMA, which continuously monitors the status of each computation core, captures this signal and initiates the response data transfer process. It accesses the internal buffer of computation core 1 via the system bus, reads the first frame of response data, and transfers it to the transmit buffer of the SPI interface. This data transfer operation is independent of the CPU. Subsequently, RxDMA sends a hardware notification to the SPI Slave and SPI Master by setting the RR signal line to an active level (e.g., pull it high), indicating that the first frame of response data is ready. The SPI Slave and SPI Master then adjust their respective internal states to prepare for receiving and sending the response data.

[0070] Step S7 is the key action that enables full-duplex communication at the application layer. After detecting a valid RR signal, the SPI Slave immediately stops outputting invalid data on the MISO line and instead reads the first frame of response data from its transmit buffer, then begins serializing and sending it to the SPI Master. It is worth emphasizing that at this time, the transmission of the second frame of command data is still proceeding synchronously on the MOSI line. This means that the MOSI and MISO lines are simultaneously transmitting valid service data, thus truly realizing full-duplex communication of the SPI interface at the application layer and completely eliminating the efficiency constraints of half-duplex transmission in the traditional "command-response" mode.

[0071] Step S8 describes the continuous pipelined operation mode after the system enters a stable state. Thereafter, the SPI Master continuously sends command data for frames 3, 4…n, while the SPI Slave continuously uploads response data corresponding to frames 2, 3…n. For each subsequent frame of command data, TxDMA allocates it to an idle core in the core array according to the cyclic scheduling rules defined by the three-core collaborative mechanism. The specific mapping relationship is determined by the formula i = ((n-1) mod 3) + 1, where n is the data frame number and i is the core index (1, 2, 3). For example, the 4th frame of data (n=4) will be allocated to core 1 for processing again according to the mapping (4-1) mod 3 + 1 = 1, at which point core 1 has completed processing the 1st frame of data and output the result. This cycle repeats continuously, with the three cores always in pipelined operations at different stages such as "computation," "data input," and "data output." Meanwhile, the AHB system bus efficiently arbitrates and schedules all data access requests between TxDMA, RxDMA, the three compute cores, and the SPI interface, ensuring the smooth operation of the entire pipeline. This deep parallel and pipelined design enables the system to process continuous data streams with stable high throughput, meeting the real-time and secure processing requirements of high-bandwidth application scenarios.

[0072] It should be noted that the core concept of this invention lies in improving throughput through the pipelined collaborative work of multiple computing cores, and is not limited to the three computing cores mentioned above. Figure 3 In the architecture shown, the number of compute core arrays can be expanded to N (N is a positive integer and not less than 3).

[0073] When the number of compute cores is N, the core technology lies in constructing a pipeline with a depth of N. The transmit DMA distributes consecutive data frames sequentially to N different compute cores according to a preset scheduling strategy (such as round-robin scheduling). The key is to ensure that while the receive DMA is retrieving data from a compute core, the transmit DMA does not simultaneously load new data into that core, thus avoiding read / write conflicts on the same memory port. This requires a pipeline depth (i.e., the number of compute cores N) of at least 3. When N = 3, as... Figure 5 The pipeline shown has reached the minimum sufficient condition; when N>3, the system will have a larger buffer depth, which can theoretically tolerate longer core operation fluctuations, but will consume more chip area and power consumption.

[0074] To illustrate this fully, the following are brief examples of scheduling with different numbers of compute cores: 1. Four-core implementation example: The core array includes four cores: the first, second, third, and fourth. The DMA scheduling order is cyclical: first core → second core → third core → fourth core → first core… The mapping relationship between the data frame sequence number n and the core index i is: i = ((n-1) mod 4) + 1. Under this configuration, when any core is processing the current data, the previous core is outputting a result, and the next core is receiving new data, resulting in a smoother pipeline.

[0075] 2. Five-core implementation example: The compute core array includes cores one through five. The scheduling order for DMA transmission is cyclical: core one → core two → core three → core four → core five → core one… The mapping relationship is: i = ((n-1) mod 5) + 1. Deeper pipelines can further hide data transfer latency, but they require higher packet continuity and increase resource overhead.

[0076] 3. General N-core implementation example: The core array consists of N (N≥3) cores. The transmit DMA uses round-robin scheduling, and the mapping relationship between the data frame sequence number n and the core index i is: i = ((n-1) mod N) + 1. This general rule ensures uniform data distribution, avoids core idleness, and achieves stable pipeline throughput.

[0077] It should be noted that more computing cores are not necessarily better. In resource-constrained embedded systems, a balance must be struck between performance, area, and power consumption. Through extensive simulation verification, the inventors have found that three computing cores are the optimal choice to balance high performance and low overhead, achieving a speedup close to the theoretical limit with minimal hardware cost while avoiding bus conflicts. Therefore, limiting the number of computing cores to at least three, and employing three computing cores in the preferred embodiment, is the essence of this invention.

[0078] It should be noted that the above embodiments are merely illustrative examples. The technical solutions of each embodiment can be combined, and all are within the protection scope of this invention.

[0079] The high-speed encryption / decryption embedded security subsystem and method provided by this invention have been described in detail above. Any obvious modifications made by those skilled in the art without departing from the essence of this invention will constitute an infringement of the patent rights of this invention and will incur corresponding legal liability.

Claims

1. An embedded security subsystem for high-speed encryption and decryption, characterized in that... This includes an SPI interface, DMA module, computing core array, CPU, and system bus; among which, The SPI interface includes a TR signal line for notifying transmission readiness and an RR signal line for notifying reception readiness; the DMA module includes a transmit DMA and a receive DMA; the computing core array includes multiple computing cores configured in parallel; the DMA module, the computing core array, the CPU, and the Slave terminal are all connected to the system bus; The transmit DMA is used in response to the first state of the TR signal line to move the current data frame from the SPI interface to an idle computing core in the computing core array and start the computing core operation; the receive DMA is used in response to the second state of the completion of any computing core operation to move the processing result of the computing core to the SPI interface and control the RR signal line to notify that the data is ready.

2. The embedded security subsystem as described in claim 1, characterized in that: The transmit DMA is configured to: while the receive DMA is transferring the processing result from the first computing core, transfer subsequent data frames to a second computing core different from the first computing core, thereby enabling the multiple computing cores to work in a pipeline-like collaborative manner.

3. The embedded security subsystem as described in claim 2, characterized in that: The computing core array includes a first computing core, a second computing core, and a third computing core, and the transmit DMA is configured to cyclically schedule the loading of data frames in the order of the first computing core, the second computing core, and the third computing core.

4. The embedded security subsystem as described in claim 3, characterized in that: The transmit DMA allocates the data frame with sequence number n to the ((n-1) mod 3+1)th compute core.

5. The embedded security subsystem as described in claim 1, characterized in that: The kernel is used to implement any one of the SM4, AES, SM1 or SM7 symmetric cryptographic algorithms.

6. The embedded security subsystem as described in claim 1, characterized in that: The Master side of the SPI interface is deployed on the host computer, and the Slave side is deployed on the security chip system.

7. A high-speed encryption / decryption method, implemented based on the embedded security subsystem described in any one of claims 1 to 6, characterized in that... Includes the following steps: Configure the DMA module and SPI interface, and complete the initialization; The Master end of the SPI interface sends the k-th frame of command data, and the Slave end of the SPI interface sends back invalid data. Once the command data transmission for the kth frame is complete, the Master terminal of the SPI interface sends a notification via the TR signal line. Send the DMA response to the notification, move the k-th frame data to the i-th computing core in the computing core array and start the operation; at the same time, the Master end of the SPI interface continues to send the (k+1)-th frame command data; When the i-th core completes its operation, the receiving DMA retrieves its result and notifies that the response is ready via the RR signal line. The Slave end of the SPI interface responds to the notification and starts uploading the k-th frame response data; at the same time, it sends a DMA to move the (k+1)-th frame data to the j-th computing core in the computing core array, where j≠i, and starts the operation; and the Master end of the SPI interface continues to send subsequent command data. Once a stable state is reached, command issuance, kernel computation, and response uploading form a parallel pipeline.

8. The high-speed encryption / decryption method as described in claim 7, characterized in that: The computing core array includes a first computing core, a second computing core, and a third computing core. The transmit DMA cyclically selects the target computing core to which data is to be loaded in the order of the first, second, and third computing cores.

9. The high-speed encryption / decryption method as described in claim 8, characterized in that: The data frame with sequence number n is assigned to the ((n-1) mod 3+1)th computational core for processing.

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