Matrix multiplication conversion method, apparatus, medium, device and product
By using a method based on systolic array convolution, the matrix data is segmented and then computed in a systolic array, which solves the problem of low matrix multiplication efficiency and achieves efficient matrix computation and cache optimization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CCORE TECH CO LTD
- Filing Date
- 2026-04-10
- Publication Date
- 2026-05-29
Smart Images
Figure CN122112418A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of neural network processor technology, and in particular to a matrix multiplication transformation method, apparatus, storage medium, electronic device and computer program product based on systolic array convolution calculation. Background Technology
[0002] In existing technologies, matrix multiplication is achieved by traversing each data point in the row matrix and each parameter in the column matrix, then multiplying the corresponding elements according to the positional relationship between the row and column matrices, accumulating the results, and then assigning the results to the corresponding positions in the resulting matrix, ultimately obtaining the product matrix.
[0003] However, existing technologies have low computational efficiency for matrix multiplication and consume significant bandwidth. Summary of the Invention
[0004] To address the problem of low efficiency in matrix multiplication in existing technologies, this application mainly provides a matrix multiplication transformation method, apparatus, storage medium, electronic device, and computer program product based on pulsating array convolution calculation.
[0005] To achieve the above objectives, the first technical solution adopted in this application is: a matrix multiplication transformation method based on systolic array convolution calculation, which includes: dividing the matrix row data of the first matrix according to the number of input channels of the input feature map of the systolic array, and inputting the divided matrix row data of the same row into the systolic array in the form of row data; dividing the matrix column data of the second matrix according to the number of input channels and the number of output channels of the weights of the systolic array, and inputting the divided matrix column data of the same row into the systolic array in the form of column data; and using the systolic array, calculating the product of the first matrix and the second matrix.
[0006] Optionally, if the number of columns in the first matrix is greater than the number of columns in the systolic array, the first matrix column data of the first matrix is segmented according to the number of columns in the systolic array; if the number of rows in the second matrix is greater than the number of rows in the systolic array, the second matrix row data of the second matrix is segmented according to the number of rows in the systolic array; and the segmented first matrix column data or the segmented second matrix row data are respectively input into the systolic array in a predetermined order.
[0007] Optionally, when the number of columns in the first matrix is less than the number of columns in the systolic array, the number of columns in the first matrix is padded to be equal to the number of columns in the systolic array using a predetermined number; and when the number of rows in the second matrix is less than the number of rows in the systolic array, the number of rows in the second matrix is padded to be equal to the number of rows in the systolic array using a predetermined number.
[0008] Optionally, the intermediate results of matrix multiplication between the first matrix column data and the second matrix row data after segmentation are stored in a pulsating array until all intermediate results of matrix multiplication between the first matrix column data and the second matrix row data after segmentation are calculated. The product of the first matrix and the second matrix is obtained by adding the multiple intermediate results of matrix multiplication.
[0009] Optionally, the intermediate results of matrix multiplication between the first matrix column data and the second matrix row data after segmentation are stored in memory; after calculating all the intermediate results of matrix multiplication between the first matrix column data and the second matrix row data after segmentation, the intermediate results of matrix multiplication are retrieved from memory, and the product of the first matrix and the second matrix is calculated using the addition operator.
[0010] Optionally, the product of the first matrix and the second matrix is obtained by adding the intermediate results of multiple matrix multiplications, including: splitting the column data of the first matrix to obtain the first split matrix, the second split matrix, the third split matrix, ... the Nth split matrix, and storing the above split matrices in the storage unit in order, where N is an integer greater than 0; when obtaining the column data of the split first matrix to calculate the intermediate results of matrix multiplication, the split matrix is read by skipping the address.
[0011] The second technical solution adopted in this application is: a matrix multiplication conversion device based on systolic array convolution calculation, which includes: an input feature map conversion module, used to segment the matrix row data of the first matrix according to the number of input channels of the input feature map of the systolic array, and input the segmented matrix row data of the same row into the systolic array in the form of row data; a weight conversion module, used to segment the matrix column data of the second matrix according to the number of input channels and output channels of the weights of the systolic array, and input the segmented matrix column data of the same row into the systolic array in the form of column data; and a calculation module, used to calculate the product of the first matrix and the second matrix using the systolic array.
[0012] The third technical solution adopted in this application is: a computer-readable storage medium storing a computer program / instruction, which is operated to execute the matrix multiplication transformation method based on systolic array convolution calculation in Solution 1.
[0013] The fourth technical solution adopted in this application is: a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the matrix multiplication transformation method based on systolic array convolution calculation in Solution 1.
[0014] The fifth technical solution adopted in this application is: a computer program product, including a computer program / instruction, which, when executed by a processor, implements the matrix multiplication transformation method based on systolic array convolution calculation as in Solution 1.
[0015] The beneficial effects that the technical solution of this application can achieve are: Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 This is a schematic diagram of a specific implementation of a matrix multiplication transformation method based on pulsating array convolution computation according to this application; Figure 2 This is a timing diagram of data input into the A array for computation in a matrix multiplication transformation method based on pulsating array convolution computation according to this application; Figure 3 This is a data layout diagram under multi-head attention based on a matrix multiplication transformation method for systolic array convolution computation proposed in this application; Figure 4 This is a schematic diagram of matrix segmentation for a matrix multiplication transformation method based on systolic array convolution computation according to this application; Figure 5 This is a schematic diagram of multipart matrix multiplication calculation for a matrix multiplication transformation method based on pulsating array convolution calculation according to this application; Figure 6 This is a schematic diagram of a specific embodiment of a matrix multiplication conversion device based on pulsating array convolution calculation according to this application.
[0018] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0019] The preferred embodiments of this application will now be described in detail with reference to the accompanying drawings, so that the advantages and features of this application can be more easily understood by those skilled in the art, thereby providing a clearer and more definite definition of the scope of protection of this application.
[0020] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.
[0021] The technical solution of this application and how it solves the above-mentioned technical problems will be described in detail below with specific embodiments. The specific embodiments described below can be combined with each other to form new embodiments. The same or similar ideas or processes described in one embodiment may not be repeated in other embodiments.
[0022] Figure 1 This paper illustrates one implementation of a matrix multiplication transformation method based on systolic array convolution computation according to this application.
[0023] Figure 1 The matrix multiplication transformation method based on systolic array convolution calculation shown includes: step S101, dividing the matrix row data of the first matrix according to the number of input channels of the input feature map of the systolic array, and inputting the divided matrix row data of the same row into the systolic array in the form of row data; step S102, dividing the matrix column data of the second matrix according to the number of input channels and output channels of the weights of the systolic array, and inputting the divided matrix column data of the same row into the systolic array in the form of column data; step S103, using the systolic array, calculating the product of the first matrix and the second matrix.
[0024] Specifically, convolution operations possess the characteristics of local connectivity and weight sharing. When matrix multiplication is implemented in convolutional form, local regions of the input data are repeatedly used for multiple output calculation points. Therefore, during the computation process of implementing matrix multiplication in convolutional form, matrix element data within the same matrix can be reused multiple times, which significantly reduces the access frequency to high-bandwidth memory such as DDR. Reducing the access frequency to high-bandwidth memory can alleviate the "memory wall" problem. Therefore, this application can improve the data reuse rate of matrix element data, thereby reducing memory access.
[0025] Regular computational pattern: Convolution operations feature a highly regular sliding window pattern, making data and computation flows predictable and regular. Therefore, convolution operations facilitate the design of fixed and efficient data paths such as systolic arrays and pulsed arrays. Furthermore, convolution operations easily implement deep pipelines, hiding data access latency. In FPGAs (Field-Programmable Gate Arrays) or ASICs (Application-Specific Integrated Circuits), convolution operations can be mapped to highly parallel multiply-accumulate arrays, completing multiple window computations per clock cycle. Therefore, convolution operations are more suitable for hardware parallelization and pipelined design. Consequently, when using convolution operations for matrix multiplication, data processing can be performed in parallel, thereby improving the computational efficiency of matrix calculations.
[0026] Most computations in modern deep learning are inherently convolutions or can be transformed into convolutions. Therefore, when hardware such as NPUs optimizes convolution computations, decomposing matrix multiplication into convolutions allows the same hardware unit to efficiently handle both deep learning and matrix multiplication computations without the need to design two separate computation engines. This approach simplifies the hardware architecture and instruction set.
[0027] Meanwhile, the data accessed by convolution is contiguous or nearly contiguous in memory, which facilitates cache prefetching and efficient use of cache blocks. Furthermore, the reuse of weights and input data makes them more likely to reside in the cache or on-chip buffer, reducing latency and power consumption when accessing off-chip DRAM. Therefore, this application's use of convolution for matrix multiplication can improve cache utilization and optimize data locality.
[0028] Furthermore, convolutional computation supports flexible computational granularity and sparsity, meaning it can be computed in blocks. Therefore, large matrix multiplications can be broken down into multiple small convolutional blocks for computation. This approach is suitable for distributed or hierarchical memory systems such as multi-level memristor tiles. Moreover, if the matrix exhibits structured sparsity, such as striped or block-based sparsity, corresponding sparse convolutional patterns can be designed to skip zero-value computations, further improving efficiency.
[0029] exist Figure 1 In the embodiment shown, the matrix multiplication transformation method based on systolic array convolution calculation includes step S101, which involves dividing the matrix row data of the first matrix according to the number of input channels of the input feature map of the systolic array, and inputting the divided matrix row data of the same row into the systolic array in the form of row data.
[0030] exist Figure 1 In the illustrated embodiment, the matrix multiplication transformation method based on pulsating array convolution calculation includes step S102. Based on the number of input and output channels of the pulsation array, the matrix column data of the second matrix is divided, and the divided matrix column data of the same row is input into the pulsation array in the form of column data. In one specific embodiment of this application, when the number of columns in the first matrix is greater than the number of columns in the systolic array, the first matrix column data of the first matrix is segmented according to the number of columns in the systolic array; when the number of rows in the second matrix is greater than the number of rows in the systolic array, the second matrix row data of the second matrix is segmented according to the number of rows in the systolic array; and the segmented first matrix column data or the segmented second matrix row data are respectively input into the systolic array in a predetermined order.
[0031] Specifically, matrix multiplication is essentially a form of vector multiplication and accumulation. As shown below, C = A × B is actually multiplying a matrix A with size M rows and N columns by a matrix with size N rows and K columns to obtain a matrix C with size M*K.
[0032]
[0033] A × B = C The examples above demonstrate that matrix multiplication has the characteristics of reusability and "sliding," therefore, as... Figure 2 As shown, matrix multiplication can be converted into a systolic array-based convolution computation that also has reusability and sliding characteristics, where the numbers represent the periodic order in which the matrix element data is fed into the systolic array (SA).
[0034] When performing matrix multiplication using a systolic array, the number of rows and columns of the matrix input into the systolic array is at most the same as the size of the SRAM (System Algorithm). The width of each row or column of data input into the systolic array is equal to the bit width of the systolic array's bus (SRAM). Therefore, if the length of a row or column of the matrix is greater than the bit width of the bus, the data for that row or column needs to be loaded into the SRAM multiple times, and the rows or columns already transferred to the SRAM are stored in the SRAM.
[0035] In one specific embodiment of this application, when the number of columns in the first matrix is less than the number of columns in the systolic array, the number of columns in the first matrix is padded to be equal to the number of columns in the systolic array using a predetermined number; and when the number of rows in the second matrix is less than the number of rows in the systolic array, the number of rows in the second matrix is padded to be equal to the number of rows in the systolic array using a predetermined number.
[0036] Specifically, if matrix A is a small matrix, meaning its number of columns is less than the number of columns in matrix SA, then the number of columns in matrix A needs to be padded with zeros to match the number of columns in the systolic array. However, there is no requirement for the number of rows in matrix A; that is, if the number of rows in matrix A is less than the number of rows in the systolic array, then matrix A does not need to be padded. Similarly, matrix B has a requirement for the number of rows but no requirement for the number of columns.
[0037] This specific embodiment transforms matrix calculations using matrix multiplication operators into calculations using convolution, eliminating the need for padding and rounding down, thus simplifying matrix multiplication calculations.
[0038] exist Figure 1 In the embodiment shown, the matrix multiplication transformation method based on systolic array convolution calculation includes step S103, which uses a systolic array to calculate the product of the first matrix and the second matrix.
[0039] Specifically, such as Figure 3 If matrix A and matrix B have the same input format, matrix B needs to be transposed once more before the multiplication operation compared to matrix A.
[0040] like Figure 3 As shown, the transpose of matrix A is arranged sequentially from head to head. That is, when transposing matrix A, the first row of data from head A1, the first row of data from head A2, and the first row of data from head A3 are arranged in sequence to generate a row of data, which is then input into the systolic array; then the second row of data from head A1, the second row of data from head A2, and the second row of data from head A3 are arranged in sequence to generate a row of data, which is then input into the systolic array, and so on, until the transpose of all data in matrix A is completed.
[0041] While transposing matrix A, matrix B is also transposed. Specifically, matrix B is transposed by arranging the first element of the first row, the first element of the second row, and the first element of the third row of A1 sequentially to generate a column of data, which is then input into the pulsation array. Next, the first elements of the fourth and fifth rows of A1 are arranged sequentially to generate another column of data, which is input into the pulsation array. This new column contains fewer data points than the previous column. This process is repeated until the transpose of matrix B is complete.
[0042] In particular, the transpose of matrix B can also be performed when inputting matrix B into the pulsating array.
[0043] Finally, the product of the first matrix and the second matrix is calculated using the computing units in the pulsating array.
[0044] In one specific embodiment of this application, the intermediate results of matrix multiplication between the segmented first matrix column data and the segmented second matrix row data are stored in a pulsating array until all intermediate results of matrix multiplication between the segmented first matrix column data and the segmented second matrix row data are calculated. The product of the first matrix and the second matrix is obtained by adding the multiple intermediate results of matrix multiplication.
[0045] In one specific embodiment of this application, the intermediate results of matrix multiplication between the segmented first matrix column data and the segmented second matrix row data are stored in memory; after calculating all the intermediate results of matrix multiplication between the segmented first matrix column data and the segmented second matrix row data, the intermediate results of matrix multiplication are retrieved from memory, and the product of the first matrix and the second matrix is calculated using the addition operator.
[0046] Specifically, such as Figure 4 When the columns of matrix A or the rows of matrix B are larger than the size of the systolic array, the matrix needs to be partitioned. In this case, matrix A is partitioned by columns, or matrix B is partitioned by rows, resulting in the corresponding first partition matrix, second partition matrix, third partition matrix, ..., Nth partition matrix. The partitioned matrices are then input into the systolic array for partial matrix multiplication. The results of these partial multiplications are stored in the systolic array and then input into the new partition matrix for further calculation until the final result is obtained. This means that intermediate calculation results do not need to be stored in external memory. Alternatively, after the calculation is complete, the intermediate calculation results can be output from the systolic array and stored in memory. After calculating the intermediate matrix multiplication results of all the partitioned first matrix column data and partitioned second matrix row data, the intermediate matrix multiplication results are retrieved from memory, and the product of the first and second matrices is calculated using the addition operator.
[0047] In one specific embodiment of this application, the product of a first matrix and a second matrix is obtained by adding multiple intermediate matrix multiplication results, including: splitting the column data of the first matrix to obtain a first split matrix, a second split matrix, a third split matrix, ..., an Nth split matrix, and storing the above split matrices in a storage unit in sequence, where N is an integer greater than 0; when calculating the intermediate matrix multiplication results by obtaining the column data of the split first matrix, the split matrix is read by skipping the address.
[0048] Specifically, such as Figure 5 As shown, the storage order of matrix A in the memory is A1, A4, A2, A5, A3 and A6; the storage order of matrix B is B1, B3, B5, B2, B4 and B6. At this time, if it is necessary to calculate the output in the order of C1, C2, C3 and C4, the data needs to be retrieved from the storage address of matrix A or matrix B.
[0049] In a scenario where intermediate matrix multiplication results of the first and second matrix columns after partitioning are stored in a systolic array until all intermediate results of matrix multiplication of the first and second matrix columns are calculated, and the product of the first and second matrices is obtained by summing multiple intermediate results, if discontinuous data extraction is required for matrix A, discontinuous data extraction is also required for matrix B. The resulting matrix C can then be stored contiguously in the systolic array. Specifically, first obtain A1 from matrix A, then B1 from matrix B; then obtain A2 from matrix A, then B3 from matrix B, and so on until the matrix calculation is complete.
[0050] In the scenario where intermediate matrix multiplication results of the first matrix column data and the second matrix row data after segmentation are stored in memory; and after calculating all intermediate matrix multiplication results of the first matrix column data and the second matrix row data, the intermediate matrix multiplication results are retrieved from memory, and the product of the first and second matrices is calculated using the addition operator, the following steps are taken: First, A1 of matrix A is retrieved from memory. Then, the data of matrix B is retrieved sequentially, and all calculation results related to A1 are calculated in a systolic array, i.e., A1B1 and A1B2 are calculated. The calculation results are then written back to memory such as DDR. Next, A2 of matrix A is retrieved sequentially, and all calculations related to A4 are calculated, i.e., A4B1 and A4B2 are obtained. A4B1 and A4B2 are then written back to memory. This process is repeated until all calculations are completed. Finally, the data is retrieved from memory and accumulated to obtain the corresponding data such as C1 and C2.
[0051] Figure 6 This paper illustrates a specific implementation of a matrix multiplication conversion device based on pulsating array convolution computation according to this application.
[0052] exist Figure 6 In the specific implementation shown, the matrix multiplication conversion device based on systolic array convolution calculation mainly includes: an input feature map conversion module 601, used to segment the matrix row data of the first matrix according to the number of input channels of the input feature map of the systolic array, and input the segmented matrix row data of the same row into the systolic array in the form of row data; a weight conversion module 602, used to segment the matrix column data of the second matrix according to the number of input channels and output channels of the weights of the systolic array, and input the segmented matrix column data of the same row into the systolic array in the form of column data; and a calculation module 603, used to calculate the product of the first matrix and the second matrix using the systolic array.
[0053] In one specific embodiment of this application, the weight data of matrix B is reshaped into convolutional kernels. When matrix B is used as weights, it is divided into multiple sub-matrices, i.e., convolutional kernels, and their arrangement order on the systolic array is determined. Simultaneously, the input data of matrix A is reshaped into multi-channel feature maps, and the order in which they are input into the array using a convolutional sliding window method is determined.
[0054] This application provides a reconfigurable systolic array hardware structure that can efficiently execute native matrix multiplication data streams and seamlessly switch to convolutional data streams. The PE (computation unit) of the systolic array supports two computation modes: the fixed weight or input flow mode of traditional systolic arrays; and convolution optimization modes such as input feature map sliding, partial path optimization, and accumulation path optimization. To adapt to the sliding window reading of convolution, this application also designs a dedicated data prefetch and buffer, supporting multi-row caching and windowed feeding of input data. This differs from the sequential block reading of standard matrix multiplication, enabling efficient execution of native matrix multiplication data streams. Furthermore, to ensure the switching between the two computation modes, this application also utilizes a low-overhead control signal or configuration register to dynamically switch the array's computation mode and data flow direction.
[0055] This application can schedule the same set of systolic array hardware according to the task type, with the systolic array performing computations according to the optimal pipeline timing for matrix multiplication or convolution. In convolution mode, dynamic data dependency management is used for data dynamic management, that is, the scheduler is used to handle data dependencies caused by overlapping sliding windows, and corresponding pipeline pauses or data forwarding mechanisms are arranged to ensure computational correctness while maximizing throughput.
[0056] The size of the matrix partitions is variable, and can be adjusted according to the number of computational units in the actual SA. In other words, the size of the matrix partitions is variable, and the size of the partitions needs to match the maximum number of computational units in the SA.
[0057] The matrix multiplication conversion device based on pulsating array convolution calculation provided in this application can be used to execute the matrix multiplication conversion method based on pulsating array convolution calculation described in any of the above embodiments. Its implementation principle and technical effect are similar, and will not be repeated here.
[0058] In one specific embodiment of this application, the functional modules of the matrix multiplication conversion device based on pulsating array convolution calculation can be directly in hardware, in software modules executed by a processor, or in a combination of both.
[0059] Software modules may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in this art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium.
[0060] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, but alternatively, it can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration. Alternatively, the storage medium can be integrated with the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in the user terminal. Alternatively, the processor and storage medium can reside as discrete components in the user terminal.
[0061] In another specific embodiment of this application, a computer-readable storage medium is provided, which stores a computer program / instructions that are operated to perform the matrix multiplication transformation method based on systolic array convolution computation described in the above embodiments.
[0062] In one specific embodiment of this application, a computer device includes a memory, a processor, and a computer program stored in the memory. The processor executes the computer program to implement the matrix multiplication transformation method based on systolic array convolution computation described in the above embodiments.
[0063] In one specific embodiment of this application, a computer program product includes a computer program / instruction that, when executed by a processor, implements the matrix multiplication transformation method based on systolic array convolution computation described in the above embodiments.
[0064] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.
[0065] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0066] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A matrix multiplication transformation method based on systolic array convolution computation, characterized in that, include: Based on the number of input channels of the input feature map of the pulsation array, the matrix row data of the first matrix is segmented, and the segmented matrix row data of the same row is input into the pulsation array in the form of row data; Based on the number of input and output channels of the pulsation array, the matrix column data of the second matrix is divided, and the matrix column data after being divided in the same row is input into the pulsation array in the form of column data. Using the pulsating array, the product of the first matrix and the second matrix is calculated.
2. The matrix multiplication transformation method based on systolic array convolution calculation according to claim 1, characterized in that, If the number of columns in the first matrix is greater than the number of columns in the pulsation array, the data in the first matrix column of the first matrix is divided according to the number of columns in the pulsation array. If the number of rows in the second matrix is greater than the number of rows in the pulsation array, the data in the second matrix rows of the second matrix are divided according to the number of rows in the pulsation array. as well as, The first matrix column data or the second matrix row data after being segmented are input into the pulsation array in a predetermined order.
3. The matrix multiplication transformation method based on systolic array convolution calculation according to claim 1, characterized in that, When the number of columns in the first matrix is less than the number of columns in the pulsation array, the number of columns in the first matrix is padded to be equal to the number of columns in the pulsation array using a predetermined number; and, When the number of rows in the second matrix is less than the number of rows in the systolic array, the number of rows in the second matrix is padded to be equal to the number of rows in the systolic array using the predetermined number.
4. The matrix multiplication transformation method based on systolic array convolution calculation according to claim 2, characterized in that, The intermediate results of matrix multiplication between the segmented column data of the first matrix and the segmented row data of the second matrix are stored in the pulsating array until all intermediate results of matrix multiplication between the segmented column data of the first matrix and the segmented row data of the second matrix are calculated. The product of the first matrix and the second matrix is obtained by adding the multiple intermediate results of matrix multiplication.
5. The matrix multiplication transformation method based on systolic array convolution calculation according to claim 2, characterized in that, The intermediate results of matrix multiplication between the column data of the first matrix after segmentation and the row data of the second matrix after segmentation are stored in memory; After calculating the intermediate matrix multiplication results of the first matrix column data and the second matrix row data after all the partitioning, the intermediate matrix multiplication results are retrieved from the memory, and the product of the first matrix and the second matrix is calculated using the addition operator.
6. The matrix multiplication transformation method based on systolic array convolution calculation according to claim 4, characterized in that, The step of adding together the intermediate results of multiple matrix multiplications to obtain the product of the first matrix and the second matrix includes: After splitting the column data of the first matrix, we obtain the first split matrix, the second split matrix, the third split matrix, ... the Nth split matrix, and store the above split matrices in the storage unit in order, where N is an integer greater than 0; When calculating the intermediate results of matrix multiplication by acquiring the first matrix column data after splitting, the jump address reads the split matrix.
7. A matrix multiplication conversion device based on pulsating array convolution calculation, characterized in that, include: The input feature map conversion module is used to divide the matrix row data of the first matrix according to the number of input channels of the input feature map of the pulsation array, and input the divided matrix row data of the same row into the pulsation array in the form of row data; The weight conversion module is used to divide the matrix column data of the second matrix according to the number of input channels and the number of output channels of the weight of the pulsation array, and input the divided matrix column data of the same row into the pulsation array in the form of column data; The calculation module is used to calculate the product of the first matrix and the second matrix using the pulsating array.
8. A computer-readable storage medium storing a computer program / instructions, characterized in that, The computer program / instructions are operated to perform the matrix multiplication transformation method based on systolic array convolution computation as described in any one of claims 1-6.
9. A computer device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the matrix multiplication transformation method based on systolic array convolution computation as described in any one of claims 1-6.
10. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instruction is executed by the processor, it implements the matrix multiplication transformation method based on systolic array convolution computation as described in any one of claims 1-6.