Pad pattern conversion method, device, equipment and medium

Abstract

Embodiments of the present application disclose a pad pattern conversion method and device, equipment and medium. A PCB file to be converted is parsed to obtain original pattern data; image recognition is performed on the solder mask layer original pattern data to obtain pattern elements of different element types; a corresponding pad pattern conversion strategy is selected based on the pad layer corresponding pattern element type to convert the pattern elements to obtain the solder mask layer pad pattern data; the circuit layer original pattern data is converted based on the solder mask layer pad pattern data to generate the circuit layer pad pattern data; and the steel mesh layer original pattern data and the drilling layer original pattern data are integrated to obtain standardized pad pattern data. Special recognition algorithms are designed for different types of pattern elements, and the solder mask layer conversion result is used as a benchmark to drive the interlayer linkage conversion of the circuit layer linkage conversion, to ensure that the two-layer pad data is consistent and conversion deviation is avoided. No manual intervention is required, and the recognition accuracy of complex patterns is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor chip soldering, and in particular to methods, apparatus, equipment and media for converting solder pad patterns. Background Technology

[0002] A printed circuit board (PCB) is the carrier for the electrical connections of electronic components. Circuit functions are achieved by etching conductive patterns onto an insulating substrate. Pads are the metal areas on a PCB used for soldering the leads of electronic components; they are crucial structures for the electrical connection and mechanical fixation between components and the PCB. In the PCB design and manufacturing process, pads, as the core structure for electronic component soldering and electrical connections, directly impact the manufacturing quality and production efficiency of PCB products due to their accurate identification and standardized conversion. ODB++ and Gerber are commonly used file formats in the PCB design field, containing multi-layered data such as solder mask layers, circuit layers, stencil layers, and drill layers. Pad conversion must be completed based on the graphic elements in these files.

[0003] However, current technologies for pad recognition and conversion mainly rely on manual processing or simple rule matching, which has many technical shortcomings. First, the recognition accuracy is low; it is difficult to accurately identify complex shapes such as single lines, multi-line enclosures, polygons, and nested loops. Second, the conversion efficiency is poor; a large number of graphic elements need to be processed manually, which is time-consuming and labor-intensive, and cannot meet the needs of large-scale production. Third, the conversion between solder mask and circuit layers can easily lead to inconsistent conversion results. Fourth, the ability to handle special graphics is weak; it has poor adaptability to special structures such as round-headed conductors, square-headed conductors, ring rectangles, and small-aperture lines. Fifth, there is a lack of intelligent optimization mechanisms; no optimization is performed for scenarios such as graphic coverage and parallel line combinations, resulting in redundant conversion operations. Therefore, there is an urgent need for a method for converting PCB graphics to pads with multi-strategy recognition capabilities and high efficiency and automation to solve the problems of inaccurate recognition, low efficiency, and poor adaptability in existing technologies. Summary of the Invention

[0004] This application provides a method, apparatus, device, and medium for converting pad patterns, which can solve the technical problems of inaccurate recognition, low efficiency, and poor adaptability in converting printed circuit board patterns to pad patterns.

[0005] In a first aspect, embodiments of this application provide a pad pattern conversion method, the pad pattern conversion method comprising: In response to the conversion command of the pad image, the PCB file of the graphic to be converted is obtained, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The PCB file containing the graphic to be converted is parsed to obtain the original graphic data of the solder mask layer, the circuit layer, the stencil layer, and the drill layer. Image recognition is performed on the original graphic data of the solder mask layer to obtain graphic elements of different element types; Based on the element type of the graphic element corresponding to the pad layer, the corresponding pad graphic conversion strategy is selected to convert the graphic element to obtain the pad graphic data of the solder mask layer. Based on the solder mask layer's pad pattern data, the original pattern data of the circuit layer is converted to generate the circuit layer's pad pattern data. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data.

[0006] In some embodiments, the element types include single-line elements, multi-line enclosing elements, combined aperture elements, nested spiral line elements, and small aperture line elements.

[0007] In some embodiments, the step of selecting a corresponding pad pattern conversion strategy to convert the graphic elements based on the element type of the graphic elements corresponding to the pad layer to obtain the pad pattern data of the solder mask layer includes: Based on the single-line element type of the pad layer, a single-line element type conversion strategy is selected to convert the identified single line segment into a single pad line segment and the identified single arc segment into a single pad arc segment. Based on the multi-line enclosure element type of the pad layer, a multi-line enclosure element type conversion strategy is selected to convert multiple line segments and multiple arc segments within the same network with electrical connection relationships into pad polygons. Based on the combined aperture element type of the pad layer, a combined aperture element type conversion strategy is selected. All elements of the pad layer are traversed to decompose the combined aperture into basic elements. Then, based on the basic elements, they are converted into corresponding pad basic elements and added. Based on the nested loop element type of the pad layer, a nested loop element type conversion strategy is selected to convert the nested loop element into the corresponding multi-layer nested loop pad structure. Based on the type of the small aperture line element in the pad layer, a small aperture line element type conversion strategy is selected, and the small aperture line elements are added to the conversion element list for unified conversion processing.

[0008] In some embodiments, the multi-line enclosure element type selection strategy based on the pad layer converts multiple line segments and multiple arc segments within the same network with electrical connections into pad polygons, including: Based on the multi-line enclosure element type selection strategy of the pad layer, multiple line segments and multiple arc segments with electrical connection relationships in the same network are extracted, and the extracted multiple line segments and multiple arc segments are grouped according to the aperture width to obtain different grouped bounding boxes. Calculate the size and position of each group of bounding boxes, and retain the bounding boxes whose size meets the preset size threshold; The contour search method is used to filter out the combination of elements that make up the closed contour from the preserved bounding boxes. The selected element combinations are merged into polygons by performing Boolean operations, and the polygons are then converted into pad polygons.

[0009] In some embodiments, the step of performing image recognition on the original graphic data of the solder mask layer to obtain graphic elements of different element types includes: Image recognition is performed on the original graphic data of the solder mask layer to extract elements from the solder mask layer network; The extracted elements are judged by their element type. If they contain only a single line segment or arc segment that is not connected by other elements, they are identified as single-line elements. If multiple line segments and arc segments are extracted from the same network, and a set of line segments sufficient to enclose a closed region is identified through bounding box filtering, contour search, and polygon filtering, then it is determined as a multi-line enclosing element. If a polygon satisfies any one of the following conditions: a concave-convex polygon without internal holes, a polygon connected to a trace, or a polygon connected to a borehole, then it is determined to be a polygon element. If the two ends of a conductor are connected by arcs, and the center of the arc is on the conductor's axis or its extension, and the radius of the arc is proportional to the width of the conductor, then it is determined to be a round-headed conductor element. If a multi-layered nested spiral line structure is identified, the bounding box relationship of each layer of lines is calculated, and it is determined whether there are nested rectangles or other regular graphic structures. If so, it is determined to be a nested spiral line element. Filter line segments with aperture sizes smaller than a preset threshold, and then search within the existing bounding box. If a set of line segments that satisfy the bounding box ratio is found, it is identified as a small aperture line element.

[0010] In some embodiments, the conversion of the original pattern data of the circuit layer based on the solder mask pattern data to generate the solder pad pattern data of the circuit layer includes: The position coordinates of the solder mask pad graphic data are mapped to the corresponding circuit layer. Based on the shape and size of the solder mask pad graphic data, the graphic elements of the circuit layer are linked and transformed to generate the solder mask pad graphic data of the circuit layer.

[0011] In some embodiments, the pad pattern data based on the solder mask layer and the pad pattern data of the circuit layer are integrated with the original pattern data of the stencil layer and the original pattern data of the drill layer to obtain standardized pad pattern data, including: Determine whether the original graphic data of the steel mesh layer and the original graphic data of the drilled layer are completely covered by the weld resist layer. If it is determined that there is an element that is completely covered by the solder mask, then delete the current element that is completely covered. Convex polygons that intersect the solder mask layer but whose center point is not within the range included by the solder mask layer's pad pattern data are converted into pad convex polygons. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data. Verify whether multiple line segments with the same aperture width are parallel and similar in shape. If they are parallel and similar in shape, treat multiple line segments with the same aperture width as a group of parallel lines and convert them in batches. Verify the consistency of network connectivity before and after the conversion to ensure that electrical connections are not affected.

[0012] Secondly, embodiments of this application also provide a pad pattern conversion device, the pad pattern conversion device comprising: The acquisition unit is used to acquire the PCB file of the graphic to be converted in response to the conversion instruction of the pad image, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The parsing unit is used to parse the PCB file of the graphic to be converted to obtain the original graphic data of the solder mask layer, the original graphic data of the circuit layer, the original graphic data of the stencil layer, and the original graphic data of the drill layer. An image recognition unit is used to perform image recognition on the original graphic data of the solder mask layer to obtain graphic elements of different element types; The first conversion unit is used to select the corresponding pad graphic conversion strategy to convert the graphic elements based on the element type of the graphic elements corresponding to the pad layer, so as to obtain the pad graphic data of the solder mask layer. The second conversion unit is used to convert the original pattern data of the circuit layer based on the solder mask pattern data to generate the solder mask pattern data of the circuit layer. The integration unit is used to integrate the original pattern data of the stencil layer and the original pattern data of the drill layer based on the solder mask pattern data and the solder pad pattern data of the circuit layer to obtain standardized solder pad pattern data.

[0013] Thirdly, embodiments of this application also provide a pad pattern conversion device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method.

[0014] Fourthly, embodiments of this application also provide a computer-readable medium storing a computer program, the computer program including program instructions that, when executed by a processor, can implement the above-described method.

[0015] This application provides a method, apparatus, device, and medium for pad pattern conversion. In response to a pad image conversion command, a PCB file containing the pattern to be converted is obtained. The PCB file includes multi-layer original design data for a solder mask layer, a circuit layer, a stencil layer, and a drill layer. The PCB file is parsed to obtain original pattern data for the solder mask layer, circuit layer, stencil layer, and drill layer. Image recognition is performed on the original pattern data for the solder mask layer to obtain graphic elements of different element types. Based on the element type of the graphic element corresponding to the pad layer, a corresponding pad pattern conversion strategy is selected to convert the graphic element, resulting in solder mask pad pattern data. The original pattern data for the circuit layer is converted based on the solder mask pad pattern data to generate circuit layer pad pattern data. Based on the solder mask pad pattern data and the circuit layer pad pattern data, the original pattern data for the stencil layer and the original pattern data for the drill layer are integrated to obtain standardized pad pattern data. In this application, a dedicated recognition algorithm is designed for different types of graphic elements, covering various structures. Inter-layer linkage conversion is driven by the solder mask conversion result as a benchmark, ensuring the consistency of pad data between the two layers and avoiding conversion deviations. The entire conversion process requires no manual intervention, significantly improving the recognition accuracy of complex graphics. It enables automated, high-precision conversion from PCB design files to standardized pad data, providing reliable assurance for subsequent soldering, assembly, and other processes. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic flowchart illustrating the pad pattern conversion method provided in this application embodiment; Figure 2 This is a schematic diagram of the single-line element type before conversion; Figure 3 This is a schematic diagram of the converted single-line element; Figure 4 This is a schematic diagram of the square-headed wire before conversion; Figure 5 This is a schematic diagram of the converted square-headed wire; Figure 6 A schematic block diagram of the pad pattern conversion device provided in the embodiments of this application; Figure 7 A schematic block diagram of the device provided in the embodiments of this application. Detailed Implementation

[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] It should be noted that any AI models, software tools, or components not belonging to this company appearing in the embodiments of this application are merely illustrative examples and do not represent actual use. The user personal information involved in the embodiments of this application is obtained by an entity authorized (with the knowledge and consent) or fully authorized by all parties through various legal and compliant means. The collection, storage, use, processing, transmission, provision, and disclosure of the information, data, and signals involved all comply with relevant laws and regulations and do not violate public order and good morals.

[0020] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0021] It should also be understood that the terminology used in this application specification is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this application specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0022] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0023] A printed circuit board (PCB) is the carrier for the electrical connections of electronic components. Circuit functions are achieved by etching conductive patterns onto an insulating substrate. Pads are the metal areas on a PCB used for soldering the leads of electronic components; they are crucial structures for the electrical connection and mechanical fixation between components and the PCB. In the PCB design and manufacturing process, pads, as the core structure for electronic component soldering and electrical connections, directly impact the manufacturing quality and production efficiency of PCB products due to their accurate identification and standardized conversion. ODB++ and Gerber are commonly used file formats in the PCB design field, containing multi-layered data such as solder mask layers, circuit layers, stencil layers, and drill layers. Pad conversion must be completed based on the graphic elements in these files.

[0024] However, current technologies for pad recognition and conversion mainly rely on manual processing or simple rule matching, which has many technical shortcomings. First, the recognition accuracy is low; it is difficult to accurately identify complex shapes such as single lines, multi-line enclosures, polygons, and nested loops. Second, the conversion efficiency is poor; a large number of graphic elements need to be processed manually, which is time-consuming and labor-intensive, and cannot meet the needs of large-scale production. Third, the conversion between solder mask and circuit layers can easily lead to inconsistent conversion results. Fourth, the ability to handle special graphics is weak; it has poor adaptability to special structures such as round-headed conductors, square-headed conductors, ring rectangles, and small-aperture lines. Fifth, there is a lack of intelligent optimization mechanisms; no optimization is performed for scenarios such as graphic coverage and parallel line combinations, resulting in redundant conversion operations. Therefore, there is an urgent need for a method for converting PCB graphics to pads with multi-strategy recognition capabilities and high efficiency and automation to solve the problems of inaccurate recognition, low efficiency, and poor adaptability in existing technologies.

[0025] This method is applicable to industrial scenarios such as PCB design file processing, CAM system data preprocessing, and PCB mass production. Figure 1 This is a flowchart illustrating the pad pattern conversion method provided in an embodiment of this application. Figure 1 As shown, the method includes the following steps S110-S160: S110. In response to the conversion instruction of the pad image, obtain the PCB file of the graphic to be converted, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. A PCB (Printed Circuit Board) is a computer-generated design file used to describe and manufacture printed circuit boards (PCBs). It's a collection of files submitted to PCB factories for actual production. The most common and standard type is the Gerber file.

[0026] The PCB file to be converted includes multi-layered original design data for solder mask, trace layers, stencil layers, and drill layers. The trace layers define electrical connections, i.e., the copper foil traces that form the conductors in the circuit schematic. Signal layers within the trace layers are used for transmitting ordinary signals; power layers provide stable power and ground references for components; the solder mask layer defines where solder mask ink is not needed, protecting traces from oxidation and preventing short circuits during soldering. The stencil layer is specifically designed for SMT (Surface Mount Technology) soldering. The stencil layer defines the location and shape of solder paste to be applied to the SMT pads. The drill layer provides data on the location, size, and type of all drill holes on the PCB.

[0027] S120. The PCB file of the graphic to be converted is parsed to obtain the original graphic data of the solder mask layer, the original graphic data of the circuit layer, the original graphic data of the stencil layer, and the original graphic data of the drill layer. Parse PCB design files to obtain the original data of the top solder mask layer, bottom solder mask layer, top circuit layer, bottom circuit layer, top stencil layer, bottom stencil layer, and drill layer, and standardize the data format.

[0028] The specific content of the original graphic data for each layer is as follows: The solder mask layer's original graphic data consists of a series of polygons, line segments, and other graphic elements, defining the areas on the solder mask where copper pads need to be exposed. The wiring layer's original graphic data constitutes the traces, fill areas, and pads for electrical connections. The stencil layer's original graphic data is usually consistent with the shape and position of the surface mount device's pads, such as window patterns, dimensions, and board surface data. The drill layer's original graphic data is a drill table, containing information such as the coordinates, diameter, whether it is copper-plated, and the mesh to which it belongs for each hole.

[0029] After parsing the PCB file containing the graphic to be converted, the data for each layer is usually stored in memory as an independent, machine-readable data structure, such as a list of vector graphics, or directly exported as a standard exchange format such as Gerber.

[0030] S130. Perform image recognition on the original graphic data of the solder resist layer to obtain graphic elements of different element types; Image recognition is performed on the original graphic data of the solder mask layer, such as a series of polygons, line segments and other graphic elements, to obtain graphic elements of different element types.

[0031] The step S130, which involves image recognition of the original graphic data of the solder mask layer to obtain graphic elements of different element types, includes steps S1301-S1307: S1301. Perform image recognition on the original graphic data of the solder resist layer and extract elements from the solder resist layer network. Image recognition is performed on the original graphic data of the solder mask layer to extract elements such as polygons and line segments from the solder mask layer network.

[0032] S1302. Determine the element type of the extracted elements. If the extracted elements contain only a single line segment or arc segment without any other connected elements, then identify them as single-line elements. A single-line element refers to a core graphic element. It is a straight line segment or arc segment with a fixed width. A single-line element is defined by the starting coordinates (X1, Y1) and the ending coordinates (X2, Y2), and includes the key attribute of line width w. In graphic data, a single-line element is usually described as: LINE (X1, Y1) (X2, Y2) WIDTH w.

[0033] By judging the element type and geometric relationship, the object is determined to be a line segment or an arc segment. The topological relationship is then judged; the object must be singular and unconnected to other elements. This process filters out independent graphic elements from a massive amount of graphics, identifying them as single-line elements that are not connected to any electrical or physical network. Further identification of independent lines provides precise target objects for subsequent advanced analysis, optimization, or correction, making it a fundamental and crucial step in intelligent PCB data processing.

[0034] In some embodiments, after determining that an element is a single line, its slope is calculated. For a line segment, the slope k = (Y2 - Y1) / (X2 - X1) is calculated; for an arc segment, the slope of the arc chord or the tangent slope at the start and end points can be calculated. After calculating the slope, optimization can be performed to identify all horizontal or vertical lines, facilitating path optimization by photoplotters or engravers. In the silkscreen layer, abnormal diagonal lines may represent incorrect placement, and diagonal lines at specific angles may be used for antennas or high-frequency matching lines.

[0035] S1303. If multiple line segments and arc segments are extracted from the same network, and a set of line segments sufficient to enclose a closed region is identified through bounding box filtering, contour search, and polygon filtering, then it is determined as a multi-line enclosing element. Here, a net refers to a collection of conductive graphics in a PCB file that have electrical connections. Graphics within the same net are electrically connected through wires, vias, etc.

[0036] For the set of all line segments or arcs in the same network, perform preliminary screening of bounding boxes: calculate the minimum bounding rectangle of each element, filter obviously irrelevant elements, reduce the search space, and construct a spatial index to output a set of candidate elements.

[0037] For multiple line segments and arc segments extracted from the same network, contour search based on graph theory is used to establish an endpoint adjacency list, construct an undirected graph, and use depth-first search to find closed loops. The validity of the loop is verified. If it is verified as a valid closed loop, the loop edge set is extracted and the contour is obtained. If it is verified as an invalid path, it is discarded.

[0038] For multiple line segments and arc segments extracted from the same network, perform polygon validity verification, check the connectivity of the edges, whether there are no self-intersections, and whether the directions are consistent. If the connectivity of the edges is continuous and closed, there are no self-intersections, and the directions are consistent, the verification is passed and the polygon set attributes are obtained, and the set is output; otherwise, the verification fails.

[0039] Multiple line segments and arc segments are extracted from the same network. By using bounding box filtering, contour search, and polygon filtering, a set of line segments that are sufficient to enclose a closed region is identified as a multi-line enclosing element.

[0040] S1304. If a polygon is defined as a polygonal element, it is defined as a polygonal element that satisfies any one of the following conditions: a concave-convex polygon without internal holes, a polygon connected to a wiring, or a polygon connected to a borehole. A non-hollow polygon refers to any simple polygon, which can be convex or concave, and has no internal holes. A polygon connected to a trace means that the polygon has an electrical connection to the trace on the PCB. A polygon connected to a drill hole means that the polygon has an electrical connection to the drill hole on the PCB.

[0041] If a polygon satisfies any one of the following conditions: a concave-convex polygon without internal holes, a polygon connected to a trace, or a polygon connected to a borehole, then it is determined to be a polygon element.

[0042] S1305. If the two ends of a conductor are connected by an arc, and the center of the arc is on the conductor axis or the extension line of the axis, and the radius of the arc is proportional to the width of the conductor, then it is determined to be a round-headed conductor element. To classify a round-ended wire element, all of the following conditions must be met simultaneously: First, determine the connection between the wire and the arc: each end of the wire must be connected to an arc. Second, determine the geometric position: the center of the arc must lie on the axis of the wire it connects to, or on an extension of that axis. Finally, consider the dimensional proportions: the radius of the arc and the width of the wire must satisfy a specific proportional relationship, such as equality or a multiple thereof; the specific proportion depends on the defined rules. When a graphic combination, including the wire and the arcs at both ends, simultaneously satisfies all three conditions, it can be identified as a round-ended wire element.

[0043] As an example, Figure 4 This is a schematic diagram of the square-headed wire before conversion. Figure 5 This is a schematic diagram of the converted square-headed wire.

[0044] S1306. If a multi-layered nested spiral line structure is identified, calculate the bounding box relationship of each layer of lines, and determine whether there are nested rectangles or other regular graphic structures. If so, it is determined to be a nested spiral line element. Identify multi-layered nested meander lines, calculate the relationship between the bounding boxes of each layer, and mark any regular graphic structures that are confirmed to be nested.

[0045] S1307. Filter line segments with aperture sizes smaller than a preset threshold, and then search within the existing bounding box. If a set of line segments that satisfy the bounding box ratio is found, it is determined to be a small aperture line element.

[0046] Filter line segments with aperture sizes smaller than a preset threshold, search within the existing bounding box, and mark the set of line segments that satisfy the bounding box ratio as small aperture line elements.

[0047] S140. Based on the element type of the graphic element corresponding to the pad layer, select the corresponding pad graphic conversion strategy to convert the graphic element to obtain the pad graphic data of the solder mask layer. The conversion of the solder mask layer is used as a benchmark to drive the coordinated conversion of the circuit layers, ensuring the consistency of the position, shape, and size of the pad data on both layers and avoiding conversion deviations. The entire conversion process requires no manual intervention. Combined with batch processing and parallel computing mechanisms, it significantly reduces processing time and meets the needs of large-scale production. Auxiliary mechanisms such as element coverage judgment and parallel line batch conversion reduce redundant operations, further improving conversion efficiency and result quality. It is compatible with ODB++ and Gerber file formats, supports comprehensive conversion of the top and bottom solder mask layers and circuit layers of PCBs, and is adaptable to various complex PCB design scenarios.

[0048] Different conversion strategies are employed for different element types to transform the graphic elements and obtain the solder mask pad graphic data. A multi-strategy approach is used for accurate identification, with dedicated recognition algorithms designed for different types of graphic elements, covering various structures such as single lines, multi-line enclosures, polygons, and special conductors, significantly improving the recognition accuracy of complex graphics. Element types include single-line elements, multi-line enclosure elements, combined aperture elements, nested loop line elements, and small aperture line elements.

[0049] S140, the step of selecting the corresponding pad graphic conversion strategy to convert the graphic elements based on the element type of the graphic elements corresponding to the pad layer to obtain the pad graphic data of the solder mask layer, includes S1401-S1405: S1401. Based on the single-line element type of the pad layer, select a single-line element type conversion strategy to convert the identified single line segment into a single pad line segment and convert the identified single arc segment into a single pad arc segment. like Figure 2The image shown is a schematic diagram of the single-line element type before conversion. Figure 3 This is a schematic diagram of the converted single-line element.

[0050] Single-line elements include single-line segments and single-line arc segments. Identified single-line segments are converted into single-pad segments, and identified single-arc segments are converted into single-pad arc segments.

[0051] S1402. Based on the multi-line enclosure element type of the pad layer, select a multi-line enclosure element type conversion strategy to convert multiple line segments and multiple arc segments in the same network with electrical connection relationship into pad polygons. Multiple line segments and multiple arc segments that are electrically connected within the same network are converted into pad polygons.

[0052] S1402, based on the multi-line enclosure element type selection strategy of the pad layer, converts multiple line segments and multiple arc segments within the same network with electrical connections into pad polygons, including steps A1-A4: A1. Based on the multi-line enclosure element type of the pad layer, select the multi-line enclosure element type conversion strategy, extract multiple line segments and multiple arc segments in the same network with electrical connection relationship, and group the extracted multiple line segments and multiple arc segments according to the aperture width to obtain different grouped bounding boxes. Multiple line segments and multiple arc segments within the same network that are electrically connected are extracted. Since the line segments in the same bounding box have a fixed proportional relationship, the extracted multiple line segments and multiple arc segments are grouped according to the aperture width to obtain bounding boxes of different groups.

[0053] A2. Calculate the size and position of each group of bounding boxes, and retain the bounding boxes whose size meets the preset size threshold; After obtaining bounding boxes by grouping, calculate the size and position of each group of bounding boxes. Filter bounding boxes whose sizes conform to the pre-designed dimensions. Keep bounding boxes whose sizes meet the preset size threshold.

[0054] A3. Based on the contour search method, select the combination of elements that make up the closed contour from the retained bounding boxes; Each graphical element can be considered as an edge of a graph, with the endpoints of the elements forming vertices. Vertices are points, and edges are line segments or arcs. A segment's internal vertices, except for its starting and ending points, do not participate in the graph construction; however, the starting and ending points of the arc must still be connected to other elements. A path starts from one vertex, follows an edge, and eventually returns to the starting point, with no two edges repeating.

[0055] The endpoints of all elements are placed in a list, and then points with a distance less than the tolerance are merged into a single vertex using clustering, such as spatial indexing or a grid. Each element corresponds to an edge, represented by two vertices: a start point and an end point. Edges within a cycle are connected sequentially using depth-first search or a dedicated cycle-finding algorithm to form a closed path. If the start and end points coincide, the contour is considered closed, and the element combinations that make up the closed contour are selected.

[0056] A4. Perform Boolean operations on the selected element combinations to merge them into polygons, and convert the polygons into pad polygons; The elements of the selected closed contours are combined using Boolean operations to form polygons. These polygons are then converted into pad polygons.

[0057] S1403. Based on the combined aperture element type of the pad layer, select the combined aperture element type conversion strategy, traverse all elements of the pad layer to decompose the combined aperture into basic elements, and then add them after converting the basic elements into the corresponding pad basic elements. For composite aperture elements, a composite aperture to pad conversion strategy is implemented. The complex aperture is decomposed into basic elements, converted into pads separately, the original aperture is deleted, and the converted pad elements are added.

[0058] S1404. Based on the nested loop element type of the pad layer, select the nested loop element type conversion strategy to convert the nested loop element into the corresponding multi-layer nested loop pad structure. Based on the nested loop element type of the pad layer, a nested loop element type conversion strategy is selected to convert the nested loop element into the corresponding multi-layer nested loop pad structure.

[0059] S1405. Based on the small aperture line element type of the pad layer, select the small aperture line element type conversion strategy and add the small aperture line elements to the conversion element list for unified conversion processing.

[0060] For small aperture line elements, implement the small aperture line to pad conversion strategy and add them to the conversion list for unified conversion.

[0061] For special combinations of graphic elements, a dedicated conversion strategy is used to complete the pad conversion.

[0062] S150. Based on the solder pad pattern data of the solder mask layer, the original pattern data of the circuit layer is converted to generate the solder pad pattern data of the circuit layer. The position coordinates of the solder mask pad graphic data are mapped to the corresponding circuit layer. Based on the shape and size of the solder mask pad graphic data, the graphic elements of the circuit layer are linked and transformed to generate the solder mask pad graphic data of the circuit layer.

[0063] S160. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drill layer are integrated to obtain standardized pad pattern data.

[0064] The step S160, which integrates the original pattern data of the stencil layer and the original pattern data of the drill layer based on the solder mask pattern data and the circuit layer pattern data to obtain standardized solder pad pattern data, includes steps S1601-S1606: S1601. Determine whether the original graphic data of the steel mesh layer and the original graphic data of the drilled layer are completely covered by the weld resist layer. S1602. If it is determined that there is an element that is completely covered by the solder mask layer, then delete the current element that is completely covered. Determine whether the original graphic data of the steel mesh layer and the original graphic data of the borehole layer are completely covered by the weld resist layer. If it is determined that there are elements completely covered by the weld resist layer, delete the currently covered elements.

[0065] S1603. Convert convex polygons that intersect with the solder mask layer but whose center point is not within the range included by the solder mask layer's pad pattern data into pad convex polygons. Convex polygons that intersect the solder mask layer but whose center point is not within the range included by the solder mask layer's pad pattern data are converted into pad convex polygons.

[0066] S1604. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, integrate the original pattern data of the stencil layer and the original pattern data of the drill layer to obtain standardized pad pattern data. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data.

[0067] S1605. Verify whether multiple line segments with the same aperture width are parallel and similar in shape. If they are parallel and similar in shape, treat multiple line segments with the same aperture width as a group of parallel lines and perform batch conversion. Verify whether multiple line segments with the same aperture width are parallel and similar in shape. If they are parallel and similar in shape, treat the multiple line segments with the same aperture width as a group of parallel lines and convert them in batches.

[0068] S1606. Verify the consistency of network connectivity before and after the conversion to ensure that electrical connections are not affected.

[0069] Verify the consistency of network connectivity before and after the conversion to ensure that electrical connections are not affected.

[0070] This application provides a method, apparatus, device, and medium for pad pattern conversion. In response to a pad image conversion command, a PCB file containing the pattern to be converted is obtained. The PCB file includes multi-layer original design data for a solder mask layer, a circuit layer, a stencil layer, and a drill layer. The PCB file is parsed to obtain original pattern data for the solder mask layer, circuit layer, stencil layer, and drill layer. Image recognition is performed on the original pattern data for the solder mask layer to obtain graphic elements of different element types. Based on the element type of the graphic element corresponding to the pad layer, a corresponding pad pattern conversion strategy is selected to convert the graphic element, resulting in solder mask pad pattern data. The original pattern data for the circuit layer is converted based on the solder mask pad pattern data to generate circuit layer pad pattern data. Based on the solder mask pad pattern data and the circuit layer pad pattern data, the original pattern data for the stencil layer and the original pattern data for the drill layer are integrated to obtain standardized pad pattern data. In this application, a dedicated recognition algorithm is designed for different types of graphic elements, covering various structures. Inter-layer linkage conversion is driven by the solder mask conversion result as a benchmark, ensuring the consistency of pad data between the two layers and avoiding conversion deviations. The entire conversion process requires no manual intervention, significantly improving the recognition accuracy of complex graphics. It enables automated, high-precision conversion from PCB design files to standardized pad data, providing reliable assurance for subsequent soldering, assembly, and other processes.

[0071] Figure 6 This is a schematic block diagram of a pad pattern conversion device provided in an embodiment of this application. Figure 6 As shown, corresponding to the above-described pad pattern conversion method, this application also provides a pad pattern conversion device 600. This pad pattern conversion device 600 includes a unit for performing the above-described pad pattern conversion, and can be configured in terminals such as desktop computers, tablet computers, and laptops. Specifically, please refer to... Figure 6 The pad pattern conversion device 600 includes an acquisition unit 601, a parsing unit 602, an image recognition unit 603, a first conversion unit 604, a second conversion unit 605, and an integration unit 606, wherein: The acquisition unit 601 is used to acquire the PCB file of the graphic to be converted in response to the conversion instruction of the pad image, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The parsing unit 602 is used to parse the PCB file of the graphic to be converted to obtain the original graphic data of the solder mask layer, the original graphic data of the circuit layer, the original graphic data of the stencil layer, and the original graphic data of the drill layer. Image recognition unit 603 is used to perform image recognition on the original graphic data of the solder resist layer to obtain graphic elements of different element types; The first conversion unit 604 is used to select the corresponding pad pattern conversion strategy to convert the graphic elements based on the element type of the graphic elements corresponding to the pad layer, so as to obtain the pad pattern data of the solder mask layer. The second conversion unit 605 is used to convert the original pattern data of the circuit layer based on the solder mask pattern data to generate the solder mask pattern data of the circuit layer. Integration unit 606 is used to integrate the original pattern data of the stencil layer and the original pattern data of the drill layer based on the solder mask pattern data and the solder pad pattern data of the circuit layer to obtain standardized solder pad pattern data.

[0072] In some embodiments, the first conversion unit 604 performs conversion on the graphic elements based on the element type corresponding to the pad layer, selecting the corresponding pad graphic conversion strategy to convert the graphic elements and obtain the pad graphic data of the solder mask layer, specifically for: Based on the single-line element type of the pad layer, a single-line element type conversion strategy is selected to convert the identified single line segment into a single pad line segment and the identified single arc segment into a single pad arc segment. Based on the multi-line enclosure element type of the pad layer, a multi-line enclosure element type conversion strategy is selected to convert multiple line segments and multiple arc segments within the same network with electrical connection relationships into pad polygons. Based on the combined aperture element type of the pad layer, a combined aperture element type conversion strategy is selected. All elements of the pad layer are traversed to decompose the combined aperture into basic elements. Then, based on the basic elements, they are converted into corresponding pad basic elements and added. Based on the nested loop element type of the pad layer, a nested loop element type conversion strategy is selected to convert the nested loop element into the corresponding multi-layer nested loop pad structure. Based on the type of the small aperture line element in the pad layer, a small aperture line element type conversion strategy is selected, and the small aperture line elements are added to the conversion element list for unified conversion processing.

[0073] In some embodiments, the first conversion unit 604, when executing a multi-line enclosure element type selection conversion strategy based on the pad layer, converts multiple line segments and multiple arc segments within the same network with electrical connections into pad polygons, specifically for: Based on the multi-line enclosure element type selection strategy of the pad layer, multiple line segments and multiple arc segments with electrical connection relationships in the same network are extracted, and the extracted multiple line segments and multiple arc segments are grouped according to the aperture width to obtain different grouped bounding boxes. Calculate the size and position of each group of bounding boxes, and retain the bounding boxes whose size meets the preset size threshold; The contour search method is used to filter out the combination of elements that make up the closed contour from the preserved bounding boxes. The selected element combinations are merged into polygons by performing Boolean operations, and the polygons are then converted into pad polygons.

[0074] In some embodiments, the image recognition unit 603 performs image recognition on the original graphic data of the solder mask layer to obtain graphic elements of different element types, specifically for: Image recognition is performed on the original graphic data of the solder mask layer to extract elements from the solder mask layer network; The extracted elements are judged by their element type. If they contain only a single line segment or arc segment that is not connected by other elements, they are identified as single-line elements. If multiple line segments and arc segments are extracted from the same network, and a set of line segments sufficient to enclose a closed region is identified through bounding box filtering, contour search, and polygon filtering, then it is determined as a multi-line enclosing element. If a polygon satisfies any one of the following conditions: a concave-convex polygon without internal holes, a polygon connected to a trace, or a polygon connected to a borehole, then it is determined to be a polygon element. If the two ends of a conductor are connected by arcs, and the center of the arc is on the conductor's axis or its extension, and the radius of the arc is proportional to the width of the conductor, then it is determined to be a round-headed conductor element. If a multi-layered nested spiral line structure is identified, the bounding box relationship of each layer of lines is calculated, and it is determined whether there are nested rectangles or other regular graphic structures. If so, it is determined to be a nested spiral line element. Filter line segments with aperture sizes smaller than a preset threshold, and then search within the existing bounding box. If a set of line segments that satisfy the bounding box ratio is found, it is identified as a small aperture line element.

[0075] In some embodiments, the second conversion unit 605 performs conversion of the original pattern data of the circuit layer based on the solder mask pattern data to generate solder pad pattern data of the circuit layer, specifically for: The position coordinates of the solder mask pad graphic data are mapped to the corresponding circuit layer. Based on the shape and size of the solder mask pad graphic data, the graphic elements of the circuit layer are linked and transformed to generate the solder mask pad graphic data of the circuit layer.

[0076] In some embodiments, the integration unit 606 integrates the original pattern data of the stencil layer and the original pattern data of the drill layer based on the solder mask pattern data and the circuit layer pattern data to obtain standardized solder pad pattern data, specifically for: Determine whether the original graphic data of the steel mesh layer and the original graphic data of the drilled layer are completely covered by the weld resist layer. If it is determined that there is an element that is completely covered by the solder mask, then delete the current element that is completely covered. Convex polygons that intersect the solder mask layer but whose center point is not within the range included by the solder mask layer's pad pattern data are converted into pad convex polygons. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data. Verify whether multiple line segments with the same aperture width are parallel and similar in shape. If they are parallel and similar in shape, treat multiple line segments with the same aperture width as a group of parallel lines and convert them in batches. Verify the consistency of network connectivity before and after the conversion to ensure that electrical connections are not affected.

[0077] This application provides a method, apparatus, device, and medium for pad pattern conversion. In response to a pad image conversion command, a PCB file containing the pattern to be converted is obtained. The PCB file includes multi-layer original design data for a solder mask layer, a circuit layer, a stencil layer, and a drill layer. The PCB file is parsed to obtain original pattern data for the solder mask layer, circuit layer, stencil layer, and drill layer. Image recognition is performed on the original pattern data for the solder mask layer to obtain graphic elements of different element types. Based on the element type of the graphic element corresponding to the pad layer, a corresponding pad pattern conversion strategy is selected to convert the graphic element, resulting in solder mask pad pattern data. The original pattern data for the circuit layer is converted based on the solder mask pad pattern data to generate circuit layer pad pattern data. Based on the solder mask pad pattern data and the circuit layer pad pattern data, the original pattern data for the stencil layer and the original pattern data for the drill layer are integrated to obtain standardized pad pattern data. In this application, a dedicated recognition algorithm is designed for different types of graphic elements, covering various structures. Inter-layer linkage conversion is driven by the solder mask conversion result as a benchmark, ensuring the consistency of pad data between the two layers and avoiding conversion deviations. The entire conversion process requires no manual intervention, significantly improving the recognition accuracy of complex graphics. It enables automated, high-precision conversion from PCB design files to standardized pad data, providing reliable assurance for subsequent soldering, assembly, and other processes.

[0078] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned pad pattern conversion device and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0079] The aforementioned pad pattern conversion device can be implemented as a computer program, which can, for example... Figure 7 It runs on the device shown.

[0080] Please see Figure 7 , Figure 7 This is a schematic block diagram of a device provided in an embodiment of this application. The device 700 can be a terminal or a server. The terminal can be an electronic device with communication functions, such as a smartphone, tablet, laptop, desktop computer, personal digital assistant, or wearable device. The server can be a standalone server or a server cluster composed of multiple servers.

[0081] See Figure 7 The device 700 includes a processor 702, a memory, and a network interface 705 connected via a system bus 701, wherein the memory may include a non-volatile medium 703 and internal memory 704.

[0082] The non-volatile medium 703 may store an operating system 7031 and a computer program 7032. The computer program 7032 includes program instructions that, when executed, cause the processor 702 to perform a pad pattern conversion.

[0083] The processor 702 provides computing and control capabilities to support the operation of the entire device 700.

[0084] The internal memory 704 provides an environment for the execution of the computer program 7032 in the non-volatile medium 703. When the computer program 7032 is executed by the processor 702, the processor 702 can perform a pad pattern conversion.

[0085] This network interface 705 is used for network communication with other devices. Those skilled in the art will understand that... Figure 7 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the device 700 to which the present application is applied. The specific device 700 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0086] The processor 702 is used to run the computer program 7032 stored in the memory to perform the following steps: In response to the conversion command of the pad image, the PCB file of the graphic to be converted is obtained, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The PCB file containing the graphic to be converted is parsed to obtain the original graphic data of the solder mask layer, the circuit layer, the stencil layer, and the drill layer. Image recognition is performed on the original graphic data of the solder mask layer to obtain graphic elements of different element types; Based on the element type of the graphic element corresponding to the pad layer, the corresponding pad graphic conversion strategy is selected to convert the graphic element to obtain the pad graphic data of the solder mask layer. Based on the solder mask layer's pad pattern data, the original pattern data of the circuit layer is converted to generate the circuit layer's pad pattern data. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data.

[0087] It should be understood that in the embodiments of this application, the processor 702 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0088] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a medium, which is a computer-readable medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0089] Therefore, this application also provides a medium. This medium can be a computer-readable medium. The medium stores a computer program, wherein the computer program includes program instructions. When executed by a processor, the program instructions cause the processor to perform the following steps: In response to the conversion command of the pad image, the PCB file of the graphic to be converted is obtained, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The PCB file containing the graphic to be converted is parsed to obtain the original graphic data of the solder mask layer, the circuit layer, the stencil layer, and the drill layer. Image recognition is performed on the original graphic data of the solder mask layer to obtain graphic elements of different element types; Based on the element type of the graphic element corresponding to the pad layer, the corresponding pad graphic conversion strategy is selected to convert the graphic element to obtain the pad graphic data of the solder mask layer. Based on the solder mask layer's pad pattern data, the original pattern data of the circuit layer is converted to generate the circuit layer's pad pattern data. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data.

[0090] The medium can be any computer-readable medium that can store program code, such as a USB flash drive, external hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0091] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0092] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0093] The steps in the methods of this application embodiment can be adjusted, merged, or deleted according to actual needs. The units in the apparatus of this application embodiment can be merged, divided, or deleted according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0094] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a medium and includes several instructions to cause a device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application.

[0095] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for converting pad patterns, characterized in that, The pad pattern conversion method includes: In response to the conversion command of the pad image, the PCB file of the graphic to be converted is obtained, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The PCB file containing the graphic to be converted is parsed to obtain the original graphic data of the solder mask layer, the circuit layer, the stencil layer, and the drill layer. Image recognition is performed on the original graphic data of the solder mask layer to obtain graphic elements of different element types; Based on the element type of the graphic element corresponding to the pad layer, the corresponding pad graphic conversion strategy is selected to convert the graphic element to obtain the pad graphic data of the solder mask layer. Based on the solder mask layer's pad pattern data, the original pattern data of the circuit layer is converted to generate the circuit layer's pad pattern data. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data.

2. The method according to claim 1, characterized in that, The element types include single-line elements, multi-line enclosing elements, combined aperture elements, nested spiral line elements, and small aperture line elements.

3. The method according to claim 2, characterized in that, Based on the element type of the graphic element corresponding to the pad layer, the corresponding pad graphic conversion strategy is selected to convert the graphic element to obtain the pad graphic data of the solder mask layer, including: Based on the single-line element type of the pad layer, a single-line element type conversion strategy is selected to convert the identified single line segment into a single pad line segment and the identified single arc segment into a single pad arc segment. Based on the multi-line enclosure element type of the pad layer, a multi-line enclosure element type conversion strategy is selected to convert multiple line segments and multiple arc segments within the same network with electrical connection relationships into pad polygons. Based on the combined aperture element type of the pad layer, a combined aperture element type conversion strategy is selected. All elements of the pad layer are traversed to decompose the combined aperture into basic elements. Then, based on the basic elements, they are converted into corresponding pad basic elements and added. Based on the nested loop element type of the pad layer, a nested loop element type conversion strategy is selected to convert the nested loop element into the corresponding multi-layer nested loop pad structure. Based on the type of the small aperture line element in the pad layer, a small aperture line element type conversion strategy is selected, and the small aperture line elements are added to the conversion element list for unified conversion processing.

4. The method according to claim 3, characterized in that, The multi-line enclosure element type selection and conversion strategy based on the pad layer converts multiple line segments and multiple arc segments within the same network with electrical connections into pad polygons, including: Based on the multi-line enclosure element type selection strategy of the pad layer, multiple line segments and multiple arc segments with electrical connection relationships in the same network are extracted, and the extracted multiple line segments and multiple arc segments are grouped according to the aperture width to obtain different grouped bounding boxes. Calculate the size and position of each group of bounding boxes, and retain the bounding boxes whose size meets the preset size threshold; The contour search method is used to filter out the combination of elements that make up the closed contour from the preserved bounding boxes. The selected element combinations are merged into polygons by performing Boolean operations, and the polygons are then converted into pad polygons.

5. The method according to claim 1, characterized in that, The process of performing image recognition on the original graphic data of the solder mask layer to obtain graphic elements of different element types includes: Image recognition is performed on the original graphic data of the solder mask layer to extract elements from the solder mask layer network; The extracted elements are judged by their element type. If they contain only a single line segment or arc segment that is not connected by other elements, they are identified as single-line elements. If multiple line segments and arc segments are extracted from the same network, and a set of line segments sufficient to enclose a closed region is identified through bounding box filtering, contour search, and polygon filtering, then it is determined as a multi-line enclosing element. If a polygon satisfies any one of the following conditions: a concave-convex polygon without internal holes, a polygon connected to a trace, or a polygon connected to a borehole, then it is determined to be a polygon element. If the two ends of a conductor are connected by arcs, and the center of the arc is on the conductor's axis or its extension, and the radius of the arc is proportional to the width of the conductor, then it is determined to be a round-headed conductor element. If a multi-layered nested spiral line structure is identified, the bounding box relationship of each layer of lines is calculated, and it is determined whether there are nested rectangles or other regular graphic structures. If so, it is determined to be a nested spiral line element. Filter line segments with aperture sizes smaller than a preset threshold, and then search within the existing bounding box. If a set of line segments that satisfy the bounding box ratio is found, it is identified as a small aperture line element.

6. The method according to claim 1, characterized in that, The process of converting the original pattern data of the circuit layer based on the solder mask pattern data to generate the solder pad pattern data of the circuit layer includes: The position coordinates of the solder mask pad graphic data are mapped to the corresponding circuit layer. Based on the shape and size of the solder mask pad graphic data, the graphic elements of the circuit layer are linked and transformed to generate the solder mask pad graphic data of the circuit layer.

7. The method according to claim 1, characterized in that, The solder pad pattern data based on the solder mask layer and the solder pad pattern data of the circuit layer are integrated with the original pattern data of the stencil layer and the original pattern data of the drill layer to obtain standardized solder pad pattern data, including: Determine whether the original graphic data of the steel mesh layer and the original graphic data of the drilled layer are completely covered by the weld resist layer. If it is determined that there is an element that is completely covered by the solder mask, then delete the current element that is completely covered. Convex polygons that intersect the solder mask layer but whose center point is not within the range included by the solder mask layer's pad pattern data are converted into pad convex polygons. Based on the solder mask layer's pad pattern data and the circuit layer's pad pattern data, the original pattern data of the stencil layer and the original pattern data of the drilled layer are integrated to obtain standardized pad pattern data. Verify whether multiple line segments with the same aperture width are parallel and similar in shape. If they are parallel and similar in shape, treat multiple line segments with the same aperture width as a group of parallel lines and convert them in batches. Verify the consistency of network connectivity before and after the conversion to ensure that electrical connections are not affected.

8. A pad pattern conversion device, characterized in that, The pad pattern conversion device includes: The acquisition unit is used to acquire the PCB file of the graphic to be converted in response to the conversion instruction of the pad image, wherein the PCB file of the graphic to be converted includes multi-layer original design data of solder mask layer, circuit layer, stencil layer and drill layer. The parsing unit is used to parse the PCB file of the graphic to be converted to obtain the original graphic data of the solder mask layer, the original graphic data of the circuit layer, the original graphic data of the stencil layer, and the original graphic data of the drill layer. An image recognition unit is used to perform image recognition on the original graphic data of the solder mask layer to obtain graphic elements of different element types; The first conversion unit is used to select the corresponding pad graphic conversion strategy to convert the graphic elements based on the element type of the graphic elements corresponding to the pad layer, so as to obtain the pad graphic data of the solder mask layer. The second conversion unit is used to convert the original pattern data of the circuit layer based on the solder mask pattern data to generate the solder mask pattern data of the circuit layer. The integration unit is used to integrate the original pattern data of the stencil layer and the original pattern data of the drill layer based on the solder mask pattern data and the solder pad pattern data of the circuit layer to obtain standardized solder pad pattern data.

9. A pad pattern conversion device, characterized in that, The method includes a memory, a processor, and a pad pattern conversion program stored in the memory and executable on the processor, wherein the processor executes the pad pattern conversion program to implement the steps of the pad pattern conversion method according to any one of claims 1 to 7.

10. A medium, characterized in that, The medium stores a program for implementing a method for converting pad patterns, the program for implementing the method for converting pad patterns being executed by a processor to implement the steps of the method for converting pad patterns as described in any one of claims 1 to 7.

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