A long short-term memory neural network circuit based on spintronics and a control method

Abstract

The application discloses a long short-term memory neural network circuit based on spintronics and a control method, which comprises an input circuit, a weight circuit and an activation function circuit. The input circuit utilizes a magnetic domain wall-magnetic tunnel junction device to realize time integration of the current time input and the previous time state by analog control of the magnetic domain wall position. The weight circuit comprises a cross array composed of multi-state magnetic domain wall-magnetic tunnel junction devices, wherein the synaptic weight is non-volatile stored as a discrete magnetic domain wall position defined by a photolithography notch. The weight circuit performs a matrix vector multiplication operation in the analog domain. The activation function circuit comprises a random magnetic tunnel junction device, which provides a nonlinear activation function by utilizing the voltage-dependent probability flipping characteristics of the random magnetic tunnel junction device. The application does not need a memristor and a conventional CMOS logic to realize the core LSTM operation, thereby significantly reducing the hardware area, power consumption and delay.

Description

Technical Field

[0001] This invention relates to the field of artificial intelligence neural network technology, and in particular to a long short-term memory neural network circuit and control method based on spintronics. Background Technology

[0002] Traditional computing architectures, namely the von Neumann architecture, face the so-called memory wall or von Neumann bottleneck problem when executing data-intensive algorithms such as neural networks. Frequent data transfers between independent processing and storage units lead to significant energy consumption and time latency, becoming a key factor limiting performance improvements. Long Short-Term Memory (LSTM) networks are widely used due to their superior ability to process time-series data. However, implementing LSTM networks on traditional CMOS-based hardware presents unique challenges. First, the recursive nature and dynamic feedback loops of LSTMs require storing and retrieving the hidden and cell states from the previous time step, resulting in an extremely high number of parameters and frequent memory access operations. Second, implementing nonlinear activation functions and large-scale matrix multiplication operations in the network requires bulky and high-power CMOS circuitry, further exacerbating hardware overhead.

[0003] To address these challenges, researchers have begun exploring the use of emerging non-volatile memory devices to build in-memory computing architectures. One approach is to utilize memristor technology. For example, existing techniques propose using dynamic memristors to achieve state superposition, using non-volatile memristor arrays to store weights and perform matrix operations, and leveraging the non-linear current-voltage characteristics of the memristors themselves to implement activation functions. However, memristor-based solutions also have their own technical limitations, such as limited read / write endurance, high inter-device variability, and challenges related to material systems. Therefore, the industry urgently needs a new hardware implementation solution based on different physical principles that can overcome all of the aforementioned limitations. Summary of the Invention

[0004] In view of the aforementioned existing problems, the present invention is proposed.

[0005] Therefore, this invention provides a long short-term memory neural network circuit and control method based on spintronics, which solves the problems of high power consumption, high latency and high area cost in traditional solutions, while avoiding the technical limitations associated with memristor-based solutions.

[0006] To solve the above-mentioned technical problems, the present invention provides the following technical solution: In a first aspect, the present invention provides a long short-term memory neural network circuit based on spintronics, comprising: The spintronic input circuit is used to receive the current input signal and the previous state signal, and to generate an integral output signal by physically accumulating the state variables through the first spintronic device. A spintronic weighting circuit, electrically connected to the spintronic input circuit, is used to store synaptic weights and perform matrix-vector multiplication on the integral output signal to generate a weighted sum signal; and The spintronic activation function circuit, electrically connected to the spintronic weighting circuit, is used to receive the weighted sum signal and generate a nonlinear activation output signal based on the probabilistic flipping behavior of the second spintronic device.

[0007] As a preferred embodiment of the spintronics-based long short-term memory neural network circuit described in this invention, the first spintronic device in the spintronic input circuit is a magnetic domain wall-magnetic tunnel junction device. The domain wall-magnetic tunnel junction device includes a ferromagnetic track, a heavy metal layer for generating spin orbital moments, and a magnetic tunnel junction stack located above the ferromagnetic track.

[0008] As a preferred embodiment of the spintronics-based long short-term memory neural network circuit described in this invention, the state variable is the physical position of the magnetic domain wall within the magnetic domain wall-magnetic tunnel junction device, and the physical position of the magnetic domain wall is controlled by the spin orbital moment generated by the current pulse applied to the heavy metal layer.

[0009] The beneficial effect of this preferred technical solution is that it directly realizes the addition operation through a physical process, completely eliminating the need for a digital adder circuit.

[0010] As a preferred embodiment of the spintronics-based long short-term memory neural network circuit described in this invention, the spintronic weighting circuit includes a cross array composed of magnetic domain wall-magnetic tunnel junction devices. The domain wall-magnetic tunnel junction device in the spin electron weighting circuit has multiple photolithographic notches in the ferromagnetic track, which are used to pin the domain walls at discrete positions.

[0011] As a preferred embodiment of the spintronics-based long short-term memory neural network circuit described in this invention, each photolithographic notch corresponds to a stable magnetic domain wall position, each magnetic domain wall position corresponds to a quantized resistance value, and each resistance value represents a quantized synaptic weight.

[0012] As a preferred embodiment of the spintronics-based long short-term memory neural network circuit described in this invention, the second spintronic device in the spintronic activation function circuit is a random magnetic tunnel junction device. The energy barrier between the high-resistivity and low-resistivity states of the second spintronic device is configured to randomly flip under thermal fluctuations; The flipping probability of the second spintronic device is related to the bias voltage applied to the second spintronic device in an S-shaped function.

[0013] The advantages of this preferred technical solution are as follows: by utilizing the inherent thermally induced random switching characteristics of the random magnetic tunnel junction, the switching probability is adjusted by the bias voltage, thereby directly realizing the S-type activation function at the device level without the need for additional nonlinear circuits, simplifying the hardware structure, and achieving low power consumption and high energy efficiency activation function.

[0014] As a preferred embodiment of the spintronics-based long short-term memory neural network circuit described in this invention, the nonlinear activation output signal generated by the spintronic activation function circuit is a time-averaged voltage or a probabilistic spike sequence, representing the hidden state after activation.

[0015] Secondly, the present invention provides a control method for a spintronics-based long short-term memory neural network circuit, comprising: A voltage pulse representing the current input and the state at the previous moment is applied to the spintronic input circuit. The state is accumulated by moving the position of the magnetic domain wall, and an integral output signal is generated. The integral output signal is applied to the cross array word line of the spintronic weighting circuit, and matrix-vector multiplication is performed through the resistors of the polystate memory cells in the array to generate a weighted sum signal on the bit line. The weighted sum signal is converted into a bias voltage and applied to a random magnetic tunnel junction device in a spintronic activation function circuit. The probabilistic flipping behavior of the random magnetic tunnel junction device is used to generate a nonlinear activation output signal. The nonlinear activation output signal is used as the hidden state output at the current moment and fed back to the spin electron input circuit for calculation in the next time step.

[0016] As a preferred embodiment of the control method for a spintronics-based long short-term memory neural network circuit according to the present invention, the control method further includes: The synaptic weights in the spin electron weighting circuit are programmed by applying spin orbital moment current pulses of specific amplitude and duration to move and fix the domain walls at the target notch position.

[0017] As a preferred embodiment of the control method for a spintronics-based long short-term memory neural network circuit according to the present invention, the control method further includes: The output of the spin electron activation function circuit is obtained by reading the state of the random magnetic tunnel junction multiple times within a time window and performing probability statistics.

[0018] Compared with existing technologies, the beneficial effects of this invention are as follows: By directly utilizing the physical principles of spintronics to execute the core LSTM operation, this invention achieves a significant reduction in hardware complexity, power consumption, and computational latency. Compared with other emerging technologies such as memristors, spintronic devices based on random magnetic tunnel junction (MTJ) devices have advantages such as non-volatility, extremely high read / write endurance, excellent scalability, and radiation resistance, providing a solid foundation for building efficient and reliable neuromorphic computing systems. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a block diagram of the overall architecture of a spintronics-based long short-term memory neural network circuit, provided as an embodiment of the present invention.

[0021] Figure 2 This is a schematic diagram of the internal structure of a standard LSTM cell in a spintronics-based long short-term memory neural network circuit, as provided in one embodiment of the present invention.

[0022] Figure 3 This is a detailed structural diagram of a spintronic input circuit based on DW-MTJ, which is a spintronic long short-term memory neural network circuit based on spintronics, provided as an embodiment of the present invention.

[0023] Figure 4 This is a schematic diagram of a cross array architecture of a spintronic weighting circuit for a spintronic long short-term memory neural network circuit, provided as an embodiment of the present invention.

[0024] Figure 5 A detailed structural diagram of a polymorphic DW-MTJ synapse with a photolithographic notch is provided for one embodiment of the present invention.

[0025] Figure 6 This is a schematic diagram of multiple stable resistive states of a multi-state DW-MTJ synapse in a spintronics-based long short-term memory neural network circuit, as provided in one embodiment of the present invention.

[0026] Figure 7 This is a detailed structural diagram of a spintronic activation function circuit based on a random MTJ for a long short-term memory neural network circuit based on spintronics, provided as an embodiment of the present invention.

[0027] Figure 8 This is a schematic diagram illustrating the S-shaped functional relationship between the input voltage and the flipping probability of a random MTJ based on a spintronics-based long short-term memory neural network circuit, as provided in one embodiment of the present invention.

[0028] Figure 9 The flowchart illustrates a control method for a spintronics-based long short-term memory neural network circuit, as provided in one embodiment of the present invention. Detailed Implementation

[0029] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0030] Example 1, referring to Figure 1 As an embodiment of the present invention, a spintronics-based long short-term memory neural network circuit is provided, including a spintronics input circuit, a spintronics weighting circuit, and a spintronics activation function circuit; Specifically, the spintronic input circuit is used to receive the current input signal and the previous state signal, and to generate an integral output signal by physically accumulating the state variables through the first spintronic device; Specifically, the spintronic weighting circuit is electrically connected to the spintronic input circuit, used to store synaptic weights and perform matrix-vector multiplication on the integral output signal to generate a weighted sum signal; and Specifically, the spintronic activation function circuit is electrically connected to the spintronic weighting circuit to receive the weighted sum signal and generate a nonlinear activation output signal based on the probabilistic flipping behavior of the second spintronic device.

[0031] In this embodiment of the invention, the first spintronic device in the spintronic input circuit is a domain wall-magnetic tunnel junction device; wherein, the domain wall-magnetic tunnel junction device includes a ferromagnetic track, a heavy metal layer for generating spin track moments, and a magnetic tunnel junction stack located above the ferromagnetic track.

[0032] In an optional embodiment, the first spintronic device may also be a magnetic tunnel junction array based on magnetic domain displacement, wherein multiple magnetic tunnel junction array units are coupled through a shared magnetic layer to achieve multi-state accumulation and storage.

[0033] In an optional embodiment, the first spintronic device may also be a device based on a spin torque oscillator, which uses its frequency modulation characteristics to perform time-domain integration of the input signal and output a corresponding oscillation signal.

[0034] In this embodiment of the invention, the state variable is the physical position of the domain wall within the domain wall-magnetic tunnel junction device, and the physical position of the domain wall is controlled by the spin orbital moment generated by the current pulse applied to the heavy metal layer.

[0035] In this embodiment of the invention, the spin electron weighting circuit includes a cross array composed of domain wall-magnetic tunnel junction devices; wherein, the domain wall-magnetic tunnel junction devices in the spin electron weighting circuit have multiple photolithographic notches in the ferromagnetic tracks, and the photolithographic notches are used to pin the domain walls at discrete positions.

[0036] In this embodiment of the invention, each photolithographic notch corresponds to a stable magnetic domain wall position, each magnetic domain wall position corresponds to a quantized resistance value, and each resistance value represents a quantized synaptic weight.

[0037] In this embodiment of the invention, the second spintronic device in the spintronic activation function circuit is a random magnetic tunnel junction device; the energy barrier between the high-resistivity state and the low-resistivity state of the second spintronic device is configured to randomly flip under thermal fluctuations; the flipping probability of the second spintronic device has an S-shaped functional relationship with the bias voltage applied to the second spintronic device.

[0038] In an optional embodiment, the second spintronic device may also be a random magnetic tunnel junction based on superparamagnetic nanoparticles, which can achieve a controllable thermal flip probability by adjusting the particle size and interface anisotropy.

[0039] In an optional embodiment, the second spintronic device may also employ a magnetic tunnel junction with voltage-modulated magnetic anisotropy effect, utilizing the continuous modulation of the energy barrier by the electric field to achieve a programmable activation function-like response.

[0040] In this embodiment of the invention, the nonlinear activation output signal generated by the spintronic activation function circuit is a time-averaged voltage or a probabilistic spike sequence, representing the hidden state after activation.

[0041] The spintronics-based long short-term memory neural network circuit provided in this embodiment significantly reduces hardware complexity, power consumption, and computational latency by directly utilizing the physical principles of spintronics to perform the core LSTM operation. Compared with other emerging technologies such as memristors, spintronic devices based on random magnetic tunnel junctions (MTJs) offer advantages such as non-volatility, extremely high read / write endurance, excellent scalability, and radiation resistance, providing a solid foundation for building efficient and reliable neuromorphic computing systems.

[0042] Example 2, refer to Figures 1-8 Based on the previous embodiment, this embodiment provides a detailed structural and functional description of a spintronics-based long short-term memory neural network circuit, in order to illustrate the technical means of the present invention.

[0043] In embodiments of the present invention, such as Figure 1 The overall architecture of the spintronics-based long short-term memory neural network circuit shown mimics the standard LSTM unit (e.g., Figure 2 The data flow (as shown) mainly includes a spintronic input circuit, a spintronic weighting circuit, and a spintronic activation function circuit. The spintronic input circuit, spintronic weighting circuit, and spintronic activation function circuit are electrically connected in sequence and contain a feedback loop from output to input.

[0044] Specifically, during operation, the input voltage representing the current input and the previous hidden state is converted into current, driving the spintronic input circuit. The output of the spintronic input circuit is a voltage signal, which is applied to the word lines of the cross array of the spintronic weighting circuit. The summed current from the bit line outputs of the spintronic weighting circuit is fed into the spintronic activation function circuit. The spintronic activation function circuit ultimately generates an output voltage representing the current hidden state.

[0045] In this embodiment of the invention, the working principle of the spintronic input circuit includes: It should be noted that the core function of the spintronic input circuit is to superimpose the current input Xt and the hidden state of the previous time step onto the LSTM input gate. In this embodiment of the invention, this function is achieved by a specially configured domain wall-magnetic tunnel junction (DW-MTJ) device (such as...). Figure 3 The implementation (as shown) uses a different approach than traditional digital adders and registers.

[0046] Specifically, the domain wall-magnetic tunnel junction device includes a ferromagnetic orbital, a heavy metal layer for generating spin orbital moments, and a magnetic tunnel junction stack located above the ferromagnetic orbital.

[0047] Specifically, an input voltage pulse is applied to the heavy metal layer, generating a spin current. This current exerts a torque (SOT) on the domain walls, causing them to move gradually along their orbits. Therefore, the position of the domain walls becomes a direct analog representation of the input signal as a function of time integral, functioning similarly to the membrane potential in biological neurons. This mechanism directly achieves addition through a physical process, completely eliminating the need for digital adder circuitry.

[0048] Specifically, this embodiment introduces a leakage mechanism to prevent integral saturation. This leakage mechanism can be achieved through inherent thermal drift, or by engineering the track geometry to create a restoring force on the domain walls, causing them to gradually return to their resting position over time. When the accumulated potential (i.e., the domain wall position) exceeds a threshold (i.e., the location of the MTJ), the resistance of the MTJ changes, generating an excitation signal, from which the circuit's output is produced.

[0049] It should be noted that using simulated positions of magnetic domain walls for integration offers significant advantages over the discrete, clock-driven operations of traditional CMOS. This allows for a more continuous and biologically realistic representation of temporal information. In CMOS, X_t + h_{t-1} is a digital addition operation, while in this invention, pulses corresponding to X_t and h_{t-1} naturally move the magnetic domain walls to positions representing their sum. This is a simulated, physical summation method that achieves hardware simplification in a novel way.

[0050] In an optional embodiment, the integral output signal can also be acquired using a vertically magnetized nanowire structure based on current-controlled domain motion, by directly modulating the domain wall position with current pulses and reading the corresponding tunnel magnetoresistance changes.

[0051] In an alternative embodiment, the acquisition of the integral output signal can also utilize a spin Hall effect driven magnetic domain displacement device, which generates a spin current in the heavy metal layer through the input current, drives the magnetic domains to move, and converts it into a detectable voltage output.

[0052] In this embodiment of the invention, the working principle of the spin electron weighting circuit includes: Specifically, the core function of the spintronic weighting circuit is to store synaptic weights and perform matrix-vector multiplication operations through a cross array architecture, such as... Figure 4 As shown in the diagram, in this cross array, a polymorphic DW-MTJ synaptic unit is integrated at the intersection of each word line and bit line, forming the basic structure for performing in-memory computation.

[0053] Specifically, such as Figure 5 The multi-state DW-MTJ synaptic unit shown is a special modification based on the traditional DW-MTJ device structure. Its core feature lies in the series of physical notches defined by photolithography within the ferromagnetic tracks of the domain walls. These notches serve as artificially designed pinning sites, providing multiple discrete and stable energy minimum locations for the domain walls, thereby achieving multi-state storage.

[0054] Specifically, synaptic weights are programmed by applying SOT current pulses of specific amplitude and duration to move domain walls and trap them in desired notches. For example... Figure 6As shown, each notch position corresponds to a unique and stable magnetic tunnel junction resistance value. For example, four discrete resistance plateaus of approximately 3.5kΩ, 4.0kΩ, 4.5kΩ and 5.0kΩ can be quantified, and each plateau represents a quantized synaptic weight value. Figure 6 The X-axis (programming pulse sequence number) represents the number of consecutive electrical pulses applied by moving the magnetic domain walls, and the Y-axis (resistance (kΩ)) represents the device resistance value measured by the MTJ readhead. Data points represent the simulated results of a single measurement. Data analysis shows that reliable multi-state storage can be achieved by precisely controlling the position and geometry of the notch. Each resistance plateau is clearly distinguishable, with only minor internal thermal noise fluctuations that do not affect state differentiation, thus verifying the feasibility and robustness of this structure as a non-volatile multi-weighted synapse.

[0055] Specifically, during forward propagation, a lower read voltage representing the input signal is applied to the word line. Based on the resistance value stored in each synaptic unit, a current is generated in the corresponding bit line according to Ohm's law. All currents flowing into the same bit line are automatically summed according to Kirchhoff's current law, thus physically completing the entire matrix-vector multiplication operation in a single step, achieving efficient analog domain multiplication and accumulation.

[0056] In an alternative embodiment, the matrix-vector multiplication step can also employ a current summation method based on magnetization vector projection, which reads the tunneling magnetoresistance change of the magnetic tunnel junction and converts it into a weighted current, thereby achieving parallel multiplication and accumulation in the analog domain.

[0057] In an alternative embodiment, the matrix-vector multiplication step can also utilize the principle of spin wave interference, modulating the phase of the spin wave through the input signal, and directly outputting the weighted summation result through the intensity of wave interference in the cross array.

[0058] It's important to note that by engineering the geometry of notched synapses, the trade-off between write controllability and resistance stability can be precisely controlled. For example, trapezoidal geometry can provide asymmetric, highly controllable weight updates, suitable for online learning scenarios; while rectangular geometry offers higher randomness but more stable resistance levels, ideal for inference tasks. This means that the same underlying technology can be used to optimize different stages of the machine learning workflow by changing the physical shape of the device.

[0059] In this embodiment of the invention, the working principle of the spin electron activation function circuit includes: Specifically, the activation function circuit is used to implement nonlinear activation functionality. The circuit consists of one or a group of MTJ devices connected in parallel, such as... Figure 7As shown. The core of the activation function circuit is a specially engineered magnetic tunnel junction device. By precisely controlling the material properties and thickness of its ferromagnetic free layer, the energy barrier between the parallel and antiparallel states of the device is designed to be very low.

[0060] Specifically, the current collected from the bit lines of the weighting circuit is converted into a bias voltage and applied to the random MTJ. Due to the low energy barrier, thermal fluctuations are sufficient to cause the MTJ to randomly flip between its high-resistivity and low-resistivity states. The applied bias voltage tilts the energy barrier, making one state more likely than the other. The relationship between the applied voltage and the probability of the MTJ being in a high-resistivity state naturally exhibits an S-shaped curve. Figure 8 The Y-axis represents the probability of flipping to a high-resistivity state, obtained by performing numerous (e.g., 1000) rapid state reads at each fixed bias voltage and statistically analyzing the proportion of high-resistivity states. The X-axis represents the DC bias voltage applied to the random magnetic tunnel junction by an external precision voltage source. The data points in the figure represent the flipping probabilities statistically obtained at each specific voltage. Experimental analysis shows that the experimental data points perfectly fit a smooth S-shaped curve (Sigmoid function). Utilizing the inherent thermally induced random flipping physical characteristics of the MTJ at low energy barriers, a nonlinear activation function can be directly implemented at the hardware level. When the input voltage is a large negative value, the flipping probability approaches 0; as the voltage increases, the probability increases smoothly, exhibiting the steepest change near 0V; when the voltage is a large positive value, the probability saturates and approaches 1. This physical behavior highly matches the ideal Sigmoid activation function in neural networks, thus directly implementing an efficient and concise nonlinear activation function at the hardware level.

[0061] Specifically, the output of the activation circuit is a time-averaged voltage or a probabilistic sequence of spikes, representing the activated value, which can be directly used as the hidden state ht.

[0062] It is important to note that using an inherently random device to implement the activation function opens a direct path to more advanced neural network paradigms or solving combinatorial optimization problems without adding any additional hardware. This randomness is not a defect that needs to be eliminated by engineering, but rather a characteristic that can be utilized. The random magnetic tunnel junction is essentially a hardware-implemented probabilistic bit. For example, Bayesian neural networks rely on sampling from probability distributions to quantify uncertainty, a process that is computationally expensive in software, while the random magnetic tunnel junction can physically implement the sampling process. Furthermore, algorithmic frameworks for solving combinatorial optimization problems such as the Traveling Salesman Problem often rely on randomized strategies parameterized by neural networks. Therefore, the LSTM circuit proposed in this invention is not only an efficient LSTM hardware implementation scheme, but also constitutes a fundamental functional unit for building future hardware-based probabilistic computers, significantly expanding its application scope and practical value.

[0063] Example 3, referring to Figure 9 Based on the previous embodiment, this embodiment provides a control method for a spintronics-based long short-term memory neural network circuit, including: A voltage pulse representing the current input and the state at the previous moment is applied to the spintronic input circuit. The state is accumulated by moving the position of the magnetic domain wall, and an integral output signal is generated. The integral output signal is applied to the cross array word line of the spintronic weighting circuit, and matrix-vector multiplication is performed through the resistors of the polystate memory cells in the array to generate a weighted sum signal on the bit line. The weighted sum signal is converted into a bias voltage and applied to the random magnetic tunnel junction device in the spintronic activation function circuit. The probabilistic flipping behavior of the random magnetic tunnel junction device is used to generate a nonlinear activation output signal. The nonlinear activation output signal is used as the hidden state output at the current moment and fed back to the spintronic input circuit for calculation of the next time step.

[0064] Specifically, the synaptic weights in the spintronic weighting circuit are programmed by applying spin orbital moment current pulses of specific amplitude and duration to move and fix the domain walls at the target notch position.

[0065] Specifically, the output of the spin electron activation function circuit is obtained by reading the state of a random magnetic tunnel junction multiple times within a time window and performing probability statistics.

[0066] In this embodiment of the invention, reference is made to Figure 9 The flowchart illustrates the control method for executing LSTM single-timestep forward propagation, which specifically includes the following steps: A voltage pulse corresponding to Xt and h_{t-1} is applied to the SOT terminal of the DW-MTJ in the input circuit, causing the domain walls to move to a new position representing their superposition. Read the MTJ resistor of the input circuit to generate a voltage Vi; apply Vi to the word lines of the weighted circuit cross array; The current collected from the bit line is gathered by a summing amplifier and applied as a bias voltage V_{act} to the random MTJ of the activation function circuit; The state of the random MTJ is read within a time window to produce the output ht. This value is then stored in a temporary latch and used as the input h_{t-1} for the next time step, thus completing the recursive loop.

[0067] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

[0068] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0069] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A long short-term memory neural network circuit based on spintronics, characterized in that, include: The spintronic input circuit is used to receive the current input signal and the previous state signal, and to generate an integral output signal by physically accumulating the state variables through the first spintronic device. A spintronic weighting circuit, electrically connected to the spintronic input circuit, is used to store synaptic weights and perform matrix-vector multiplication on the integral output signal to generate a weighted sum signal. as well as The spintronic activation function circuit, electrically connected to the spintronic weighting circuit, is used to receive the weighted sum signal and generate a nonlinear activation output signal based on the probabilistic flipping behavior of the second spintronic device.

2. The spintronics-based long short-term memory neural network circuit as described in claim 1, characterized in that, The first spintronic device in the spintronic input circuit is a magnetic domain wall-magnetic tunnel junction device. The domain wall-magnetic tunnel junction device includes a ferromagnetic track, a heavy metal layer for generating spin orbital moments, and a magnetic tunnel junction stack located above the ferromagnetic track.

3. The spintronics-based long short-term memory neural network circuit as described in claim 2, characterized in that, The state variable is the physical position of the domain wall within the domain wall-magnetic tunnel junction device, and the physical position of the domain wall is controlled by the spin orbital moment generated by the current pulse applied to the heavy metal layer.

4. The spintronics-based long short-term memory neural network circuit as described in claim 3, characterized in that, The spintronic weighting circuit includes a cross array composed of domain wall-magnetic tunnel junction devices; The domain wall-magnetic tunnel junction device in the spin electron weighting circuit has multiple photolithographic notches in the ferromagnetic track, which are used to pin the domain walls at discrete positions.

5. The spintronics-based long short-term memory neural network circuit as described in claim 4, characterized in that, Each photolithographic notch corresponds to a stable domain wall position, each domain wall position corresponds to a quantized resistance value, and each resistance value represents a quantized synaptic weight.

6. The spintronics-based long short-term memory neural network circuit as described in claim 5, characterized in that, The second spintronic device in the spintronic activation function circuit is a random magnetic tunnel junction device; The energy barrier between the high-resistivity and low-resistivity states of the second spintronic device is configured to randomly flip under thermal fluctuations; The flipping probability of the second spintronic device is related to the bias voltage applied to the second spintronic device in an S-shaped function.

7. The spintronics-based long short-term memory neural network circuit as described in claim 6, characterized in that, The nonlinear activation output signal generated by the spintronic activation function circuit is a time-averaged voltage or a probabilistic spike sequence, representing the hidden state after activation.

8. A control method for a spintronics-based long short-term memory neural network circuit, employing the spintronics-based long short-term memory neural network circuit described in claims 1-7, characterized in that... The control method includes: A voltage pulse representing the current input and the state at the previous moment is applied to the spintronic input circuit. The state is accumulated by moving the position of the magnetic domain wall, and an integral output signal is generated. The integral output signal is applied to the cross array word line of the spintronic weighting circuit, and matrix-vector multiplication is performed through the resistors of the polystate memory cells in the array to generate a weighted sum signal on the bit line. The weighted sum signal is converted into a bias voltage and applied to a random magnetic tunnel junction device in a spintronic activation function circuit. The probabilistic flipping behavior of the random magnetic tunnel junction device is used to generate a nonlinear activation output signal. The nonlinear activation output signal is used as the hidden state output at the current moment and fed back to the spin electron input circuit for calculation in the next time step.

9. The control method for a spintronics-based long short-term memory neural network circuit as described in claim 8, characterized in that, The control method further includes: The synaptic weights in the spin electron weighting circuit are programmed by applying spin orbital moment current pulses of specific amplitude and duration to move and fix the domain walls at the target notch position.

10. The control method for a spintronics-based long short-term memory neural network circuit as described in claim 9, characterized in that, The control method further includes: The output of the spin electron activation function circuit is obtained by reading the state of the random magnetic tunnel junction multiple times within a time window and performing probability statistics.

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