Display device and electronic device

Abstract

A display device and an electronic device are provided. The display device includes a display panel including a plurality of pixels, and a display panel driver configured to drive the display panel. The plurality of pixels include first sub-pixels having a first viewing angle and second sub-pixels having a second viewing angle different from the first viewing angle. The first sub-pixels emit light based on first sub-pixel compensation signals, and the second sub-pixels emit light based on second sub-pixel compensation signals. The first sub-pixel compensation signals can be generated based on a first clock signal group, and the second sub-pixel compensation signals can be generated based on a second clock signal group. The second clock signal group can maintain an inactive level when the first sub-pixels emit light.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device with reduced power consumption and an electronic device including the display device. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, multiple emitter lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, an emitter driver that provides emitter signals to the emitter lines, and a drive controller that controls the gate driver, data driver, and emitter driver.

[0003] Typically, the drive controller can generate data signals for producing data voltages based on power signals and clock signals. Summary of the Invention

[0004] An embodiment of the present invention provides a display device with reduced power consumption.

[0005] Embodiments of the present invention also provide an electronic device with reduced power consumption.

[0006] According to an embodiment of the present invention, a display device includes: a display panel including a plurality of pixels; and a display panel driver configured to drive the display panel. The plurality of pixels includes a first sub-pixel having a first viewing angle and a second sub-pixel having a second viewing angle different from the first viewing angle. The first sub-pixel emits light based on a first sub-pixel compensation signal, and the second sub-pixel emits light based on a second sub-pixel compensation signal. The first sub-pixel compensation signal is generated based on a first clock signal group, and the second sub-pixel compensation signal is generated based on a second clock signal group. When the first sub-pixel emits light, the second clock signal group can remain at an inactive level.

[0007] In an embodiment, the display panel driver may include: a clock signal outputter configured to output a first clock signal group and a second clock signal group; a pixel compensator configured to output a first sub-pixel compensation signal and a second sub-pixel compensation signal based on an enable signal; and a power controller configured to apply a power signal to the pixel compensator.

[0008] In this embodiment, when the enable signal has an inactive level, the pixel compensator can output a first sub-pixel compensation signal, but may not output a second sub-pixel compensation signal.

[0009] In an embodiment, when the enable signal has an inactive level, the first clock signal group can be switched, and the second clock signal group can remain at an inactive level.

[0010] In an embodiment, the pixel compensator may include: a first pixel compensator configured to output a first sub-pixel compensation signal; and a second pixel compensator configured to output a second sub-pixel compensation signal. The electrical signal may include a first electrical signal applied to the first pixel compensator and a second electrical signal applied to the second pixel compensator. When the enable signal has an inactive level, the first electrical signal may be applied to the first pixel compensator, and the second electrical signal may not be applied to the second pixel compensator.

[0011] In an embodiment, when the enable signal has an active level, the first clock signal group can be switched, and the second clock signal group can be switched.

[0012] In an embodiment, the pixel compensator may include: a first pixel compensator configured to output a first sub-pixel compensation signal; and a second pixel compensator configured to output a second sub-pixel compensation signal. The electrical signal may include a first electrical signal applied to the first pixel compensator and a second electrical signal applied to the second pixel compensator. When an enable signal has an active level, the first electrical signal may be applied to the first pixel compensator, and the second electrical signal may be applied to the second pixel compensator.

[0013] In an embodiment, the first activation period of the first clock signal group switching may not overlap with the second activation period of the second clock signal group switching.

[0014] In one embodiment, during the first active period, the second clock signal group may remain at an inactive level.

[0015] In an embodiment, the pixel compensator may include: a first pixel compensator configured to output a first sub-pixel compensation signal; and a second pixel compensator configured to output a second sub-pixel compensation signal. The second pixel compensator may include: a second pixel compensation signal outputter configured to output the second sub-pixel compensation signal; and a second pixel compensation data memory configured to apply second pixel compensation data to the second pixel compensation signal outputter. The second pixel compensation signal outputter may include a hold trigger for performing data holding.

[0016] In this embodiment, the frame period for driving the display panel may include a first frame period and a second frame period. The first frame period may include a first active period and a first idle period. The second frame period may include a second active period and a second idle period that is longer than the first idle period. During the second idle period, the first clock signal group and the second clock signal group may remain at an inactive level.

[0017] According to an embodiment of the present invention, a display device includes a display panel, including a first display area and a second display area; and a display panel driver configured to drive the display panel. The first display area includes a first sub-pixel having a first viewing angle, and the second display area includes the first sub-pixel and a second sub-pixel having a second viewing angle different from the first viewing angle. The first sub-pixel emits light based on a first data signal, and the second sub-pixel emits light based on a second data signal. The first data signal is generated based on a first sub-pixel compensation signal, and the second data signal is generated based on a second sub-pixel compensation signal. The first sub-pixel compensation signal is generated based on a first clock signal group, and the second sub-pixel compensation signal is generated based on a second clock signal group. When the first sub-pixel of the second display area emits light, the second clock signal group remains at an inactive level.

[0018] In an embodiment, the display panel driver may include: a clock signal outputter configured to output a first clock signal group and a second clock signal group; a pixel compensator configured to output a first sub-pixel compensation signal and a second sub-pixel compensation signal based on an enable signal; and a power controller configured to apply a power signal to the pixel compensator.

[0019] In an embodiment, when the enable signal has an inactive level, the first clock signal group can be switched, and the second clock signal group can remain at an inactive level.

[0020] In an embodiment, when the enable signal has an active level, the first clock signal group can be switched, and the second clock signal group can be switched.

[0021] In this embodiment, the display panel can be driven in either a first mode or a second mode. In the first mode, a first sub-pixel of the second display area can emit light, and a second sub-pixel of the second display area can remain non-illuminating. In the second mode, a first sub-pixel of the second display area can remain non-illuminating, and a second sub-pixel of the second display area can emit light.

[0022] In one embodiment, when the display panel is driven in the first mode, the second clock signal group can remain at an inactive level.

[0023] In an embodiment, when the display panel is driven in a first mode, the second power signal applied to the second sub-pixel compensator that outputs the second sub-pixel compensation signal may have an inactive level.

[0024] According to an embodiment of the present invention, an electronic device includes: a processor configured to input image data and input control signals; a display panel including a plurality of pixels; and a display panel driver configured to drive the display panel based on the input image data and the input control signals. The plurality of pixels includes a first sub-pixel having a first viewing angle and a second sub-pixel having a second viewing angle different from the first viewing angle. The first sub-pixel emits light based on a first sub-pixel compensation signal, and the second sub-pixel emits light based on a second sub-pixel compensation signal. The first sub-pixel compensation signal is generated based on a first clock signal group, and the second sub-pixel compensation signal is generated based on a second clock signal group. When the first sub-pixel emits light, the second clock signal group remains at an inactive level.

[0025] In this embodiment, the display panel may include a first display area and a second display area. The first display area may include a first sub-pixel, and the second display area may include a first sub-pixel and a second sub-pixel. When the first sub-pixel of the second display area emits light, the second clock signal group may remain at an inactive level.

[0026] As described above, the output of the clock signal group and the power signal can be controlled based on the enable signal. Therefore, the power consumption of the display device can be reduced.

[0027] Furthermore, the drive controller may include a hold trigger and a hold memory. Therefore, pre-applied data can be retained even when the power signal to the drive controller is turned off or cut off. This improves the calculation speed of the drive controller. For example, it can improve the signal generation speed of the drive controller. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0030] Figure 2 This is a diagram showing a display panel included in a display device.

[0031] Figure 3 This is a block diagram showing a drive controller included in a display device.

[0032] Figure 4 It is shown that it includes Figure 3 A block diagram of the common pixel compensator in the driver controller.

[0033] Figure 5 It is shown that it includes Figure 3 A block diagram of the dedicated pixel compensator in the drive controller.

[0034] Figure 6 It is shown Figure 3 The timing diagram of the period during which the drive controller is driven.

[0035] Figure 7 It is shown that it includes Figure 6 The time sequence diagram of the sub-time periods in the second time period.

[0036] Figure 8 It is shown Figure 3 The drive controller in Figure 7 A flowchart of the operations during the first sub-period.

[0037] Figure 9 It is shown Figure 3 The drive controller in Figure 7 A flowchart of the operations during the second sub-period.

[0038] Figure 10 It is shown that it includes Figure 1 A block diagram of the frame period in which the display panel in a display device is driven.

[0039] Figure 11 It shows when Figure 1 When the display panel is driven at a variable frequency Figure 3 The timing diagram of the period during which the drive controller is driven.

[0040] Figure 12 It is shown Figure 3 The drive controller in Figure 11 A flowchart of the operations during the second time period.

[0041] Figure 13 It is shown that it includes Figure 1 A block diagram of the drive controller in the display device.

[0042] Figure 14 It is shown Figure 13 The timing diagram of the period during which the drive controller is driven.

[0043] Figure 15 It is shown that it includes Figure 1 A diagram of the display panel in a display device.

[0044] Figure 16 This is a block diagram illustrating an electronic device according to an embodiment of the concept of the present invention.

[0045] Figure 17 It is shown that Figure 16 The diagram shows an example of an electronic device implemented as an automotive electronic device. Detailed Implementation

[0046] The concept of the invention will be explained in detail below with reference to the accompanying drawings.

[0047] Figure 1 This is a block diagram illustrating a display device 1 according to an embodiment of the concept of the present invention.

[0048] Reference Figure 1 The display device 1 may include a display panel 100 and a display panel driver. The display panel driver may include a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a transmit driver 600.

[0049] The display panel 100 may have a display area for displaying images and a peripheral area placed adjacent to the display area.

[0050] The display panel 100 may include multiple gate lines GL, multiple data lines DL, multiple emitter lines EL, and multiple pixels PX. Each of the multiple pixels PX is electrically connected to a corresponding gate line in the multiple gate lines GL, a corresponding data line in the multiple data lines DL, and a corresponding emitter line in the multiple emitter lines EL. The gate lines GL may extend in a first direction D1. The data lines DL may extend in a second direction D2 intersecting the first direction D1. The emitter lines EL may extend in the first direction D1.

[0051] The drive controller 200 can be controlled from an external device (e.g., from...) Figure 16 The processor 1010 in the processor receives input image data IMG and input control signal CONT. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. For example, the input control signal CONT may include a master clock signal and a data enable signal DE (see...). Figure 6 The input control signal CONT may also include... Figure 6 The vertical synchronization signal VSYNC and the horizontal synchronization signal. The input control signal CONT may also include the enable signal EN and the flag signal FG (see [link to relevant documentation]). Figure 6 ).

[0052] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0053] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. For example, the first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0054] The drive controller 200 can generate a second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT, and output the second control signal CONT2 to the data driver 500. For example, the second control signal CONT2 may include a horizontal start signal and a load signal.

[0055] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500. The data signal DATA may include a common pixel data signal PUCS and a dedicated pixel data signal PRCS (see...). Figure 3 ).

[0056] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0057] The drive controller 200 can generate a fourth control signal CONT4 for controlling the operation of the transmitter driver 600 based on the input control signal CONT, and output the fourth control signal CONT4 to the transmitter driver 600.

[0058] The gate driver 300 can generate gate signals to be supplied to a plurality of pixels PX in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signals to the gate line GL.

[0059] In one embodiment, the gate driver 300 may be disposed in the peripheral region. Alternatively, the gate driver 300 may be integrated into the peripheral region.

[0060] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to the level of the data signal DATA.

[0061] In an embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0062] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type. The analog data voltage VDATA can be a pixel data voltage (see...). Figure 4 Public pixel compensation data (PUCDATA). Figure 4 The common pixel compensation data PUCDATA can be the voltage corresponding to the data signal DATA. The data driver 500 can output the data voltage VDATA to the data line DL.

[0063] In one embodiment, the data driver 500 may be located in the peripheral area. Alternatively, the data driver 500 may be integrated into the peripheral area.

[0064] The transmitter driver 600 can generate a transmission signal in response to a fourth control signal CONT4 received from the drive controller 200. The transmitter driver 600 can output the transmission signal to the display panel 100. The transmitter driver 600 can generate the transmission signal based on a drive voltage. For example, the drive voltage can include a high transmission voltage and a low transmission voltage. The transmission signal can switch between high and low transmission voltages.

[0065] In one embodiment, the transmit driver 600 may be disposed in the peripheral region. Alternatively, the transmit driver 600 may be integrated into the peripheral region.

[0066] Although for the sake of explanation, Figure 1 The diagram shows a gate driver 300 disposed on a first side of the display panel 100 and an emitter driver 600 disposed on a second side of the display panel 100; however, the inventive concept is not limited thereto. The gate driver 300 and the emitter driver 600 may be disposed on the first side of the display panel 100. For example, the gate driver 300 and the emitter driver 600 may be disposed on the same side of the display area of ​​the display panel 100 on a peripheral area of ​​the display panel 100. For example, the gate driver 300 and the emitter driver 600 may be integrally formed with each other.

[0067] Figure 2 It is shown that it includes Figure 1 A diagram of the display panel 100 in the display device 1.

[0068] Reference Figure 1 and Figure 2 The display panel 100 may include multiple pixels PX. Each pixel PX may include a first sub-pixel PU-SPX and a second sub-pixel PR-SPX. The first sub-pixel PU-SPX may include a light-emitting element having a first viewing angle VA1. The second sub-pixel PR-SPX may include a light-emitting element having a second viewing angle VA2. The first viewing angle VA1 may be different from the second viewing angle VA2. For example, the first viewing angle VA1 may be wider than the second viewing angle VA2. For example, the first sub-pixel PU-SPX may be referred to as a common sub-pixel. For example, the second sub-pixel PR-SPX may be referred to as a dedicated sub-pixel.

[0069] In an embodiment, the first sub-pixel PU-SPX may include a first red sub-pixel emitting red light, a first green sub-pixel emitting green light, and a first blue sub-pixel emitting blue light. However, the inventive concept is not limited to the number of sub-pixels included in the first sub-pixel PU-SPX as described above. Furthermore, the inventive concept is not limited to the color of each sub-pixel included in the first sub-pixel PU-SPX as described above.

[0070] In an embodiment, the second sub-pixel PR-SPX may include a second red sub-pixel emitting red light, a second green sub-pixel emitting green light, and a second blue sub-pixel emitting blue light. However, the inventive concept is not limited to the number of sub-pixels included in the second sub-pixel PR-SPX as described above. Furthermore, the inventive concept is not limited to the color of each sub-pixel included in the second sub-pixel PR-SPX as described above.

[0071] In an embodiment, the size of each of the second red sub-pixel, the second green sub-pixel, and the second blue sub-pixel may be the same as, or smaller than, the size of each of the first red sub-pixel, the first green sub-pixel, and the first blue sub-pixel.

[0072] Figure 3 This is a block diagram showing an example (represented by 200A) of a drive controller 200 included in the display device 1. Figure 4 It is shown that it includes Figure 3 Block diagram of the common pixel compensator 230 in the drive controller 200A. Figure 5 It is shown that it includes Figure 3 Block diagram of the dedicated pixel compensator 240 in the drive controller 200A.

[0073] Reference Figures 1 to 5 The drive controller 200A may include a clock signal output unit 210, a power controller 220, and a pixel compensator PC.

[0074] Clock signal outputter 210 can output a first clock signal group CLKG1 and a second clock signal group CLKG2. Clock signal outputter 210 can output the first clock signal group CLKG1 in response to a common pixel clock signal request signal RPUS. Clock signal outputter 210 can output the second clock signal group CLKG2 in response to a dedicated pixel clock signal request signal RPRS. The first clock signal group CLKG1 can include multiple clock signals. The second clock signal group CLKG2 can include multiple clock signals. The clock signals can switch between clock high and clock low levels. For example, the clock signals can periodically switch between clock high and clock low levels.

[0075] The power controller 220 can output a first power signal PO1 and a second power signal PO2. The power controller 220 can output the first power signal PO1 in response to a common pixel power request signal EPUS. The power controller 220 can output the second power signal PO2 in response to a dedicated pixel power request signal EPRS. The first power signal PO1 and the second power signal PO2 can have active or inactive levels. The active first power signal PO1 can activate the common pixel compensator 230. The inactive first power signal PO1 can deactivate the common pixel compensator 230. The active second power signal PO2 can activate the dedicated pixel compensator 240, and the inactive second power signal PO2 can deactivate the dedicated pixel compensator 240.

[0076] The pixel compensator PC can generate compensation data signals to compensate for the input image data IMG. For example, the input image data IMG is compensated based on the levels of the display panel 100. For example, the levels of the display panel 100 may include information about the degradation of the display panel 100, characteristics of the manufacturing process, driving time, etc. The drive controller 200A can perform compensation operations for compensating the display panel 100. For example, the compensation operations may include calculation operations, compensation data loading operations, degradation data receiving operations, grayscale data loading operations, and grayscale data calculation operations. The calculation operation may represent an operation to convert the grayscale of the input image data IMG. The compensation data loading operation may represent an operation to receive data for grayscale conversion from non-volatile memory. The degradation data receiving operation may represent an operation to receive data about the degradation and driving time of the display panel 100 from a stress converter for converting grayscale based on the received data. The grayscale data loading operation may represent an operation to receive grayscale data corresponding to the characteristics of the manufacturing process of the display panel 100. The grayscale data calculation operation may represent a calculation operation for converting the grayscale of the input image data IMG based on the grayscale data. The pixel compensator PC can perform compensation operations based on the enable signal EN.

[0077] The pixel compensator PC may include a common pixel compensator 230 and a dedicated pixel compensator 240.

[0078] The common pixel compensator 230 can output a common pixel clock request signal RPUS and a common pixel power request signal EPUS based on the enable signal EN. The common pixel compensator 230 can receive a first clock signal group CLKG1 and a first power signal PO1. The common pixel compensator 230 can perform a compensation operation based on the first clock signal group CLKG1 and the first power signal PO1. The common pixel compensator 230 can perform a compensation operation for the first sub-pixel PU-SPX based on the first clock signal group CLKG1 and the first power signal PO1. The common pixel compensator 230 can output a common pixel data signal PUCS reflecting the compensation operation of the common pixel compensator 230. For example, the common pixel data signal PUCS can be referred to as the first sub-pixel compensation signal. The first sub-pixel PU-SPX can emit light based on the common pixel data signal PUCS.

[0079] In an embodiment, the common pixel compensator 230 may include a common pixel compensation signal output device 230-1 and a common pixel compensation data memory 230-2. The common pixel compensation signal output device 230-1 may receive a first power signal PO1, a first clock signal group CLKG1, and common pixel compensation data PUCDATA. The common pixel compensation data PUCDATA may include data for performing compensation operations. For example, the common pixel compensation data PUCDATA may include data for performing compensation operations on a first sub-pixel PU-SPX. For example, the common pixel compensation data PUCDATA may include multiple gamma voltage lookup tables corresponding to a preset brightness. The common pixel compensation signal output device 230-1 may include a hold trigger. The hold trigger can perform data hold. Even when no power is applied, the hold trigger can store the received data. The common pixel compensation data memory 230-2 may be a hold memory. Even when no power is applied, the hold memory can store data.

[0080] The dedicated pixel compensator 240 can output a dedicated pixel clock request signal RPRS and a dedicated pixel power request signal EPRS based on the enable signal EN. When the enable signal EN has an active level, the dedicated pixel compensator 240 can output the dedicated pixel clock request signal RPRS and the dedicated pixel power request signal EPRS. The dedicated pixel compensator 240 can receive a second clock signal group CLKG2 and a second power signal PO2. The dedicated pixel compensator 240 can perform a compensation operation based on the second clock signal group CLKG2 and the second power signal PO2. The dedicated pixel compensator 240 can perform a compensation operation for the second sub-pixel PR-SPX based on the second clock signal group CLKG2 and the second power signal PO2. The dedicated pixel compensator 240 can output a dedicated pixel data signal PRCS reflecting the compensation operation of the dedicated pixel compensator 240. For example, the dedicated pixel data signal PRCS can be referred to as the second sub-pixel compensation signal. The second sub-pixel PR-SPX can emit light based on the dedicated pixel data signal PRCS.

[0081] In this embodiment, the dedicated pixel compensator 240 may include a dedicated pixel compensation signal output device 240-1 and a dedicated pixel compensation data memory 240-2. The dedicated pixel compensation signal output device 240-1 may receive a second power signal PO2, a second clock signal group CLKG2, and dedicated pixel compensation data PRCDATA. The dedicated pixel compensation data PRCDATA may include data for performing compensation operations. For example, the dedicated pixel compensation data PRCDATA may include data for performing compensation operations on a second sub-pixel PR-SPX. For example, the dedicated pixel compensation data PRCDATA may include multiple gamma voltage lookup tables corresponding to a preset brightness. The dedicated pixel compensation signal output device 240-1 may include a hold trigger. The dedicated pixel compensation data memory 240-2 may be a hold memory.

[0082] In an embodiment, the common pixel compensator 230 and / or the dedicated pixel compensator 240 may include a hold trigger and a hold memory. The common pixel compensator 230 and / or the dedicated pixel compensator 240 may include a hold trigger and a hold memory, such that even if the power applied to the common pixel compensator 230 and / or the dedicated pixel compensator 240 is turned off or interrupted, the common pixel compensator 230 and / or the dedicated pixel compensator 240 can retain previously received data. Therefore, the calculation speed of the common pixel compensator 230 and / or the dedicated pixel compensator 240 can be improved. Therefore, the signal generation speed of the common pixel compensator 230 and / or the dedicated pixel compensator 240 can be improved.

[0083] In other words, if the common pixel compensator 230 and / or the dedicated pixel compensator 240 do not include a hold trigger, and if the common pixel compensator 230 and / or the dedicated pixel compensator 240 are powered off, the data stored in the common pixel compensator 230 and / or the dedicated pixel compensator 240 may be deleted. Therefore, if the common pixel compensator 230 and / or the dedicated pixel compensator 240 are powered on, data (e.g., calculated parameters and lookup tables) may need to be loaded from flash memory. Therefore, when operating the display device 1, the common pixel compensator 230 and / or the dedicated pixel compensator 240 may not perform power-on and power-off operations in real time. In contrast, since the common pixel compensator 230 and / or the dedicated pixel compensator 240 according to embodiments of the present invention may include a hold trigger and a hold memory, pre-received data can be retained even if the common pixel compensator 230 and / or the dedicated pixel compensator 240 are powered off. Therefore, the common pixel compensator 230 and / or the dedicated pixel compensator 240 can perform power-on and power-off operations in real time.

[0084] Figure 6 It is shown Figure 3 The timing diagram of the period during which the drive controller 200A is driven.

[0085] Reference Figures 1 to 6 The time periods during which the display panel 100 is driven may include a first time period TP1A, a second time period TP2A, and a third time period TP3A.

[0086] During the first time period TP1A, the vertical synchronization signal VSYNC can be at an active level. During the first time period TP1A, the vertical synchronization signal VSYNC can switch between an active and inactive level. When the vertical synchronization signal VSYNC is at an active level, a gate signal can be generated.

[0087] During the first time period TP1A, the data enable signal DE can be at an active level. When the data enable signal DE is at an active level, the data voltage VDATA can be applied to the display panel 100. For example, when the data enable signal DE is at an active level, the data voltage VDATA can be applied to the pixel PX.

[0088] In an embodiment of the present invention, a data voltage VDATA can be applied to the second sub-pixel PR-SPX based on a flag signal FG. The emission of the second sub-pixel PR-SPX can be controlled based on the flag signal FG. For example, when the flag signal FG has an active level, the data voltage VDATA can be applied to the second sub-pixel PR-SPX. For example, when the flag signal FG has an inactive level, the application of the data voltage VDATA to the second sub-pixel PR-SPX can be stopped. When the flag signal FG has an inactive level, the second sub-pixel PR-SPX can stop emitting light based on the flag signal FG.

[0089] During the first time period TP1A, the flag signal FG can have an inactive level. When the flag signal FG has an inactive level, the second sub-pixel PR-SPX may not receive the data voltage VDATA. For example, when the flag signal FG has an inactive level, the data voltage VDATA may not be applied to the second sub-pixel PR-SPX.

[0090] During the first time period TP1A, the enable signal EN can have an inactive level. Because the enable signal EN can have an inactive level during the first time period TP1A, the dedicated pixel compensator 240 can not receive the second clock signal group CLKG2 and the second power signal PO2. Because the enable signal EN can have an inactive level during the first time period TP1A, only the first sub-pixel PU-SPX can be driven. Therefore, the dedicated pixel compensator 240 can stop receiving the second clock signal group CLKG2 and the second power signal PO2. Because the enable signal EN can have an inactive level during the first time period TP1A, compensation operation for the second sub-pixel PR-SPX can be omitted. Furthermore, because the enable signal EN can have an inactive level during the first time period TP1A, the generation of the dedicated pixel data signal PRCS can be stopped.

[0091] In the second time period TP2A, the vertical synchronization signal VSYNC can have an active level. For example, in the second time period TP2A, the vertical synchronization signal VSYNC can switch between an active level and an inactive level. In the second time period TP2A, the data enable signal DE can have an active level. In the second time period TP2A, the flag signal FG can have an active level. When the flag signal FG has an active level, the data voltage VDATA can be applied to the second sub-pixel PR-SPX. In the second time period TP2A, the enable signal EN can have an active level. In the second time period TP2A, since the enable signal EN can have an active level, the dedicated pixel compensator 240 can receive the second clock signal group CLKG2 and the second power signal PO2. In the second time period TP2A, since the enable signal EN can have an active level, compensation operation for the second sub-pixel PR-SPX can be performed. In the second time period TP2A, since the enable signal EN can have an active level, the dedicated pixel data signal PRCS can be generated.

[0092] In the third time period TP3A, the vertical synchronization signal VSYNC can have an active level. For example, in the third time period TP3A, the vertical synchronization signal VSYNC can switch between an active and inactive level. In the third time period TP3A, the data enable signal DE can have an active level. In the third time period TP3A, the flag signal FG can have an inactive level. In the third time period TP3A, the enable signal EN can have an inactive level. In the third time period TP3A, since the enable signal EN can have an inactive level, the dedicated pixel compensator 240 can not receive the second clock signal group CLKG2 and the second power signal PO2. In the third time period TP3A, since the enable signal EN can have an inactive level, the compensation operation for the second sub-pixel PR-SPX can be omitted. In the third time period TP3A, since the enable signal EN can have an inactive level, the generation of the dedicated pixel data signal PRCS can be stopped.

[0093] In an embodiment of the present invention, the output of the second clock signal group CLKG2 and the output of the second power signal PO2 can be controlled based on the enable signal EN. Therefore, the power consumption of the display device 1 can be reduced.

[0094] Figure 7 It is shown that it includes Figure 6 The time series diagram of sub-time periods SP1A, SP2A and SP3A in the second time period TP2A. Figure 8 It is shown Figure 3 A block diagram of the operation of the drive controller 200A during the first sub-period SP1A. Figure 9 It is shown Figure 3A block diagram of the operation of the drive controller 200A during the second sub-period SP2A.

[0095] Reference Figures 1 to 9 The second time period TP2A may include the first sub-time period SP1A, the second sub-time period SP2A, and the third sub-time period SP3A.

[0096] In the first sub-period SP1A, the data enable signal DE can be at an active level. In the first sub-period SP1A, the flag signal FG can be at an inactive level. In the first sub-period SP1A, the first clock signal group CLKG1 can be switched. In the first sub-period SP1A, the second clock signal group CLKG2 can remain unchanged. For example, in the first sub-period SP1A, the second clock signal group CLKG2 can maintain a DC voltage, thus having an inactive level. For example, the first sub-period SP1A (the period during which the first clock signal group CLKG1 switches) can be referred to as the first active period.

[0097] During the first sub-period SP1A, the data enable signal DE can be active. Since the data enable signal DE can be active during the first sub-period SP1A, the common pixel clock request signal RPUS and the common pixel power request signal EPUS can also be active. Because the common pixel clock request signal RPUS and the common pixel power request signal EPUS can be active, the common pixel compensator 230 can receive the first clock signal group CLKG1 and the first power signal PO1. Therefore, the common pixel compensator 230 can perform compensation operations for the first sub-pixel PU-SPX. Furthermore, the common pixel compensator 230 can output the common pixel data signal PUCS.

[0098] During the first sub-period SP1A, the flag signal FG can have an inactive level. Because the flag signal FG can have an inactive level, the dedicated pixel clock request signal RPRS and the dedicated pixel power request signal EPRS can also have inactive levels. Since the dedicated pixel clock request signal RPRS and the dedicated pixel power request signal EPRS can have inactive levels, the dedicated pixel compensator 240 can stop receiving the second clock signal group CLKG2 and the second power signal PO2. For example, the dedicated pixel compensator 240 can choose not to receive the second clock signal group CLKG2 and the second power signal PO2. Therefore, the dedicated pixel compensator 240 can stop performing compensation operations for the second sub-pixel PR-SPX during the first sub-period SP1A. Furthermore, the dedicated pixel compensator 240 can stop outputting the dedicated pixel data signal PRCS during the first sub-period SP1A.

[0099] In the second sub-period SP2A, the data enable signal DE can have an active level. In the second sub-period SP2A, the flag signal FG can have an active level. In the second sub-period SP2A, the first clock signal group CLKG1 can stop switching. For example, in the second sub-period SP2A, the first clock signal group CLKG1 can maintain a DC voltage to have an inactive level. In the second sub-period SP2A, the second clock signal group CLKG2 can switch. For example, the period during which the second clock signal group CLKG2 switches in the second sub-period SP2A can be referred to as the second active period.

[0100] In the second sub-period SP2A, the flag signal FG can have an active level. Since the flag signal FG can have an active level, the common pixel clock request signal RPUS and the common pixel power request signal EPUS can have inactive levels. Because the common pixel clock request signal RPUS and the common pixel power request signal EPUS can have inactive levels, the common pixel compensator 230 can stop receiving the first clock signal group CLKG1 and the first power signal PO1. Therefore, the common pixel compensator 230 can stop performing compensation operations for the first sub-pixel PU-SPX during the second sub-period SP2A. Furthermore, the common pixel compensator 230 can stop outputting the common pixel data signal PUCS during the second sub-period SP2A.

[0101] In the second sub-period SP2A, the flag signal FG can have an active level. Since the flag signal FG can have an active level, the dedicated pixel clock request signal RPRS and the dedicated pixel power request signal EPRS can also have active levels. Because the dedicated pixel clock request signal RPRS and the dedicated pixel power request signal EPRS can have active levels, the dedicated pixel compensator 240 can receive the second clock signal group CLKG2 and the second power signal PO2. Therefore, the dedicated pixel compensator 240 can perform compensation operations for the second sub-pixel PR-SPX during the second sub-period SP2A. Furthermore, the dedicated pixel compensator 240 can output the dedicated pixel data signal PRCS during the second sub-period SP2A.

[0102] In the third sub-period SP3A, the data enable signal DE can be at an active level. In the third sub-period SP3A, the flag signal FG can be at an inactive level. In the third sub-period SP3A, the first clock signal group CLKG1 can be switched. For example, in the third sub-period SP3A, the second clock signal group CLKG2 can remain unchanged. For example, in the third sub-period SP3A, the second clock signal group CLKG2 can maintain a DC voltage to have an inactive level. In an embodiment, compensation operations can be performed for the first sub-pixel PU-SPX until the flag signal FG becomes active again.

[0103] In an embodiment of the present invention, during the first active period, the second clock signal group CLKG2 can maintain a DC voltage to have an inactive level. In contrast, during the second active period, the first clock signal group CLKG1 can maintain a DC voltage to have an inactive level. For example, the first and second active periods may not overlap. Because the first and second active periods may not overlap, the period during which compensation operations are performed for the first sub-pixel PU-SPX and the period during which compensation operations are performed for the second sub-pixel PR-SPX may not overlap. Therefore, the reliability of the compensation operation can be improved.

[0104] Figure 10 It is shown that it includes Figure 1 A block diagram of the frame period in which the display panel 100 in the display device 1 is driven.

[0105] Reference Figures 1 to 10 The display panel 100 can be driven at a variable frequency. A first frame period FR1 may include an active period AC and a first blank period BL1. During the active period AC, a data voltage VDATA can be applied to the pixel PX. For example, the start of the active period AC may be synchronized with the vertical sync signal VSYNC. During the first blank period BL1, the application of the data voltage VDATA to the pixel PX can be stopped. A second frame period FR2 may include an active period AC and a second blank period BL2. During the second blank period BL2, the application of the data voltage VDATA to the pixel PX can be stopped. The lengths of the first blank period BL1 and the second blank period BL2 can be different. For example, when the display panel 100 is driven at a first driving frequency in the first frame period FR1 and at a second driving frequency higher than the first driving frequency in the second frame period FR2, the length of the first blank period BL1 may be longer than the length of the second blank period BL2. For example, the length of the second blank period BL2 can also be longer than the length of the first blank period BL1, and in the second blank period BL2, each of the first clock signal group CLKG1 and the second clock signal group CLKG2 can maintain a DC voltage to have an inactive level.

[0106] Figure 11 It shows when Figure 1 When the display panel 100 is driven at a variable frequency Figure 3 The timing diagram of the period during which the drive controller 200A is driven. Figure 12 It is shown Figure 3 The drive controller 200A in Figure 11 A flowchart of the operations during the second TP2B period.

[0107] Reference Figures 1 to 12 The time periods driven by the display panel 100 at a variable frequency may include a first time period TP1B, a second time period TP2B, a third time period TP3B, and a fourth time period TP4B.

[0108] In the first time period TP1B, the vertical synchronization signal VSYNC can be active. In the first time period TP1B, the enable signal EN can be active. In the first time period TP1B, the data enable signal DE can be active. In the first time period TP1B, the flag signal FG can be active.

[0109] In the first time period TP1B, since the enable signal EN, the data enable signal DE, and the flag signal FG can have an active level, the common pixel data signal PUCS and the dedicated pixel data signal PRCS can be generated.

[0110] In the second time period TP2B, the length of the blank period can be increased. In the second time period TP2B, the enable signal EN can have an active level. In the second time period TP2B, the data enable signal DE can remain at an inactive level. In the second time period TP2B, the flag signal FG can remain at an inactive level. The second time period TP2B can correspond to the first blank period BL1 and / or the second blank period BL2.

[0111] In the second time period TP2B, since the length of the blank time period can be increased and the data enable signal DE and the flag signal FG can have an inactive level, the generation of the common pixel data signal PUCS and the dedicated pixel data signal PRCS can be stopped.

[0112] In the third time period TP3B, the vertical synchronization signal VSYNC can be active. In the third time period TP3B, the enable signal EN can be active. In the third time period TP3B, the data enable signal DE can be active. In the third time period TP3B, the flag signal FG can be active.

[0113] In the third time period TP3B, since the enable signal EN, the data enable signal DE, and the flag signal FG can have an active level, a common pixel data signal PUCS and a dedicated pixel data signal PRCS can be generated.

[0114] In the fourth time period TP4B, the vertical synchronization signal VSYNC can be active. In the fourth time period TP4B, the enable signal EN can be inactive. In the fourth time period TP4B, the data enable signal DE can be active. In the fourth time period TP4B, the flag signal FG can be inactive.

[0115] In the fourth time period TP4B, since the enable signal EN and the flag signal FG can have inactive levels, the generation of the dedicated pixel data signal PRCS can be stopped. In the fourth time period TP4B, since the data enable signal DE can have an active level, the common pixel data signal PUCS can be generated.

[0116] In embodiments of the present invention, the generation of the common pixel data signal PUCS and the dedicated pixel data signal PRCS can be controlled. Furthermore, when the display panel 100 is driven at a variable frequency, the generation of the common pixel data signal PUCS and the dedicated pixel data signal PRCS can be controlled based on low-frequency periods (e.g., the length of blank periods). For example, the output of the first clock signal group CLKG1 and the output of the second clock signal group CLKG2 can be controlled in response to the vertical synchronization signal VSYNC. Therefore, the power consumption of the display device 1 can be further reduced.

[0117] Figure 13 It is shown that it includes Figure 1 A block diagram of another example of the drive controller 200 in the display device 1 (represented by 200B). Figure 14 It is shown Figure 13 The timing diagram of the period during which the drive controller 200B is driven.

[0118] Reference Figure 1 , Figure 2 , Figure 13 and Figure 14 The drive controller 200B may include a clock signal output unit 210B, a power controller 220B, and an integrated pixel compensator 230B.

[0119] The clock signal output unit 210B can output the integrated clock signal group TCLKG in response to the integrated clock request signal RTS.

[0120] The power controller 220B can output an integrated power signal TPO in response to the integrated power request signal EPS.

[0121] The integrated pixel compensator 230B can perform compensation operations for the first sub-pixel PU-SPX based on the input control signal CONT, the integrated clock signal group TCLKG, and the integrated power signal TPO. Furthermore, the integrated pixel compensator 230B can perform compensation operations for the second sub-pixel PR-SPX based on the integrated clock signal group TCLKG and the integrated power signal TPO. The integrated pixel compensator 230B can output a common pixel data signal PUCS and a dedicated pixel data signal PRCS.

[0122] The time periods during which the drive controller 200B is driven may include the first time period TP1C, the second time period TP2C, and the third time period TP3C.

[0123] In the first time period TP1C, the vertical synchronization signal VSYNC can be active, the enable signal EN can be inactive, the data enable signal DE can be active, and the flag signal FG can be inactive. Therefore, the common pixel data signal PUCS can be generated in the first time period TP1C. However, the dedicated pixel data signal PRCS may not be generated in the first time period TP1C.

[0124] In the second time period TP2C, the vertical synchronization signal VSYNC, the enable signal EN, the data enable signal DE, and the flag signal FG can all be active. The second time period TP2C can include a first sub-time period SP1C and a second sub-time period SP2C. In the first sub-time period SP1C, the data enable signal DE can be active, and the flag signal FG can be inactive. Therefore, in the first sub-time period SP1C, the common pixel data signal PUCS can be generated, but the dedicated pixel data signal PRCS may not be generated. In the second sub-time period SP2C, the data enable signal DE and the flag signal FG can both be active. Therefore, in the second sub-time period SP2C, both the common pixel data signal PUCS and the dedicated pixel data signal PRCS can be generated. Through the first sub-time period SP1C and the second sub-time period SP2C, the first sub-pixel PU-SPX and the second sub-pixel PR-SPX can be driven in a time-division manner.

[0125] In the third time period TP3C, the vertical synchronization signal VSYNC can be active, the enable signal EN can be inactive, the data enable signal DE can be active, and the flag signal FG can be inactive. Therefore, the common pixel data signal PUCS can be generated. However, in the third time period TP3C, the generation of the dedicated pixel data signal PRCS can be stopped.

[0126] In embodiments of the present invention, a common pixel data signal PUCS and a dedicated pixel data signal PRCS can be generated based on an integrated clock signal group TCLKG and an integrated power signal TPO. Therefore, the number of clock signals and power signals used to generate the common pixel data signal PUCS and the dedicated pixel data signal PRCS can be reduced. Consequently, the power consumption of the display device 1 can be reduced.

[0127] Figure 15 It is shown that it includes Figure 1 A diagram of the display panel 100 in the display device 1.

[0128] Reference Figures 1 to 15 The display panel 100 may include a first display area AA1 and a second display area AA2.

[0129] The first display area AA1 may include a first sub-pixel PU-SPX. For example, the first display area AA1 may not include a second sub-pixel PR-SPX. The second display area AA2 may include both the first sub-pixel PU-SPX and the second sub-pixel PR-SPX. However, the inventive concept is not limited to the number of display areas included in the display panel 100. For example, the display panel 100 may also include a third display area. The third display area may include the first sub-pixel PU-SPX, but may not include the second sub-pixel PR-SPX.

[0130] The display panel 100 according to an embodiment of the present invention can be driven in a first mode or a second mode.

[0131] When the display panel 100 is driven in the first mode, the first sub-pixel PU-SPX of the first display area AA1 and the first sub-pixel PU-SPX of the second display area AA2 can emit light. In the first mode, the second sub-pixel PR-SPX of the second display area AA2 can be de-driven and can not emit light. When the display panel 100 is driven in the first mode, the second clock signal group CLKG2 can maintain a DC voltage to have an inactive level. When the display panel 100 is driven in the first mode, the second power signal PO2 can have an inactive level.

[0132] When the display panel 100 is driven in the second mode, not only does the first sub-pixel PU-SPX of the first display area AA1 emit light, but the second sub-pixel PR-SPX of the second display area AA2 can also emit light. In the second mode, the first sub-pixel PU-SPX of the second display area AA2 may not emit light. When the display panel 100 is driven in the second mode, the second clock signal group CLKG2 can be switched. When the display panel 100 is driven in the second mode, the second power signal PO2 may have an activation level.

[0133] Figure 16 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the concept of the present invention. Figure 17 It is shown that Figure 16 The diagram shows an example of an electronic device 1000 implemented as an automotive electronic device.

[0134] Reference Figure 16 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be... Figure 1 The display device 1. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0135] In an embodiment, such as Figure 17 As shown, the electronic device 1000 according to the embodiment can be implemented as an automotive electronic device.

[0136] Reference Figures 1 to 17 The electronic device 1000 may include a first display panel 100-1, a second display panel 100-2, and a third display panel 100-3. The first display panel 100-1 may include a first sub-pixel PU-SPX. For example, the first display panel 100-1 may include only the first sub-pixel PU-SPX and may not include the second sub-pixel PR-SPX. The second display panel 100-2 may include the first sub-pixel PU-SPX. For example, the second display panel 100-2 may include only the first sub-pixel PU-SPX and may not include the second sub-pixel PR-SPX. The third display panel 100-3 may include both the first sub-pixel PU-SPX and the second sub-pixel PR-SPX.

[0137] However, the electronic device 1000 according to the embodiment is not limited thereto. For example, the electronic device 1000 may be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0138] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be connected to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be connected to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0139] Processor 1010 can output input image data IMG and input control signal CONT to Figure 1 The drive controller 200.

[0140] The memory device 1020 can store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.).

[0141] Storage device 1030 may include a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. I / O device 1040 may include input devices (such as a keyboard, keypad, mouse, touchpad, touchscreen, etc.) and output devices (such as a printer, speaker, etc.). In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 provides power for the operation of electronic device 1000. Display device 1060 may be connected to other components via a bus or other communication link.

[0142] although Figure 17 An embodiment of an electronic device implemented as an automotive electronic device is shown, but the inventive concept is not limited thereto. The electronic device according to the inventive concept can be a television, monitor, laptop computer, or tablet computer. Furthermore, the electronic device can be an automobile.

[0143] The display device according to embodiments of the present invention can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, MP3 players, etc.

[0144] The foregoing is illustrative of the inventive concept and is not to be construed as limiting it. Although several embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications may be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, the device plus function clause is intended to cover the structures described herein that perform the functions, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims and their equivalents included therein.

Claims

1. A display device, the display device comprising: The display panel includes multiple pixels; as well as A display panel driver is configured to drive the display panel. The plurality of pixels includes a first sub-pixel having a first viewpoint and a second sub-pixel having a second viewpoint different from the first viewpoint. Wherein, the first sub-pixel emits light based on a first sub-pixel compensation signal, and the second sub-pixel emits light based on a second sub-pixel compensation signal. Wherein, the first sub-pixel compensation signal is generated based on the first clock signal group, and the second sub-pixel compensation signal is generated based on the second clock signal group, and When the first sub-pixel emits light, the second clock signal group remains at an inactive level.

2. The display device according to claim 1, wherein, The display panel driver includes: A clock signal output device is configured to output the first clock signal group and the second clock signal group; A pixel compensator is configured to output a first sub-pixel compensation signal and a second sub-pixel compensation signal based on an enable signal; and A power controller is configured to apply a power signal to the pixel compensator.

3. The display device according to claim 2, wherein, When the enable signal has an inactive level, the pixel compensator outputs the first sub-pixel compensation signal and does not output the second sub-pixel compensation signal.

4. The display device according to claim 3, wherein, When the enable signal has the inactive level, the first clock signal group switches, and the second clock signal group maintains the inactive level.

5. The display device according to claim 3, wherein, The pixel compensator includes: The first pixel compensator is configured to output the first sub-pixel compensation signal; and The second pixel compensator is configured to output the second sub-pixel compensation signal. The power signal includes a first power signal applied to the first pixel compensator and a second power signal applied to the second pixel compensator. When the enable signal has the inactive level, the first power signal is applied to the first pixel compensator, and the second power signal is not applied to the second pixel compensator.

6. The display device according to claim 3, wherein, When the enable signal has an active level, the first clock signal group switches, and the second clock signal group switches.

7. The display device according to claim 3, wherein, The pixel compensator includes: The first pixel compensator is configured to output the first sub-pixel compensation signal; and The second pixel compensator is configured to output the second sub-pixel compensation signal. The power signal includes a first power signal applied to the first pixel compensator and a second power signal applied to the second pixel compensator. When the enable signal has an active level, the first power signal is applied to the first pixel compensator, and the second power signal is applied to the second pixel compensator.

8. The display device according to claim 2, wherein, The first activation period of the first clock signal group switching does not overlap with the second activation period of the second clock signal group switching.

9. The display device according to claim 8, wherein, During the first active period, the second clock signal group maintains the inactive level.

10. The display device according to claim 2, wherein, The pixel compensator includes: The first pixel compensator is configured to output the first sub-pixel compensation signal; and The second pixel compensator is configured to output the second sub-pixel compensation signal. The second pixel compensator includes: The second pixel compensation signal outputter is configured to output the second sub-pixel compensation signal; and The second pixel compensation data memory is configured to apply second pixel compensation data to the second pixel compensation signal output device, and The second pixel compensation signal output device includes a hold trigger that performs data holding.

11. The display device according to claim 1, wherein, The frame period for which the display panel is driven includes a first frame period and a second frame period. The first frame period includes a first active period and a first blank period. The second frame period includes a second active period and a second blank period that is longer than the first blank period. During the second blank period, the first clock signal group and the second clock signal group maintain the inactive level.

12. A display device, the display device comprising: The display panel includes a first display area and a second display area; as well as A display panel driver is configured to drive the display panel. The first display area includes a first sub-pixel having a first viewing angle. The second display area includes the first sub-pixel and a second sub-pixel having a second viewpoint different from the first viewpoint. Wherein, the first sub-pixel emits light based on a first data signal, and the second sub-pixel emits light based on a second data signal. The first data signal is generated based on the first sub-pixel compensation signal, and the second data signal is generated based on the second sub-pixel compensation signal. Wherein, the first sub-pixel compensation signal is generated based on the first clock signal group, and the second sub-pixel compensation signal is generated based on the second clock signal group, and Specifically, when the first sub-pixel of the second display area emits light, the second clock signal group remains at an inactive level.

13. The display device according to claim 12, wherein, The display panel driver includes: A clock signal output device is configured to output the first clock signal group and the second clock signal group; A pixel compensator is configured to output a first sub-pixel compensation signal and a second sub-pixel compensation signal based on an enable signal; and A power controller is configured to apply a power signal to the pixel compensator.

14. The display device according to claim 13, wherein, When the enable signal has an inactive level, the first clock signal group switches, and the second clock signal group maintains the inactive level.

15. The display device according to claim 13, wherein, When the enable signal has an active level, the first clock signal group switches, and the second clock signal group switches.

16. The display device according to claim 12, wherein, The display panel is driven in either a first mode or a second mode. In the first mode, the first sub-pixel of the second display area emits light, and the second sub-pixel of the second display area does not emit light. In the second mode, the first sub-pixel of the second display area does not emit light, and the second sub-pixel of the second display area emits light.

17. The display device according to claim 16, wherein, When the display panel is driven in the first mode, the second clock signal group maintains the inactive level.

18. The display device according to claim 16, wherein, When the display panel is driven in the first mode, the second power signal applied to the second sub-pixel compensator that outputs the second sub-pixel compensation signal has an inactive level.

19. An electronic device, the electronic device comprising: The processor is configured to output input image data and input control signals; The display panel includes multiple pixels; as well as The display panel driver is configured to drive the display panel based on the input image data and the input control signal. The plurality of pixels includes a first sub-pixel having a first viewpoint and a second sub-pixel having a second viewpoint different from the first viewpoint. Wherein, the first sub-pixel emits light based on a first sub-pixel compensation signal, and the second sub-pixel emits light based on a second sub-pixel compensation signal. Wherein, the first sub-pixel compensation signal is generated based on the first clock signal group, and the second sub-pixel compensation signal is generated based on the second clock signal group, and When the first sub-pixel emits light, the second clock signal group remains at an inactive level.

20. The electronic device according to claim 19, wherein, The display panel includes a first display area and a second display area. Wherein, the first display area includes the first sub-pixel, and the second display area includes both the first sub-pixel and the second sub-pixel. Specifically, when the first sub-pixel of the second display area emits light, the second clock signal group maintains the inactive level.

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