Display device and driving method thereof

Abstract

The present disclosure provides a display device and a driving method thereof. The display device includes a first driver disposed in a plurality of peripheral portions and driving a plurality of light emitting devices in the plurality of peripheral portions, a second driver disposed in a central region and driving a plurality of light emitting devices in the central region, wherein a number of the light emitting devices driven by the first driver is different from a number of the light emitting devices driven by the second driver.

Description

Technical Field

[0001] This disclosure generally relates to apparatuses and methods, and particularly to, for example, but not limited to, display devices and methods for driving the same. Background Technology

[0002] Display devices are used in a variety of electronic devices such as TVs, mobile phones, laptops, and tablets. Display devices include self-emissive organic light-emitting displays (OLEDs) and liquid crystal displays (LCDs) that require a separate light source.

[0003] Recently, display devices incorporating light-emitting diodes (LEDs) have garnered attention as next-generation display devices. LEDs are made from inorganic materials rather than organic materials. Therefore, compared to liquid crystal displays or organic light-emitting displays, LED-based display devices offer faster turn-on speeds, superior luminous efficiency, and the ability to display high-brightness images.

[0004] The descriptions provided in the Background section should not be considered prior art simply because they are mentioned in or associated with that section. The discussion in the Background section may include information describing one or more aspects of the subject matter art, and the descriptions in that section do not limit this disclosure. Summary of the Invention

[0005] According to one aspect of this disclosure, a display device is provided, the display device comprising: a substrate divided into a unit driving region, the unit driving region including a plurality of light-emitting devices and including a plurality of peripheral portions and a central region different from the plurality of peripheral portions; a first driver disposed in the plurality of peripheral portions and driving the plurality of light-emitting devices in the plurality of peripheral portions; a second driver disposed in the central region and driving the plurality of light-emitting devices in the central region; and a controller driving the first driver and the second driver, wherein the number of light-emitting devices driven by the first driver is different from the number of light-emitting devices driven by the second driver.

[0006] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the claimed inventive concept.

[0007] Other systems, methods, features, and advantages will be or will become apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional systems, methods, features, and advantages are intended to be included within the scope of this specification and disclosure, and are protected by the appended claims. Nothing in this section should be construed as limiting those claims. Further aspects and advantages are discussed below in conjunction with embodiments of this disclosure. Attached Figure Description

[0008] The accompanying drawings, which are included to provide a further understanding of this disclosure and are incorporated in and form part of this application, illustrate implementations of this disclosure and, together with the specification, serve to explain the principles of this disclosure. In the drawings:

[0009] Figure 1 This is a diagram illustrating a display device according to an implementation of the present disclosure.

[0010] Figure 2 This is a plan view of a display device according to an implementation of the present disclosure.

[0011] Figure 3 It is a plan view of the display panel according to the implementation of this disclosure.

[0012] Figure 4 It is a plan view of the unit driving area of ​​the display panel according to the implementation of this disclosure.

[0013] Figure 5 This is a diagram that schematically illustrates the structure of subpixels of a display panel according to an implementation of the present disclosure.

[0014] Figure 6 An example is shown of the driving timing diagram of n row lines and one column line included in the first sub-driving area of ​​a display panel according to an implementation of the present disclosure.

[0015] Figure 7 It is a plan view of the display panel according to the implementation of this disclosure.

[0016] Figure 8 This is a detailed cross-sectional view of the display panel according to the implementation of this disclosure, and is along... Figure 7 The cross-sectional view taken from line AB.

[0017] Figure 9 This is a diagram illustrating a substrate including multiple peripheral portions in a display device according to an implementation of the present disclosure.

[0018] Figure 10 This is a diagram illustrating the connection relationship between a driver and a sub-pixel disposed in a unit driving region in a display device according to an implementation of the present disclosure.

[0019] Figure 11 This is a diagram illustrating the driving timing of a driver located at the peripheral portion of a display device according to an implementation of this disclosure.

[0020] Figure 12 This is a diagram illustrating the operation of a controller in a display device according to an implementation of the present disclosure.

[0021] Figure 13This is a diagram illustrating data input for each region in a display device according to an implementation of the present disclosure.

[0022] Throughout the accompanying drawings and detailed embodiments, unless otherwise stated, the same reference numerals should be understood to refer to the same elements, features, and structures. For clarity, illustrative purposes, the relative dimensions and depictions of these elements may be exaggerated. Detailed Implementation

[0023] Implementations of this disclosure relate to display devices, and more specifically, to a driving architecture and method for display devices that include a non-rectangular display area (e.g., rounded corners) in the periphery. Because the display area of ​​the display device deviates from a standard rectangular shape, the number and arrangement of light-emitting devices may become uneven. This can pose challenges to the peripheral portion of the display, where driving circuitry may be connected to column lines that do not have a complete set of corresponding light-emitting devices, potentially leading to voltage float artifacts and unintended emission.

[0024] Therefore, the implementations disclosed herein can provide a display device with an improved driving architecture to address these challenges. In some implementations, the display substrate is conceptually divided into a central region and multiple peripheral portions, with a first driver for the peripheral portions and a second driver for the central region. The controller is configured to provide modified image data to the first driver, wherein the modified data includes black image data for driving instances corresponding to the locations of missing light-emitting devices in the peripheral portions. The application of this black image data prevents corresponding column lines from floating to undesirable voltages. This directional driving method allows for seamless image rendering on non-rectangular displays without artifacts in peripheral portions (e.g., corners). Furthermore, by preventing accidental light emission, image quality and contrast can be improved, which can contribute to a better overall user experience and potentially reduced power consumption.

[0025] The advantages and features of this specification, as well as the methods for achieving these advantages and features, will become clear from the accompanying drawings and the detailed description of the implementations. However, this specification is not limited to the implementations described below and can be implemented in different forms. These implementations are provided only to fully disclose this disclosure and to fully convey the scope of this disclosure to those skilled in the art, and this specification is defined by the disclosed claims.

[0026] Additional advantages and features of this disclosure will be set forth in part in the following description, and in part will become apparent to those skilled in the art upon reading the following, or may be learned by practice of this disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the written description, claims, and drawings.

[0027] Furthermore, this disclosure is made in view of the above-mentioned problems, and one aspect of this disclosure is to provide a display device that, since the driver is not located at the periphery (e.g., at the corner), the display device is able to reduce the size of the periphery.

[0028] Furthermore, this disclosure is made in view of the above-mentioned problems, and one aspect of this disclosure is to provide a low-power display device because the driver is not located at the periphery (e.g., at the corner).

[0029] Implementations of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. The process of the described steps and / or operations is merely illustrative; however, the order of the steps and / or operations is not limited to that described herein and may be modified in accordance with manners known in the art, unless the steps and / or operations must occur in a specific order. The names of the corresponding elements used in the following explanation may be chosen solely for convenience in writing the specification and may therefore differ from the names used in actual products.

[0030] The advantages and features of this disclosure and its implementations will be illustrated by the following description of the implementations with reference to the accompanying drawings. However, this disclosure may be embodied in different forms and should not be construed as limited to the implementations set forth herein. Rather, these implementations are provided so that this disclosure will be thorough and complete, and will fully communicate the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0031] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings to describe implementations of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. Throughout the specification, the same reference numerals refer to the same elements. In the following description, detailed descriptions identifying relevant known functions or configurations will be omitted or briefly provided where such descriptions would unnecessarily obscure the focus of this disclosure. Where the terms "comprising," "having," and "including" are used as described in this disclosure, an additional part may be added unless "only" is used. Unless otherwise stated, singular terms may include plural forms.

[0032] When interpreting components, even if the error range is not explicitly described separately, it is interpreted as including the error range.

[0033] When describing positional relationships, such as "above," "over," "below," and "next to," one or more parts may be positioned between two other parts unless "exactly" or "directly" is used. Terms such as "below," "lower," "above," and "upper" are used herein to describe relationships between elements shown in the figures. It should be understood that these terms are spatially relative and based on the orientation depicted in the figures.

[0034] The description of time relationships can include describing time priority relationships as "after", "immediately following", or "before", and can be discontinuous unless "immediately" or "directly" is used.

[0035] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Therefore, the first component mentioned below, within the technical concept of this disclosure, may also be the second component.

[0036] It should be understood that although the terms “first,” “second,” “A,” “B,” “(a),” and “(b)” may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0037] If a component is described as “connected,” “linked,” “attached,” or “attached” to another component, then that component may be directly connected, linked, connected, or attached to that other component. However, it should be understood that other components may be inserted between each component that may be indirectly connected, linked, connected, or attached without any specific description.

[0038] It should be understood that if a component or layer is described as "in contact" or "overlapping" with another component or layer, then that component or layer may be in direct contact or overlap with the other component or layer. However, unless otherwise explicitly described, other components may be inserted between each component that may be indirect contact or overlap.

[0039] The term “at least one” should be understood to include any and all combinations of one or more of the associated listed items. For example, “at least one of the first element, the second element, and the third element” means a combination of all three listed elements, a combination of any two of the three elements, and each individual element (the first element, the second element, or the third element).

[0040] The terms “first direction,” “second direction,” “third direction,” “X-axis direction,” “Y-axis direction,” and “Z-axis direction” should not be understood merely as geometrically perpendicular to each other, but can be interpreted as indicating a wider range of directions within which the configuration of this disclosure can be functionally effective.

[0041] The features of each of the various implementations in this specification may be partially or wholly connected or combined with each other, and various interconnections and drives are technically possible. Each of the implementations may be implemented independently of each other or together in a related relationship.

[0042] The implementation of this disclosure will be described in detail below with reference to the accompanying drawings.

[0043] Figure 1 The diagram illustrates a display device according to an implementation of the present disclosure, and Figure 2 This is a plan view of a display device according to an implementation of the present disclosure.

[0044] Reference Figure 1 The display device 100 according to the implementation of the present disclosure may include a display panel 110, a cover member 118 disposed on the display panel 110, a flexible printed circuit 102 connected to the display panel 110, and a printed circuit board 104 connected to the flexible printed circuit 102.

[0045] The display device 100 according to the implementation of the present disclosure may further include a support substrate 106 disposed below the display panel 110 to support the lower part of the display panel 110, a polarizing layer 114 disposed on the display panel 110, a first adhesive layer 112 disposed between the display panel 110 and the polarizing layer 114, and a second adhesive layer 116 disposed between the polarizing layer 114 and the cover member 118.

[0046] The display panel 110 may include a substrate 210. The substrate 210 may have components, such as multiple metal layers and multiple insulating material layers, formed therein. The substrate 210 may be made of an insulating material. For example, the substrate 210 may be made of glass or resin. Alternatively, the substrate 210 may be made of a flexible material. For example, the substrate 210 may be made of a flexible plastic material, such as polyimide (PI). However, the implementations of this disclosure are not limited to these.

[0047] Display panel 110 can display information, images, and / or screens provided to the user. For example, display panel 110 may include a display area DA and a non-display area NDA. For example, substrate 210 may include a display area DA and a non-display area NDA. The display area DA and the non-display area NDA are not limited to substrate 210, but can be described throughout the display device 100.

[0048] The display area DA can be an area in which an image is displayed. The display area DA can include multiple pixels P. Each of the multiple pixels P can include multiple sub-pixels. Each of the multiple sub-pixels can be provided with at least one light-emitting device. The light-emitting device can be configured differently depending on the type of the display device 100. For example, when the display device 100 is an inorganic light-emitting display device, the light-emitting device can be an inorganic light-emitting device, and can be a light-emitting diode (LED), a micro-LED, or a miniature light-emitting diode (MLED), but the implementation of this disclosure is not limited to this.

[0049] The non-display area NDA can be an area in which an image is not displayed. Various wiring and circuits for driving multiple pixels P in the display area DA can be set in the non-display area NDA. For example, various driving circuits and various wirings can be set in the non-display area NDA, and pad portions 211 connected to integrated circuits and printed circuits can be set in the non-display area NDA, but the implementation of this disclosure is not limited to this.

[0050] For example, the driving circuit may include a data driving circuit and / or a gating driving circuit, but the implementation of this disclosure is not limited thereto. Wiring on the substrate 210 may be provided with control signals supplied for controlling the driving circuit. For example, the control signals may include various timing signals, including clock signals, input data enable signals, and synchronization signals, but the implementation of this disclosure is not limited thereto. The control signals may be supplied to the substrate 210 from the outside via the pad portion 211. For example, circuit components such as the flexible printed circuit 102 and the printed circuit board 104 may be connected to the pad portion 211.

[0051] According to this disclosure, the non-display area NDA may include a first non-display area NDA1, a curved area BA, and a second non-display area NDA2. For example, the first non-display area NDA1 may be a region surrounding at least a portion of the display area DA. The curved area BA may be a region extending from at least one of the plurality of edges of the first non-display area NDA1, and may be a flexible region. The second non-display area NDA2 is a region extending from the curved area BA, and may include a pad portion 211. For example, the curved area BA may be in a curved state, while the remaining area of ​​the substrate 210 other than the curved area BA may be in a flat state. In this case, when the curved area BA is bent, the second non-display area NDA2 may be located on the rear surface of the display area DA. However, the implementation of this disclosure is not limited to this.

[0052] The display area DA of the substrate 210 or the display device 100 can be configured in various shapes according to the design of the display device 100. For example, the display area DA can be configured in a rectangular shape with four rounded corners, but the implementation of this disclosure is not limited to this. As another example, the display area DA can be configured in a rectangular shape or a circular shape with four corners, but the implementation of this disclosure is not limited to this.

[0053] According to the implementation of this disclosure, the width of the second non-display area NDA2, where the pad portion 211 is provided, can be greater than the width of the curved area BA. Additionally, the width of the display area DA can be greater than the width of the curved area BA. Although the width of the curved area BA is shown as being smaller than the width of other areas of the substrate 210, the shape of the substrate 210 including the curved area BA is exemplary, and the implementation of this disclosure is not limited thereto.

[0054] Reference Figure 1 and Figure 2 The flexible printed circuit 102 and the printed circuit board 104 can be disposed below the display panel 110. The flexible printed circuit 102 and the printed circuit board 104 can be disposed at one edge of the display panel 110, but the implementation of this disclosure is not limited to this. One side of the flexible printed circuit 102 can be connected to the display panel 110, and the other side of the flexible printed circuit 102 can be connected to the printed circuit board 104, but the implementation of this disclosure is not limited to this. The flexible printed circuit 102 can be a flexible film, but the implementation of this disclosure is not limited to this.

[0055] The pad portion 211, located in the second non-display area NDA2, includes multiple pads and a driving assembly including at least one flexible printed circuit 102 and a printed circuit board 104 that can be attached or joined. The multiple pads included in the pad portion 211 are electrically connected to at least one flexible printed circuit 102 and can transmit various signals (or power) from the printed circuit board 104 and at least one flexible printed circuit 102 to a driving circuit located in the display area DA (e.g., Figure 3 The driver DRV).

[0056] The flexible printed circuit 102 can be a film on which various components are disposed. For example, a first circuit component 230 (e.g., a gating driver integrated circuit and / or a data driver integrated circuit) can be disposed in one or more flexible printed circuits 102, but the implementation of this disclosure is not limited thereto. The first circuit component 230 can be a component that processes data and drive signals to display an image. Depending on the mounting method, the first circuit component 230 can be disposed by methods such as chip-on-glass (COG), chip-on-film (COF), or tape-on-carrier (TCP), but the implementation of this disclosure is not limited thereto. The flexible printed circuit 102 can be attached to or bonded to multiple pads via a conductive adhesive layer, but the implementation of this disclosure is not limited thereto.

[0057] The printed circuit board 104 may be a component electrically connected to the flexible printed circuit 102 and supplying signals to the first circuit assembly 230. The printed circuit board 104 may be disposed on one side of the flexible printed circuit 102 and may be electrically connected to the flexible printed circuit 102. Various components for supplying various signals to the first circuit assembly 230 may be disposed on the printed circuit board 104. For example, various second circuit assemblies 240 (e.g., timing controllers, power supply units, memory, processors, etc.) may be disposed on the printed circuit board 104. For example, the second circuit assembly 240 disposed on the printed circuit board 104 may include a timing controller and / or a power management integrated circuit (PMIC), but implementations of this disclosure are not limited thereto.

[0058] The printed circuit board 104 may include at least one hole, but the implementations of this disclosure are not limited thereto. An internal component for sensing ambient light or temperature, which can be provided to multiple sensors, may be disposed in the area corresponding to the at least one hole. For example, the internal component may include an ambient light sensor (ALS) or a temperature sensor, but the implementations of this disclosure are not limited thereto. For example, the hole may be a transmission hole, etc., but the implementations of this disclosure are not limited thereto.

[0059] Reference Figure 1 The polarizing layer 114 can be disposed on the display panel 110 and can prevent or reduce the light generated from external light sources from entering the display panel 110 and affecting the light-emitting device.

[0060] The cover member 118 can be disposed on the polarizing layer 114 and can be a member used to protect the display panel 110.

[0061] The second adhesive layer 116 can be disposed between the polarizing layer 114 and the cover member 118. The second adhesive layer 116 can attach the cover member 118 to the display panel 110 or the polarizing layer 114.

[0062] The first adhesive layer 112 can be disposed between the display panel 110 and the polarizing layer 114. The first adhesive layer 112 can attach the polarizing layer 114 to the display panel 110. The first adhesive layer 112 can be omitted.

[0063] Each of the first adhesive layer 112 and the second adhesive layer 116 may include an optically transparent adhesive (OCA), an optically transparent resin (OCR), or a pressure-sensitive adhesive (PSA), but the implementation of this disclosure is not limited thereto.

[0064] The support substrate 106 can be disposed between the display panel 110 and the printed circuit board 104 to enhance the rigidity of the display panel 110. The support substrate 106 can be a back plate, but the implementation of this disclosure is not limited to this.

[0065] Figure 3 It is a plan view of the display panel according to the implementation of this disclosure, and Figure 4 It is a plan view of the unit driving area of ​​the display panel according to the implementation of this disclosure.

[0066] Reference Figure 3 The display area DA of the display panel 110 according to the implementation of this disclosure may include multiple unit driving areas UDA.

[0067] Reference Figure 3 The display panel 110 according to the implementation of this disclosure may include a driver DRV disposed in each of a plurality of unit driving regions UDA. For example, the driver DRV may be a driver chip fabricated on a semiconductor substrate using a metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication process, but the implementation of this disclosure is not limited thereto.

[0068] Reference Figure 3 Each unit drive region in a multi-unit drive region UDA can be a drive region driven by a single driver DRV. In other words, multiple unit drive regions UDA can be independent drive regions driven by different drivers DRVs.

[0069] Reference Figure 3 According to an implementation of the present disclosure, the display panel 110 may include a substrate 210, which includes a display area DA and a plurality of pixels P arranged in a matrix in the display area DA.

[0070] Multiple pixels P can be disposed in each of multiple unit driving regions UDA. Each of the multiple pixels P may include multiple sub-pixels SP. Each of the multiple sub-pixels SP may include at least one light-emitting device.

[0071] For example, multiple sub-pixels SP may include a first sub-pixel SPa, a second sub-pixel SPb, and a third sub-pixel SPc, but are not limited thereto. The first sub-pixel SPa may include a first light-emitting device that emits light of a first color, the second sub-pixel SPb may include a second light-emitting device that emits light of a second color, and the third sub-pixel SPc may include a third light-emitting device that emits light of a third color. For example, the first color light, the second color light, and the third color light may be red light, green light, and blue light, but are not limited thereto.

[0072] Reference Figure 4 The display panel 110 according to the implementation of this disclosure may include a plurality of light-emitting devices ED. Each of the plurality of sub-pixels SP may include a light-emitting device ED.

[0073] For example, the first sub-pixel SPPa may include a first light-emitting device EDa, the second sub-pixel SPb may include a second light-emitting device EDb, and the third sub-pixel SPc may include a third light-emitting device EDc.

[0074] Reference Figure 4 The display panel 110 according to the implementation of this disclosure may include multiple row lines RL and multiple column lines CL.

[0075] Each of the multiple row lines RL can extend along the row direction. The multiple row lines RL can be electrically connected to the first electrode of each of the multiple light-emitting devices ED.

[0076] Each of the multiple column lines CL can extend along the column direction. The multiple column lines CL can be electrically connected to the second electrode of each of the multiple light-emitting devices ED.

[0077] For example, the first electrode of each of the plurality of light-emitting devices (EDs) can be an anode, and the second electrode of each of the plurality of light-emitting devices (EDs) can be a cathode. As another example, the first electrode of each of the plurality of light-emitting devices (EDs) can be a cathode, and the second electrode of each of the plurality of light-emitting devices (EDs) can be an anode.

[0078] Each of the multiple row lines RL can be electrically connected to the second electrode of each of the multiple light-emitting devices ED. In other words, the second electrode of each of the multiple light-emitting devices ED can be connected to a single row line RL.

[0079] Each of the multiple column lines CL can be electrically connected to the first electrode of each of the multiple light-emitting devices ED. In other words, the first electrode of each of the multiple light-emitting devices ED can be connected to a single column line CL.

[0080] Reference Figure 4The width of each of the multiple row lines RL can be greater than the width of each of the multiple column lines CL.

[0081] Reference Figure 4 The display panel 110 according to the implementation of this disclosure may include multiple drivers DRV. The multiple drivers DRV can drive multiple light-emitting devices ED, multiple column lines CL, and multiple row lines RL.

[0082] Multiple driver DRVs can be embedded in the display panel 110. Multiple driver DRVs can be set in the display area DA and can be set on the substrate 210.

[0083] Multiple driver DRVs can be configured to correspond to multiple unit drive areas (UDAs). In other words, one driver DRV can be configured within one unit drive area (UDA).

[0084] Each of the multiple drivers DRV can drive multiple row lines RL and multiple column lines CL in a corresponding unit drive region UDA. Correspondingly, multiple light-emitting devices ED in the corresponding unit drive region UDA can emit light.

[0085] Multiple drivers DRV can be set in the display area DA and can be positioned closer to the substrate 210 than multiple light-emitting devices ED.

[0086] For example, multiple line lines RL can be driven sequentially. Alternatively, multiple line lines RL can be driven simultaneously. Yet another example is that two or more line lines RL can be driven simultaneously.

[0087] For example, during any display driving period, among the multiple row lines RL arranged in a unit driving area UDA, at least one row line RL can be driven, while the remaining row lines RL may not be driven.

[0088] According to the implementation of this disclosure, the voltage applied to the horizontal line RL can be referred to as a low-potential voltage, and this low-potential voltage can also be referred to as the horizontal line voltage or cathode voltage. The low-potential voltage can have various voltage values ​​depending on the driving type or driving state. For example, the low-potential voltage may include a first low-potential voltage, a second low-potential voltage, and a third low-potential voltage.

[0089] Driving a row line RL can mean applying a first low potential voltage to the row line RL. Not driving a row line RL can mean applying a second low potential voltage higher than the first low potential voltage to the row line RL. Therefore, light-emitting devices ED that overlap with the driven row line RL can emit light, while light-emitting devices ED that overlap with the undriven row line RL can not emit light.

[0090] For example, any first row line RL among multiple row lines RL can receive a first low potential voltage during a first time period, and can receive a second low potential voltage higher than the first low potential voltage during a second time period different from the first time period. Therefore, a light-emitting device ED overlapping with a first row line RL can emit light during the first time period, and may not emit light during the second time period different from the first time period. For example, the first time period and the second time period can be included in one display driving period. Alternatively, the first time period and the second time period can be included in different display driving periods.

[0091] Reference Figure 4 A more detailed description of the structure of a unit drive region UDA.

[0092] Reference Figure 4 For example, a unit driving region UDA can be divided into a first sub-driving region SDA1 and a second sub-driving region SDA2. As another example, a unit driving region UDA can be divided into three or more sub-driving regions. As yet another example, a unit driving region UDA may not be divided into two or more sub-driving regions.

[0093] Reference Figure 4 A unit driving region UDA consists of a driver DRV and (2n×m) pixels P(1,1) to P(2n,m) driven by the driver DRV.

[0094] In the implementation of this disclosure, n can be the row number, the number of rows in each of the first sub-driving region SDA1 and the second sub-driving region SDA2, the number of row lines RL in each of the first sub-driving region SDA1 and the second sub-driving region SDA2, or the number of pixel rows in each of the first sub-driving region SDA1 and the second sub-driving region SDA2. m can be the column number, the number of columns in each of the first sub-driving region SDA1 and the second sub-driving region SDA2, the number of column lines CL in each of the first sub-driving region SDA1 and the second sub-driving region SDA2, or the number of pixel columns in each of the first sub-driving region SDA1 and the second sub-driving region SDA2.

[0095] In the implementation of this disclosure, n can be a natural number of 1 or greater, and m can be a natural number of 1 or greater.

[0096] Reference Figure 4 , (2n×m) pixels P(1,1) to P(2n,m) can be arranged in 2n rows R(1) to R(2n) and m columns C(1) to C(m).

[0097] Among the (2n×m) pixels P(1,1) to P(2n,m), (n×m) pixels arranged in the first row R(1) to the nth row R(n) can be set in the first sub-driving region SDA1.

[0098] Among the (2n×m) pixels P(1,1) to P(2n,m), the pixels arranged in rows (n+1) to 2n R(n+1) to R(2n) can be set in the second sub-driving region SDA2.

[0099] Reference Figure 4 A unit driving region UDA can include 2n line lines RL(1) to RL(2n) to drive (2n×m) pixels P(1,1) to P(2n,m).

[0100] Among the 2n line lines RL(1) to RL(2n), the first line line RL(1) to the nth line line RL(n) can be set in the first sub-driving area SDA1. Among the 2n line lines RL(1) to RL(2n), the (n+1)th to the 2nth line lines RL(n+1) to RL(2n) can be set in the second sub-driving area SDA2.

[0101] Each of the 2n row lines RL(1) to RL(2n) can overlap with m pixels. For example, the first row line RL(1) can overlap with m pixels P(1,1) to P(1,m) arranged in the first row R(1). The nth row line RL(n) can overlap with m pixels P(n,1) to P(n,m) arranged in the nth row R(n). The (n+1)th row line RL(n+1) can overlap with m pixels P(n+1,1) to P(n+1,m) arranged in the (n+1)th row R(n+1). The 2nth row line RL(2n) can overlap with m pixels P(2n,1) to P(2n,m) arranged in the 2nth row R(2n).

[0102] For example, the first row line RL(1) can be connected to the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(1,1) to P(1,m) arranged in the first row R(1). More specifically, the first row line RL(1) can be connected to the second electrode of the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(1,1) to P(1,m) arranged in the first row R(1).

[0103] For example, the nth row line RL(n) can be connected to the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(n,1) to P(n,m) arranged in the nth row R(n). More specifically, the nth row line RL(n) can be connected to the first electrode of the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(n,1) to P(n,m) arranged in the nth row R(n).

[0104] For example, the (n+1)th row line RL(n+1) can be connected to the k sub-pixels SPPa, SPb, and SPc included in each of the m pixels P(n+1, 1) to P(n+1, m) arranged in the (n+1)th row R(n+1). More specifically, the (n+1)th row line RL(n+1) can be connected to the first electrode of the k sub-pixels SPPa, SPb, and SPc included in each of the m pixels P(n+1, 1) to P(n+1, m) arranged in the (n+1)th row R(n+1).

[0105] For example, the 2n-th row line RL(2n) can be connected to the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(2n, ​​1) to P(2n, ​​m) arranged in the 2n-th row R(2n). More specifically, the 2n-th row line RL(2n) can be connected to the first electrode of the k sub-pixels SPa, SPb, and SPc included in each of the m pixels P(2n, ​​1) to P(2n, ​​m) arranged in the 2n-th row R(2n).

[0106] Reference Figure 4 A single driving region (UDA) can include (m×k×2) columns of lines CL to drive (2n×m) pixels P(1,1) to P(2n,m). Here, k represents the number of subpixels SP included in a pixel P. Figure 4 In the example, k is 3. That is, a pixel P can include three sub-pixels SPa, SPb, and SPc.

[0107] The first sub-driving region SDA1 may include (m×k×2) columns CL to drive (n×m) pixels P(1,1) to P(n,m). Figure 4 In the example, k is 3. That is, the first sub-driving region SDA1 can include 3m column lines CL.

[0108] In the first sub-driving region SDA1, k column lines CLa, CLb, and CLc can be set in each of the m columns C(1) to C(m). Figure 4In the example, k is 3. In the first sub-driving region SDA1, m columns C(1) to C(m) can include three column lines CLa, CLa, and CLa.

[0109] In each of the m columns C(1) to C(m), each of the k column lines CL can be commonly connected to the n pixels arranged in the corresponding column. In each of the m columns C(1) to C(m), each of the k column lines CL can be commonly connected to the first electrode of the n light-emitting devices arranged in the corresponding column. Figure 4 In the example, k is 3. In each of the m columns C(1) to C(m), three column lines CLa, CLb, and CLc can be connected to the first electrodes of the 3n light-emitting devices ED included in the n pixels arranged in the corresponding column. For example, in each of the m columns C(1) to C(m), the first column line CLa can be connected to the first electrodes of the n first light-emitting devices EDa included in the n pixels arranged in the corresponding column. In each of the m columns C(1) to C(m), the second column line CLb can be connected to the first electrodes of the n second light-emitting devices EDb included in the n pixels arranged in the corresponding column. In each of the m columns C(1) to C(m), the third column line CLc can be connected to the first electrodes of the n third light-emitting devices EDc included in the n pixels arranged in the corresponding column.

[0110] The second sub-driving region SDA2 may include (m×k) column lines CL to drive (n×m) pixels P(n+1, 1) to P(2n, ​​m). Figure 4 In the example, k is 3. That is, the second sub-driving region SDA2 can include 3m column lines CL.

[0111] In the second sub-driving region SDA2, k column lines can be set in each of the m columns C(1) to C(m). Figure 4 In the example, k is 3. In the second sub-driving region SDA2, m columns C(1) to C(m) can include three column lines CLa, CLa, and CLa.

[0112] In each of the m columns C(1) to C(m), each of the k column lines CL can be commonly connected to the n pixels arranged in the corresponding column. In each of the m columns C(1) to C(m), each of the k column lines CL can be commonly connected to the first electrode of the n light-emitting devices arranged in the corresponding column. Figure 4In the example, k is 3. In each of the m columns C(1) to C(m), three column lines CLa, CLb, and CLc can be connected to the first electrodes of the 3n light-emitting devices ED included in the n pixels arranged in the corresponding column. For example, in each of the m columns C(1) to C(m), the first column line CLa can be connected to the first electrodes of the n first light-emitting devices EDa included in the n pixels arranged in the corresponding column. In each of the m columns C(1) to C(m), the second column line CLb can be connected to the first electrodes of the n second light-emitting devices EDb included in the n pixels arranged in the corresponding column. In each of the m columns C(1) to C(m), the third column line CLc can be connected to the first electrodes of the n third light-emitting devices EDc included in the n pixels arranged in the corresponding column.

[0113] Figure 5 This is a diagram schematically illustrating the structure of a subpixel SP of a display panel according to an implementation of the present disclosure.

[0114] Reference Figure 5 According to the implementation of this disclosure, the sub-pixel SP may include: a light-emitting device ED, which includes a first electrode Ecl and a second electrode Erl; a column driver C-DRV for driving column lines CL electrically connected to the first electrode Ecl of the light-emitting device ED; and a row driver R-DRV for driving row lines RL electrically connected to the second electrode Erl of the light-emitting device ED.

[0115] Reference Figure 5 A light-emitting device (ED) may include a first electrode Ecl and a second electrode Erl. The first electrode Ecl may be electrically connected to a column line CL, and the second electrode Erl may be electrically connected to a row line RL. For example, the first electrode Ecl may be an anode, and the second electrode Erl may be a cathode. As another example, the first electrode Ecl may be a cathode, and the second electrode Erl may be an anode.

[0116] Reference Figure 5 The column driver C-DRV included in the unit driving region UDA can be connected to and drive the multiple column lines CL included in the unit driving region UDA. Each of the multiple column lines CL can be commonly connected to the first electrode Ecl of each of the multiple light-emitting devices ED included in the multiple sub-pixels SP arranged in the corresponding column.

[0117] Reference Figure 5The row driver R-DRV included in the unit driving region UDA can be connected to and drive multiple row lines RL included in the unit driving region UDA. Each of the multiple row lines RL can be commonly connected to the second electrode Erl of each of the multiple light-emitting devices ED included in the multiple sub-pixels SP arranged in the corresponding row.

[0118] Reference Figure 5 The column driver C-DRV may include master nodes, including a first node N1, a second node N2, a third node N3, and a fourth node N4. The column driver C-DRV may include a driving transistor DRT and a first light-emitting control transistor EMT1.

[0119] The first node N1 can be a node to which a voltage Vg is applied to control the on / off state of the driving transistor DRT. The second node N2 can be a node electrically connected to a high-potential voltage node NVDD to which a high-potential voltage VDD is applied. The third node N3 can be a node connected to the driving transistor DRT and the first light-emitting control transistor EMT1. The fourth node N4 can be a node electrically connected to the first light-emitting control transistor EMT1 and the light-emitting device ED, and can also be a node electrically connected to the column line CL. Here, the source or drain electrode of the first light-emitting control transistor EMT1 and the first electrode Ecl of the light-emitting device ED can be jointly connected to the column line CL.

[0120] The driving transistor DRT can supply the driving current for the light-emitting device ED to emit light. The driving transistor DRT is connected between the second node N2 and the third node N3, and the connection between the second node N2 and the third node N3 can be controlled according to the voltage of the first node N1.

[0121] The gate electrode of the driving transistor DRT can be electrically connected to the first node N1, and a gate voltage Vg can be applied thereon. The drain or source electrode of the driving transistor DRT can be electrically connected to the second node N2. The source or drain electrode of the driving transistor DRT can be electrically connected to the third node N3.

[0122] The first light-emitting control transistor EMT1 can control whether the path through which the drive current flows is connected, and can control whether the light-emitting device ED emits light.

[0123] When the driving transistor DRT and the first light-emitting control transistor EMT1 are turned on between the high potential voltage VDD and the low potential voltage VSS, the driving current can be supplied to the light-emitting device ED through the driving transistor DRT and the first light-emitting control transistor EMT1. Therefore, the light-emitting device ED can emit light.

[0124] The first light-emitting control transistor EMT1 is connected between the third node N3 and the fourth node N4, and the connection between the third node N3 and the fourth node N4 can be controlled according to the first light-emitting control signal EM1. The first light-emitting control signal EM1 can be applied to the gate electrode of the first light-emitting control transistor EMT1. The drain electrode or source electrode of the first light-emitting control transistor EMT1 can be electrically connected to the third node N3. The source electrode or drain electrode of the first light-emitting control transistor EMT1 can be electrically connected to the fourth node N4.

[0125] The first emission control signal EM1 may be a pulse width modulated signal that varies at predefined intervals (e.g., each frame, or each subframe included in a frame), but the implementation of this disclosure is not limited to this.

[0126] The first light-emitting control signal EM1 can be generated by the driver DRV, or supplied to the driver DRV from drive-related circuitry such as a timing controller.

[0127] Reference Figure 5 The row driver R-DRV can drive at least one row line RL by supplying a low potential voltage VSS to at least one row line RL.

[0128] The row driver R-DRV can perform display enable or display disable driving on a row line RL.

[0129] The line driver R-DRV can supply a low-potential voltage to a line line RL to enable the display, thereby enabling the display on line RL. The line driver R-DRV can also supply a low-potential voltage to a line line RL to disable the display, thereby disabling the display.

[0130] The low-potential voltage used to indicate the power-on drive and the low-potential voltage used to indicate the power-off drive can be different. For example, the low-potential voltage used to indicate the power-on drive can be lower than the low-potential voltage used to indicate the power-off drive. In the implementation of this disclosure, the "low-potential voltage used to indicate the power-on drive" is referred to as the "first low-potential voltage," and the "low-potential voltage used to indicate the power-off drive" is referred to as the "second low-potential voltage."

[0131] Reference Figure 5 In addition to the driving transistor DRT and the first light-emitting control transistor EMT1, the column driver C-DRV may also include at least one switching element and / or at least one transistor. Each of all transistors included in the column driver C-DRV may be an n-type transistor or a p-type transistor.

[0132] The column driver C-DRV may also include at least one capacitor.

[0133] The column driver C-DRV may also include at least one circuit element. For example, at least one circuit element may include a power output buffer.

[0134] Reference Figure 5 The row driver R-DRV may include at least one switching element and / or at least one transistor. Each of all transistors included in the row driver R-DRV may be an n-type transistor or a p-type transistor.

[0135] The line driver R-DRV may also include at least one circuit element. For example, at least one circuit element may include a power output buffer.

[0136] Reference Figure 5 The column driver C-DRV and the row driver R-DRV may be internal circuitry included in the driver DRV. As another example, the column driver C-DRV and the row driver R-DRV may be circuitry not included in the driver DRV, but rather formed on the substrate 210 of the display panel 110.

[0137] Figure 6 An example is shown of the driving timing diagram of n row lines RL(n) and one column line CL included in the first sub-driving area SDA1 of a display panel 110 according to an implementation of the present disclosure.

[0138] The row driver R-DRV of the driver DRV can drive n row lines RL(1) to RL(n) set in the first sub-drive area SDA1.

[0139] The driving of each of the n row lines RL(1) to RL(n) arranged in the first sub-driving region SDA1 may include: a display on drive for illuminating the light-emitting device ED in each of the n row lines RL(1) to RL(n); and a display off drive for disabling the light-emitting device ED in each of the n row lines RL(1) to RL(n).

[0140] The following method can be used as an example to illustrate the driving order of each of the n line lines RL(1) to RL(n) set in the first sub-driving region SDA1.

[0141] For example, the display enable driver for each of multiple line lines RL can be executed sequentially. As another example, the display enable driver for each of multiple line lines RL can be executed simultaneously. As yet another example, the display enable driver for each of two or more line lines RL can be executed simultaneously. In the following description, for ease of explanation, the case of sequentially executing the display enable driver for each of multiple line lines RL will be used as an example. However, this disclosure is not limited to this.

[0142] The row driver R-DRV of the driver DRV can sequentially drive n row lines RL(1) to RL(n) set in the first sub-drive area SDA1. That is, the display start drive periods D_ON(1) to D_ON(n) for the n row lines RL(1) to RL(n) set in the first sub-drive area SDA1 can be sequential.

[0143] Based on any one of the n row lines RL(1) to RL(n) set in the first sub-driving region SDA1, the display enable driving period D_ON(1) for the corresponding row line RL can occur at least once during the display driving period D. During the display driving period D, all remaining time except for the display enable driving period D_ON(1) for the corresponding row line RL can be a display disable driving period.

[0144] Reference Figure 6 During any display driving period D, among the n row lines RL(1) to RL(n) arranged in the unit driving area UDA, at least one row line RL can be driven to enable display, and the remaining row lines RL can be driven to disable display without driving to enable display.

[0145] For example, during any display driving period D, among the n row lines RL(1) to RL(n) arranged in the unit driving area UDA, the display enable drive can be executed on the first row line RL(1), and the display disable drive can be executed on the second row line RL(2) to the nth row line RL(n), without executing the display enable drive.

[0146] For example, during any display driving period D, among the n row lines RL(1) to RL(n) arranged in the unit driving area UDA, the display enable driving can be performed on the second row line RL(2), and the display disable driving can be performed on the first row line RL(1) and the third row line RL(3) to the nth row line RL(n), without performing the display enable driving.

[0147] For example, during any display driving period D, among the n row lines RL(1) to RL(n) arranged in the unit driving area UDA, the display enable drive can be performed on the third row line RL(3), and the display disable drive can be performed on the first row line RL(1), the second row line RL(2), and the fourth row line RL(4) to the nth row line RL(n), without performing the display enable drive.

[0148] For example, during any display driving period D, among the n row lines RL(1) to RL(n) arranged in the unit driving area UDA, the display enable drive can be executed on the (n-1)th row line RL(n-1), and the display disable drive can be executed on the first row line RL(1) to the (n-2)th row line RL(n-2) and the nth row line RL(n), without executing the display enable drive.

[0149] For example, during any display driving period D, among the n row lines RL(1) to RL(n) arranged in the unit driving area UDA, the display enable drive can be executed on the nth row line RL(n), and the display disable drive can be executed on the first row line RL(1) to the (n-1)th row line RL(n-1), without executing the display enable drive.

[0150] Reference Figure 6 Performing a display enable drive on any of the n row lines RL(1) to RL(n) located in the unit drive area UDA means supplying a first low potential voltage VSS1 with a predefined level to the corresponding row line RL. When a display enable drive is performed on any row line RL, the light-emitting device ED arranged corresponding to the row line RL can emit light.

[0151] When a display turn-off drive is executed instead of a display-on drive on any of the n row lines RL(1) to RL(n) set in the unit drive area UDA, it can be understood that a second low potential voltage VSS2 with a predefined level is supplied to the corresponding row line RL. When a display turn-off drive is executed on any row line RL, the light-emitting device ED arranged corresponding to the row line RL may not emit light.

[0152] The first low-level voltage VSS1 can be a low-level voltage VSS used to indicate that the drive is on, and the second low-level voltage VSS2 can be a low-level voltage VSS used to indicate that the drive is off. The second low-level voltage VSS2 can be higher than the first low-level voltage VSS1.

[0153] Reference Figure 6Any one of the n row lines RL(1) to RL(n) arranged in the unit driving region UDA can receive a first low potential voltage VSS1 during a first time period, and can be supplied with a second low potential voltage VSS2 higher than the first low potential voltage VSS1 during a second time period different from the first time period. For example, the first time period and the second time period can be included in one display driving time period D. As another example, the first time period and the second time period can be included in different display driving time periods D.

[0154] For example, among the n row lines RL(1) to RL(n) arranged in the unit drive area UDA, the first row line RL(1) can receive a first low potential voltage VSS1 during the first display on drive period D_ON(1), and can receive a second low potential voltage VSS2 higher than the first low potential voltage VSS1 during the second display on drive period D_ON(2) which is different from the first display on drive period D_ON(1).

[0155] For example, during the first display on-drive period D_ON(1), the first row line RL(1) can receive the first low potential voltage VSS1, while the second row line RL(2) to the nth row line RL(n) can receive the second low potential voltage VSS2. During the second display on-drive period D_ON(2), the second row line RL(2) can receive the first low potential voltage VSS1, while the first row line RL(1) and the third row line RL(3) to the nth row line RL(n) can receive the second low potential voltage VSS2.

[0156] For example, during the first display on-drive period D_ON(1), multiple light-emitting devices ED arranged in the first row overlapping with the first row line RL(1) can emit light, while multiple light-emitting devices ED arranged in the second to nth rows overlapping with the second row line RL(2) to the nth row line RL(n) can not emit light. During the second display on-drive period D_ON(2), multiple light-emitting devices ED arranged in the second row overlapping with the second row line RL(1) can emit light, while multiple light-emitting devices ED arranged in the first and third to nth rows overlapping with the first row line RL(1) and the third row line RL(3) to the nth row line RL(n) can not emit light.

[0157] For example, the first display on-drive period D_ON (1) and the second display on-drive period D_ON (2) can be included in one display drive period D. Alternatively, the first display on-drive period D_ON (1) and the second display on-drive period D_ON (2) can be included in different display drive periods D.

[0158] Reference Figure 6(m×k) column lines CL can be set in the unit drive area UDA. In the unit drive area UDA, the (m×k) column lines CL can intersect with n row lines RL(1) to RL(n). Figure 6 The column line CL shown can be one of (m×k) column lines CL.

[0159] During the display driving period D, each of the (m×k) column lines CL that intersects with the n row lines RL(1) to RL(n) can be synchronized with the display on-drive periods D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n), and can be applied with the display voltage VEM required for the corresponding light-emitting device ED to emit light. Here, the display voltage VEM is also called the light-emitting drive voltage.

[0160] During the display driving period D, for all remaining time except for the display on drive periods D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n), a reset voltage VRST can be applied to each of the (m×k) column lines CL that intersect with the n row lines RL(1) to RL(n).

[0161] The display voltage VEM can be a voltage that varies based on a constant voltage or an image signal. The reset voltage VRST can be a voltage lower than the display voltage VEM, and can be a constant voltage or a variable voltage.

[0162] During the display driving period D, during the display turn-on driving period D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n), the voltage difference VEM-VSS1 between the display voltage VEM applied to the corresponding column line CL and the first low potential voltage VSS1 applied to the corresponding row line RL can be the display turn-on voltage ΔVon.

[0163] The light-emitting device ED can be connected between the corresponding column line CL and the corresponding row line RL. The display voltage VEM and the first low potential voltage VSS1 can be applied to the first electrode Ecl and the second electrode Erl of the light-emitting device ED, respectively.

[0164] The display turn-on voltage ΔVon is the voltage difference between the first electrode Ecl and the second electrode Erl of the corresponding light-emitting device ED, and can be the voltage that enables the corresponding light-emitting device ED to emit light. For example, the display turn-on voltage ΔVon can be greater than or equal to a threshold voltage, which is an inherent characteristic value of the corresponding light-emitting device ED.

[0165] During all remaining time periods other than the display on-drive periods D_ON(1) to D_ON(n) of each of the n row lines RL(1) to RL(n), the voltage difference VRST-VSS2 between the reset voltage VRST applied to the corresponding column line CL and the second low potential voltage VSS2 applied to the corresponding row line RL can be the display off voltage ΔVoff.

[0166] The light-emitting device (ED) can be connected between the corresponding column line CL and the corresponding row line RL. The reset voltage VRST and the second low potential voltage VSS2 can be applied to the first electrode Ecl and the second electrode Erl of the light-emitting device ED, respectively.

[0167] The display off voltage ΔVoff is the voltage difference between the first electrode Ecl and the second electrode Erl of the corresponding light-emitting device (ED), and can be the voltage that prevents the ED from emitting light. For example, the display off voltage ΔVoff can be less than a threshold voltage, which is an inherent characteristic value of the ED. That is, the display on voltage ΔVon can be greater than or equal to the display off voltage ΔVoff.

[0168] The circuitry for driving n light-emitting devices ED(1) to ED(n) connected to a column line CL in a display panel 110 according to an implementation of the present disclosure will be described in more detail below.

[0169] Figure 7 It is a plan view of the display panel according to the implementation of this disclosure.

[0170] Reference Figure 7 According to the implementation of the present disclosure, the substrate 210 of the display panel 110 may include a display area DA and a non-display area NDA. The non-display area NDA may include a first non-display area NDA1, a curved area BA, and a second non-display area NDA2.

[0171] Reference Figure 7 Multiple driver DRVs can be set in the display area DA. Each of the multiple driver DRVs can be used for driving. Figure 4 The corresponding unit driving region UDA includes the circuitry for the light-emitting devices of multiple sub-pixels. Each of the multiple driver DRVs may include a row driver R-DRV for driving multiple row lines and a column driver C-DRV for driving multiple column lines, in order to drive... Figure 4 The corresponding unit driving region UDA includes multiple light-emitting devices (EDs).

[0172] Reference Figure 7 The pad portion 211, which includes multiple pads PD, can be set in the second non-display area NDA2.

[0173] Reference Figure 7 Multiple signal lines SL and multiple link lines LL can be provided on the substrate 210 for signal transmission between multiple drivers DRV and pad portions 211 located in the display area DA. The multiple signal lines SL can be electrically connected between the multiple link lines LL and the multiple drivers DRV. The multiple link lines LL can electrically connect multiple pads PD to the multiple signal lines SL.

[0174] Reference Figure 7 Multiple link lines LL can be set in the non-display area NDA, and all or part of each of the multiple signal lines SL can be set in the display area DA.

[0175] Each of the multiple driver DRVs can receive various signals to perform drive operations via multiple link lines LL and multiple signal lines SL. These various signals can include the various power voltages and signals required for the drive operation of each of the multiple driver DRVs.

[0176] As the bending region BA bends, a portion of the multiple link lines LL may also bend. Stress concentrates on the bent portion of the link lines LL, and therefore, cracks may form in the link lines LL. Therefore, to reduce cracking during bending of the bending region BA, the multiple link lines LL can be formed of a conductive material with excellent ductility. For example, the multiple link lines LL can be formed of a conductive material with excellent ductility (e.g., gold (Au), silver (Ag), or aluminum (Al)), but the implementation of this disclosure is not limited to this. Alternatively, the multiple link lines LL can be formed of one of various conductive materials used in the display region DA. For example, the multiple link lines LL can be formed of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), silver (Ag), and magnesium (Mg), or alloys thereof, but the implementation of this disclosure is not limited to this. The multiple link lines LL can be configured in a multilayer structure including various conductive materials. For example, the multiple link lines LL can consist of a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but the implementation of this disclosure is not limited to this.

[0177] Multiple link lines LL can be configured in various shapes to alleviate stress. At least a portion of the multiple link lines LL disposed on the curved region BA can extend in the same direction as the extension direction of the curved region BA, or can extend in a direction different from the extension direction of the curved region BA, to alleviate stress. For example, when the curved region BA extends from the first non-display region NDA1 to the second non-display region NDA2 in one direction, at least a portion of the link lines LL disposed on the curved region BA can extend in a direction inclined to that direction. As another example, at least a portion of the multiple link lines LL can be configured in patterns having various shapes. For example, at least a portion of the multiple link lines LL disposed on the curved region BA can have a shape in which a conductive pattern is repeatedly arranged, the conductive pattern having at least one of the following shapes: diamond shape, rhombus shape, trapezoidal shape, triangular wave shape, sawtooth wave shape, sine wave shape, circular wave shape, and Ω shape, but the implementation of this disclosure is not limited to this. Therefore, in order to reduce or minimize the stress and corresponding cracks concentrated on the multiple link lines LL, the multiple link lines LL can be formed in various shapes, including the shapes described above, but the implementation of this disclosure is not limited to these.

[0178] Figure 8 This is a detailed cross-sectional view of the display panel 110 according to the implementation of this disclosure, and is along... Figure 7 The cross-sectional view taken from line AB.

[0179] Figure 8 This is an enlarged cross-sectional view of the sub-pixel SP of the display panel 110 according to the implementation method of this specification. Figure 8 It is a cross-sectional view of the display area DA, the first non-display area NDA, the curved area BA, and the second non-display area NDA2.

[0180] In addition, for ease of display, Figure 7 This shows that line AB does not overlap with signal line SL and link line LL, but Figure 7 The AB line is designed to show the same or substantially the same position as the adjacent signal line SL and link line LL.

[0181] Reference Figure 8 The buffer layer 1511 may be disposed on the substrate 210. The buffer layer 1511 may include a first buffer layer 1511a and a second buffer layer 1511b. The first buffer layer 1511a and the second buffer layer 1511b may be disposed in the display area DA, the first non-display area NDA1 and the second non-display area NDA2, and may not be disposed in all or part of the curved area BA. However, the present disclosure is not limited thereto.

[0182] The first buffer layer 1511a and the second buffer layer 1511b can reduce the penetration of moisture or impurities through the substrate 210. The first buffer layer 1511a and the second buffer layer 1511b can be formed of inorganic insulating material. For example, the first buffer layer 1511a and the second buffer layer 1511b can be formed of single or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the implementation of this disclosure is not limited to this.

[0183] For example, portions of the first buffer layer 1511a and the second buffer layer 1511b located in the bending region BA can be removed. By removing the areas (openings) of the first buffer layer 1511a and the second buffer layer 1511b, the upper surface of the substrate 210 located in the bending region BA can be exposed.

[0184] By removing the first buffer layer 1511a and the second buffer layer 1511b from the bending region BA, cracks in the first buffer layer 1511a and the second buffer layer 1511b that may occur during bending can be reduced or minimized.

[0185] Multiple alignment keys MK can be provided between the first buffer layer 1511a and the second buffer layer 1511b. The multiple alignment keys MK can identify the position of the driver DRV during the manufacturing process of the display panel 110. For example, the multiple alignment keys MK can align the position of the driver DRV transferred to the adhesive layer 1512. Alternatively, the multiple alignment keys MK can be omitted.

[0186] The adhesive layer 1512 may be disposed on the second buffer layer 1511b. The adhesive layer 1512 may be disposed in the display area DA, the first non-display area NDA1, the curved area BA, and the second non-display area NDA2. For example, at least a portion of the adhesive layer 1512 may be removed from the non-display area NDA including the curved area BA. For example, the adhesive layer 1512 may be formed from any of the following: adhesive polymer, epoxy resin, UV-curable resin, polyimide-based material, acrylate-based material, polyurethane-based material, and polydimethylsiloxane (PDMS), but implementations of this disclosure are not limited thereto.

[0187] The driver DRV can be disposed on the adhesive layer 1512 in the display area DA. When the driver DRV is implemented as a driver chip (driver integrated circuit), the driver can be mounted on the adhesive layer 1512 by a transfer process, but the implementation of this disclosure is not limited to this.

[0188] The display panel 110 may further include a side protective layer 1513 disposed on the side surfaces of the plurality of driver DRVs, and an upper protective layer 1514 disposed on the plurality of driver DRVs and the side protective layer 1513. For example, the side protective layer 1513 may include at least one of a first protective layer 1513a and a second protective layer 1513b disposed on the side surfaces of the plurality of driver DRVs, and in some cases, may also include at least one additional protective layer. The first protective layer 1513a and the second protective layer 1513b may be disposed on the adhesive layer 1512. The first protective layer 1513a and the second protective layer 1513b may surround the side surfaces of the driver DRVs, but the implementation of this disclosure is not limited thereto. For example, the second protective layer 1513b may be configured to cover at least a portion of the upper surface of the driver DRV. For example, at least one of the first protective layer 1513a and the second protective layer 1513b disposed on the curved region BA may be omitted. For example, the first protective layer 1513a may be entirely disposed in the display area DA and the non-display area NDA, while the second protective layer 1513b may be partially disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2. For example, at least a portion of the second protective layer 1513b may be removed in all or part of the curved area BA. However, the implementation of this disclosure is not limited to this.

[0189] For example, the side protective layer 1513, including at least one of the first protective layer 1513a and the second protective layer 1513b, may be formed of an organic insulating material (organic layer), but the implementation of this disclosure is not limited to this. For example, the first protective layer 1513a and the second protective layer 1513b may be formed of photoresist, polyimide (PI), photoacrylic acid-based materials, etc., but the implementation of this disclosure is not limited to this. For example, the first protective layer 1513a and the second protective layer 1513b may be a coating layer or an insulating layer, but the implementation of this disclosure is not limited to this.

[0190] According to the implementation of this disclosure, multiple line connection patterns (LCPs) can be disposed on the second protective layer 1513b in the display area DA. The multiple line connection patterns (LCPs) can be lines used to electrically connect the driver DRV to other components. For example, the driver DRV can be electrically connected to multiple column lines CL, multiple row lines RL, multiple row connection electrodes RCE, etc., via the multiple line connection patterns (LCPs).

[0191] For example, multiple line connection patterns (LCPs) may include a first line connection pattern (LCP1), a second line connection pattern (LCP2), a third line connection pattern (LCP3), and a fourth line connection pattern (LCP4), but the implementation of this disclosure is not limited to this. For example, the first line connection pattern (LCP1), the second line connection pattern (LCP2), the third line connection pattern (LCP3), and the fourth line connection pattern (LCP4) may be disposed in different metal layers.

[0192] For example, multiple first-line connection patterns LCP1 can be disposed on the second protective layer 1513b. The multiple first-line connection patterns LCP1 can be electrically connected to the driver DRV. The multiple first-line connection patterns LCP1 can transmit the voltage output from the driver DRV to the column line CL or row line RL.

[0193] The display panel 110 may further include a side protective layer 1513, which includes at least one of a first protective layer 1513a and a second protective layer 1513b, and an upper protective layer 1514 disposed on a plurality of driver DRVs. For example, the upper protective layer 1514 may include a third protective layer 1514, and in some cases, may also include at least one additional protective layer. The third protective layer 1514 may be disposed on the second protective layer 1513b and a plurality of first line connection patterns LCP1. The third protective layer 1514 may be disposed entirely in the display area DA and the non-display area NDA. In the curved area BA, the third protective layer 1514 may cover the side surface of the second protective layer 1513b and the upper surface of the first protective layer 1513a.

[0194] For example, the third protective layer 1514 can be formed of an organic insulating material. For example, the third protective layer 1514 can be formed of photoresist, polyimide (PI), photoacrylic acid-based materials, etc., but the implementation of this disclosure is not limited to these. For example, the first protective layer 1513a, the second protective layer 1513b, and the third protective layer 1514 can be formed of the same or substantially the same insulating material, or at least one of the first protective layer 1513a, the second protective layer 1513b, and the third protective layer 1514 can be formed of an insulating material different from the rest. The implementation of this disclosure is not limited to these.

[0195] Multiple second-line connection patterns LCP2 can be disposed on the third protective layer 1514. The multiple second-line connection patterns LCP2 can be electrically connected or directly connected to the driver DRV. For example, a portion of the second-line connection pattern LCP2 can be directly connected to or indirectly connected to the driver DRV through contact holes in the third protective layer 1514. Another portion of the second-line connection pattern LCP2 can be electrically connected to the first-line connection pattern LCP1 through contact holes in the third protective layer 1514. However, the implementation of this disclosure is not limited to this. The voltage output from the driver DRV can be transmitted to the column line CL or row line RL through connection patterns different from the multiple second-line connection patterns LCP2.

[0196] The first insulating layer 1515a can be disposed on a plurality of second line connection patterns LCP2. The first insulating layer 1515a can be completely disposed within the display area DA and the non-display area NDA, but the implementation of this disclosure is not limited thereto. The first insulating layer 1515a can be formed of an organic insulating material, but the implementation of this disclosure is not limited thereto. For example, the first insulating layer 1515a can be formed of photoresist, polyimide (PI), photoacrylic acid-based materials, etc., but the implementation of this disclosure is not limited thereto.

[0197] Multiple third-wire connection patterns LCP3 can be disposed on the first insulating layer 1515a. The multiple third-wire connection patterns LCP3 can be electrically connected to multiple second-wire connection patterns LCP2. For example, the third-wire connection patterns LCP3 can be electrically connected to the second-wire connection patterns LCP2 through contact holes in the first insulating layer 1515a.

[0198] The second insulating layer 1515b can be disposed on a plurality of third-line connection patterns LCP3. The second insulating layer 1515b can be disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2, and may not be disposed in all or part of the curved area BA, but the implementation of this disclosure is not limited thereto. For example, the second insulating layer 1515b can be removed from all or part of the curved area BA. The second insulating layer 1515b can be formed of an organic insulating material, but the implementation of this disclosure is not limited thereto. For example, the second insulating layer 1515b can be formed of photoresist, polyimide (PI), photoacrylic acid-based materials, etc., but the implementation of this disclosure is not limited thereto.

[0199] Multiple fourth-wire connection patterns LCP4 can be disposed on the second insulating layer 1515b. The multiple fourth-wire connection patterns LCP4 can be electrically connected to multiple third-wire connection patterns LCP3. For example, the fourth-wire connection patterns LCP4 can be electrically connected to the third-wire connection patterns LCP3 through contact holes in the second insulating layer 1515b.

[0200] Reference Figure 8According to an implementation of this disclosure, multiple pad connection patterns (PCPs) can be disposed on the second protective layer 1513b in the non-display area (NDA). The multiple pad connection patterns (PCPs) can be wires used to transmit signals from the flexible printed circuit 102 to the pad portion 211 to the driver DRV of the display area (DA). For example, the multiple pad connection patterns (PCPs) can be electrically connected to multiple pads (PDs) and can receive signals from the flexible printed circuit 102 through the multiple pads (PDs). The flexible printed circuit 102 can be connected to the printed circuit board 104 (see [link to relevant documentation]). Figure 1 and Figure 2 ).

[0201] For example, multiple pad connection patterns PCP can extend from pad portion 211 toward display area DA and route signals to display area DA. In this case, multiple pad connection patterns PCP can be used as link lines LL (see...). Figure 7 Multiple pad connection patterns (PCPs) may include a first pad connection pattern (PCP1), a second pad connection pattern (PCP2), a third pad connection pattern (PCP3), and a fourth pad connection pattern (PCP4).

[0202] Multiple first pad connection patterns PCP1 can be disposed on the second protective layer 1513b. Each of the multiple first pad connection patterns PCP1 can be disposed on the second non-display area NDA2, the curved area BA, and the first non-display area NDA1. Each of the multiple first pad connection patterns PCP1 may include a first portion disposed in the curved area BA, a second portion extending from the first portion to the first non-display area NDA1, and a third portion extending from the first portion to the second non-display area NDA2. Each of the multiple first pad connection patterns PCP1 may also extend a portion of the first non-display area NDA1 to the display area DA. The multiple first pad connection patterns PCP1 can transmit signals from the flexible printed circuit 102 to the pad portion 211 to the driver DRV of the display area DA.

[0203] Each of the plurality of first pad connection patterns PCP1 can be electrically connected to the pad PD of the pad portion 211 via a connection pattern disposed in the second non-display area NDA2. Here, the connection pattern that electrically connects each of the plurality of first pad connection patterns PCP1 to the pad PD may include at least one of the second pad connection pattern PCP2, the third pad connection pattern PCP3, and the fourth pad connection pattern PCP4 disposed in the second non-display area NDA2.

[0204] Each of the plurality of first pad connection patterns PCP1 can be electrically connected to the driver DRV via a connection pattern disposed in the display area DA. Here, the connection pattern that electrically connects each of the plurality of first pad connection patterns PCP1 to the driver DRV may include at least one of the second pad connection pattern PCP2, the third pad connection pattern PCP3, and the fourth pad connection pattern PCP4 disposed in the display area DA.

[0205] Multiple second pad connection patterns PCP2 can be disposed on the third protective layer 1514. Multiple second pad connection patterns PCP2 can be disposed in the second non-display area NDA2. The second pad connection patterns PCP2 can be electrically connected to the first pad connection pattern PCP1 through contact holes in the third protective layer 1514. Therefore, signals supplied from the flexible printed circuit 102 can be transmitted to the first pad connection pattern PCP1 through the second pad connection patterns PCP2.

[0206] The third pad connection pattern PCP3 can be disposed on the first insulating layer 1515a. The third pad connection pattern PCP3 can also be disposed in the second non-display area NDA2. The third pad connection pattern PCP3 can be electrically connected to the second pad connection pattern PCP2 through the contact holes of the first insulating layer 1515a. Therefore, signals supplied from the flexible printed circuit 102 can be transmitted to the second pad connection pattern PCP2 through the third pad connection pattern PCP3, and signals transmitted to the second pad connection pattern PCP2 can be transmitted to the first pad connection pattern PCP1.

[0207] The fourth pad connection pattern PCP4 can be disposed on the second insulating layer 1515b. The fourth pad connection pattern PCP4 can be disposed in the second non-display area NDA2. The fourth pad connection pattern PCP4 can be electrically connected to the third pad connection pattern PCP3 through the contact holes of the second insulating layer 1515b. The pad PD of the pad portion 211 can be electrically connected to the fourth pad connection pattern PCP4 through the contact holes of the third insulating layer 1515c.

[0208] Signals supplied from the flexible printed circuit 102 can be input to pads PD of the pad portion 211. Signals input to pads PD can be transmitted to a third pad connection pattern PCP3 via a fourth pad connection pattern PCP4. Signals transmitted to the third pad connection pattern PCP3 can then be transmitted to a first pad connection pattern PCP1 via a second pad connection pattern PCP2. Signals transmitted to the first pad connection pattern PCP1 can be transmitted to the driver DRV via connection patterns provided in the display area DA.

[0209] Reference Figure 8Multiple line connection patterns (LCPs) and multiple pad connection patterns (PCPs) can be disposed in different metal layers. The multiple line connection patterns (LCPs) and multiple pad connection patterns (PCPs) can be formed from any of the conductive materials with excellent ductility or various conductive materials used in the display area (DA).

[0210] For example, at least a portion of the metal pattern (e.g., the first pad connection pattern PCP1) disposed in the curved region BA can be formed of a conductive material with excellent ductility, such as gold (Au), silver (Ag), or aluminum (Al), but the implementation of this disclosure is not limited thereto. As another example, the multiple line connection patterns LCP and the multiple pad connection patterns PCP can be formed of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), silver (Ag), and magnesium (Mg), or alloys thereof, but the implementation of this disclosure is not limited thereto.

[0211] The third insulating layer 1515c can be disposed on multiple line connection patterns LCP and multiple pad connection patterns PCP. The third insulating layer 1515c can be disposed in the display area DA, the first non-display area NDA1, and the second non-display area NDA2, and can be disposed in all or part of the curved area BA, but the implementation of this disclosure is not limited thereto. In the curved area BA, a portion of the third insulating layer 1515c can be removed. The third insulating layer 1515c can be formed of an organic insulating material, but the implementation of this disclosure is not limited thereto. For example, the third insulating layer 1515c can be formed of photoresist, polyimide (PI), photoacrylic acid-based materials, etc., but the implementation of this disclosure is not limited thereto.

[0212] Multiple embankment BNKs may be disposed on the third insulating layer 1515c in the display area DA. The multiple embankment BNKs may overlap with at least a portion of each of the multiple sub-pixels SPa, SPb, and SPc. For example, the first sub-pixel SPa may include a first light-emitting device EDa that emits light of a first color, the second sub-pixel SPb may include a second light-emitting device EDc that emits light of a second color, and the third sub-pixel SPc may include a third light-emitting device EDc that emits light of a third color.

[0213] As an example, one light-emitting device (ED) can be provided on each of the multiple embankment BNKs. As another example, two or more light-emitting devices (EDs) can be provided on each of the multiple embankment BNKs. The two or more light-emitting devices (EDs) provided on each of the multiple embankment BNKs can be light-emitting devices of the same type. For example, light-emitting devices of the same type can be light-emitting devices that emit light of the same color. For example, the two or more light-emitting devices (EDs) provided on each of the multiple embankment BNKs can include a main light-emitting device and redundant light-emitting devices.

[0214] In the display area DA, multiple row connection electrodes RCE can be disposed on the third insulating layer 1515c. The multiple row connection electrodes RCE can transmit the low potential voltage VSS output from the driver DRV to the row line RL.

[0215] In the display area DA, multiple column lines CL can be provided on the third insulating layer 1515c. The multiple column lines CL can be provided in the area between multiple dike sections BNK. For example, the multiple column lines CL can be provided adjacent to any one of the multiple dike sections BNK.

[0216] Each of the multiple column lines CL may include a wiring portion and a column connection electrode CCE protruding from that wiring portion. The wiring portion and column connection electrode CCE included in each of the multiple column lines CL may be integrally formed, or they may be different metals electrically connected to each other.

[0217] For example, each of the multiple column lines CL may include a column connection electrode CCE that protrudes upward from an adjacent embankment BNK among the multiple embankment BNKs. The column connection electrode CCE of each of the multiple column lines CL may extend on the side and top surfaces of the embankment BNK. The column connection electrode CCE may be an electrode electrically connected to each of the multiple column lines CL, or a portion protruding from each of the multiple column lines CL.

[0218] According to the implementation of this disclosure, at least two of the column connection electrode CCE, column line CL, row connection electrode RCE, and pad PD can be disposed on the same layer. The column connection electrode CCE, column line CL, row connection electrode RCE, and pad PD can be formed of a single layer or multiple layers of conductive material, but the implementation of this disclosure is not limited thereto. For example, at least two of the column connection electrode CCE, column line CL, row connection electrode RCE, and pad PD can be formed of multiple layers of indium tin oxide (ITO) / titanium (Ti) / aluminum (Al) / titanium (Ti), but the implementation of this disclosure is not limited thereto.

[0219] According to the implementation of this disclosure, a solder pattern SDP can be provided on the column connection electrode CCE of each of a plurality of sub-pixels. The solder pattern SDP can bond the light-emitting device ED to the column connection electrode CCE. The column connection electrode CCE and the light-emitting device ED can be electrically connected to each other via eutectic bonding using the solder pattern SDP, but the implementation of this disclosure is not limited thereto. For example, when the solder pattern SDP is formed of indium (In) and the first electrode Ecl of the light-emitting device ED is formed of gold (Au), the solder pattern SDP and the first electrode Ecl of the light-emitting device ED can be bonded to each other by applying heat and pressure during the transfer process of the light-emitting device ED. The light-emitting device ED can be bonded to the solder pattern SDP and the column connection electrode CCE via eutectic bonding without the need for a separate adhesive. For example, the solder pattern SDP can be formed of indium (In), tin (Sn) or an alloy thereof, but the implementation of this disclosure is not limited thereto. For example, the solder pattern SDP can be a bonding pad or a connection pad, but the implementation of this disclosure is not limited thereto.

[0220] According to the implementation of this disclosure, a passivation layer 1516 can be provided on multiple column lines CL, multiple column connection electrodes CCE, multiple row connection electrodes RCE and a third insulating layer 1515c.

[0221] For example, passivation layer 1516 can be disposed in display area DA, first non-display area NDA1, and second non-display area NDA2. At least a portion of passivation layer 1516 can be removed from all or part of the curved area BA. In the second non-display area NDA2, the portion of passivation layer 1516 covering multiple pads PD can be removed.

[0222] Since the passivation layer 1516 can cover the remaining area except for the area where the curved region BA, multiple pads PD, and solder pattern SDP are provided, the penetration of moisture or impurities into the light-emitting device ED can be reduced. For example, the passivation layer 1516 can be composed of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the implementation of this disclosure is not limited to this. For example, the passivation layer 1516 can be a protective layer, an insulating layer, etc., but the implementation of this disclosure is not limited to this.

[0223] According to the implementation of this disclosure, the light-emitting device (ED) is described as having a vertical structure, but the implementation of this disclosure is not limited to this. For example, the ED may have a horizontal structure or a flip-chip structure.

[0224] According to the implementation of this disclosure, a first optical layer 1517a can be disposed in the display area DA surrounding multiple light-emitting devices ED. For example, the first optical layer 1517a can cover multiple light-emitting devices ED and embankment BNK in multiple sub-pixels SP. For example, the first optical layer 1517a can cover a portion of the embankment BNK, a passivation layer 1516, and the area between multiple light-emitting devices ED. The first optical layer 1517a can be disposed between or cover multiple light-emitting devices ED and multiple embankment BNK included in a pixel. For example, the first optical layer 1517a can extend along a first direction X and can be spaced apart from each other along a second direction Y. For example, the first optical layer 1517a can be disposed between the passivation layer 1516 and the row line RL to surround the sides of the light-emitting devices ED and embankment BNK, but the implementation of this disclosure is not limited to this. For example, the first optical layer 1517a can be a diffuse layer, a sidewall diffuse layer, etc., but the implementation of this disclosure is not limited to this.

[0225] The first optical layer 1517a may include an organic insulating material in which fine particles are distributed, but the implementation of this disclosure is not limited to this. For example, the first optical layer 1517a may be formed of a siloxane in which fine metal particles such as titanium dioxide (TiO2) particles are distributed, but the implementation of this disclosure is not limited to this. Light from multiple light-emitting devices (EDs) can be scattered by the fine particles distributed in the first optical layer 1517a and emitted to the outside of the display device 100. Therefore, the first optical layer 1517a can improve the extraction efficiency of light emitted from multiple light-emitting devices (EDs).

[0226] For example, the first optical layer 1517a can be disposed in each of the multiple pixels, or it can be disposed in some pixels disposed in the same row, but the implementation of this disclosure is not limited to this. For example, the first optical layer 1517a can be disposed in each of the multiple pixels, or multiple pixels can share a first optical layer 1517a. As another example, each of the multiple sub-pixels can individually include the first optical layer 1517a, but the implementation of this disclosure is not limited to this.

[0227] According to the implementation of this disclosure, in the display area DA, the second optical layer 1517b can be disposed on the passivation layer 1516. For example, the second optical layer 1517b can be configured to surround the first optical layer 1517a. For example, the second optical layer 1517b can be in contact with the side surface of the first optical layer 1517a. For example, the second optical layer 1517b can be disposed in the area between multiple pixels. However, the implementation of this disclosure is not limited to this. For example, the second optical layer 1517b can be a diffuse layer, a diffuse layer window, a window diffuse layer, etc., but the implementation of this disclosure is not limited to this.

[0228] The second optical layer 1517b may be formed of an organic insulating material, but the implementation of this disclosure is not limited to this. The second optical layer 1517b may be formed of the same or substantially the same material as the first optical layer 1517a, but the implementation of this disclosure is not limited to this. For example, the first optical layer 1517a may include fine particles, while the second optical layer 1517b may not include fine particles. For example, the second optical layer 1517b may be formed of a siloxane, but the implementation of this disclosure is not limited to this.

[0229] For example, the thickness of the first optical layer 1517a may be less than the thickness of the second optical layer 1517b, but the implementation of this disclosure is not limited to this. Therefore, when viewed in a plan view, the area where the first optical layer 1517a is disposed may include a recess that is recessed from the upper surface of the second optical layer 1517b.

[0230] According to the implementation of this disclosure, the row line RL can be disposed on the first optical layer 1517a and the second optical layer 1517b. For example, the row line RL can be electrically connected to multiple row connection electrodes RCE through the contact holes of the second optical layer 1517b. For example, the row line RL can be disposed on multiple light-emitting devices ED. For example, the row line RL may include a transparent conductive oxide, such as indium tin oxide (ITO) or indium zinc oxide (IZO), but the implementation of this disclosure is not limited to these. For example, the row line RL can contact the second electrode Erl of the light-emitting device ED. For example, the row line RL can overlap with the first optical layer 1517a. For example, the row line RL can cover the outer plane of the first optical layer 1517a.

[0231] The row lines RL can extend continuously along the first direction X of the substrate 210. Therefore, the row lines RL can be commonly connected to multiple pixels arranged in the first direction X of the substrate 210. For example, the row lines RL can be commonly connected to multiple pixels.

[0232] According to the implementation of this disclosure, the line line RL can extend continuously on the first optical layer 1517a, the second optical layer 1517b, and the light-emitting device ED. The region where the first optical layer 1517a is disposed may include a recess that extends from the upper surface of the second optical layer 1517b. Therefore, since the first portion of the line line RL disposed on the first optical layer 1517a is disposed along the recess, this first portion can be disposed at a lower position than the second portion of the line line RL disposed on the second optical layer 1517b.

[0233] The third optical layer 1517c can be disposed on the row lines RL. The third optical layer 1517c can overlap with the plurality of light-emitting devices ED and the first optical layer 1517a. Since the third optical layer 1517c is disposed on the row lines RL and the plurality of light-emitting devices ED, it can improve the appearance of muras that may occur in some of the plurality of light-emitting devices ED. For example, when the plurality of light-emitting devices ED are transferred onto the substrate 210 of the display panel 110, areas with uneven gaps between the plurality of light-emitting devices ED may appear due to process deviations, etc. When the gaps between the plurality of light-emitting devices ED are uneven, the light-emitting area of ​​each of the plurality of light-emitting devices ED may be unevenly set, and the user may visually perceive muras. Therefore, since the third optical layer 1517c is configured to uniformly diffuse light above the upper part of the plurality of light-emitting devices ED, the visibility of light emitted from some of the light-emitting devices ED like muras can be reduced. Therefore, since the light emitted from multiple light-emitting devices (EDs) is uniformly scattered and extracted to the outside of the display device 100 by the third optical layer 1517c, the brightness uniformity of the display device 100 can be improved.

[0234] The third optical layer 1517c can be formed from an organic insulating material in which fine particles are distributed, but the implementation of this disclosure is not limited to this. For example, the third optical layer 1517c can be formed from a siloxane in which fine metal particles such as titanium dioxide (TiO2) particles are distributed, but the implementation of this disclosure is not limited to this. For example, the third optical layer 1517c can be formed from a material that is the same as or substantially the same as the material of the first optical layer 1517a, but the implementation of this disclosure is not limited to this. For example, the third optical layer 1517c can be a diffuse layer, an upper diffuse layer, etc., but the implementation of this disclosure is not limited to this.

[0235] According to the implementation of this disclosure, light from multiple light-emitting devices (EDs) can be scattered by fine particles distributed in the third optical layer 1517c and emitted to the outside of the display device 100. The third optical layer 1517c can uniformly mix the light emitted from the multiple light-emitting devices (EDs) to further improve the brightness uniformity of the display device 100. In addition, the light scattered from the multiple fine particles can improve the light extraction efficiency of the display device 100, so the display device 100 can be driven at low power.

[0236] In the display area DA, a black matrix BM can be disposed on the row lines RL, the first optical layer 1517a, the second optical layer 1517b, and the third optical layer 1517c. For example, the black matrix BM can fill the contact holes of the second optical layer 1517b. Since the black matrix BM can cover the display area DA, color mixing of multiple sub-pixels and reflection of external light can be reduced. For example, since the black matrix BM is disposed in the contact holes where the row lines RL and the row connection electrodes RCE are connected, light leakage between multiple adjacent sub-pixels can be reduced or prevented.

[0237] For example, the black matrix BM can be formed from an opaque material, but the implementation of this disclosure is not limited to this. For example, the black matrix BM can be an organic insulating material with added black pigment or black dye, but the implementation of this disclosure is not limited to this.

[0238] In the display area DA, a cover layer 1518 can be disposed on the black matrix BM. The cover layer 1518 can protect the components beneath it. For example, the cover layer 1518 can be formed of an organic insulating material, but the implementation of this disclosure is not limited to this. For example, the cover layer 1518 can be formed of photoresist, polyimide (PI), photoacrylic-based materials, etc., but the implementation of this specification is not limited to this. For example, the cover layer 1518 can be a coating layer, an insulating layer, etc., but the implementation of this disclosure is not limited to this.

[0239] The polarizing layer 114 can be disposed on the cover layer 1518 via the first adhesive layer 112. The cover member 118 can be disposed on the polarizing layer 114 via the second adhesive layer 116. For example, the first adhesive layer 112 and the second adhesive layer 116 may include optically transparent adhesive (OCA), optically transparent resin (OCR), pressure-sensitive adhesive (PSA), etc., but the implementation of this disclosure is not limited to these.

[0240] According to an implementation of this disclosure, a plurality of pads PD can be disposed on a third insulating layer 1515c in a second non-display area NDA2. For example, at least a portion of the plurality of pads PD can be exposed from a passivation layer 1516. For example, the plurality of pads PD can be electrically connected to a fourth pad connection pattern PCP4 through contact holes in the third insulating layer 1515c.

[0241] An adhesive layer ACF can be disposed on multiple pads PD. The adhesive layer ACF can be an adhesive layer in which conductive balls are distributed in an insulating material, but the implementation of this disclosure is not limited to this. When heat or pressure is applied to the adhesive layer ACF, the conductive balls can be electrically connected to each other and have conductive properties during a portion of the heat or pressure applied. The adhesive layer ACF can be disposed between the multiple pads PD and the flexible printed circuit 102 to attach or bond the flexible printed circuit 102 to the multiple pads PD. For example, the adhesive layer ACF can be an anisotropic conductive film (ACF), but the implementation of this disclosure is not limited to this.

[0242] The flexible printed circuit 102 can be disposed on the adhesive layer ACF. The flexible printed circuit 102 can be electrically connected to multiple pads PD through the adhesive layer ACF. Therefore, the signal supplied from the flexible printed circuit 102 can be transmitted to the driver DRV of the display area DA through the multiple pads PD, the fourth pad connection pattern PCP4, the third pad connection pattern PCP3, the second pad connection pattern PCP2, and the first pad connection pattern PCP1.

[0243] Reference Figure 8 The display panel 110 according to the implementation of the present disclosure may include a substrate 210, a layer stack 1410 on a plurality of driver DRVs disposed on the substrate 210, an optical layer 1517a disposed between a plurality of light-emitting devices EDa, EDb, EDc, an adhesive layer 116 disposed on the optical layer 1517a and the plurality of light-emitting devices EDa, EDb, EDc, and a cover member 118 disposed on the adhesive layer 116.

[0244] Reference Figure 8 Multiple column lines CL can be set between the layer stack 1410 and multiple light-emitting devices EDa, EDb and EDc.

[0245] Reference Figure 8 Multiple line lines RL can be disposed on multiple light-emitting devices EDa, EDb, and EDc, as well as the optical layer 1517a. Multiple line lines RL can be disposed between multiple light-emitting devices EDa, EDb, and EDc, the optical layer 1517a, and the adhesive layer 116.

[0246] Reference Figure 8 The layer stack 1410 may include a plurality of protective layers 1513a, 1513b and 1514 disposed on the side and top surfaces of each of the plurality of driver DRVs, a plurality of insulating layers 1515a, 1515b and 1515c disposed on the plurality of protective layers, and a dam BNK disposed on the plurality of insulating layers.

[0247] The plurality of protective layers 1513a, 1513b and 1514 may further include a side protective layer 1513 disposed on the side surface of each of the plurality of driver DRVs and an upper protective layer 1514 disposed on the upper surface of each of the plurality of driver DRVs.

[0248] The side protective layer 1513 may include a first protective layer 1513a disposed on the substrate 210 and a second protective layer 1513b disposed on the first protective layer 1513a.

[0249] The upper protective layer 1514 may include a second protective layer 1513b and a third protective layer 1514 disposed on multiple driver DRVs.

[0250] The plurality of insulating layers 1515a, 1515b, and 1515c may include a first insulating layer 1515a disposed on the upper protective layer 1514 and a second insulating layer 1515b disposed on the first insulating layer 1515a. The plurality of insulating layers 1515a, 1515b, and 1515c may also include a third insulating layer 1515c disposed on the second insulating layer 1515b.

[0251] Each of the multiple light-emitting devices EDa, EDb and EDc can be disposed on the embankment BNK and positioned in the opening of the optical layer 1517a.

[0252] At least a portion of each of the multiple column lines CL can extend on the embankment BNK on the multiple insulating layers 1515a, 1515b and 1515c. Each of the multiple row lines RL can be disposed on the optical layer 1517a and the multiple light-emitting devices EDa, EDb and EDc.

[0253] The first electrode Ecl of each of the plurality of light-emitting devices EDa, EDb, and EDc can be electrically connected to at least a portion of the column line CL extending on the embankment BNK. The second electrode Erl of each of the plurality of light-emitting devices EDa, EDb, and EDc can be electrically connected to one of the plurality of row lines RL.

[0254] Reference Figure 8 The display panel 110 according to the implementation of this disclosure may include a plurality of line connection patterns LCP for connecting each of the plurality of lines, including a plurality of row lines RL and a plurality of column lines CL, to a plurality of drivers DRV.

[0255] The plurality of line connection patterns (LCPs) may include: a first line connection pattern LCP1 disposed on the side protective layer 1513; a second line connection pattern LCP2 disposed on the upper protective layer 1514 and electrically connected to the first line connection pattern LCP1 through a hole in the upper protective layer 1514; a third line connection pattern LCP3 disposed on the first insulating layer 1515a and electrically connected to the second line connection pattern LCP2 through a hole in the first insulating layer 1515a; and a fourth line connection pattern LCP4 disposed on the second insulating layer 1515b and electrically connected to the third line connection pattern LCP3 through a hole in the second insulating layer 1515b.

[0256] The first connection pattern LCP1 can be electrically connected to one of the multiple drivers DRV. The fourth connection pattern LCP4 can be electrically connected to at least one second electrode Erl of the multiple light-emitting devices EDa, EDb and EDc, or can be electrically connected to at least one first electrode Ecl of the multiple light-emitting devices EDa, EDb and EDc.

[0257] The side protection layer 1513 disposed on the side surface of each of the multiple driver DRVs may include two or more organic layers.

[0258] Each of the first protective layer 1513a and the second protective layer 1513b as the side protective layer 1513, the third protective layer 1514 as the upper protective layer 1514, and the first to third insulating layers 1515a, 1515b and 1515c can be formed of an organic layer.

[0259] Figure 9 This is a diagram illustrating a substrate 210 including multiple peripheral portions in a display device according to an implementation of the present disclosure.

[0260] Reference Figure 9 The display panel 110 may include multiple unit drive areas (UDAs). (See reference...) Figure 9 The unit driving region UDA is shown as a square. The substrate 210 may include a unit driving region UDA having a rectangular shape. The substrate 210 may have a rectangular shape, and in this case, the corners of the rectangular shape may have a rounded shape.

[0261] Reference Figure 9 The substrate 210 may include a plurality of peripheral portions 110a, 110b, 110c and 110d. Each of the plurality of peripheral portions 110a, 110b, 110c and 110d may have a circular shape or a curved shape.

[0262] Reference Figure 9The first peripheral portion 110a can be positioned at the upper right end of the substrate 210, and the second peripheral portion 110b can be positioned at the upper left end of the substrate 210. The third peripheral portion 110c can be positioned at the lower right end of the substrate 210, and the fourth peripheral portion 110d can be positioned at the lower left end of the substrate 210.

[0263] Reference Figure 9 It can be seen that the first outer part 110a has been magnified.

[0264] Reference Figure 9 The first peripheral portion 110a may include four unit drive regions UDA1, UDA2, UDA3 and UDA4.

[0265] The first unit driving region UDA1 may be the region at the upper left end of the first peripheral portion 110a. The first unit driving region UDA1 may be the region where the first driver DRV1 is disposed. The first unit driving region UDA1 may include a first sub-pixel arrangement region UDA1a and a first peripheral region UDA1b. The first sub-pixel arrangement region UDA1a may be the region where multiple sub-pixels SP are disposed. The first peripheral region UDA1b may be the region corresponding to the outer periphery of the first sub-pixel arrangement region UDA1a. The boundary between the first sub-pixel arrangement region UDA1a and the first peripheral region UDA1b may have a curved shape. The first peripheral region UDA1b may be the region where no light-emitting device ED is disposed. For example, the first peripheral region UDA1b may be a masking region of a non-display region NDA, a first non-display region NDA1, a curved region BA, or a black matrix BM, but is not limited thereto. Alternatively, the first peripheral region UDA1b may be a region where a portion of the substrate 210 is cut and removed, but is not limited thereto.

[0266] The second unit driving region UDA2 can be the region below the lower right end of the first peripheral portion 110a. The second unit driving region UDA2 can be the region where the second driver DRV2 is disposed. The second unit driving region UDA2 can include the second sub-pixel arrangement region UDA2a and the second peripheral region UDA2b.

[0267] The third unit driving region UDA3 can be the area at the upper right end of the first peripheral portion 110a. The third unit driving region UDA3 can be a region within it where no driver DRV is configured. The third unit driving region UDA3 can include a third sub-pixel arrangement region UDA3a and a third peripheral region UDA3b. The boundary between the third sub-pixel arrangement region UDA3a and the third peripheral region UDA3b can extend to the boundary between the first sub-pixel arrangement region UDA1a and the first peripheral region UDA1b. The boundary between the third sub-pixel arrangement region UDA3a and the third peripheral region UDA3b can extend to the boundary between the second sub-pixel arrangement region UDA2a and the second peripheral region UDA2b.

[0268] The fourth unit drive region UDA4 can be the area at the lower left end of the first peripheral portion 110a. The fourth unit drive region UDA4 can be the area in which the fourth driver DRV4 is disposed. Therefore, three drivers DRV1, DRV2 and DRV4 can be disposed in the first peripheral portion 110a.

[0269] In the third unit driving region UDA3, the third sub-pixel arrangement region UDA3a is narrower than the other sub-pixel arrangement regions UDA1a and UDA2a, and the arrangement of light-emitting devices ED can be less.

[0270] In other words, the third peripheral region UDA3b can be relatively wider than the other peripheral regions UDA1b and UDA2b. Therefore, there may be insufficient space in the third unit drive region UDA3 to house the driver DRV. Thus, the driver DRV may not need to be located in the third unit drive region UDA3.

[0271] Reference Figure 9 This can show multiple sub-pixels SP set in the third unit driving area UDA3.

[0272] Since the driver DRV is not set in the third unit driving region UDA3, the drivers DRV1 and DRV2, which are located in areas other than the third unit driving region UDA3, can drive multiple sub-pixels SP set in the third unit driving region UDA3.

[0273] Reference Figure 9 The first driver DRV1 can drive the first sub-pixel group SPG1 located in the third unit driving region UDA3. The second driver DRV2 can drive the second sub-pixel group SPG2 located in the third unit driving region UDA3.

[0274] For example, a first subpixel group SPG1 is illustrated to contain three subpixels SP, and a second subpixel group SPG2 is illustrated to contain at least six subpixels SP. However, the number of subpixels SP included in subpixel groups SPG1 and SPG2 is not limited to this.

[0275] Figure 10 This is a diagram illustrating the connection relationship between the driver DRV in a display device according to an implementation of the present disclosure and the sub-pixels SP disposed in the unit driving area UDA.

[0276] The connection relationships between the driver DRVa located in the central region 110e, the driver DRVb located in the peripheral region, and the sub-pixels located in the unit driving region UDA will be described. For ease of description, it will be assumed that the driver DRVa located in the central region 110e drives n light-emitting devices. In the peripheral region, the area without a driver DRV can be the non-driver region 110a3.

[0277] Refer to together Figure 9 and Figure 10 The driver DRVa of the central region 110e can be configured in the central region 110e to be electrically connected to n light-emitting devices ED of the sub-pixels disposed in the central region 110e.

[0278] In the central region 110e, the first light-emitting device EDa1 can be electrically connected between the first row line RLa1 and the first column line CLa1. The second light-emitting device EDa2 can be electrically connected between the second row line RLa2 and the first column line CLa1. Since the above characteristics are the same or substantially the same in the third light-emitting device EDa3 to the nth light-emitting device EDan, their repeated description will be omitted.

[0279] Next, the first peripheral portion 110a may include a first peripheral portion 110a1 and a second peripheral portion 110a2. The peripheral portion driver DRVb may be disposed in the first peripheral portion 110a1, and the peripheral portion driver DRVb may drive sub-pixels disposed in a unit driving region UDA other than the unit driving region UDA in which the peripheral portion driver DRVb is disposed.

[0280] For example, a peripheral driver DRVb can be located in the first peripheral portion 110a1. The peripheral driver DRVb located in the first peripheral portion 110a1 can be electrically connected to a sub-pixel of the first peripheral portion 110a1, or it can be electrically connected to a first sub-pixel group SPG1 located in the non-driver region 110a3. This is the same or substantially the same for the driver DRVb located in the second peripheral portion 110a2. The driver DRVb located in the second peripheral portion 110a2 can be electrically connected to a second sub-pixel group SPG2.

[0281] As described above, the number of sub-pixels driven by the peripheral portion driver DRVb can differ from the number of sub-pixels driven by the driver DRVa of the central region 110e. In other words, a portion of the substrate is removed from the plurality of peripheral portions 110a, 110b, 110c, and 110d to have a circular or curved shape, so the area of ​​the non-driver region 110a3 may be smaller than the area of ​​the central region 110e. Therefore, the number of sub-pixels driven by the peripheral portion driver DRVb may be relatively less than the number of sub-pixels driven by the driver DRVa of the central region 110e.

[0282] For example, the driver DRVa in the central region 110e drives the first light-emitting device EDa1 and the second light-emitting device EDa2, while the peripheral driver DRVb can drive only the third light-emitting device EDa3 to the nth light-emitting device EDaan, without driving the light-emitting device ED corresponding to the first light-emitting device EDa1 and the light-emitting device ED corresponding to the second light-emitting device EDa2.

[0283] In the first peripheral portion 110a1, the light-emitting device ED may not be connected between the first row line RLb1 and the first column line CLb1. Similarly, the light-emitting device ED may not be connected between the second row line RLb2 and the first column line CLa1. The third light-emitting device EDb3 may be electrically connected between the third row line RLb3 and the first column line CLa1. In the following description, the remaining fourth to nth light-emitting devices EDb4 may be electrically connected between their respective row lines and the first column line CLa1 in the same manner as in the central region 110e. Although the above describes the case where only the first light-emitting device EDa1 and the second light-emitting device EDa2 are not connected, this disclosure is not limited thereto.

[0284] Figure 11 This is a diagram illustrating the driving timing of the driver DRV of a display device according to an implementation of the present disclosure, located at peripheral portions 110a, 110b, 110c, and 110d. Figure 12 This is a diagram illustrating the operation of a controller in a display device according to an implementation of the present disclosure. Figure 13 This is a diagram illustrating data input for each area in a display device according to an implementation of the present disclosure.

[0285] Reference Figures 9 to 13 Let's explain them together.

[0286] Reference Figures 9 to 13First, during the (n-1)th driving period Tn-1 in the central region 110e, the voltage state of the (n-1)th row line RLan-1 can change from the second low potential voltage VSS2 to the first low potential voltage VSS1. In this case, the voltage state of the first column line CLa1 can change from the reset voltage VRST to the display voltage VEM. The voltage difference between the (n-1)th row line RLan-1 and the first column line CLa1 can become the display on-state voltage Von, where the (n-1)th light-emitting device EDan-1 can emit light. Afterward, the voltage state of the (n-1)th row line RLan-1 changes again from the first low potential voltage VSS1 to the second low potential voltage VSS2.

[0287] Next, during the nth driving period Tn, the same or substantially the same characteristics as those in the (n-1)th row line RLan are repeated in the nth row line RLan-1, and the voltage state of the first column line CLa1 is also repeated.

[0288] The light-emitting device ED can emit light when the voltage difference between its two ends is equal to or greater than the display turn-on voltage Von. Although the light-emitting device ED can be turned on simply by controlling the voltage difference between its two ends to be equal to the display turn-on voltage Von, the light-emitting device ED may turn on at unexpected times for various reasons.

[0289] Reference Figures 9 to 11 The driver DRVa of the aforementioned central region 110e can supply the display voltage VEM to the first column line CLa1 during the first driving period T1. Since the first light-emitting device EDa1 emits light during the first driving period T1, current flows through the first light-emitting device EDa1.

[0290] On the other hand, even if the peripheral driver DRVb supplies the display voltage VEM to the first column line CLb1 during the first driving period T1, the first light-emitting device EDb1 is absent, so current cannot flow through it. Therefore, current cannot flow out through the first light-emitting device EDb1, and consequently, the voltage level of the first column line CLb1 rises to the floating voltage Vf. When the voltage level of the first column line CLb1 rises to the floating voltage Vf, the voltage difference ΔVon1 between the first column line CLb1 and the first row line RLb1 increases, so the third light-emitting device EDb3 to the nth light-emitting device EDbn may emit light unexpectedly.

[0291] To prevent this, the peripheral driver DRVb can drive the first column line CLb1 by dividing it into a black drive period and a normal drive period.

[0292] For example, the black driving period can be the first driving period T1 and the second driving period T2, while the normal driving period can be the third driving period T3 to the nth driving period Tn.

[0293] Reference Figure 12 The control unit 250 or the second circuit component 240 (e.g., a timing controller) corresponding to the external system can supply black image data to multiple peripheral drivers DRVb so that output image data including black image data can be applied to the first column line CLb1 during the black drive period corresponding to the first drive period T1 and the second drive period T2. In other words, when the first row line RLb1 or the second row line RLb2 is supplied with a first low potential voltage VSS1, the output image data corresponding to the black image data can be applied to the first column line CLb1.

[0294] Reference Figure 11 During the normal drive periods corresponding to the third drive period T3 to the nth drive period Tn, the controller supplies normal data to the peripheral driver DRVb. Therefore, the voltage difference ΔVon3 between the third column line CLb3 and the first row line RLb1 can be the normal display turn-on voltage Von. Since this is the same for other row lines, its repeated description will be omitted.

[0295] Generally speaking, the black driving period can be shorter than the normal driving period, but it is not limited to this, and it can be determined according to the number of light-emitting devices (EDs) between the row lines and column lines.

[0296] As described above, multiple peripheral components can be driven according to black driving periods and normal driving periods. When the display device 100 has such Figure 13 When referring to the four peripheral portions shown, peripheral regions 110a_f, 110b_f, 110c_f, and 110d_f can refer to column lines and row lines in multiple peripheral portions that are not connected to the light-emitting device (ED). Therefore, the black image data applied during the black driving period can be the output image data with respect to peripheral regions 110a_f, 110b_f, 110c_f, and 110d_f.

[0297] In this way, when the display device 100 has multiple peripheral parts, the controller (such as 240 and 250) can modulate rectangular input image data from the outside into black image data, and the multiple peripheral part drivers DRVb can drive the output image data by dividing the driving period into a black driving period and a normal driving period.

[0298] Furthermore, even if there is no light-emitting device (ED) between the first row line RLb1 or the second row line RLb2 and the first column line CLb1, black image data will still be supplied to the first column line CLb1. Therefore, the voltage level of the first column line CLb1 will not rise to the floating voltage Vf, and the third light-emitting device EDb3 to the nth light-emitting device EDbn may not emit light. Additionally, even if the third light-emitting device EDb3 to the nth light-emitting device EDbn emits light during the black driving period, it will not be identified as a defect because it is in a black grayscale state. Alternatively, even if the third light-emitting device EDb3 to the nth light-emitting device EDbn emits light during the black driving period, it may be in a relatively lower grayscale state compared to the light-emitting devices ED of adjacent sub-pixels.

[0299] The implementation of the above disclosure will be briefly described below.

[0300] A display according to an implementation of the present disclosure includes: a substrate divided into a unit driving region, the unit driving region including a plurality of light-emitting devices, and including a plurality of peripheral portions and a central region different from the plurality of peripheral portions; a first driver disposed in the plurality of peripheral portions and driving the plurality of light-emitting devices in the plurality of peripheral portions; a second driver disposed in the central region and driving the plurality of light-emitting devices in the central region; and a controller driving the first driver and the second driver, wherein the number of light-emitting devices driven by the first driver is different from the number of light-emitting devices driven by the second driver.

[0301] In a display according to an implementation of the present disclosure, each of the plurality of peripheral portions includes a subpixel arrangement area provided with a plurality of light-emitting devices and a peripheral area outside the subpixel arrangement area.

[0302] In a display according to an implementation of the present disclosure, the subpixel arrangement area is divided into a peripheral driver area provided with a first driver and a non-driver area not provided with a first driver.

[0303] In a display according to an implementation of the present disclosure, a plurality of light-emitting devices in the peripheral driver region and non-driver region are driven by a first driver.

[0304] In a display according to an implementation of the present disclosure, data including black image data not supplied to a plurality of light-emitting devices is applied to a first driver.

[0305] In a display according to an implementation of the present disclosure, the first driver includes multiple column lines and multiple row lines connected to multiple light-emitting devices, and the light-emitting devices are not disposed between at least one column line and at least one row line.

[0306] In a display according to an implementation of the present disclosure, the number of light-emitting devices connected to at least one column line is different from the number of light-emitting devices connected to another column line.

[0307] In a display according to an implementation of the present disclosure, in a first driver, the number of light-emitting devices connected to at least one column line is less than the number of light-emitting devices connected to another column line.

[0308] In a display according to an implementation of the present disclosure, data including black image data is applied to at least one column line of light-emitting devices having a different number of connections.

[0309] In a display according to an implementation of this disclosure, black image data is not applied to multiple light-emitting devices.

[0310] In a display according to an implementation of the present disclosure, at least one column line with a different number of connected light-emitting devices is driven by dividing it into a black driving period and a normal driving period.

[0311] In a display according to an implementation of this disclosure, black image data is applied during a black driving period.

[0312] In a display according to an implementation of the present disclosure, during a black driving period, a plurality of light-emitting devices connected to at least one column line do not emit light.

[0313] In a display according to an implementation of this disclosure, the black driving period is shorter than the normal driving period.

[0314] In a display according to an implementation of this disclosure, the controller receives input data and modulates the input data to include black and white image data.

[0315] In a display according to an implementation of this disclosure, the controller supplies data including black image data to the first driver.

[0316] In a display according to an implementation of this disclosure, the controller stores position information for applying black image data.

[0317] In a display according to an implementation of the present disclosure, the controller is disposed outside the substrate.

[0318] In a display according to an implementation of the present disclosure, the peripheral portion includes a first unit driving region and a second unit driving region. The first unit driving region includes a first sub-pixel arrangement region and a first peripheral region. The second unit driving region includes a second sub-pixel arrangement region and a second peripheral region. The area of ​​the second sub-pixel arrangement region is smaller than the area of ​​the first sub-pixel arrangement region.

[0319] In a display according to an implementation of the present disclosure, the boundary between the second sub-pixel arrangement area and the second peripheral area has a curved shape.

[0320] Those skilled in the art will understand that this disclosure is not limited to the above-described implementation and drawings, and that various substitutions, modifications, and alterations can be made to the content of this disclosure without departing from the technical concept or scope thereof. Therefore, the scope of this disclosure is defined by the appended claims, and it is intended that all changes or modifications derived from the meaning, scope, and equivalent concepts of the claims fall within the scope of this disclosure.

Claims

1. A display device, the display device comprising: A substrate, the substrate including a display area, the display area including a plurality of corners and a central area different from the plurality of corners; Multiple light-emitting devices are disposed within the display area; A first driving circuit is disposed in the plurality of corners and configured to drive the plurality of light-emitting devices in the plurality of corners; A second driving circuit is disposed in the central region and configured to drive the plurality of light-emitting devices in the central region; as well as A controller configured to drive the first drive circuit and the second drive circuit. The number of light-emitting devices driven by the first driving circuit is different from the number of light-emitting devices driven by the second driving circuit.

2. The display device according to claim 1, wherein, Each of the plurality of corners includes a sub-pixel arrangement area where a subset of the plurality of light-emitting devices is disposed and a substrate removal area outside the sub-pixel arrangement area.

3. The display device according to claim 2, wherein, The sub-pixel arrangement area is divided into a corner driver area with the first driving circuit and a non-driver area without the first driving circuit.

4. The display device according to claim 3, wherein, The multiple light-emitting devices in the corner driver region and the non-driver region are driven by the first driving circuit.

5. The display device according to claim 3, wherein, The controller is configured to provide the first drive circuit with data including black image data, wherein the black image data is used to prevent light emission from at least one of the plurality of light-emitting devices.

6. The display device according to claim 1, wherein, The first driving circuit is connected to multiple column lines and multiple row lines, which are connected to the multiple light-emitting devices; and The light-emitting device is not located at the intersection of at least one column line and at least one row line.

7. The display device according to claim 6, wherein, For the first driving circuit, the number of light-emitting devices connected to the at least one column line is different from the number of light-emitting devices connected to the other column line.

8. The display device according to claim 6, wherein, For the first driving circuit, the number of light-emitting devices connected to the at least one column line is less than the number of light-emitting devices connected to the other column line.

9. The display device according to claim 7, wherein, The controller is configured to provide data, including black image data, to be applied to at least one column line of light-emitting devices having a different number of connections.

10. The display device according to claim 9, wherein, Applying the black image data to the at least one column line prevents light from emanating from any light-emitting device connected to the at least one column line.

11. A display device, the display device comprising: A substrate, the substrate including a display area, the display area including a central area and multiple peripheral portions, wherein the display area includes multiple row lines and multiple column lines; Multiple light-emitting devices, each light-emitting device being disposed at the intersection of one of the multiple row lines and one of the multiple column lines; A plurality of first driving circuits are disposed within the plurality of peripheral portions and connected to a first subset of the plurality of row lines and the plurality of column lines located within the plurality of peripheral portions; A plurality of second drive circuits are disposed within the central region and connected to a second subset of the plurality of row lines and the plurality of column lines located within the central region; and A controller, connected to the plurality of first drive circuits and the plurality of second drive circuits, Wherein, at least one of the peripheral portions includes a sub-pixel arrangement area and a peripheral area, and Specifically, within the outer perimeter area, no light-emitting device is placed at the intersection of the first column line and the first row line.

12. The display device according to claim 11, wherein, Each of the plurality of peripheral portions includes a sub-pixel arrangement area where the plurality of light-emitting devices are disposed and a peripheral area outside the sub-pixel arrangement area.

13. The display device according to claim 12, wherein, The sub-pixel arrangement area is divided into a first region including one of the plurality of first driving circuits and a non-driver region without driving circuits.

14. The display device according to claim 13, wherein, One of the plurality of first driving circuits disposed in the first region is connected to the light-emitting device located in the non-driving region.

15. The display device according to claim 11, wherein, The number of light-emitting devices connected to the first column line is less than the number of light-emitting devices connected to the second column line located in the central region.

16. The display device according to claim 11, wherein, The first column line and the third column line are connected to the same first driving circuit among the plurality of first driving circuits, and The number of light-emitting devices connected to the first column line is different from the number of light-emitting devices connected to the third column line.

17. The display device according to claim 16, wherein, The number of light-emitting devices connected to the first column line is less than the number of light-emitting devices connected to the third column line.

18. A method for driving a display device, the display device comprising a substrate having a display area, the display area comprising a plurality of row lines, a plurality of column lines, a plurality of light-emitting devices, and a controller, the plurality of light-emitting devices being disposed at the intersections of the row lines and the column lines, the method comprising the following steps: The controller identifies the target intersection point of the target column line and the target row line within the outer portion of the display area, where no light-emitting device is provided; as well as The drive circuit controlled by the controller applies a data signal to the target column line during the drive period corresponding to the target row line to prevent the voltage of the target column line from increasing to the floating voltage.

19. The method according to claim 18, wherein, The data signal includes black and white image data.

20. The method of claim 19, further comprising the step of: The controller receives the input image data for display. as well as The controller generates the black image data by modulating the input image data based on the identified target intersection.

Images