Display panel and display device
By employing a cascaded structure and an adjustment module controlled by the same clock signal line in the scan drive circuit, the power consumption and delay issues caused by multiple clock signal lines are solved, achieving low power consumption and fast signal switching.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUHAN TIANMA MICRO ELECTRONICS CO LTD
- Filing Date
- 2026-03-25
- Publication Date
- 2026-05-29
AI Technical Summary
The large number of clock signal lines in existing scan drive circuits makes it difficult to reduce power consumption, and the timing differences between clock signals cause output delays, affecting the working status of the display panel.
Multiple cascaded scanning drive circuits are used. The first output module and the second output module output signals of different levels at the same node, and the two adjustment modules are controlled by the same clock signal line, which reduces the number of clock signal line connections and realizes fast signal switching by working together with the adjustment modules.
It effectively reduces the number of clock signal lines in the scan drive circuit, lowers circuit power consumption, and improves the speed and accuracy of signal switching, thereby enhancing the display effect.
Smart Images
Figure CN122116786A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology
[0002] In existing designs, the scan drive circuit typically requires the participation of a partial clock signal to complete the output process of the required gate drive signal. Furthermore, each stage of the scan drive circuit requires a large number of clock signal lines, which is detrimental to reducing the power consumption of the scan drive circuit. In addition, the switching states of some transistors in existing scan drive circuits often require the coordinated action of multiple clock signals. The timing differences between these clock signals can easily cause these transistors to take a longer time to reach the required turn-on state, affecting the output process of the gate drive signal and thus interfering with the operation of the display panel. Summary of the Invention
[0003] This application provides a display panel and display device to solve the problems of difficulty in reducing power consumption and interference with the panel's working state caused by the large number of clock signal lines connected to the scanning drive circuit.
[0004] In view of this, this application provides a display panel including multiple cascaded scan drive circuits and pixel circuits, wherein the output terminal of the scan drive circuit outputs an electrical signal to the pixel circuit through a scan signal line.
[0005] The scan drive circuit includes: A first output module and a second output module; the output terminals of the first output module and the second output module, and the scan signal line are electrically connected to the same node. When the first output module is turned on, it outputs a first signal, and when the second output module is turned on, it outputs a second signal. The level of the first signal is lower than the level of the second signal.
[0006] A first adjustment module and a second adjustment module; the output terminal of the first adjustment module is electrically connected to the control terminal of the first output module, and the output terminal of the second adjustment module is electrically connected to the control terminal of the second output module; both the first adjustment module and the second adjustment module are electrically connected to the first clock signal line.
[0007] Based on the same inventive concept, this application also provides a display device, including the above-mentioned display panel.
[0008] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects: The functions of the first and second adjustment modules in controlling the on / off states of the first and second output modules, respectively, both require the participation of electrical signals received by the two adjustment modules. Among these, the clock signal is a relatively important type of electrical signal that the two adjustment modules need to receive. When both the first and second adjustment modules are electrically connected to the first clock signal line, it means that the clock signals required by the two adjustment modules can be provided by the same clock signal line (the first clock signal line). In this case, it can be understood that the scan drive circuit is connected to only one clock signal line. This design helps to minimize the number of clock signal lines connected to the scan drive circuit, thereby helping to reduce circuit power consumption. Attached Figure Description
[0009] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0010] Figure 1 This is an equivalent circuit diagram of a portion of the structure of a scan drive circuit in related technologies; Figure 2 for Figure 1 The diagram shows a portion of the electrical signals received by the scan drive circuit and the timing changes corresponding to the potentials at some nodes. Figure 3 A schematic diagram of a partial structure of a display panel provided in this application; Figure 4 An equivalent circuit diagram of a partial structure of a scanning drive circuit provided in this application; Figure 5 for Figure 4 The diagram shows a portion of the electrical signals received by the scan drive circuit and the timing changes corresponding to the potentials at some nodes. Figure 6 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application; Figure 7 This is a schematic diagram of a display device provided in this application. Detailed Implementation
[0011] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.
[0012] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.
[0013] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0014] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.
[0015] Figure 1 This is an equivalent circuit diagram of a portion of the structure of a scan drive circuit in related technologies. Figure 2 for Figure 1 The diagram shows a portion of the electrical signals received by the scan drive circuit and the timing changes corresponding to the potentials at some nodes. For ease of understanding, Figure 2 The diagram shows the timing changes of the electrical signals received by the scan drive circuit via the input signal line Ina, the first type of clock line CK, and the second type of clock line XCK, as well as the timing changes of the potentials of nodes N1, N2, and the output terminal OUT'.
[0016] In related technologies, such as Figure 1 As shown, the existing scan drive circuit 01' includes a first signal output transistor M1 and a second signal output transistor M2. Combined with... Figure 1 and Figure 2 When the first signal output transistor M1 is turned on, the output terminal OUT' of the existing scan drive circuit 01' outputs a low-level signal VGL; when the second signal output transistor M2 is turned on, the output terminal OUT' of the existing scan drive circuit 01' outputs a high-level signal VGH; then the gate drive signal output by the existing scan drive circuit 01' can switch between high and low levels.
[0017] The existing scan drive circuit 01' also includes a first control unit 011' and a second control unit 012'. Some transistors and capacitors within the first control unit 011' can participate in controlling the on / off state of the first signal output transistor M1, and some transistors and capacitors within the second control unit 012' can participate in controlling the on / off state of the second signal output transistor M2. Both the first control unit 011' and the second control unit 012' are electrically connected to the first type of clock line CK and the second type of clock line XCK, respectively. This means that both control units can control the on / off states of the first and second signal output transistors M1 and M2 with the participation of the clock signals transmitted by the first type of clock line CK and the second type of clock line XCK, respectively. This implies that each existing scan drive circuit 01' needs to be electrically connected to at least two clock signal lines (CK, XCK). This existing design results in a large number of clock signal lines connected to the existing scan drive circuit 01', which is detrimental to reducing circuit power consumption.
[0018] In addition, combined Figure 1 and Figure 2 The process by which the gate drive signal output by the existing scan drive circuit 01' switches from a high-level signal VGH to a low-level signal VGL (this process can correspond to...) Figure 2 The first period (in the process) can be carried out according to the following steps: First, under the influence of the on / off state of the transistors within the second control unit 012', the potential at the control terminal of the second signal output transistor M2 (which can be considered as the potential of node N1) rises, and the second signal output transistor M2 turns off, stopping the output of the high-level signal VGH to the output terminal OUT'. Simultaneously, the clock signal transmitted by the first type of clock line CK is at a low level. This clock signal controls the first type of transistor M3 in the first control unit 011' to turn on, and the low-level signal transmitted by the input signal line IN is written to node N2 (i.e., the control terminal of the first signal output transistor M1). Then, the first signal output transistor M1 turns on, and the low-level signal VGL begins to be written to the output terminal OUT'. However, at this time, the first signal output transistor M1 is not yet fully turned on, so the potential at the output terminal OUT' fails to reach the expected low-level standard quickly.
[0019] Subsequently, when the clock signal of the second type clock line XCK switches from high level to low level, with the participation of the third regulating capacitor C3', the potential of node N2 is further pulled down, the turn-on degree of the first signal output transistor M1 is further increased, and the potential of the output terminal OUT' is further pulled down until the expected low level standard is reached.
[0020] like Figure 2As shown, the potential change at the output terminal OUT' can be presented as a step-like pattern in the timing diagram. This phenomenon can easily cause the gate drive signal output by the existing scan drive circuit 01' to fail to quickly reach the expected level, resulting in output delay, which in turn can easily affect the working state of the pixel circuit. The above-mentioned output delay problem can be regarded as being caused by the timing difference between the first type of clock line CK and the second type of clock line XCK. It can be understood that the operation of the existing scan drive circuit 01' depends on a complex number of clock signals, which causes the above-mentioned output delay problem.
[0021] Furthermore, the existing scan drive circuit 01' may also include a second type transistor M4, a third type transistor M5, a fourth type transistor M6, a first adjustment capacitor C1', a second adjustment capacitor C2', a fourth adjustment capacitor C4', a fifth type transistor M7, a sixth type transistor M8, a seventh type transistor M9, an eighth type transistor M10, and a ninth type transistor M11, etc. The specific connection method of the above structure in the circuit is as follows: Figure 1 As shown, it will not be elaborated further here.
[0022] Figure 3 This is a schematic diagram of a partial structure of a display panel provided in this application. Figure 4 This application provides an equivalent circuit diagram of a partial structure of a scanning drive circuit. Figure 5 for Figure 4 The diagram shows a portion of the electrical signals received by the scan drive circuit and the timing changes corresponding to the potentials at some nodes. For ease of understanding, Figure 5 The diagram shows the timing changes of the electrical signals received by the scan drive circuit via the first input signal line and the first type of clock signal line, as well as the timing changes of the potentials of the first node X1, the second node X2, and the output terminal OUT.
[0023] To address the aforementioned problems, this application provides a display panel 10, such as... Figure 3 As shown, the display panel 10 includes multiple cascaded scan drive circuits 01 and pixel circuits 02. The output of the scan drive circuit 01 outputs an electrical signal to the pixel circuit 02 through a scan signal line 03. Specifically, the multiple pixel circuits 02 can be arranged in an array along a first direction X and a second direction Y. The pixel circuits 02 can receive the scan drive signal provided by the scan drive circuit 01 through the scan signal line 03 extending along the first direction X. This scan drive signal can be used to control the on / off state of some transistors in the pixel circuit 02. The same scan signal line 03 can provide scan drive signals to multiple pixel circuits 02 arranged along the first direction X.
[0024] like Figure 4As shown, the scan drive circuit 01 includes a first output module 11 and a second output module 21. The output terminals of the first output module 11, the second output module 21, and the scan signal line 03 are electrically connected to the same node. That is, the electrical signals output by the first output module 11 and the second output module 21 can be transmitted to the scan signal line 03 through the output terminal OUT of the scan drive circuit 01.
[0025] The first output module 11 includes a first output transistor T1. The first terminal of the first output transistor T1 is electrically connected to the first signal line 04, and the second terminal of the first output transistor T1 is electrically connected to the output terminal OUT of the scan drive circuit 01. When the first output transistor T1 is turned on, the electrical signal transmitted by the first signal line 04 can be written to the output terminal OUT through the first output transistor T1.
[0026] The second output module 21 includes a second output transistor T2. The first terminal of the second output transistor T2 is electrically connected to the second signal line 05, and the second terminal of the second output transistor T2 is electrically connected to the output terminal OUT of the scan drive circuit 01. When the second output transistor T2 is turned on, the electrical signal transmitted by the second signal line 05 can be written to the output terminal OUT through the second output transistor T2.
[0027] The first output transistor T1 and the second output transistor T2 can be turned on at different times.
[0028] like Figure 5 As shown, the first output module 11 outputs a first signal when it is turned on, and the second output module 21 outputs a second signal when it is turned on. The level of the first signal is lower than the level of the second signal. The first signal can be a low-level signal, and the second signal can be a high-level signal.
[0029] like Figure 4As shown, the scan drive circuit 01 also includes a first adjustment module 12 and a second adjustment module 22. The output terminal of the first adjustment module 12 is electrically connected to the control terminal of the first output module 11, and the output terminal of the second adjustment module 22 is electrically connected to the control terminal of the second output module 21. The electrical signal generated by the first adjustment module 12 can participate in controlling the switching state of the first output module 11, and the electrical signal generated by the second adjustment module 22 can participate in controlling the switching state of the second output module 21. Specifically, the electrical signal generated by the first adjustment module 12 can adjust the potential of the first node X1 (the potential of the first node X1 can be regarded as the control terminal potential of the first output module 11), and the electrical signal generated by the second adjustment module 22 can adjust the potential of the second node X2 (the potential of the second node X2 can be regarded as the control terminal potential of the second output module 21). Through the coordinated operation of the two adjustment modules, the first output module 11 and the second output module 21 can be turned on in a time-division manner, thereby enabling the scan drive circuit 01 to output scan drive signals (the aforementioned first signal and second signal) at different potentials.
[0030] Both the first adjustment module 12 and the second adjustment module 22 are electrically connected to the first clock signal line ck1.
[0031] In this embodiment, the functions of the first adjustment module 12 and the second adjustment module 22 in controlling the on / off states of the first output module 11 and the second output module 21, respectively, both require the participation of electrical signals received by the two adjustment modules. Among these, the clock signal is a relatively important type of electrical signal that the two adjustment modules need to receive. When both the first adjustment module 12 and the second adjustment module 22 are electrically connected to the first clock signal line ck1, it means that the clock signals that the two adjustment modules need to receive can be provided by the same clock signal line (first clock signal line ck1). In this case, it can be understood that the scan drive circuit 01 is connected to only one clock signal line. This design helps to minimize the number of clock signal lines connected to the scan drive circuit 01, thereby helping to reduce circuit power consumption.
[0032] Furthermore, the transistors in the scan drive circuit 01 can include P-type transistors and N-type transistors. For ease of understanding, this application only uses P-type transistors in the scan drive circuit 01 as an example, and does not mean that the transistor type in the scan drive circuit 01 in this application is limited to P-type.
[0033] Based on this, combined Figure 4 and Figure 5 In the scan drive circuit 01, the enable signal for each transistor can be a low-level signal, and the disable signal can be a high-level signal. Specifically, when the control terminal of a transistor receives an enable signal, the transistor is turned on; when the control terminal of a transistor receives a disable signal, the transistor is turned off.
[0034] Figure 6 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application.
[0035] Combination Figure 3 , Figure 4 and Figure 6 The control terminals of some transistors in the pixel circuit 02 can be electrically connected to the aforementioned scan signal line 03. Different scan signal lines 03 can transmit different scan drive signals. Correspondingly, the same pixel circuit 02 can receive scan drive signals output by multiple scan drive circuits 01.
[0036] For example, the pixel circuit 02 may include a first light-emitting control transistor 71, a second light-emitting control transistor 72, a data writing transistor 73, a first reset transistor 74, a second reset transistor 75, and a threshold grabbing transistor 76; the control terminals of the first light-emitting control transistor 71 and the second light-emitting control transistor 72 are electrically connected to the first control line V1, the control terminals of the data writing transistor 73 and the threshold grabbing transistor 76 are electrically connected to the second control line V2, and the control terminals of the first reset transistor 74 and the second reset transistor 75 are electrically connected to the third control line V3; the first control line V1, the second control line V2, and the third control line V3 are all scan signal lines 03, and the above control lines may correspond to different scan driving circuits 01.
[0037] Furthermore, the pixel circuit 02 may also include a driving transistor 77 and a storage capacitor 78, and some structures in the pixel circuit 02 may also be electrically connected to the first power signal line PVDD, the first reset line Vref1, the second reset line Vref2, and the data line Data, etc. For details on the specific connection methods of the aforementioned transistors, capacitors, and signal lines, please refer to [link to documentation]. Figure 6 This will not be elaborated upon here.
[0038] In some embodiments of this application, such as Figure 4 As shown, the scan drive circuit 01 also includes a first capacitor C1. The first plate of the first capacitor C1 is electrically connected to the control terminal of the first output module 11, and the second plate of the first capacitor C1 is electrically connected to the output terminal OUT of the scan drive circuit 01.
[0039] Combination Figure 4 and Figure 5 In the first stage S1, when the potential of the second node X2 is low, the second output module 21 is turned on, and the high-level signal transmitted by the second signal line 05 is written to the output terminal OUT. Then the potential of the output terminal OUT and the potential of the second plate of the first capacitor C1 can both be high. At the same time, the first output module 11 is in the off state.
[0040] like Figure 5As shown, in the first stage S1, when the potential of the second node X2 switches from low to high, the second output module 21 switches from on to off. Simultaneously, the clock signal transmitted by the first clock signal line ck1 becomes low, so the first transistor T3 in the first adjustment module 12 turns on, and the input signal transmitted by the first input signal line 06 (which is a low-level signal at this time) is written to the first node X1. In this case, the potential of the first plate of the first capacitor C1 and the control terminal potential of the first output transistor T1 are both low, so the first output transistor T1 turns on, and a potential difference is formed between the first and second plates of the first capacitor C1. Subsequently, the low-level signal transmitted by the first signal line 04 begins to be written to the second plate of the first capacitor C1, and the potential of the second plate decreases accordingly. However, under the influence of the self-drop characteristic of the first capacitor C1, the potential of the first plate is further pulled down, and the potential of the first node X1 decreases further, thus further increasing the degree of onset of the first output transistor T1. Therefore, in this embodiment, the first output transistor T1 can be "fully turned on" in a short time, which helps to ensure that the first signal transmitted by the first signal line 04 is completely written to the output terminal OUT in a short time. This helps to avoid step-like changes in the potential of the output terminal OUT, thereby improving the timing accuracy of the scan drive signal and improving the display effect.
[0041] In some embodiments of this application, such as Figure 4 As shown, the first adjustment module 12 includes a first transistor T3 and a second transistor T4.
[0042] The first terminal of the first transistor T3 is electrically connected to the first input signal line 06, the second terminal of the first transistor T3 is electrically connected to the first terminal of the second transistor T4, and the control terminal of the first transistor T3 is electrically connected to the first clock signal line ck1.
[0043] The second terminal of the second transistor T4 is electrically connected to the control terminal of the first output module 11. The control terminal of the second transistor T4 is electrically connected to the first signal line 04. The first signal line 04 transmits a first signal to the control terminal of the second transistor T4 and the input terminal of the first output module 11.
[0044] In this embodiment, the first signal can be a low-level signal. The second transistor T4 can remain on while receiving the first signal, allowing the input signal written by the first transistor T3 to be further written to the control terminal of the first output module 11. Furthermore, the first signal transmitted via the first signal line 04 can be multiplexed as the gate control signal of the second transistor T4. That is, the control terminal of the second transistor T4 and the input terminal of the first output module 11 can be electrically connected to the same signal line. This design simplifies the overall wiring design and reduces fabrication difficulty.
[0045] In some embodiments of this application, such as Figure 4 As shown, the first adjustment module 12 also includes a third transistor T5 and a second capacitor C2. The first end of the third transistor T5 is electrically connected to the first input signal line 06, the second end of the third transistor T5 is electrically connected to the first plate of the second capacitor C2, and the other plate of the second capacitor C2 is electrically connected to the second signal line 05.
[0046] The second signal line 05 transmits the second signal to the second capacitor C2 and the input terminal of the second output module 21. Considering that the second signal can be a high-level signal, the second plate of the second capacitor C2 and the input terminal of the second output module 21 can both correspond to a higher potential.
[0047] The control terminals of the third transistor T5 and the first transistor T3 are electrically connected to the first clock signal line ck1 at the same node.
[0048] In this embodiment, the third transistor T5 and the first transistor T3 can both correspond to the same first input signal line 06, and both transistors can also correspond to the same first clock signal line ck1. This design improves the utilization rate of some signal lines in the scan drive circuit 01 while ensuring the normal function of each structure in the scan drive circuit 01. It is beneficial to simplify the wiring design, minimize the number of signal lines connected to the scan drive circuit 01, and help reduce the power consumption of the circuit.
[0049] In some embodiments of this application, such as Figure 4 As shown, the second adjustment module 22 includes a fourth transistor T6. The first end of the fourth transistor T6 is electrically connected to the second signal line 05. The first end of the fourth transistor T6 and the input end of the second output module 21 both receive the second signal transmitted by the second signal line 05.
[0050] The second terminal of the fourth transistor T6 is electrically connected to the control terminal of the second output module 21. The control terminal of the fourth transistor T6 and the second terminal of the third transistor T5 are both electrically connected to the same plate of the second capacitor C2. When the third transistor T5 is turned on, the input signal transmitted by the first input signal line 06 can be further transmitted to the control terminal of the fourth transistor T6. Therefore, the on / off state of the fourth transistor T6 can be considered as being controlled by the input signal. After the input signal is written to the control terminal of the fourth transistor T6, under the action of the second capacitor C2 and the second signal transmitted by the second signal line 05, the potential of the control terminal of the fourth transistor T6 can be maintained for a period of time, meaning that the on / off state of the fourth transistor T6 can be relatively continuous.
[0051] In this embodiment, the second signal line 05, the second capacitor C2 and the third transistor T5 are used to control the opening and closing state of the fourth transistor T6. This helps to reuse some signal lines (such as the second signal line 05) and transistor structures, which is beneficial to simplifying the design of the scan drive circuit 01. At the same time, it ensures the control of the second adjustment module 22 over the working state of the second output module 21.
[0052] In some embodiments of this application, such as Figure 4 As shown, the second adjustment module 22 also includes a fifth transistor T7, a sixth transistor T8, and a third capacitor C3.
[0053] The first terminal of the fifth transistor T7 is electrically connected to the second signal line 05. Both the first terminal of the fifth transistor T7 and the input terminal of the second output module 21 receive the second signal transmitted by the second signal line 05. The second terminal of the fifth transistor T7 is electrically connected to the control terminal of the sixth transistor T8, and the control terminal of the fifth transistor T7 is electrically connected to the first input signal line 06.
[0054] The first terminal of the sixth transistor T8 is electrically connected to the first clock signal line ck1, the second terminal of the sixth transistor T8 is electrically connected to the control terminal of the second output module 21, the first plate of the third capacitor C3 is electrically connected to the first terminal of the sixth transistor T8, and the second plate of the third capacitor C3 is electrically connected to the control terminal of the sixth transistor T8.
[0055] When the input signal transmitted by the first input signal line 06 is a low-level signal, the fifth transistor T7 is turned on, and the second signal (high-level signal) transmitted by the second signal line 05 is written to the second plate of the third capacitor C3 and the control terminal of the sixth transistor T8. If the clock signal transmitted by the first clock signal line ck1 changes from a high level to a low level while the fifth transistor T7 is turned on, the potential of the control terminal of the sixth transistor T8 is pulled low due to the self-drop effect of the third capacitor C3, and the sixth transistor T8 is turned on. The clock signal of the first clock signal line ck1 (which is low at this time) can be written to the control terminal of the second output module 21, and the second output module 21 is turned on.
[0056] In this embodiment, some signal lines connected to each structure in the second adjustment module 22 (e.g., the first input signal line 06, the second signal line 05, and the first clock signal line ck1) can be regarded as secondary reuse of the signal lines connected to the first adjustment module 12. This design is beneficial to further reduce the number of signal lines connected to the scan drive circuit 01 and to reduce circuit power consumption.
[0057] In some embodiments of this application, combined with Figure 3 and Figure 4The first input signal line 06 transmits the electrical signal or start signal output by the previous scanning drive circuit 01.
[0058] For the first-level scan drive circuit 01, the input signal transmitted by the first input signal line 06 connected to it can be regarded as the start signal; for the nth-level scan drive circuit 01 (n is an integer and n≥2), the input signal transmitted by the first input signal line 06 connected to it can be the electrical signal output by the output terminal OUT of the previous-level scan drive circuit 01.
[0059] In some embodiments of this application, such as Figure 4 As shown, the second output module 21 includes a second output transistor T2 and a fourth capacitor C4. The first terminal of the second output transistor T2 and the first plate of the fourth capacitor C4 are both electrically connected to the second signal line O5, and the control terminal of the second output transistor T2 is electrically connected to the second plate of the fourth capacitor C4. The output terminal of the second output transistor T2 is electrically connected to a scan signal line, and the second signal line O5 is used to transmit a second signal.
[0060] In this embodiment, the second signal can be a high-level signal. The first plate of the fourth capacitor C4 is electrically connected to the second signal line O5, allowing the second signal to be written to the first plate. When a low-level signal is written to the control terminal of the second output transistor T2 (at which point the second output transistor T2 is turned on), a low-level signal is also written to the second plate. At this time, a potential difference is formed between the first and second plates, and this potential difference can persist due to the capacitance characteristics. If the second signal is a constant high-level signal, the second output transistor T2 can remain on for a relatively long time while the potential difference persists.
[0061] In some embodiments of this application, such as Figure 4 As shown, the first output module 11 includes a first output transistor T1. The first terminal of the first output transistor T1 is electrically connected to a first signal line 04, the second terminal of the first output transistor T1 is electrically connected to a scan signal line 03, and the control terminal of the first output transistor T1 is electrically connected to the first plate of a first capacitor C1. The first signal line 04 is used to transmit a first signal.
[0062] Among them, the first output transistor T1 is a P-type transistor.
[0063] In this embodiment, the first output transistor T1 is a P-type transistor, meaning that the enable signal corresponding to the first output transistor T1 can be a low-level signal. The lower the control terminal potential of the first output transistor T1, the greater the degree to which the first output transistor T1 is turned on. Therefore, in this embodiment, the self-drop effect of the first capacitor C1 helps to further lower the control terminal potential of the first output transistor T1 when the scan signal output by the output terminal OUT is switched, thereby improving the switching speed of the scan signal and thus improving the display effect.
[0064] In some embodiments of this application, both the first signal and the second signal are constant voltage signals.
[0065] In this embodiment, the first signal is a constant voltage signal and can be a low-level signal, which helps to keep the second transistor T4 in the first adjustment module 12 on for a long time, so that the input signal can be written to the control terminal of the first output transistor T1. The second signal is a constant voltage signal and can be a high-level signal, which helps to participate in maintaining the control terminal potentials of the second output transistor T2 and the fourth transistor T6, and maintain the working state of the scan drive circuit 01.
[0066] Figure 7 This is a schematic diagram of a display device provided in this application.
[0067] This application provides a display device 20, such as... Figure 7 As shown, the display device 20 includes the aforementioned display panel 10. The display device 20 can be a mobile phone, or it can also be an electronic device such as a computer or television.
[0068] In the display device 20 provided in this application embodiment, the number of signal lines required to be connected in the scan drive circuit 01 is significantly reduced, the circuit power consumption is effectively reduced, and the phenomenon of step-like timing changes when the scan signal output by the scan drive circuit 01 switches between high and low levels is effectively suppressed.
[0069] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.
Claims
1. A display panel, characterized in that, It includes multiple cascaded scan drive circuits and pixel circuits, and the output terminal of the scan drive circuit outputs an electrical signal to the pixel circuit through a scan signal line; The scanning drive circuit includes: A first output module and a second output module; the output terminals of the first output module, the second output module, and the scanning signal line are electrically connected to the same node; the first output module outputs a first signal when it is turned on, and the second output module outputs a second signal when it is turned on, wherein the level of the first signal is lower than the level of the second signal; A first adjustment module and a second adjustment module; the output terminal of the first adjustment module is electrically connected to the control terminal of the first output module, and the output terminal of the second adjustment module is electrically connected to the control terminal of the second output module; both the first adjustment module and the second adjustment module are electrically connected to the first clock signal line.
2. The display panel according to claim 1, characterized in that, The first output module further includes a first capacitor, the first plate of the first capacitor being electrically connected to the control terminal of the first output module, and the second plate of the first capacitor being electrically connected to the output terminal of the scanning drive circuit.
3. The display panel according to claim 1, characterized in that, The first adjustment module includes a first transistor and a second transistor; The first terminal of the first transistor is electrically connected to the first input signal line, the second terminal of the first transistor is electrically connected to the first terminal of the second transistor, and the control terminal of the first transistor is electrically connected to the first clock signal line. The second terminal of the second transistor is electrically connected to the control terminal of the first output module, and the control terminal of the second transistor is electrically connected to the first signal line; the first signal line transmits the first signal to the control terminal of the second transistor and the input terminal of the first output module.
4. The display panel according to claim 3, characterized in that, The first adjustment module further includes a third transistor and a second capacitor. The first end of the third transistor is electrically connected to the first input signal line, and the second end of the third transistor is electrically connected to one plate of the second capacitor. The second plate of the second capacitor is electrically connected to the second signal line. The second signal line transmits the second signal to the second capacitor and the input end of the second output module. The control terminal of the third transistor, the control terminal of the first transistor, and the first clock signal line are electrically connected to the same node.
5. The display panel according to claim 4, characterized in that, The second adjustment module includes a fourth transistor, the first terminal of which is electrically connected to the second signal line. The first terminal of the fourth transistor and the input terminal of the second output module both receive the second signal transmitted by the second signal line. The second terminal of the fourth transistor is electrically connected to the control terminal of the second output module, and the control terminal of the fourth transistor and the second terminal of the third transistor are both electrically connected to the same plate of the second capacitor.
6. The display panel according to claim 3, characterized in that, The second adjustment module also includes a fifth transistor, a sixth transistor, and a third capacitor; The first terminal of the fifth transistor is electrically connected to the second signal line, and both the first terminal of the fifth transistor and the input terminal of the second output module receive the second signal transmitted by the second signal line; the second terminal of the fifth transistor is electrically connected to the control terminal of the sixth transistor, and the control terminal of the fifth transistor is electrically connected to the first input signal line. The first terminal of the sixth transistor is electrically connected to the first clock signal line, the second terminal of the sixth transistor is electrically connected to the control terminal of the second output module, the first plate of the third capacitor is electrically connected to the first terminal of the sixth transistor, and the second plate of the third capacitor is electrically connected to the control terminal of the sixth transistor.
7. The display panel according to claim 6, characterized in that, The first input signal line transmits the electrical signal or start signal output by the scanning drive circuit of the previous stage.
8. The display panel according to claim 1, characterized in that, The second output module includes a second output transistor and a fourth capacitor; the first terminal of the second output transistor and the first plate of the fourth capacitor are both electrically connected to a second signal line, and the control terminal of the second output transistor is electrically connected to the second plate of the fourth capacitor; the output terminal of the second output transistor is electrically connected to the scan signal line; the second signal line is used to transmit the second signal.
9. The display panel according to claim 2, characterized in that, The first output module includes a first output transistor, a first terminal of the first output transistor is electrically connected to a first signal line, a second terminal of the first output transistor is electrically connected to the scan signal line, and a control terminal of the first output transistor is electrically connected to the first plate of the first capacitor; the first signal line is used to transmit the first signal. The first output transistor is a P-type transistor.
10. The display panel according to claim 1, characterized in that, Both the first signal and the second signal are constant voltage signals.
11. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.