Memory, storage system, electronic device, and operating method of memory

Abstract

The embodiment of the application discloses a kind of memory, storage system, electronic equipment and the operating method of memory, belong to storage technical field.The voltage generating subcircuit in the peripheral circuit of the memory not only includes VCP_REG, but also includes VCP test unit.Wherein, VCP_REG is used to provide VCP to the capacitance of storage unit when the memory is in user mode such as reading and writing data.VCP test unit is used to provide VCP to the capacitance of storage unit when the memory is in test mode such as testing SA performance.So, when the performance of SA needs to be tested, it is not necessary to provide adjustable VCP to the capacitance of storage unit by VCP_REG, but adjustable VCP is output by a separate VCP test unit, so that the change of VCP output by VCP test unit can be flexibly set according to test requirements.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, storage system, electronic device, and method of operating the memory. Background Technology

[0002] Dynamic random access memory (DRAM) consists of multiple memory cells arranged in an array and a sensing amplifier (SA). When reading data from a memory cell, the SA senses the difference between the voltage on the bit line (BL) to which the memory cell is coupled and the voltage on the complementary bit line. This difference is usually called the sensing margin, and the data stored in the memory cell is determined based on this sensing margin. Therefore, it is necessary to probe the performance of the SA in many scenarios. Summary of the Invention

[0003] This application provides an embodiment of a memory, a storage system, an electronic device, and a method for operating the memory, which can avoid the VCP fine-tuning range being too small or the fine-tuning accuracy being low during SA testing. The technical solution is as follows:

[0004] On the one hand, a memory is provided, the memory including peripheral circuitry and a memory array coupled to the peripheral circuitry, the memory array including a plurality of memory cells, each memory cell including a capacitor;

[0005] The peripheral circuit includes a voltage generating sub-circuit, which has a capacitor substrate voltage VCP power supply terminal. The VCP power supply terminal is used to couple the capacitor. The voltage generating sub-circuit includes a VCP adjustment unit VCP_REG and a VCP test unit. The output terminal of the VCP_REG and the output terminal of the VCP test unit are both coupled to the VCP power supply terminal.

[0006] The VCP_REG is used to: operate when the memory is in user mode, to output VCP to the VCP power supply terminal, where user mode is the mode in which the memory works normally;

[0007] The VCP test unit is used to: operate when the memory is in test mode, to output VCP to the VCP power supply terminal, wherein the test mode is a mode for testing the performance of the memory.

[0008] In one possible implementation, the voltage range of VCP that the VCP test unit can output is greater than the voltage range of VCP that the VCP_REG can output.

[0009] In one possible implementation, the VCP test unit can output a VCP voltage accuracy that is higher than that of the VCP_REG.

[0010] In one possible implementation, the VCP test unit has a reference voltage input terminal, and the VCP test unit includes a voltage divider adjustable circuit and an amplifier;

[0011] The first terminal of the voltage divider is coupled to the reference voltage input terminal, the second terminal of the voltage divider is grounded, the third terminal of the voltage divider is coupled to the input terminal of the amplifier, and the output terminal of the amplifier is coupled to the VCP power supply terminal.

[0012] In one possible implementation, the voltage divider adjuster includes a variable resistor.

[0013] In one possible implementation, the amplifier includes a rail-to-rail amplifier RTR_AMP.

[0014] In one possible implementation, the VCP test unit further includes a first fixed resistor, a first end of which is coupled to the reference voltage input terminal, and a second end of which is coupled to the first end of the voltage divider adjuster.

[0015] In one possible implementation, the VCP test unit further includes a second fixed resistor, the first end of which is coupled to the second end of the voltage divider adjustable resistor, and the second end of the second fixed resistor is used for grounding.

[0016] In one possible implementation, the peripheral circuit further includes a control logic sub-circuit, wherein the control terminal of the VCP_REG and the control terminal of the VCP test unit are both coupled to the control logic sub-circuit.

[0017] The control logic sub-circuit is used to: send a first enable signal to the VCP_REG when it is determined that the memory is in the user mode, or send a second enable signal to the VCP test unit when it is determined that the memory is in the test mode;

[0018] The VCP_REG is used to: receive the first enable signal and start working based on the first enable signal;

[0019] The VCP test unit is used to: receive the second enable signal and start working based on the second enable signal.

[0020] In one possible implementation, the VCP power supply terminal is used to be coupled to the capacitors of each memory cell in the memory array.

[0021] On the other hand, a storage system is provided, the storage system including the memory provided above;

[0022] And a controller coupled to the memory and configured to control the memory;

[0023] The controller is used to control the VCP_REG to output VCP when the memory is in user mode, or to control the VCP test unit to output VCP when the memory is in test mode.

[0024] In one possible implementation, the controller is used to:

[0025] When it is determined that the memory is in the user mode, a first instruction is sent to the control logic sub-circuit in the peripheral circuit, so that the control logic sub-circuit sends a first enable signal to the VCP_REG based on the first instruction. The first instruction is used to indicate that the memory is in the user mode, and the first enable signal is used to trigger the VCP_REG to start working.

[0026] When it is determined that the memory is in the test mode, a second instruction is sent to the control logic sub-circuit, so that the control logic sub-circuit sends a second enable signal to the VCP test unit based on the second instruction. The second instruction is used to indicate that the memory is in the test mode, and the second enable signal is used to trigger the VCP test unit to start working.

[0027] On the other hand, an electronic device is provided, which includes the aforementioned storage system.

[0028] On the other hand, a method for operating a memory is provided, the memory including peripheral circuitry and a memory array coupled to the peripheral circuitry, the memory array including a plurality of memory cells, each memory cell including a capacitor; the peripheral circuitry including a voltage generating subcircuit, the voltage generating subcircuit having a capacitor substrate voltage VCP power supply terminal, the VCP power supply terminal being used to couple to the capacitor, the voltage generating subcircuit including a VCP adjustment unit VCP_REG and a VCP test unit; the method includes:

[0029] When the control logic sub-circuit in the peripheral circuit determines that the memory is in the user mode, it sends a first enable signal to the VCP_REG. The VCP_REG receives the first enable signal and starts working based on the first enable signal to output VCP to the VCP power supply terminal; or,

[0030] When the control logic sub-circuit determines that the memory is in the test mode, it sends a second enable signal to the VCP test unit. The VCP test unit receives the second enable signal and starts working based on the second enable signal to output VCP to the VCP power supply terminal.

[0031] In one possible implementation, the memory is also coupled to a controller for controlling the memory;

[0032] The control logic sub-circuit in the peripheral circuitry determines that the memory is in the user mode, including:

[0033] When the control logic sub-circuit receives a first instruction from the controller, it determines that the memory is in the user mode.

[0034] The control logic sub-circuit determines that the memory is in the test mode, including:

[0035] When the control logic sub-circuit receives a second instruction from the controller, it determines that the memory is in the test mode.

[0036] In one possible implementation, after the control logic subcircuit sends a second enable signal to the VCP test unit when it determines that the memory is in the test mode, the method further includes:

[0037] The control logic sub-circuit sequentially sends multiple voltage adjustment commands to the VCP test unit. Each voltage adjustment command is used to indicate a voltage value, and the difference between the voltage values ​​indicated by two adjacent voltage adjustment commands is the reference step size.

[0038] When the VCP test unit receives a voltage adjustment command, it outputs VCP to the VCP power supply terminal based on the voltage value indicated by the voltage adjustment command.

[0039] In one possible implementation, each voltage adjustment instruction includes a bit sequence, the total number of bits in the bit sequence being a reference number, and the bit value corresponding to the bit sequence being used to indicate the voltage value indicated by the corresponding voltage adjustment instruction.

[0040] This application provides a memory whose peripheral circuitry includes a voltage generation sub-circuit comprising not only VCP_REG but also a VCP test unit. VCP_REG provides VCP to the capacitor of the memory cell when the memory is in user mode, such as when reading or writing data. The VCP test unit provides VCP to the capacitor of the memory cell when the memory is in test mode, such as when testing SA performance. Thus, when SA performance needs to be tested, it is not necessary to provide a finely adjustable VCP to the capacitor of the memory cell through VCP_REG; instead, a separate VCP test unit outputs a finely adjustable VCP. This allows for flexible setting of the VCP output by the VCP test unit according to test requirements, thereby avoiding excessively small adjustment range or low adjustment accuracy of VCP during SA testing. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of the structure of a memory provided in an embodiment of this application;

[0043] Figure 2 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0044] Figure 3 This is a schematic diagram of the structure of a peripheral circuit provided in an embodiment of this application;

[0045] Figure 4 This is a schematic diagram illustrating the working principle of a DRAM provided in an embodiment of this application;

[0046] Figure 5 This is a schematic diagram of the structure of a voltage generating sub-circuit provided in an embodiment of this application;

[0047] Figure 6 This is a schematic diagram of the structure of a VCP test unit provided in an embodiment of this application;

[0048] Figure 7 This is a schematic diagram of another VCP test unit provided in an embodiment of this application;

[0049] Figure 8 This is a schematic diagram of another VCP test unit provided in an embodiment of this application;

[0050] Figure 9This is a schematic diagram of another VCP test unit provided in an embodiment of this application;

[0051] Figure 10 This is a schematic diagram of another VCP test unit provided in an embodiment of this application;

[0052] Figure 11 This is a schematic diagram of another peripheral circuit provided in an embodiment of this application;

[0053] Figure 12 This is a comparative diagram of VCP_REG and VCP output by a VCP test unit provided in an embodiment of this application;

[0054] Figure 13 This is a schematic diagram of the architecture of a storage system provided in an embodiment of this application;

[0055] Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0056] Figure 15 This is a flowchart of a memory operation method provided in an embodiment of this application. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0058] The memory and related circuits involved in the embodiments of this application will be explained below.

[0059] Figure 1 This is a schematic diagram of the structure of a memory 10 provided in an embodiment of this application.

[0060] The memory 10 in this embodiment can be a volatile memory, such as DRAM or Static Random-Access Memory (SRAM). Optionally, the memory 10 can also be a non-volatile memory, such as Re-random access memory (ReRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory (which can also be considered a subset of EEPROM), Ferroelectric Random Access Memory (FRAM), and Magnetoresistant Random Access Memory (MRAM). Optionally, the memory 10 can also be other semiconductor elements capable of storing information. Each type of memory can have different configurations, which will not be described in detail here.

[0061] like Figure 1 As shown, the memory 10 typically includes a memory array 101 and peripheral circuitry 102. The peripheral circuitry 102 is coupled to the memory array 101.

[0062] In response to a control signal received from peripheral circuitry 102, storage array 101 can perform operations such as writing and reading data. In some embodiments, storage array 101 may include multiple storage cells. This application does not limit the specific arrangement of storage array 101.

[0063] The following example, using DRAM as an example of memory 10, further illustrates the memory provided in the embodiments of this application.

[0064] Figure 2 This is a schematic diagram of another memory structure provided in an embodiment of this application. For example... Figure 2 As shown, the memory includes a memory array 101, peripheral circuitry 102 coupled to the memory array 101, and multiple word lines (WL) and multiple bit lines (BL).

[0065] The memory array 101 includes multiple memory cells 110 arranged in an array, each memory cell including a transistor and a capacitor. It should be noted that... Figure 2 The following description uses a 1T1C (i.e., one memory cell includes one transistor and one capacitor) DRAMA as an example. Optionally, the embodiments of this application can also be applied to other types of DRAM, such as 2T1C or 3T1C DRAM, which will not be illustrated here.

[0066] like Figure 2 As shown, multiple storage cells 110 located in the same row are coupled to a WL, and multiple storage cells located in the same column are coupled to a BL.

[0067] Peripheral circuitry 102 (also referred to as control and sensing circuitry) may include any suitable digital, analog, and / or mixed-signal circuitry for facilitating the operation of the memory array. For example, peripheral circuitry may include page buffers, decoders (e.g., row decoders and column decoders), SAs, drivers (e.g., word line drivers), input / output (I / O) circuitry, charge pumps, voltage sources or generators, current or voltage references, any portion of the aforementioned functional circuitry (e.g., sub-circuits), or one or more of any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). As an example, the peripheral circuitry uses complementary metal-oxide-semiconductor (CMOS) technology.

[0068] Figure 3 This is a schematic diagram of the structure of a peripheral circuit 102 provided in an embodiment of this application, as shown below. Figure 3 As shown, the peripheral circuit 102 includes a sense amplifier (SA) and an IO (input / output) circuit 121, a column decoder 122, a row decoder 123, a control logic sub-circuit 124, a refresh counter 125, a multiplexer (MUX) 126, a row address latch 127, a column address latch 128, a data input buffer 129, and a data output buffer 130.

[0069] The control logic sub-circuit 124 can be coupled to various circuits in the peripheral circuitry and is configured to control the operation of each circuit. For example, the control logic sub-circuit 124 is used to parse control signals sent by an external controller to trigger read and write operations on the memory array 101.

[0070] The sense amplifier and I / O circuit 121 can be configured to read data from the memory array 101 and program (write) data to the memory array 101 according to control signals from the control logic sub-circuit 124, and store the relevant data to the data output buffer 130. The sense amplifier and I / O circuit 121 can also receive data to be written from the data input buffer 129 and store a page of programming data (i.e., write data) to be programmed into a page of the memory array 101.

[0071] The refresh counter 125 can be configured to record the row that needs to be refreshed next, and the refresh counter 125 will be updated after a refresh operation is completed. The row address latch 127 can be configured to receive the row address to be operated on. The MUX 126 is used to select a row address from the refresh counter 125 and the row address latch 127 as the current row address to be operated on.

[0072] Row decoder 123 can be configured to map row addresses to specific word lines, ultimately opening the specified row. Column decoder 122 can be configured to map column addresses to specific CSLs (Column Selection Lines), ultimately selecting the specific column.

[0073] In addition, such as Figure 3 As shown, the peripheral circuitry 102 also includes a voltage generation sub-circuit 131, which can also be referred to as a voltage generator or voltage source. The voltage generation sub-circuit 131 is used to power the memory array and other components in the peripheral circuitry. For example, the voltage generation sub-circuit 131 is configured to be controlled by a control logic sub-circuit 124 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 101.

[0074] In this embodiment, the voltage generating sub-circuit 131 includes a cell cap subplate voltage (VCP) power supply terminal, which is used to provide VCP to the substrate of the capacitor of each memory cell in the memory array. In other words, the VCP power supply terminal in the voltage generating sub-circuit 131 is used to couple to the substrate of the capacitor of each memory cell in the memory array. Figure 3 (The connection relationship is not shown in the diagram). VCP will be explained in detail later, so it will not be discussed here.

[0075] It should be noted that, Figure 3 The peripheral circuit shown is an example and does not constitute a limitation on the peripheral circuits provided in the embodiments of this application. It should be understood that in some examples, the peripheral circuit may also include... Figure 3 Additional components not shown in the diagram will not be illustrated here.

[0076] The above description of the memory-related hardware embodiments has similar beneficial effects to the method embodiments described below. For technical details not disclosed in the memory-related hardware embodiments, please refer to the description of the method embodiments in this application for understanding.

[0077] For ease of understanding later, the following will use... Figure 4The working principle of DRAM will be illustrated using an example.

[0078] like Figure 4 As shown, each memory cell 110 includes a transistor M0 and a capacitor C0. The gate of the transistor M0 is coupled to WL, its first terminal is coupled to BL, and its second terminal is coupled to one end of the capacitor C0. The other end of the capacitor C0 (i.e., the substrate) is used for coupling... Figure 3 The voltage generating sub-circuit 131 shown provides the VCP power supply terminal.

[0079] Continue to refer to Figure 4 Each WL is coupled to the gate of a transistor M0 in a plurality of memory cells 110 located in the same row, and each BL is coupled to the first electrode of a plurality of memory cells 110 located in the same column. Furthermore, each pair of adjacent BLs can be complementary bit lines and can be coupled to the same SA.

[0080] Understandably, when data needs to be written to a certain memory cell 110, an enable voltage can be applied to WL, which is coupled to the memory cell 110, to turn on the transistor M0 in the memory cell 110. At the same time, the data to be written can be loaded to BL, which is coupled to the memory cell 110, and the data to be written can then be written to the capacitor C0 through the turned-on transistor M0.

[0081] When data stored in a memory cell 110 needs to be read, the BL coupled to the memory cell 110 and its complementary bit line BLB can be pre-charged first. Then, an enable voltage can be applied to the WL coupled to the memory cell 110 to turn on the transistor M0 in the memory cell 110. After transistor M0 is turned on, capacitor C0 can share charge with BL. Specifically, if the data stored in capacitor C0 is 1, the voltage of BL can increase slightly based on this charge-sharing operation; if the data stored in capacitor C0 is 0, the voltage of BL can decrease slightly based on this charge-sharing operation. SA can then sense and amplify the voltage difference between BL and BLB based on the voltage of the complementary bit line BLB, i.e., obtain a sensing margin, thereby enabling the reading of data stored in capacitor C0.

[0082] Understandably, reference Figure 4 The storage array 101 may include multiple blocks, and BL and BLB may be coupled to storage cells 110 in different blocks. For example Figure 3 The BL in block B1 can be coupled to the storage unit 110 in block B1, and the BLB can be coupled to the storage unit 110 in block B2.

[0083] based on Figure 4As illustrated in the working principle, the ability of the sensing margin (SA) to acquire sensing margin has a crucial impact on the memory's ability to correctly read data. Therefore, in some scenarios, to probe the performance of the SA, the minimum sensing margin that the SA can sense can be measured, i.e., the bottom sensing margin. The sensing margin of the SA is significantly related to the value of VCP provided by the cell cap sub-plate voltage (VCP) power supply terminal coupled to the memory cell. Therefore, in measuring the bottom sensing margin of the SA, it is necessary to fine-tune the VCP value of the VCP power supply terminal coupled to the memory cell, thereby measuring the bottom sensing margin of the SA under different VCP values.

[0084] Based on this, embodiments of this application provide a memory whose peripheral circuitry includes not only VCP_REG but also a VCP test unit. VCP_REG provides VCP to the capacitor of the memory cell when the memory is in user mode, such as when reading or writing data. The VCP test unit provides VCP to the capacitor of the memory cell when the memory is in test mode, such as when testing SA performance. Thus, when SA performance needs to be tested, it is not necessary to provide a finely adjustable VCP to the capacitor of the memory cell through VCP_REG; instead, a separate VCP test unit outputs a finely adjustable VCP. This allows for flexible setting of the VCP output by the VCP test unit according to test requirements, thereby avoiding excessively small adjustment range or low adjustment accuracy of VCP during SA testing.

[0085] The internal structure of the memory provided in the embodiments of this application will be further described below.

[0086] In this embodiment, the memory includes peripheral circuitry and a memory array coupled to the peripheral circuitry. The memory array includes multiple memory cells, and each memory cell includes a capacitor.

[0087] The peripheral circuit includes a voltage generating sub-circuit. Figure 5 This is a schematic diagram of a voltage generating sub-circuit provided in an embodiment of this application. For example... Figure 5 As shown, the voltage generating sub-circuit has a VCP power supply terminal 51, which is used to couple the capacitors of the memory cells in the memory array.

[0088] Continue to refer to Figure 5 The voltage generation sub-circuit includes a VCP adjustment unit (VCP_REG) 52 and a VCP test unit 53. The output terminals of both VCP_REG 52 and VCP test unit 53 are coupled to the VCP power supply terminal 51.

[0089] It is understood that the memory array includes multiple memory cells. Therefore, the VCP power supply terminal used to couple the capacitors of the memory cells in the memory array can be understood as: the VCP power supply terminal 51 is used to couple to the capacitors of each memory cell in the memory array. In other words, the substrates of the capacitors of all memory cells in the memory array are coupled to the VCP power supply terminal 51, so that VCP is output to the substrates of the corresponding capacitors through the VCP power supply terminal 51.

[0090] In this embodiment, VCP_REG 52 is used to: operate when the memory is in user mode, to output VCP to the VCP power supply terminal 51, where user mode is the normal operating mode of the memory; VCP test unit 53 is used to: operate when the memory is in test mode, to output VCP to the VCP power supply terminal 51, where test mode is the mode for testing the performance of the memory.

[0091] User mode refers to the mode in which the memory operates normally, such as the mode in which the memory reads and writes data normally. Test mode refers to the mode in which the memory tests its performance, such as the mode in which the memory operates when testing the performance of the Storage Module (SA).

[0092] Therefore, in this embodiment, the voltage generation sub-circuit for outputting VCP includes not only VCP_REG but also a VCP test unit. Thus, when testing the performance of SA, it is unnecessary to provide a finely tuned VCP to the capacitor of the storage cell via VCP_REG. Instead, a separate VCP test unit outputs a finely tuned VCP. This allows for flexible settings of the VCP output by the VCP test unit according to testing requirements, thereby avoiding excessively small adjustment ranges or low adjustment accuracy of VCP during SA testing.

[0093] In some embodiments, the voltage range of VCP that the VCP test unit can output is greater than the voltage range of VCP that VCP_REG can output.

[0094] During the testing of the low-level sensing margin of SA, it is necessary to fine-tune the VCP output from the VCP power supply terminal. In some embodiments, during the testing of the low-level sensing margin of SA, the VCP output from the VCP power supply terminal can be fine-tuned from one voltage value to another, and the change in the sensing margin of SA is detected during this process. The range between these two voltage values ​​is the voltage range of VCP output by the VCP test unit.

[0095] In this embodiment of the application, in order to accurately test the low value of the sensing margin of SA, the voltage range of VCP that the VCP test unit can output is designed to be as large as possible, so as to avoid the following problem: because the voltage range of VCP that the VCP test unit can output is too small, the low value of the sensing margin of SA tested is not accurate enough.

[0096] For example, the VCP voltage range that a typical VCP_REG can output is 367.5mV to 685.6mV, while the VCP test unit provided in this application embodiment can output a VCP voltage range of 100.4mV to 946.7mV.

[0097] In some embodiments, the voltage accuracy of VCP output by the VCP test unit is higher than that of VCP output by VCP_REG.

[0098] In the process of testing the low value of the sensing margin of SA, it is necessary to fine-tune the VCP output of the VCP power supply terminal. In some embodiments, the VCP output of the VCP power supply terminal is usually adjusted step by step according to a fixed fine-tuning step size. Therefore, the voltage accuracy of VCP that the VCP test unit or VCP_REG can be understood as: the fine-tuning step size designed for the VCP output of the VCP power supply terminal during the testing of memory performance.

[0099] In order to accurately test the low value of the sensing margin of SA, the voltage accuracy of VCP output by the VCP test unit should be designed to be as high as possible, that is, the fine-tuning step size should be designed to be as small as possible, so as to avoid the following problem: the voltage accuracy of VCP output by the VCP test unit is too low, resulting in an inaccurate low value of the sensing margin of SA.

[0100] For example, the VCP fine-tuning step size that VCP can output by VCP is generally 10mV, while the VCP test unit provided in this application embodiment can reduce the VCP fine-tuning step size to 6.7mV, thereby improving the voltage accuracy of VCP that the VCP test unit can output.

[0101] Specifically, VCP_REG 52 includes a low dropout regulator (LDO) to output VCP to the VCP power supply terminal 51 when the memory is operating normally. This application embodiment does not limit the internal structure of VCP_REG.

[0102] The structure of the VCP test unit 53 provided in the embodiments of this application will be described in detail below.

[0103] Figure 6This is a schematic diagram of the structure of a VCP test unit provided in an embodiment of this application. Figure 6 As shown, the VCP test unit 53 has a reference voltage input terminal 531, and the VCP test unit 53 includes a voltage divider adjustable unit 532 and an amplifier 533.

[0104] Among them, the first terminal a1 of the voltage divider adjustable unit 532 is coupled to the reference voltage input terminal 531, the second terminal a2 of the voltage divider adjustable unit 532 is used for grounding, the third terminal a3 of the voltage divider adjustable unit 532 is coupled to the input terminal b1 of the amplifier 533, and the output terminal b2 of the amplifier 533 is coupled to the VCP power supply terminal 51.

[0105] The reference voltage input terminal 531 is used to input a reference voltage with a fixed value, which may be labeled V-ref. For example, the reference voltage may be 1.2V.

[0106] The voltage divider adjustable unit 532 is used to output a divided voltage of the reference voltage to the amplifier 533 by means of voltage division, and the voltage divider adjustable unit 532 can adjust the magnitude of its own output divided voltage, so that the VCP test unit can gradually output the changing VCP within a certain voltage range according to a certain fine adjustment step size.

[0107] Amplifier 533 is used for impedance matching, thereby preventing the voltage output from the third terminal a3 of the voltage divider from being affected by other components connected after the VCP power supply terminal 51. In other words, amplifier 533 acts as an isolation unit. Figure 6 As shown, amplifier 533 includes a positive input terminal, a negative input terminal, and an output terminal. Figure 6 The positive input terminal of amplifier 533 is labeled b1, and the output terminal of amplifier 533 is labeled b2. The third terminal a3 of voltage divider adjustable circuit 532 is connected to the positive input terminal b1 of amplifier 533, and the negative input terminal of amplifier 533 is connected to the output terminal b2. Thus, amplifier 533 acts as a voltage follower, meaning the voltage at output terminal b2 of amplifier 533 changes in accordance with the voltage at the positive input terminal b1, and the voltage at output terminal b2 of amplifier 533 is not affected by other components connected after the VCP power supply terminal 51.

[0108] like Figure 6 As shown, in some embodiments, the voltage divider 532 includes a variable resistor. That is, in the embodiments of this application, the voltage division of the reference voltage input to the reference voltage input terminal 531 can be finely adjusted by adjusting the resistance value of the variable resistor to output a gradually changing VCP.

[0109] In this application, technicians can design the resistance adjustment step size of the variable resistor based on the requirements of the VCP fine-tuning step size. For example, if the relevant test requires a VCP fine-tuning step size of 5mV, the technician can design the resistance adjustment step size of the variable resistor based on the impedance of each component in the VCP test unit. That is, the technician can design the step size for each resistance adjustment of the variable resistor so that the change in VCP output by the VCP test unit is 5mV. This application does not provide a detailed description of this aspect in its embodiments.

[0110] Alternatively, in the embodiments of this application, the voltage divider adjustable device 532 can be implemented not only by a variable resistor, but also by devices such as MOSFETs or diodes, which will not be described in detail here.

[0111] Additionally, in some embodiments, amplifier 533 includes a rail-to-rail amplifier (RTR_AMP). Figure 7 This is a schematic diagram of another VCP test unit provided in an embodiment of this application. For example... Figure 7 As shown, in Figure 6 Based on the VCP test unit shown, the amplifier is RTR_AMP.

[0112] The RTR_AMP is a special type of operational amplifier whose input and output signals can approach the upper and lower limits of the supply voltage (i.e., the voltage at the third terminal a3 of the voltage divider 532), also known as the "rails". Normally, the output range of an amplifier is limited by its supply voltage range. When the output signal approaches the upper and lower limits of the supply voltage (i.e., the voltage at the third terminal a3 of the voltage divider 532), a typical operational amplifier will experience distortion or truncation. However, the RTR_AMP, through special circuit design and technology, allows the output signal to approach the upper and lower limits of the supply voltage, thus avoiding distortion problems.

[0113] In other words, RTR_AMP can make the upper and lower limits of the voltage range of VCP output by the VCP test unit as close as possible to the upper and lower limits of the voltage range of the third terminal a3 of the voltage divider 532.

[0114] Figure 8 This is a schematic diagram of another VCP test unit provided in an embodiment of this application. For example... Figure 8 As shown, in Figure 6 Based on the VCP test unit shown, the VCP test unit 53 further includes a first fixed resistor Rt, the first end of the first fixed resistor Rt is coupled to the reference voltage input terminal 531, and the second end of the first fixed resistor Rt is coupled to the first terminal a1 of the voltage divider adjustable unit 532.

[0115] By using the first fixed resistor Rt, the lower limit of the voltage output from the third terminal a3 of the voltage divider 532 can be prevented from being 0, which also prevents the lower limit of the voltage input to the amplifier 533 from being 0.

[0116] For example, if the reference voltage input at the reference voltage input terminal 531 is 1.2V, and there is no first fixed resistor Rt, the lower limit of the voltage output at the third terminal a3 of the voltage divider 532 is 0. Through the voltage division effect of the first fixed resistor Rt, the lower limit of the voltage output at the third terminal a3 of the voltage divider 532 can be raised to 100.4mV, so as to avoid the voltage output at the third terminal a3 of the voltage divider 532 being too small, which would cause the amplifier 533 to malfunction.

[0117] Figure 9 This is a schematic diagram of another VCP test unit provided in an embodiment of this application. For example... Figure 9 As shown, in Figure 6 Based on the VCP test unit shown, the VCP test unit 53 also includes a second fixed resistor Rb. The first end of the second fixed resistor Rb is coupled to the second end a2 of the voltage divider adjustable unit 532, and the second end of the second fixed resistor Rb is used for grounding.

[0118] The second fixed resistor Rb can prevent the upper limit of the voltage output from the third terminal a3 of the voltage divider 532 from being too large, which also prevents the upper limit of the voltage input to the amplifier 533 from being too large.

[0119] For example, if the reference voltage input at the reference voltage input terminal 531 is 1.2V, and there is no second fixed resistor Rb, the upper limit of the voltage output at the third terminal a3 of the voltage divider 532 is 1200mV. Through the voltage division effect of the second fixed resistor Rb, the upper limit of the voltage output at the third terminal a3 of the voltage divider 532 can be reduced to 946.7mV, so as to avoid the voltage output at the third terminal a3 of the voltage divider 532 being too large and exceeding the voltage withstand limit of the amplifier 533.

[0120] Figure 10 This is a schematic diagram of another VCP test unit provided in an embodiment of this application. Figure 10 Taking the VCP test unit 53, which includes a reference voltage input terminal 531, a first fixed resistor Rt, a variable resistor R, a second fixed resistor Rb, and RTR_AMP, as an example. Regarding... Figure 10 The connection relationships and functions of the various components can be referred to in the aforementioned embodiments, and will not be repeated here.

[0121] Furthermore, the above describes how the VCP test unit outputs a gradually changing VCP using a single reference voltage input terminal and a voltage divider adjuster. Optionally, in other embodiments, multiple reference voltage input terminals can be directly configured in the VCP test unit. The multiple reference voltages input at these terminals can vary gradually in steps, so that these multiple reference voltages can be directly output as VCP sequentially. This will not be described in detail here.

[0122] It is understood that the VCP test unit may also include more or fewer other components, which will not be described in detail in this embodiment of the application.

[0123] In addition, based on Figure 3 As shown in the peripheral circuit diagram, the peripheral circuit also includes a control logic sub-circuit, which is used to control the output voltage of the voltage generation sub-circuit. The following section discusses... Figure 5 The relationship between the voltage generation sub-circuit shown and the control logic sub-circuit in the peripheral circuit is explained in detail.

[0124] Figure 11 This is a schematic diagram of another peripheral circuit provided in an embodiment of this application. For example... Figure 11 As shown, the control terminals of VCP_REG and VCP test unit are both coupled to the control logic sub-circuit.

[0125] The control logic sub-circuit is used to: send a first enable signal to VCP_REG when it is determined that the memory is in user mode, or send a second enable signal to the VCP test unit when it is determined that the memory is in test mode.

[0126] Accordingly, VCP_REG is used to: receive a first enable signal and start working based on the first enable signal; the VCP test unit is used to: receive a second enable signal and start working based on the second enable signal.

[0127] The first enable signal enables VCP_REG. In other words, VCP_REG is in a closed state before receiving the first enable signal and does not output VCP to the VCP power supply. VCP_REG will only become active after receiving the first enable signal, and will then output VCP to the VCP power supply.

[0128] For example, the first enable signal includes a voltage signal used to activate various devices in VCP_REG, such as LDOs. It should be noted that in scenarios where the first enable signal includes a voltage signal, the control logic subcircuit controls other voltage sources in the voltage generation subcircuit to input voltage signals to VCP_REG.

[0129] Accordingly, the second enable signal is used to enable the VCP test unit. In other words, the VCP test unit is in a closed state before receiving the second enable signal and does not output VCP to the VCP power supply terminal. The VCP test unit will only be in an active state after receiving the second enable signal, so as to output VCP to the VCP power supply terminal.

[0130] For example, the second enable signal includes a voltage signal used to activate the various devices in the VCP test unit. For instance, the second enable signal may include a reference voltage signal input to the reference voltage input terminal. It should be noted that in scenarios where the second enable signal includes a voltage signal, the control logic sub-circuit controls other voltage sources in the voltage generation sub-circuit to input voltage signals to the VCP test unit.

[0131] Furthermore, in this embodiment, the control logic sub-circuit will only control one of VCP_REG and the VCP test unit to work at any given time. In other words, VCP_REG and the VCP test unit will not work simultaneously.

[0132] In addition, in some embodiments, after the control logic subcircuit sends a second enable signal to the VCP test unit when it determines that the memory is in test mode, the control logic subcircuit also sends a plurality of voltage adjustment instructions to the VCP test unit in sequence. Each of these voltage adjustment instructions is used to indicate a voltage value, and the difference between the voltage values ​​indicated by two adjacent voltage adjustment instructions is a reference step size. When the VCP test unit receives a voltage adjustment instruction, it outputs VCP to the VCP power supply terminal based on the voltage value indicated by the voltage adjustment instruction.

[0133] In this case, the reference step size can be the aforementioned fine-tuning step size. In this way, the control logic sub-circuit can use these multiple voltage adjustment commands to control the VCP output of the VCP test unit to gradually change according to the fine-tuning step size.

[0134] For example, each voltage adjustment instruction includes a bit sequence, the total number of bits in the bit sequence being a reference number, and the bit value corresponding to the bit sequence being used to indicate the voltage value indicated by the corresponding voltage adjustment instruction.

[0135] For example, a bit sequence may consist of six bits. The control logic subcircuit adjusts the bit values ​​within this bit sequence to indicate different voltage values. For instance, after sending a second enable signal, the control logic subcircuit sequentially sends ten 6-bit bit sequences. The combination of bit values ​​in each bit sequence indicates a voltage value. When the VCP test unit receives any bit sequence, it determines the voltage value requiring fine-tuning based on the combination of bit values ​​in that bit sequence, and then outputs the corresponding voltage to the VCP power supply terminal.

[0136] Alternatively, the control logic sub-circuit can also control the VCP output of the VCP test unit to change gradually in other ways, which will not be illustrated here.

[0137] Furthermore, in this embodiment, the control logic sub-circuit can determine whether the memory is currently in user mode or test mode in response to instructions from an external controller coupled to the memory. This will be explained in detail below.

[0138] In some embodiments, an external controller coupled to the memory is used to perform the following functions:

[0139] (1) When it is determined that the memory is in user mode, a first instruction is sent to the control logic sub-circuit in the peripheral circuit so that the control logic sub-circuit sends a first enable signal to VCP_REG based on the first instruction. The first instruction is used to indicate that the memory is in user mode, and the first enable signal is used to trigger VCP_REG to start working.

[0140] (2) When it is determined that the memory is in test mode, a second instruction is sent to the control logic sub-circuit so that the control logic sub-circuit sends a second enable signal to the VCP test unit based on the second instruction. The second instruction is used to indicate that the memory is in test mode, and the second enable signal is used to trigger the VCP test unit to start working.

[0141] For example, the controller is configured with a display interface that includes selection options corresponding to user mode and selection options corresponding to test mode. When the controller detects an operation on the selection option for user mode, it determines that the memory is in user mode. Correspondingly, when the controller detects an operation on the selection option for test mode, it determines that the memory is in test mode.

[0142] For example, before the memory leaves the factory, technicians can select the test mode option on the controller's display interface to trigger the controller to send a second instruction to the control logic sub-circuit, which in turn triggers the control logic sub-circuit to send a second enable signal to the VCP test unit, which then provides VCP to the VCP power supply terminal. After the memory leaves the factory, when the user needs to use the memory to read and write data normally, the user can select the user mode option on the controller's display interface to trigger the controller to send a first instruction to the control logic sub-circuit, which in turn triggers the control logic sub-circuit to send a first enable signal to VCP_REG, which then provides VCP to the VCP power supply terminal.

[0143] Furthermore, the embodiments of this application do not limit the form of the first instruction and the second instruction. Any signal that can realize the function corresponding to the aforementioned first instruction and second instruction can be used as the first instruction and second instruction required by the embodiments of this application.

[0144] Furthermore, all the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of this application, and the embodiments of this application will not be described in detail one by one.

[0145] In summary, the embodiments of this application provide a memory whose peripheral circuitry includes not only VCP_REG but also a VCP test unit. VCP_REG provides VCP to the capacitor of the memory cell when the memory is in user mode, such as when reading or writing data. The VCP test unit provides VCP to the capacitor of the memory cell when the memory is in test mode, such as when testing SA performance. Thus, when SA performance needs to be tested, it is not necessary to provide a finely adjustable VCP to the capacitor of the memory cell through VCP_REG; instead, a separate VCP test unit outputs a finely adjustable VCP. This allows for flexible setting of the VCP output by the VCP test unit according to test requirements, thereby avoiding excessively small adjustment range or low adjustment accuracy of VCP during SA testing.

[0146] Figure 12 This is a comparative diagram of VCP_REG and VCP output by the VCP test unit provided in an embodiment of this application. Figure 12 The line marked by the black dots in the middle is a schematic diagram of the voltage change of VCP output by the VCP test unit. Each small black dot represents a VCP output by the VCP test unit after fine-tuning according to the fine-tuning step size. Figure 12 The line marked by the black triangle in the middle is a schematic diagram of the voltage change of VCP output by VCP_REG. Each small black triangle is a VCP output by VCP_REG after fine-tuning according to the fine-tuning step size.

[0147] like Figure 12As shown, the VCP output by the VCP test unit has a smaller fine-tuning step size, meaning the output VCP voltage accuracy is higher. Furthermore, the VCP output by the VCP test unit has a wider voltage range.

[0148] Figure 13 This is a schematic diagram of the architecture of a storage system provided in an embodiment of this application. For example... Figure 13 As shown, the storage system 1300 includes a memory as described in the foregoing embodiments, and a controller coupled to the memory and configured to control the memory.

[0149] In this embodiment, the controller is used to control VCP_REG to output VCP when the memory is in user mode, or to control the VCP test unit to output VCP when the memory is in test mode.

[0150] The functions of the controller and the memory in the storage system can be referred to in the aforementioned embodiments, and will not be repeated here.

[0151] Additionally, the controller can be configured to manage data stored in memory and communicate with external devices (e.g., a host). In other embodiments, the controller can also be configured to control memory operations, such as read, erase, and program operations. In other embodiments, the controller can also be configured to manage various functions relating to data stored or to be stored in memory, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In other embodiments, the controller is also configured to process error correction codes relating to data read from or written to memory.

[0152] Alternatively, the controller may also perform any other suitable function, such as formatting memory; for example, the controller may communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0153] It should be noted that the interface protocols include at least one of the following: USB protocol, MMC protocol, PCI (Peripheral Component Interconnect) protocol, PCI High Speed ​​(PCI-E) protocol, ATA (Advanced Technology Attachment) protocol, Serial ATA protocol, Parallel ATA protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Drive Interface) protocol, IDE (Integrated Development Environment) protocol, and Firewall (Firewire) protocol.

[0154] In addition, this application also provides an electronic device. This electronic device can be any of the following: a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0155] Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 1400 may include the storage system 1300 mentioned above, and may also include at least one of a central processing unit (CPU) and a cache.

[0156] In addition, this application embodiment also provides a method for operating a memory. The memory includes peripheral circuitry and a memory array coupled to the peripheral circuitry. The memory array includes multiple memory cells, each memory cell including a capacitor. The peripheral circuitry includes a voltage generation sub-circuit. The voltage generation sub-circuit has a capacitor substrate voltage VCP power supply terminal, which is used to couple the capacitor. The voltage generation sub-circuit includes a VCP adjustment unit VCP_REG and a VCP test unit.

[0157] Figure 15 This is a flowchart illustrating an operation method for a memory provided in an embodiment of this application. Figure 15 As shown, the method 1500 includes the following steps.

[0158] Step 1501: When the control logic sub-circuit in the peripheral circuit determines that the memory is in user mode, it sends a first enable signal to VCP_REG. VCP_REG receives the first enable signal and starts working based on the first enable signal to output VCP to the VCP power supply terminal. Alternatively,

[0159] Step 1502: When the control logic sub-circuit determines that the memory is in test mode, it sends a second enable signal to the VCP test unit. The VCP test unit receives the second enable signal and starts working based on the second enable signal to output VCP to the VCP power supply terminal.

[0160] In some embodiments, the memory is also coupled to a controller for controlling the memory;

[0161] The control logic sub-circuit in the peripheral circuit can determine that the memory is in user mode by: the control logic sub-circuit determines that the memory is in user mode when it receives the first instruction from the controller.

[0162] Accordingly, the control logic sub-circuit can determine that the memory is in test mode by receiving a second instruction from the controller.

[0163] In addition, in some embodiments, after the control logic subcircuit sends a second enable signal to the VCP test unit when it determines that the memory is in test mode, the control logic subcircuit sequentially sends multiple voltage adjustment instructions to the VCP test unit. Each voltage adjustment instruction is used to indicate a voltage value, and the difference between the voltage values ​​indicated by two adjacent voltage adjustment instructions is a reference step size. When the VCP test unit receives a voltage adjustment instruction, it outputs VCP to the VCP power supply terminal based on the voltage value indicated by the voltage adjustment instruction.

[0164] For example, each voltage adjustment instruction includes a bit sequence, the total number of bits in the bit sequence being a reference number, and the bit value corresponding to the bit sequence being used to indicate the voltage value indicated by the corresponding voltage adjustment instruction.

[0165] The detailed implementation methods in the above embodiments can be referred to the foregoing embodiments, and will not be repeated here.

[0166] In the embodiments of this application, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It is understood that "first," "second," etc., may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0167] It should be understood that the phrase "some embodiments" throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0168] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0169] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0170] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A memory, characterized in that, The memory includes peripheral circuitry and a memory array coupled to the peripheral circuitry. The memory array includes multiple memory cells, each of which includes a capacitor. The peripheral circuit includes a voltage generating sub-circuit, which has a capacitor substrate voltage VCP power supply terminal. The VCP power supply terminal is used to couple the capacitor. The voltage generating sub-circuit includes a VCP adjustment unit VCP_REG and a VCP test unit. The output terminal of the VCP_REG and the output terminal of the VCP test unit are both coupled to the VCP power supply terminal. The VCP_REG is used to: operate when the memory is in user mode, to output VCP to the VCP power supply terminal, where user mode is the mode in which the memory works normally; The VCP test unit is used to: operate when the memory is in test mode, to output VCP to the VCP power supply terminal, wherein the test mode is a mode for testing the performance of the memory.

2. The memory as claimed in claim 1, characterized in that, The voltage range of VCP that the VCP test unit can output is greater than the voltage range of VCP that the VCP_REG can output.

3. The memory as claimed in claim 1, characterized in that, The VCP voltage accuracy output by the VCP test unit is higher than that output by the VCP_REG.

4. The memory as claimed in claim 1, characterized in that, The VCP test unit has a reference voltage input terminal, and the VCP test unit includes a voltage divider adjustable circuit and an amplifier; The first terminal of the voltage divider is coupled to the reference voltage input terminal, the second terminal of the voltage divider is grounded, the third terminal of the voltage divider is coupled to the input terminal of the amplifier, and the output terminal of the amplifier is coupled to the VCP power supply terminal.

5. The memory as claimed in claim 4, characterized in that, The voltage divider adjuster includes a variable resistor.

6. The memory as claimed in claim 4, characterized in that, The amplifier includes a rail-to-rail amplifier (RTR AMP).

7. The memory as claimed in claim 4, characterized in that, The VCP test unit further includes a first fixed resistor, the first end of which is coupled to the reference voltage input terminal, and the second end of which is coupled to the first end of the voltage divider adjustable unit.

8. The memory as claimed in claim 4, characterized in that, The VCP test unit also includes a second fixed resistor, the first end of which is coupled to the second end of the voltage divider adjustable resistor, and the second end of the second fixed resistor is used for grounding.

9. The memory according to any one of claims 1-8, characterized in that, The peripheral circuit also includes a control logic sub-circuit, and the control terminal of the VCP_REG and the control terminal of the VCP test unit are both coupled to the control logic sub-circuit. The control logic sub-circuit is used to: send a first enable signal to the VCP_REG when it is determined that the memory is in the user mode, or send a second enable signal to the VCP test unit when it is determined that the memory is in the test mode; The VCP_REG is used to: receive the first enable signal and start working based on the first enable signal; The VCP test unit is used to: receive the second enable signal and start working based on the second enable signal.

10. The memory as claimed in claim 1, characterized in that, The VCP power supply terminal is used to couple to the capacitors of each memory cell in the memory array.

11. A storage system, characterized in that, The storage system includes: The memory according to any one of claims 1-10; And a controller coupled to the memory and configured to control the memory; The controller is configured to control the VCP_REG to output VCP when the memory is in user mode, or to control the VCP test unit to output VCP when the memory is in test mode.

12. The storage system as claimed in claim 11, characterized in that, The controller is used for: When it is determined that the memory is in the user mode, a first instruction is sent to the control logic sub-circuit in the peripheral circuit, so that the control logic sub-circuit sends a first enable signal to the VCP_REG based on the first instruction. The first instruction is used to indicate that the memory is in the user mode, and the first enable signal is used to trigger the VCP_REG to start working. When it is determined that the memory is in the test mode, a second instruction is sent to the control logic sub-circuit, so that the control logic sub-circuit sends a second enable signal to the VCP test unit based on the second instruction. The second instruction is used to indicate that the memory is in the test mode, and the second enable signal is used to trigger the VCP test unit to start working.

13. An electronic device, characterized in that, The electronic device includes the storage system as described in claim 11 or 12.

14. A method for operating a memory, characterized in that, The memory includes peripheral circuitry and a memory array coupled to the peripheral circuitry. The memory array includes multiple memory cells, each memory cell including a capacitor. The peripheral circuitry includes a voltage generation sub-circuit, which has a capacitor substrate voltage (VCP) power supply terminal for coupling to the capacitor. The voltage generation sub-circuit includes a VCP adjustment unit (VCP_REG) and a VCP testing unit. The method includes: When the control logic sub-circuit in the peripheral circuit determines that the memory is in the user mode, it sends a first enable signal to the VCP_REG. The VCP_REG receives the first enable signal and starts working based on the first enable signal to output VCP to the VCP power supply terminal; or, When the control logic sub-circuit determines that the memory is in the test mode, it sends a second enable signal to the VCP test unit. The VCP test unit receives the second enable signal and starts working based on the second enable signal to output VCP to the VCP power supply terminal.

15. The method as described in claim 14, characterized in that, The memory is also coupled to a controller for controlling the memory; The control logic sub-circuit in the peripheral circuitry determines that the memory is in the user mode, including: When the control logic sub-circuit receives a first instruction from the controller, it determines that the memory is in the user mode. The control logic sub-circuit determines that the memory is in the test mode, including: When the control logic sub-circuit receives a second instruction from the controller, it determines that the memory is in the test mode.

16. The storage system as claimed in claim 14, characterized in that, After the control logic subcircuit sends a second enable signal to the VCP test unit when it determines that the memory is in the test mode, the method further includes: The control logic sub-circuit sequentially sends multiple voltage adjustment commands to the VCP test unit. Each voltage adjustment command is used to indicate a voltage value, and the difference between the voltage values ​​indicated by two adjacent voltage adjustment commands is the reference step size. When the VCP test unit receives a voltage adjustment command, it outputs VCP to the VCP power supply terminal based on the voltage value indicated by the voltage adjustment command.

17. The storage system as claimed in claim 16, characterized in that, Each voltage adjustment instruction includes a bit sequence, the total number of bits in the bit sequence being a reference number, and the bit value corresponding to the bit sequence being used to indicate the voltage value indicated by the corresponding voltage adjustment instruction.

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