Memory repair system, repair method, and chip

Abstract

The application relates to a memory repair system, a repair method and a chip, wherein the memory repair system comprises a fault test module, a fault repair module, a decoder and a plurality of memories, wherein each memory is sequentially connected with the input ends of the fault test module, the fault repair module and the decoder, and the output end of the decoder is also connected with each memory; all the memories share the fault test module and the fault repair module; the fault test module is used for detecting fault information of each memory and transmitting the fault information to the fault repair module; the fault repair module is used for analyzing the fault information to obtain repair information; the decoder is used for decoding the repair information and transmitting the repair information to a target memory, so that the target memory is repaired according to the repair information. Through the application, the problems of high wiring difficulty and high power consumption of memory self-repair are solved.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to memory repair systems, repair methods and chips. Background Technology

[0002] Semiconductor chips are manufactured using semiconductor manufacturing processes and then tested by testing equipment in wafer, bare die, or packaged form. Testing identifies and selects faulty components or chips, and when some memory cells fail, repair operations can be performed to salvage the semiconductor chip. In integrated circuits, to improve memory chip yield, a portion of the internal space is used as a redundant memory bit area during memory design. When a faulty bit is detected, this redundant memory bit can be used to replace the faulty bit for repair.

[0003] Currently, the mainstream method for testing memory is MBIST (Memory Built-In Self-Test). MBIST not only tests the memory but also performs MBISR (Memory Built-In Self-Repair) when a memory fault is detected and redundant row / column resources exist. In this technology, each memory corresponds to a set of MBISR circuits, and repair information is stored in its own BISR row / column registers. Repair is performed independently through dedicated repair ports, ensuring no interference between memories. However, both MBIST and MBISR require inserting multiple hardware circuits into the original memory, significantly increasing the memory area. Furthermore, inserting multiple hardware circuits also increases wiring complexity and power consumption.

[0004] There is currently no effective solution to the problems of difficult self-healing wiring and high power consumption in related technologies. Summary of the Invention

[0005] This embodiment provides a memory repair system, repair method, and chip to solve the problems of high wiring difficulty and high power consumption in memory self-repair technology.

[0006] In the first aspect, this embodiment provides a memory repair system, including: a fault testing module, a fault repair module, a decoder, and a plurality of memories, wherein each memory is sequentially connected to the input terminals of the fault testing module, the fault repair module, and the decoder, and the output terminal of the decoder is also connected to each memory.

[0007] All memory modules share the fault testing module and the fault repair module;

[0008] The fault testing module is used to detect fault information of each memory and transmit the fault information to the fault repair module; the fault repair module is used to analyze the fault information to obtain repair information, and the decoder is used to decode the repair information and transmit it to the target memory so as to repair the target memory according to the repair information.

[0009] In some embodiments, the fault testing module includes a self-test controller, a comparator, and a self-test interface. The input of the comparator is connected to the self-test interface, the self-test interface is connected to the plurality of memories, and the output of the comparator is connected to the fault repair module.

[0010] The self-test controller is used to generate test data and send the test data to the self-test interface;

[0011] The self-test interface is used to send the test data to the comparator and several of the memories;

[0012] The memory performs read and write operations based on the test data and transmits the read results to the self-test interface.

[0013] The self-test interface is also used to receive the read result of the memory and transmit the read result to the comparator;

[0014] The comparator is used to compare the test data and the readout results to obtain fault information, and to feed the fault information back to the fault repair module.

[0015] In some embodiments, the fault repair module includes a self-repair controller, a self-repair row register, a self-repair column register, a repair analysis module, and a fuse box. The self-repair controller is connected to the self-repair row register and the self-repair column register. The self-repair row register and the self-repair column register are respectively connected to the repair analysis module, and the repair analysis module is connected to the fault test module.

[0016] During the fault repair phase, the repair analysis module analyzes the fault information to obtain repair information for several memories. The self-repair controller controls the self-repair row register and the self-repair column register to receive the repair information and compresses the repair information before storing it in the fuse box.

[0017] The self-healing controller is also used to decompress the repair information in the fuse box, store the repair information in the self-healing row register or the self-healing column register, and control the self-healing row register or the self-healing column register to transmit the repair information to the decoder.

[0018] In some embodiments, the repair analysis module is further configured to:

[0019] For each target fault point, when the row and column where the target fault point is located have been detected, the repair analysis module counts the number of fault points in the row and the number of fault points in the column where the target fault point is located.

[0020] The number of row fault points and column fault points of all target fault points are statistically compared to obtain the comparison results;

[0021] The repair information for the target fault point is determined based on the comparison results.

[0022] In some embodiments, the memory repair system further includes a power supply controller, one end of which is connected to a self-repair controller, and the other end of which is connected to a self-repair row register and a self-repair column register;

[0023] The power supply controller is used to supply power to the self-repairing row register and the self-repairing column register according to their operating status.

[0024] Secondly, this embodiment provides a chip including the memory repair system described in the first aspect above.

[0025] Thirdly, this embodiment provides a memory fault repair method, applied to the memory repair system described in the first aspect above, the method comprising:

[0026] The repair information in the fuse box of the fault repair module is decompressed; the repair information is obtained by the fault test module detecting fault information in several memories and transmitting it to the repair analysis module for analysis; the fault repair module includes a self-repair controller, a repair analysis module, and a fuse box.

[0027] The repair information is transmitted to the decoder so that the decoder can decode the repair information to obtain the target fault repair information;

[0028] The target memory is matched and repaired according to the target fault repair information.

[0029] In some embodiments, before decompressing the repair information in the fuse box of the fault repair module, the method further includes:

[0030] During the fault repair phase, the repair information obtained by the repair analysis module based on the fault information in several memories is compressed and stored in the fuse box.

[0031] In some embodiments, the fault repair module further includes a self-repairing row register and a self-repairing column register, and before transmitting the repair information to the decoder, it further includes:

[0032] The repair information is decompressed and stored in the self-repairing row register or the self-repairing column register, and then transmitted to the decoder through the self-repairing row register or the self-repairing column register.

[0033] In some embodiments, for each target fault point in the plurality of memories, repair information for all the target fault points is obtained by repeating the following steps:

[0034] For each target fault point, when the row and column where the target fault point is located have been detected, the repair analysis module counts the number of fault points in the row and the number of fault points in the column where the target fault point is located, and obtains the comparison result.

[0035] The repair information for the target fault point is determined based on the comparison results.

[0036] Compared with related technologies, the memory repair system provided in this embodiment includes: a fault testing module, a fault repair module, a decoder, and several memories. Each memory is sequentially connected to the input terminals of the fault testing module, the fault repair module, and the decoder, and the output terminal of the decoder is also connected to each memory. All memories share the fault testing module and the fault repair module. The fault testing module is used to detect fault information of each memory and transmit the fault information to the fault repair module. The fault repair module is used to analyze the fault information to obtain repair information. The decoder is used to decode the repair information and transmit it to the target memory to repair the target memory according to the repair information. This solves the problems of high difficulty and high power consumption in memory self-repair wiring and reduces the difficulty and power consumption of memory self-repair wiring.

[0037] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 This is a schematic diagram of the memory repair system structure in this embodiment.

[0040] Figure 2 This is a schematic diagram of another memory repair system structure in this embodiment.

[0041] Figure 3 This is a schematic diagram of the preferred memory repair system structure in this embodiment.

[0042] Figure 4 This is a flowchart of the memory fault repair method in this embodiment.

[0043] Figure 5 This is a schematic diagram of a faulty memory in the memory fault repair method of this embodiment.

[0044] Figure 6 This is a flowchart of another memory fault repair method in this embodiment. Detailed Implementation

[0045] To better understand the purpose, technical solution, and advantages of this application, the application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0046] Unless otherwise defined, the technical or scientific terms used in this application shall have the general meaning understood by one of ordinary skill in the art to which this application pertains. Words such as “a,” “an,” “an,” “the,” “the,” and “these” used in this application do not indicate quantitative limitation and may be singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that comprises a series of steps or modules (units) is not limited to the listed steps or modules (units) but may include steps or modules (units) not listed, or may include other steps or modules (units) inherent to these processes, methods, products, or devices. Words such as “connected,” “linked,” and “coupled” used in this application are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. Normally, the character " / " indicates that the objects before and after it are in an "or" relationship. The terms "first," "second," "third," etc., used in this application are merely to distinguish similar objects and do not represent a specific order of objects.

[0047] In related technologies, each memory is configured with its own MBISR circuit. The repair information for each memory is stored in the BISR row / column registers within its respective MBISR circuit. These BISR row / column registers are connected in series to the MBISR controller within the MBISR circuit. Each memory performs repair based on the repair information in its own BISR row / column registers through its own repair port, ensuring that each memory operates independently. However, deploying independent repair circuits for each memory significantly increases the chip's physical area, thereby increasing chip cost. Furthermore, from the perspective of internal circuit layout, the routing of interconnects must adhere to strict electrical rules. Specifically, interconnects must not intersect during horizontal and vertical routing; any intersection will inevitably cause a short circuit, affecting the chip's normal function and stability. In addition, to meet the routing requirements of complex circuits, the internal circuitry of the chip needs to be layered. This process involves not only the planning and design of multi-layered structures but also precise via drilling to achieve electrical connections between different layers of circuitry. Meanwhile, various factors must be considered during the cabling process, including but not limited to signal interference, the differences in characteristics between high-frequency and low-frequency signals, and their impact on the cable layout. Therefore, as the number of cables to be laid increases, the technical challenges and complexity of the cabling process rise exponentially, significantly increasing the difficulty of cabling.

[0048] Based on this, a memory repair system is provided in this embodiment. Figure 1 This is a schematic diagram of the memory repair system structure in this embodiment, as shown below. Figure 1 As shown, the memory repair system 10 includes: a fault testing module 11, a fault repair module 12, a decoder 13, and several memories 14. Each memory 14 is sequentially connected to the input terminals of the fault testing module 11, the fault repair module 12, and the decoder 13, respectively. The output terminal of the decoder 13 is also connected to each memory 14. All memories 14 share the fault testing module 11 and the fault repair module 12. The fault testing module 11 is used to detect fault information of each memory 14 and transmit the fault information to the fault repair module 12. The fault repair module 12 is used to analyze the fault information to obtain repair information. The decoder 13 is used to decode the repair information and transmit it to the target memory to repair the target memory according to the repair information.

[0049] Specifically, such as Figure 1As shown, in the memory repair system of this embodiment, multiple memories 14 are connected to the same fault testing module 11. The same fault testing module 11 performs fault detection on each memory 14. The fault detection module 11 is connected to a fault repair module 12. The fault repair module 12 analyzes the fault information detected by the fault detection module 11 to obtain repair information for the faulty memories. This fault information includes the location information of the faulty memories and the location information of the non-faulty memories. The repair information includes the location information of the faulty memories. The fault repair module 12 is connected to a decoder 13. The fault repair module 12 transmits the repair information to the decoder 13, which decodes the repair information. The output of the decoder 13 is connected to each memory 14. The decoder 13 transmits the decoded repair information to the repair port of the faulty target memory. Based on the decoded repair information, the target memory is repaired using redundant rows or columns.

[0050] In this embodiment, all memories share the same fault testing module for fault testing and the same fault repair module for fault repair. This avoids configuring a separate fault detection circuit and fault repair circuit for each memory, thereby reducing the number of circuit modules, reducing the difficulty of memory self-repair wiring and layout, and also greatly reducing the chip area.

[0051] In some embodiments, the fault testing module includes a self-test controller, a comparator, and a self-test interface. The input of the comparator is connected to the self-test interface, the self-test interface is connected to several memories, and the output of the comparator is connected to the fault repair module. The self-test controller is used to generate test data and send the test data to the self-test interface. The self-test interface is used to send the test data to the comparator and several memories. The memories read and write based on the test data and transmit the read results to the self-test interface. The self-test interface is also used to receive the read results from the memories and transmit the read results to the comparator. The comparator is used to compare the test data and the read results to obtain fault information and feed the fault information back to the fault repair module.

[0052] Specifically, Figure 2 This is a schematic diagram of another memory repair system structure in this embodiment, as shown below. Figure 2 As shown, based on the circuit operation logic, Figure 1The fault test module 11 includes a self-test controller (MBIST controller) 21, a comparator 22, and a self-test interface 23, which together constitute the fault test circuit in this embodiment. Each memory 14 is connected to the self-test interface 23, which is connected to the input of the comparator 22. The output of the comparator 22 is connected to the fault repair module 12. In the Memory Built-in Self-Test (BIST), the self-test controller 21 connects to the comparator 22 and all memories 14 through the self-test interface 23. The self-test controller 21 outputs test vectors, read / write control signals, and clock signals to each memory 14 through the self-test interface 23. Several memories 14 perform read / write operations based on the test vectors to obtain the read results of each memory 14. Each memory 14 transmits its read results to the comparator 22 through the self-test interface 23. The self-test controller 21 generates expected data and sends the expected data to the comparator 22 through the self-test interface 23. Comparator 22 compares the read results of each memory 14 bit by bit with the expected data to generate an error vector, thereby accurately locating the fault position and detecting the fault information of the memory. This fault information is then transmitted to the fault repair module. The fault information includes the location information of the faulty memory, the location information of the non-faulty memory, and the row and column positions to be repaired. Physically, to facilitate sharing of the fault test circuit, comparator 22 is generally placed within the self-test controller (MBIST controller) 21. In this embodiment, the location of comparator 22 is not specifically limited and can be set according to actual needs.

[0053] In another embodiment, the fault repair module includes a self-repair controller, a self-repair row register, a self-repair column register, a repair analysis module, and a fuse box. The self-repair controller is connected to the self-repair row register and the self-repair column register. The self-repair row register and the self-repair column register are respectively connected to the repair analysis module, and the repair analysis module is connected to the fault test module.

[0054] During the fault repair phase, the repair analysis module obtains repair information for several memories based on the fault information analysis. The self-repair controller is used to control the self-repair row register and the self-repair column register to receive the repair information and compress the repair information and store it in the fuse box. The self-repair controller is also used to decompress the repair information in the fuse box, store the repair information in the self-repair row register or the self-repair column register, and control the self-repair row register or the self-repair column register to pass the repair information to the decoder.

[0055] Specifically, such as Figure 2 As shown, based on the circuit operation logic, Figure 1The fault repair module 12 includes a self-repair controller (MBISR controller) 24, several self-repair row registers (BISR rows) 25, several self-repair column registers (BISR columns) 26, a repair analysis module, and a fuse box 27. The repair analysis module includes a built-in repair analysis (BIRA) 28, row fuse group registers 291, and column fuse group registers 292. The built-in repair analysis (BIRA) 28 receives fault information transmitted by the comparator 22, analyzes the fault information, and stores it in either the row fuse group register 291 or the column fuse group register 292. The fault information transmitted by the comparator 22 includes the detected memory location and its status information. The status information includes two states: "faulty" and "not faulty." The built-in repair analysis (BIRA) 28 analyzes the status information in the fault information to obtain the faulty memory and its specific row and column positions. Based on the analysis results, it generates repair information, which includes the location of the faulty memory and the row and column positions to be repaired, indicating that the location needs to be repaired. After the built-in repair analysis (BIRA) 28 analyzes and obtains the repair information, it stores the repair information into the corresponding row fuse group register 291 or column fuse group register 292 according to the fault location in the repair information. The self-repair controller (MBISR controller) 24 controls the row fuse group register 291 or column fuse group register 292 to store the repair information into the corresponding self-repair row register (BISR row) 25 or self-repair column register (BISR column) 26. Under the control of the self-repair controller (MBISR controller) 24, the repair information in the self-repair row register (BISR row) 25 and self-repair column register (BISR column) 26 is then compressed, and the compressed repair information is stored in the fuse box 27. During memory fault repair, the repair information in fuse box 27 is decompressed by the self-repair controller (MBISR controller) 24. The decompressed repair information is stored in the self-repair row register (BISR row) 25 or the self-repair column register (BISR column) 26. The self-repair row register (BISR row) 25 or the self-repair column register (BISR column) 26 transmits the decompressed repair information to the decoder 13. The decoder 13 decodes the decompressed repair information to obtain the target fault repair information, which includes the specific memory cell and the row and column positions to be repaired within the specific memory cell. Based on the target memory cell and the row and column positions to be repaired corresponding to the target fault repair information, the decoder 13 automatically maps the access to redundant rows / columns when the faulty row / column of the target memory cell is accessed during subsequent use, thereby achieving the repair of the target fault location.

[0056] In this embodiment, row fuse group register 291 and column fuse group register 292 are mainly used to store and transmit repair information, serving as intermediate units for repair information processing. Self-repairing row register (BISR row) 25 and self-repairing column register (BISR column) 26 directly participate in the application of repair information, guiding the decoder to perform repair operations; they are key execution units in the repair process. Furthermore, in terms of physical structure, for ease of sharing, the built-in Repair Analysis (BIRA) and comparator circuitry in the original self-test interface are moved to the self-test controller (MBIST controller).

[0057] In this embodiment, several self-repairing row registers (BISR rows) 25 and several self-repairing column registers (BISR columns) 26 are pooled so that all self-repairing row registers (BISR rows) 25 and self-repairing column registers (BISR columns) 26 can be shared by the memory 14, thereby decoupling the one-to-one binding relationship between memory and register in the prior art. Specifically, N memories, from memory 1 to memory N, share a repair circuit, and each of their shared self-repairing row registers (BISR rows) 25 and self-repairing column registers (BISR columns) 26 has m (m<=N) entries. When there are k (k<=N) row / column defects in the N memories, and k<=m, the self-repairing row registers (BISR rows) 25 and self-repairing column registers (BISR columns) 26 can store the addresses of the faulty rows and columns of all memories 14, thereby realizing the recording of memory defect addresses on demand. For example, there are 10 memory devices in total, with 4 BISR row registers and 4 BISR column registers. There are 3 defects in the memory devices, namely the 3rd row of memory device 1, the 5th column of memory device 6, and the 9th column of memory device 8. In this case, 1 BISR row register will be used to record the defective row address of memory device 1, and 2 BISR column registers will be used to record the defective column addresses of memory device 6 and memory device 8, respectively.

[0058] In this embodiment, the repair analysis module is also used to: for each target fault point, when the row and column where the target fault point is located have been detected, the repair analysis module counts the number of row fault points and column fault points where the target fault point is located; compares the number of row fault points and column fault points where all target fault points are located to obtain the comparison result; and determines the repair information of the target fault point based on the comparison result.

[0059] Specifically, after a fault point is detected, it is designated as the target fault point. Repair resources are not initially calculated or allocated for this target fault point. Once the row and column containing the target fault point have been detected, the built-in Repair Analysis (BIRA) 28 in the repair analysis module compares the number of fault points in the row and column. The row or column with more fault points is selected as the repair information for that fault point. For example, if the number of fault points in the row containing the target fault point is greater than the number of fault points in the column containing the target fault point, then redundant rows are used for repair. This process is repeated for each fault point. The final repair information is obtained by comparing the number of fault points in the rows and columns containing all target fault points. This repair information includes the location of the fault memory, the row and column positions to be repaired, and the row and / or column repair methods. Specifically, redundant rows or redundant columns can be specified for repair based on the data format of the repair information.

[0060] For example, the target fault repair information obtained by the decoder is 000100000101. From the target fault repair information 000100000101, the memory index is decoded as 0001, indicating that this repair information is for memory 1. After removing the memory index, the decoder obtains 00000101. The decoder outputs 00000101 to the repair port of memory 1, indicating that the third row in memory 1 needs to be repaired, and redundant rows are used for repair. The format of the target fault repair information can be set according to actual conditions; this embodiment does not impose specific limitations on it.

[0061] After the repair information is transmitted to the decoder, the decoder decodes the repair information to obtain the target fault repair information. The obtained target fault repair information contains the memory index. The decoder outputs the target fault repair information after removing the index to the repair port corresponding to the target memory, prompting the use of the specified row and / or column repair method to repair the target fault row and column positions.

[0062] In some embodiments, the memory repair system further includes a power supply controller, one end of which is connected to the self-repair controller, and the other end of which is connected to the self-repair row register and the self-repair column register; the power supply controller is used to supply power to the self-repair row register and the self-repair column register according to their operating status.

[0063] Specifically, Figure 3 This is a schematic diagram of the preferred memory repair system structure in this embodiment, as shown below. Figure 3 As shown, in Figure 2Based on this, the memory repair system also includes a power supply controller 31. One end of the power supply controller 31 is connected to the self-repair controller (MBISR controller) 24, and the other end of the power supply controller 31 is connected to the self-repair row register (BISR row) 25 and the self-repair column register (BISR column) 26, respectively. In order to further reduce the power consumption of the memory repair system, in this embodiment, the power supply controller 31 is added to control the power supply of the self-repair row register (BISR row) 25 and the self-repair column register (BISR column) 26. During the repair process, the power supply is provided to the self-repair row register (BISR row) 25 and the self-repair column register (BISR column) 26 that need to be repaired, and the power supply is stopped for the unused self-repair row register (BISR row) 25 and the self-repair column register (BISR column) 26, thereby reducing the overall energy consumption.

[0064] This embodiment provides a memory fault repair method, which is applied to the memory fault repair system described in any of the above embodiments. Figure 4 This is a flowchart of the memory fault repair method in this embodiment, as follows: Figure 4 As shown, the process includes the following steps:

[0065] Step S401: Decompress the repair information in the fuse box of the fault repair module; the repair information is obtained by the fault test module detecting fault information in several memories and transmitting it to the repair analysis module for analysis; the fault repair module includes a self-repair controller, a repair analysis module and a fuse box.

[0066] Specifically, the fault repair module includes a self-repair controller, a repair analysis module, and a fuse box. Before decompressing the repair information in the fuse box of the fault repair module, during the fault repair stage, the repair analysis module analyzes the fault information in several memories to obtain repair information. The self-repair controller compresses the repair information from the memories obtained by the repair analysis module and stores it in the fuse box.

[0067] The fault testing module detects fault information in each memory unit. This fault information includes the location of the memory cell and its status (faulty or not faulty). The repair analysis module analyzes this fault information to identify the faulty memory unit and its specific row and column positions. Based on the analysis results, repair information is generated, including the location of the faulty memory unit and the row and column positions to be repaired. This information is stored in the corresponding row or column fuse group register. The fuse group register then stores the fault information in the corresponding BISR row or column register. After storage, the self-repair controller compresses the repair information from the BISR row and column registers into the fuse box for storage. During the repair phase, the self-repair controller decompresses the repair information from the fuse box each time power is applied.

[0068] For example, all memories within the same repair sharing group are first numbered, for example, from 1 to N, and these numbers serve as the memory indices. The fault test module performs a built-in self-test (MBIST) on the memories. After the test, a comparator verifies the test results for each memory, and then the repair analysis module analyzes the test results to obtain repair information. This repair information includes the location of the faulty memory and the row / column position to be repaired. The address of the faulty row / column is recorded in the BISR row register or BISR column register. For example, if the 3rd row of memory 1 is faulty, it will be recorded as 000100000101, where the first 4 bits represent the index of the faulty memory, and the last 8 bits represent the address of the faulty row in the memory. This repair information is compressed by the self-repair controller and stored in the fuse box. During the built-in self-repair (MBISR) phase, each time power is applied, the self-repair controller decompresses the repair information from the fuse box and transmits it to the decoder.

[0069] Step S402: The repair information is transmitted to the decoder so that the decoder can decode the repair information to obtain the target fault repair information.

[0070] Specifically, the self-healing controller transmits the repair information to the decoder. The decoder decodes the decompressed repair information to obtain the target fault repair information and decodes the memory index contained in the target fault repair information. The index indicates which target memory the repair information needs to be transmitted to. Then, the decoder outputs the value of the target fault repair information (with the index removed) to the repair port corresponding to the target memory. At this time, the repair ports of other memories are unaffected.

[0071] Step S403: Match the target memory and repair it according to the target fault repair information.

[0072] Specifically, in step S402 above, after the target fault repair information is obtained by decoding, the index of the memory obtained by decoding can be matched with the repair port of the target memory, and the value of the target fault repair information obtained by decoding can identify the row or column in the target memory that needs to be repaired. The faulty row or faulty column in the memory is repaired by the redundant row or redundant column of the memory.

[0073] Through steps S401 to S403, the repair information in the fuse box of the fault repair module is decompressed; the repair information is obtained by the fault test module detecting fault information in several memories and transmitting it to the repair analysis module for analysis; the fault repair module includes a self-repair controller, a repair analysis module, and a fuse box; the repair information is transmitted to the decoder so that the decoder decodes the repair information to obtain the target fault repair information; the target memory is matched and repaired according to the target fault repair information. Compared with the prior art, which requires a separate test circuit and repair circuit for each memory, this embodiment uses a common fault test module and a fault repair module. All memories are tested through the common fault test module and repaired through a common fault repair circuit, reducing the number of circuit modules, thereby reducing the chip wiring difficulty and the power consumption of chip fault repair. By decoupling the correspondence between memory and BISR row / column registers through a pooled set of self-repairing registers (BISR row / column registers), the idle BISR registers can be selected for recording based on the actual fault situation. This enables different memory systems to autonomously select BISR row / column registers when faults occur in different rows or columns, thereby achieving the repair of faults in different rows / columns of different memory systems.

[0074] In some embodiments, the fault repair module further includes a self-repairing row register and a self-repairing column register. Before the decoder decodes the repair information to obtain the target fault repair information, it also includes:

[0075] After the repair information is decompressed, it is stored in the self-repairing row register or the self-repairing column register, and then the repair information is passed to the decoder through the self-repairing row register or the self-repairing column register.

[0076] Specifically, the fault repair module includes a self-repairing row register and a self-repairing column register. After the self-repairing controller decompresses the repair information from the fuse box, it first stores the repair information in the self-repairing row register and the self-repairing column register, and then the self-repairing row register and the self-repairing column register transmit the repair information to the decoder.

[0077] In another embodiment, for each target fault point in several memories, repair information for all target fault points is obtained by repeating the following steps:

[0078] For each target fault point, when the row and column where the target fault point is located have been detected, the control repair analysis module counts the number of fault points in the row and column where the target fault point is located, and obtains the comparison results; based on the comparison results, the repair information of the target fault point is determined.

[0079] Specifically, when detecting memory fault locations, the typical approach is to determine whether to use row-based or column-based repair as the test progresses. This means that repair resources are immediately calculated and allocated after a fault point is detected. This method can lead to suboptimal resource allocation, resulting in low resource utilization and waste. For example, after detecting a fault point, column-based repair might be prioritized. However, if multiple fault points are found in the same row during subsequent detection, the lack of redundant column resources can lead to resource exhaustion and an inability to repair all subsequent faults. Furthermore, making a decision for each fault point leads to frequent calculations and high energy consumption. Therefore, in this embodiment, after detecting a fault point, repair resources are not immediately calculated or allocated for that fault point. After both the row and column containing the fault point have been detected, the number of fault points in each row and column is compared. The row or column with more fault points is selected as the repair information for that fault point. For example, if the number of fault points in the row containing the fault point exceeds the number of fault points in the column containing the fault point, then redundant rows are used to repair that fault point. For instance, Figure 5 This is a schematic diagram of a faulty memory in the memory fault repair method of this embodiment. For this memory, its redundant resources are 5 redundant rows and 5 redundant columns, such as... Figure 5 As shown, the gray squares in this memory represent faulty locations, while the white squares represent fault-free locations. Using traditional repair methods, a repair strategy is calculated immediately after a single fault is detected. If detection is performed row-by-row, repairing the faulty location would require six redundant rows. However, the memory only has five redundant rows available for repair. In this case, the memory might become unrepairable and may be rendered unusable. Alternatively, if detection is performed column-by-column, four redundant columns can be used for repair. Therefore, it is evident that traditional repair methods carry the risk of failure.

[0080] Based on this, the repair method in this embodiment is as follows: If detection is performed row by row, after detecting the first fault point in the first row, the repair strategy is not calculated immediately. Instead, the detection continues to check all positions in the row and column containing the fault point, i.e., continue checking row by row until all rows and columns containing the fault point have been checked. In this example, all positions have been checked. Then, the fault points are statistically analyzed. It can be found that if redundant rows are used for repair, 6 redundant rows are needed; if redundant columns are used for repair, 4 redundant columns are needed; if both redundant rows and redundant columns are used for repair, 5 redundant rows and 1 redundant column can be used, or 4 redundant rows and 2 redundant columns, or 1 redundant row and 3 redundant columns, etc. Based on the obtained repair schemes, the scheme with the fewest resources is further selected as the final repair information, i.e., the optimized repair information. Repair is then performed according to this optimized repair information, thereby achieving efficient resource utilization. All detected fault points are allocated repair resources in this manner. By comparing the number of fault points in the fault row and the fault column, the direction with higher fault density is selected for repair, thereby reducing the amount of repair resources required. It should be noted that this optimization does not change the original test order or increase the number of tests. The test method can be row-by-row testing, column-by-column testing, row-column combination testing, random testing, etc. Only the timing of repair resource calculation is adjusted to reduce the number of calculations, optimize resource allocation, improve the utilization rate of repair resources, enhance repair efficiency, and avoid resource waste.

[0081] Furthermore, the optimized repair information includes the location of the faulty memory, the row and column positions to be repaired, and the specific repair method for each row / column. The specific row / column repair method can be represented by the data structure of the repair information. For example, the data structure can be a padded structure. Specific bit regions are pre-defined in the memory repair information data structure. For instance, a repair information data can be divided into two parts, with the first few bits representing row-related repair information and the last few bits representing column-related repair information. When data is padded, valid information is filled into the corresponding positions according to the actual repair requirements. If only the first few bits are padded, and the last few bits are default values ​​(e.g., all 0s), it indicates that a row-related repair method is used; conversely, if the last few bits are padded, and the first few bits are default values, it indicates that a column-related repair method is used; if both the first and last few bits are padded, it may indicate that both row and column-related repair operations need to be performed simultaneously, or it may be a more complex repair instruction. For example, when the decoder obtains the target fault repair information as 000100000101, it indicates that the third row of storage 1 needs to be repaired using a redundant row. In subsequent use, when the third row of storage 1 is accessed, it will be automatically mapped to the redundant row for access, thereby achieving the repair of the storage.

[0082] This embodiment also provides a memory fault repair method. Figure 6 This is a flowchart of another memory fault repair method in this embodiment, such as... Figure 6 As shown, the process includes the following steps:

[0083] Step S601: Detect fault information in several memories using the fault test module;

[0084] Step S602: The repair analysis module analyzes the fault information in several memories to obtain repair information, and compresses and stores the repair information in the fuse box; wherein, for each target fault point in several memories, the following steps are repeated to obtain the repair information for all target fault points:

[0085] For each target fault point, when the row and column where the target fault point is located have been detected, the repair analysis module counts the number of fault points in the row and column where the target fault point is located to obtain the comparison results; the repair information of the target fault point is determined based on the comparison results.

[0086] Step S603: The self-repair controller decompresses the repair information in the fuse box and stores the decompressed repair information into the self-repair row register or the self-repair column register.

[0087] Step S604: The self-repair controller controls the self-repair row register or the self-repair column register to pass the repair information to the decoder;

[0088] Step S605: The decoder decodes the repair information to obtain the target fault repair information;

[0089] Step S606: Match the target memory and repair it according to the target fault repair information.

[0090] Through steps S601 to S606, compared to the prior art which requires configuring a separate test circuit and repair circuit for each memory, this embodiment uses a common fault test module and fault repair module. All memories are tested through the common fault test module and repaired through a common fault repair circuit, reducing the number of circuit modules, thereby reducing the chip wiring difficulty and the power consumption of chip fault repair. By using a pooled set of self-repairing registers (BISR row / column registers), the correspondence between the memory and the BISR row / column registers is decoupled. Idle BISR registers can be selected for recording based on the actual fault situation, enabling different memories to autonomously select BISR row / column registers when faults occur in different rows or columns, thus achieving repair of different rows / columns of different memories. Furthermore, during fault detection, detection continues after a fault point is detected until the row and column containing the fault point are tested, and then a comprehensive judgment is made on whether row repair or column repair should be used, achieving optimal configuration of minimal repair resources.

[0091] In addition, this application also provides a chip including the memory repair system described above. The various components of this system can be integrated into a single chip or disposed in different chips or circuit boards, establishing data communication links between these chips or circuit boards. Technical details of the memory repair system can be found in the descriptions of the above embodiments; to avoid repetition, they will not be repeated here.

[0092] It should be understood that the chip mentioned in the embodiments of this application can be a memory chip, a system-on-a-chip, a microcontroller, an automotive-grade chip, etc. When the chip powers on, its internal memory repair system starts working, performing built-in self-repair on the internal memory. The memory fault repair method steps can be executed at any time and repeated throughout the chip's lifespan without additional software calls or external intervention. This enables rapid and efficient detection and repair of memory faults, greatly improving the chip's reliability and stability, and providing strong protection for the chip's normal operation in various complex environments.

[0093] It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. All other embodiments derived by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0094] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0095] Obviously, the accompanying drawings are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar situations based on these drawings without any creative effort. Furthermore, it is understood that although the work done in this development process may be complex and lengthy, for those skilled in the art, certain design, manufacturing, or production modifications made based on the technical content disclosed in this application are merely conventional technical means and should not be considered as insufficient disclosure of this application.

[0096] The term "embodiment" in this application refers to a specific feature, structure, or characteristic described in connection with an embodiment that may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily imply the same embodiment, nor does it imply that it is mutually exclusive with or independent of other embodiments. It will be clearly or implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0097] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of patent protection. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A memory repair system, characterized in that, include: The system includes a fault testing module, a fault repair module, a decoder, and several memory units. Each memory is sequentially connected to the input terminals of the fault test module, the fault repair module, and the decoder, and the output terminal of the decoder is also connected to each memory. All memory modules share the fault testing module and the fault repair module; The fault testing module is used to detect fault information of each memory and transmit the fault information to the fault repair module; the fault repair module is used to analyze the fault information to obtain repair information, and the decoder is used to decode the repair information and transmit it to the target memory so as to repair the target memory according to the repair information.

2. The memory repair system according to claim 1, characterized in that, The fault testing module includes a self-test controller, a comparator, and a self-test interface. The input of the comparator is connected to the self-test interface, the self-test interface is connected to the plurality of memories, and the output of the comparator is connected to the fault repair module. The self-test controller is used to generate test data and send the test data to the self-test interface; The self-test interface is used to send the test data to the comparator and several of the memories; The memory performs read and write operations based on the test data and transmits the read results to the self-test interface. The self-test interface is also used to receive the read result of the memory and transmit the read result to the comparator; The comparator is used to compare the test data and the readout results to obtain fault information, and to feed the fault information back to the fault repair module.

3. The memory repair system according to claim 1, characterized in that, The fault repair module includes a self-repair controller, a self-repair row register, a self-repair column register, a repair analysis module, and a fuse box. The self-repair controller is connected to the self-repair row register and the self-repair column register. The self-repair row register and the self-repair column register are respectively connected to the repair analysis module. The repair analysis module is connected to the fault test module. During the fault repair phase, the repair analysis module analyzes the fault information to obtain repair information for several memories. The self-repair controller controls the self-repair row register and the self-repair column register to receive the repair information and compresses the repair information before storing it in the fuse box. The self-healing controller is also used to decompress the repair information in the fuse box, store the repair information in the self-healing row register or the self-healing column register, and control the self-healing row register or the self-healing column register to transmit the repair information to the decoder.

4. The memory repair system according to claim 3, characterized in that, The repair analysis module is also used for: For each target fault point, when the row and column where the target fault point is located have been detected, the repair analysis module counts the number of fault points in the row and the number of fault points in the column where the target fault point is located. The number of row fault points and column fault points of all target fault points are statistically compared to obtain the comparison results; The repair information for the target fault point is determined based on the comparison results.

5. The memory repair system according to claim 3, characterized in that, The memory repair system also includes a power supply controller, one end of which is connected to a self-repair controller, and the other end of which is connected to a self-repair row register and a self-repair column register. The power supply controller is used to supply power to the self-repairing row register and the self-repairing column register according to their operating status.

6. A chip, characterized in that, Includes the memory repair system as described in any one of claims 1 to 5.

7. A method for repairing memory faults, characterized in that, The method, applied to the memory repair system according to any one of claims 1 to 5, comprises: The repair information in the fuse box of the fault repair module is decompressed; the repair information is obtained by the fault test module detecting fault information in several memories and transmitting it to the repair analysis module for analysis; the fault repair module includes a self-repair controller, a repair analysis module, and a fuse box. The repair information is transmitted to the decoder so that the decoder can decode the repair information to obtain the target fault repair information; The target memory is matched and repaired according to the target fault repair information.

8. The memory fault repair method according to claim 7, characterized in that, Before decompressing the repair information in the fuse box of the fault repair module, the method further includes: During the fault repair phase, the repair information obtained by the repair analysis module based on the fault information in several memories is compressed and stored in the fuse box.

9. The memory fault repair method according to claim 7, characterized in that, The fault repair module further includes a self-repairing row register and a self-repairing column register. Before transmitting the repair information to the decoder, the method further includes: The repair information is decompressed and stored in the self-repairing row register or the self-repairing column register, and then transmitted to the decoder through the self-repairing row register or the self-repairing column register.

10. The memory fault repair method according to claim 7, characterized in that, The method further includes: For each target fault point in the plurality of memories, repair information for all target fault points is obtained by repeating the following steps: For each target fault point, when the row and column where the target fault point is located have been detected, the repair analysis module counts the number of fault points in the row and the number of fault points in the column where the target fault point is located, and obtains the comparison result. The repair information for the target fault point is determined based on the comparison results.

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