A group delay equalization circuit, automatic equalization system and method

Abstract

The application discloses a group time delay equalization circuit, an automatic equalization system and method, the group time delay equalization circuit comprises an adjustable group time delay equalizer in a single-stage structure or a multi-stage cascade; the group time delay automatic equalization system comprises a frequency conversion channel to be optimized, a vector network analyzer to test a group time delay, a group time delay equalizer, a host computer and control software; after the final target group time delay fluctuation parameter of the frequency conversion channel is determined, the initial parameters of the frequency conversion channel and the group time delay equalizer are tested, and the control voltage of the group time delay equalizer is adjusted in cooperation with the control software, so that the group time delay fluctuation of the frequency conversion channel and the group time delay equalizer in cascade satisfies the target requirement, and the application has great flexibility and practicality.

Description

Technical Field

[0001] This invention relates to the field of radio frequency signal transmission technology, and in particular to a group delay equalization circuit, an automatic equalization system, and a method. Background Technology

[0002] For radio frequency signal transmission, especially communication signal transmission sensitive to group delay fluctuations, link group delay fluctuations directly affect the demodulation quality, particularly in telemetry and remote sensing fields where the intermediate frequency (IF) of the frequency conversion link is relatively low. This is due to the characteristics of a low IF link, narrow system IF bandwidth, and high out-of-band suppression requirements, which easily lead to unacceptable group delay fluctuations that negatively impact demodulation results.

[0003] Currently, most communication systems still rely on superheterodyne frequency conversion. Filters in the intermediate frequency (IF) band have a significant impact on group delay ripple, and flat group delay ripple is required under stringent communication quality conditions. Existing solutions address this by designing distributed parameters to form a slow-wave structure, altering the group delay response characteristics of signal transmission and coupling to achieve negative group delay. This can also be achieved by superimposing positive group delay characteristics at certain frequencies to reduce positive group delay parameters and thus lower group delay ripple in the link. However, this approach suffers from low flexibility, complex circuitry, and large space requirements, making it unsuitable for group delay equalization of low-frequency IF signals. Another approach involves designing and combining multiple group delay and amplitude compensation networks to adjust group delay ripple parameters in the system. However, this results in complex parallel network structures for group delay compensation networks. Furthermore, changing the operating frequency necessitates redesigning multiple group delay compensation networks, and in broadband signal scanning scenarios, the initially designed compensation amount may be inappropriate, lacking adaptability.

[0004] Therefore, in order to solve the problem of large group delay fluctuations, it is still a technical challenge that needs to be solved by those skilled in the art to develop an innovative group delay frequency automatic adjustment equalization circuit to correct the group delay fluctuations of the intermediate frequency filter, and at the same time automatically equalize the group delay of the radio frequency broadband signal by controlling the group delay frequency and group delay amplitude of the equalizer circuit through software. Summary of the Invention

[0005] To address the aforementioned technical problems, this invention provides a group delay equalization circuit, an automatic equalization system, and a method. By continuously adjusting the group delay through voltage control, it achieves continuous compensation and adjustment of the intermediate frequency group delay within a certain frequency range, and stores the optimized state parameters in the control circuit memory to maintain the compensation state. If special compensation characteristics are required, compensation can be achieved using a superimposed waveform generated by multiple cascaded stages, realizing complex group delay compensation waveforms.

[0006] This invention is achieved using the following technical solution:

[0007] A group delay equalization circuit includes an adjustable group delay equalizer with a single-stage structure or multiple cascaded stages. The single-stage structure of the adjustable group delay equalizer includes a control module consisting of a microcontroller (MCU), a flash memory, two digital-to-analog converters (DACs), and a symmetrical resonant network. The MCU and the flash memory are bidirectionally connected. The MCU is connected to each of the two DACs. The outputs of the two DACs are each connected to a driver module and then to the symmetrically arranged differential input interfaces VT1 and VT2 of the symmetrical resonant network. The flash memory is used to store optimized configuration parameters and solidify the group delay compensation state.

[0008] Specifically, an adjustable capacitor C1 is provided between the differential input interface VT1 and the differential input interface VT2 of the symmetrical resonant network. Resistors R1 and R2 are connected in series between the adjustable capacitor C1 and the differential input interface VT1 and the differential input interface VT2, respectively. Two adjustable capacitors C2 are connected in parallel across the two ends of the adjustable capacitor C1. An inductor L2 is connected in parallel between the two adjustable capacitors C2 and ground. The symmetrical resonant network also includes an inductor L1 that forms a parallel resonant branch with the two adjustable capacitors C2.

[0009] Specifically, a filter capacitor C3 is connected in parallel to ground between the differential input interface VT1 and the resistor R1, and a filter capacitor C4 is connected in parallel to ground between the differential input interface VT2 and the resistor R2.

[0010] Specifically, the adjustable capacitors C1 and C2 are varactor diodes, based on the group delay propagation response characteristics of the all-pass filter network. and approximate output waveform The center frequency of the group delay compensation is changed by adjusting the capacitance value of the adjustable capacitor C2, and the peak value of the group delay compensation is changed by adjusting the capacitance value of the adjustable capacitor C1.

[0011] Specifically, the multi-stage cascaded adjustable group delay equalizer includes a control module and multiple stages of symmetrical resonant networks. The control module is connected to the drive module corresponding to each stage of the symmetrical resonant network. By selecting different equalization paths for the symmetrical resonant networks, the delay compensation amount of each symmetrical resonant network is controlled to achieve complex group delay compensation waveforms. The group delay frequency range and group delay value of each stage are calculated and calibrated based on the initial state being a straight-through state without group delay fluctuations. Among them, the adjustable voltage range of the DAC is determined by the operating frequency range and the group delay value; the voltage control range of the variable capacitance is within 0V to 15V, and the output voltage range of the DAC driver covers 0V to 30V.

[0012] On the other hand, an automatic group delay equalization system includes a frequency conversion channel for optimizing group delay, a vector network analyzer for testing group delay, and an adjustable group delay equalizer, all interconnected. It also includes a main control computer configured with control software. The main control computer is bidirectionally connected to the vector network analyzer to read the instrument's group delay data, and bidirectionally connected to the adjustable group delay equalizer to modify the equalization parameters based on the read data.

[0013] On the other hand, a group delay automatic equalization method includes the following steps:

[0014] Step S1: Set up an automatic equalization system and test the initial group delay data within the frequency band of the frequency channel to be compensated. The latency fluctuation of the test group was obtained. Represented as , and These represent the initial group delay data. The maximum and minimum values; define the target group delay fluctuation. After obtaining the group delay equilibrium state, the state is as follows: ;

[0015] Step S2: Testing After determining the frequency point, adjust the voltages of differential input interfaces VT1 and VT2, and change the capacitance value of adjustable capacitor C2 so that the center frequency of group delay compensation equals... Frequency points;

[0016] Step S3: Adjust the voltage difference between differential input interface VT1 and differential input interface VT2 to change the capacitance value of adjustable capacitor C1, thereby adjusting the group delay amplitude at this frequency point;

[0017] Step S4: Calculate the new test group latency and with The comparison is performed; if the result is better than the previous state, the voltages of differential input interfaces VT1 and VT2 are increased, and vice versa; thus, the new test group delay is obtained. ; Indicates the number of comparisons and ; and These represent the new group latency data. The maximum and minimum values;

[0018] Step S5: Repeat steps S2 to S4 to correct the parameters of adjustable capacitor C1 and adjustable capacitor C2 and optimize the group delay parameters.

[0019] Step S6: In the main control computer control software, set the number of iterations and the group delay equalization circuit level used, configure the optimization strategy. If the preset number of optimizations of each group delay equalization circuit level does not reach the target value, start the next adjustable group delay equalization circuit level for compensation; repeat steps S1 to S5 until the target group delay is reached.

[0020] The beneficial effects of this invention are as follows:

[0021] This application's technical solution addresses the need for equalization of different group delays at the same frequency. The equalization amount can be automatically adjusted through control algorithm software and instruments. In circuits with the same center frequency, the group delay of multi-stage circuits can be used to superimpose and compensate for unconventional equalization waveforms. This method is characterized by good adaptability and high efficiency. Furthermore, the group delay fluctuation of the circuit can be automatically optimized on a vector network analyzer, and the voltage data configured after achieving the optimal group delay fluctuation can be stored in the control circuit's memory.

[0022] Based on a 1-second time for each test data acquisition and comparison, it would take approximately 100 seconds to complete 100 optimization adjustments to the group delay equalization. Within the range achievable by the group delay equalizer, automatic optimization of the target group delay fluctuation can be completed in 2 minutes. Furthermore, group delay optimization can be achieved as long as the group delay equalization is within the equalizer's frequency band.

[0023] The frequency and range of the adjustable group delay equalization circuit can be designed according to requirements to achieve automatic equalization of the required circuit, which has great flexibility and practicality. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a single-stage structure of the adjustable group delay equalizer in an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a multi-stage cascaded adjustable group delay equalizer in an embodiment of the present invention;

[0027] Figure 3 This is a diagram of the automatic group delay balancing system architecture in an embodiment of the present invention;

[0028] Figure 4 This is a schematic diagram illustrating the relationship between the adjustable capacitor C1 and the group delay parameter in an embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram illustrating the relationship between the adjustable capacitor C2 and the group delay parameter in an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of the automatic group delay equalization method in an embodiment of the present invention;

[0031] Figure 7 This is a schematic diagram of the automatic group delay equalization waveform optimization characteristics in an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0033] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0034] The following is in conjunction with the appendix Figure 1 ~Attached Figure 7 The following describes some embodiments of the present invention in detail. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0035] This invention proposes a group delay equalization circuit, an automatic equalization system, and a method. In a preferred embodiment, the group delay equalization circuit includes a single-stage or multi-stage cascaded adjustable group delay equalizer. The single-stage structure of the adjustable group delay equalizer includes a control module composed of a microcontroller (MCU), a flash memory, two DACs (digital-to-analog converters), and a symmetrical resonant network. The MCU and the flash memory are bidirectionally connected, and the MCU is connected to the two DACs respectively. The output terminals of the two DACs are each connected to a driver module and then to the symmetrical resonant network.

[0036] In this embodiment, the symmetrical resonant network includes symmetrically arranged differential input interfaces VT1 and VT2, which receive differential analog signals from the driving module and form the differential inputs of an all-pass filter. An adjustable capacitor C1 is disposed between differential input interfaces VT1 and VT2. Resistors R1 and R2 are connected in series between the adjustable capacitor C1 and the differential input interfaces VT1 and VT2, respectively. Two adjustable capacitors C2 are connected in parallel across the adjustable capacitor C1, and an inductor L2 is connected in parallel to ground between the two adjustable capacitors C2. The symmetrical resonant network also includes an inductor L1 that forms a parallel resonant branch with the two adjustable capacitors C2. A filter capacitor C3 is connected in parallel to ground between differential input interface VT1 and resistor R1, and a filter capacitor C4 is connected in parallel to ground between differential input interface VT2 and resistor R2.

[0037] In one embodiment, the single-stage structure of the adjustable group delay equalizer is an all-pass filter circuit structure. Adjustable capacitors C1 and C2 are varactor diodes. The capacitance values ​​of C1 and C2 can be changed by outputting voltages through differential input interfaces VT1 and VT2 via a driver. The center frequency and amplitude of the group delay within the passband change accordingly. Resistors R1 and R2 form the DC voltage feed circuit for the varactor diodes, and C3 and C4 are the filter capacitors of the feed circuit. Driving the unit circuit through differential input interfaces VT1 and VT2 allows adjustment of a certain frequency range and a certain group delay amplitude. This adjustment range enables group delay equalization within a certain bandwidth.

[0038] In this embodiment, the group delay equalization of the single-stage structure of the adjustable group delay equalizer is specifically as follows:

[0039] All-pass filter network group delay transmission response characteristics Its output waveform is approximately as follows By applying voltage to the varactor diode and changing its capacitance value, the group delay waveform can be transformed. Adjusting the value of the adjustable capacitor C2 changes the center frequency of the group delay compensation, while adjusting the value of the adjustable capacitor C1 changes the peak value of the group delay compensation. Based on this characteristic, the frequency and amplitude of the group delay can be corrected by controlling the voltage at the varactor diode port using software and the output driver of a DAC (digital-to-analog converter). The control software can simultaneously read the group delay fluctuation data tested in the instrument, automatically compare it with the target group delay data, and then confirm whether the results meet the requirements for group delay correction using the testing instrument.

[0040] In a preferred embodiment, the multi-stage cascaded adjustable group delay equalizer includes a control module and a multi-stage symmetrical resonant network. Different equalization paths are selected for each symmetrical resonant network, and the delay compensation amount of each network is controlled to achieve complex group delay compensation waveforms. The group delay frequency range and group delay value of each stage are calculated and calibrated based on the initial state being a direct-through state without group delay fluctuations. Specifically, the adjustable voltage range of the DAC (Digital-to-Analog Converter) is determined by the operating frequency range and the group delay value; the variable capacitance voltage control range is within 0V to 15V, and the DAC driver output voltage range covers 0V to 30V. Figure 2 As shown, the principle of achieving arbitrary group delay equalization is described using a third-order group delay equalization circuit as an example. This can be extended to group delay equalization circuits of more orders. The group delay equalization of a multi-stage cascaded adjustable group delay equalizer is as follows:

[0041] (1) Based on the target frequency of the system and the required group delay equalization range, the first level of equalization data is first performed to equalize the frequency point of the minimum group delay in the system to the group delay value close to the sideband position; if the target group delay fluctuation is achieved, the current DAC parameters are fixed.

[0042] (2) The second-stage group delay equalization circuit equalizes the maximum group delay value by controlling the voltage to the frequency point of the current minimum group delay; if the target group delay fluctuation is achieved, the current DAC parameters are fixed.

[0043] (3) The third-level group delay equalization circuit equalizes the maximum group delay value by controlling the voltage to the frequency point of the current minimum group delay; if the target group delay fluctuation is achieved, the current DAC parameters are fixed.

[0044] For situations requiring multi-stage group delay compensation, the voltage of each group delay compensation circuit can be controlled and compensated individually. Through the superposition of these characteristics, more complex waveform and numerical compensation can be achieved. Taking a 70MHz-100MHz group delay equalization circuit as an example... Figure 4 , Figure 5 By configuring the values ​​of adjustable capacitors C1 and C2 in different ways, the group delay characteristics can be quantitatively calculated to obtain the range of capacitors with good parameters, which serves as the boundary of the compensation correction control voltage. The range of variables for the entire group delay correction process can then be determined.

[0045] This invention proposes a group delay automatic equalization system, such as... Figure 3As shown, the system includes interconnected frequency converter channels with group delay to be optimized, a vector network analyzer for testing group delay, and an adjustable group delay equalizer, as well as a main control computer equipped with control software. The main control computer is bidirectionally connected to the vector network analyzer to read the group delay data from the instruments, and bidirectionally connected to the adjustable group delay equalizer to modify the equalization parameters based on the read data. After determining the final target group delay fluctuation parameters of the frequency converter channels, the initial parameters of the frequency converter channels and the group delay equalizer are tested. The control voltage of the group delay equalizer is adjusted using the control software to ensure that the group delay fluctuation of the cascaded frequency converter channels and group delay equalizer meets the target requirements.

[0046] This invention also proposes a group delay automatic equalization method, such as... Figure 6 As shown, it includes the following steps:

[0047] Step S1: Set up an automatic equalization system and test the initial group delay data within the frequency band of the frequency channel to be compensated. The test group latency was obtained. Represented as , and These represent the initial group delay data. The maximum and minimum values; define the target group delay. The objective of group delay equilibrium is obtained as follows: ;

[0048] Step S2: Testing After determining the frequency point, adjust the voltages of differential input interfaces VT1 and VT2 (the relationship between the voltages of VT1 and VT2 and the frequency range is known through previous circuit testing), and change the capacitance value of the adjustable capacitor C2 so that the center frequency point of the group delay compensation equals... Frequency points;

[0049] Step S3: Adjust the voltage difference between differential input interface VT1 and differential input interface VT2 (the relationship between the voltage of VT1-VT2 and the group delay amplitude range is known through previous circuit testing) to change the capacitance value of adjustable capacitor C1, thereby adjusting the group delay amplitude at this frequency point;

[0050] Step S4: Calculate the new test group latency and with The comparison is performed; if the result is better than the previous state, the voltages of differential input interfaces VT1 and VT2 are increased, and vice versa; thus, the new test group delay is obtained. ; Indicates the number of comparisons and ; and These represent the new group latency data. The maximum and minimum values;

[0051] Step S5: Repeat steps S2 to S4 to correct the parameters of adjustable capacitor C1 and adjustable capacitor C2 and optimize the group delay parameters.

[0052] Step S6: In the main control computer software, set the number of iterations and the group delay equalization circuit level used, for example, set 100 iterations and 3 levels of group delay equalization. The optimization strategy can be as follows: if the target value is not reached after 10 optimizations of each level of group delay equalization circuit, then activate the second level of adjustable group delay equalization circuit. Repeat steps S1 to S5 until the target group delay is achieved.

[0053] The software control algorithm described above optimizes the lowest group delay frequency point in each iteration. Through multi-level group delay equalization compensation of low group delay points within the frequency band, the complex group delay waveform can ultimately be compensated into a flat ripple characteristic. The automatic group delay equalization waveform optimization feature is as follows: Figure 7 As shown.

[0054] For the foregoing embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0055] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A group delay equalization circuit, characterized in that, The adjustable group delay equalizer includes a single-stage structure or a multi-stage cascaded structure. The single-stage structure of the adjustable group delay equalizer includes a control module consisting of a microcontroller (MCU), a flash memory, two DACs (digital-to-analog converters), and a symmetrical resonant network. The MCU is bidirectionally connected to the flash memory and is connected to the two DACs. The outputs of the two DACs are each connected to a driver module and then to the symmetrically arranged differential input interfaces VT1 and VT2 of the symmetrical resonant network. The FLASH is used to store optimized configuration parameters and solidify the group delay compensation status. An adjustable capacitor C1 is provided between the differential input interface VT1 and the differential input interface VT2 of the symmetrical resonant network. Resistors R1 and R2 are connected in series between the adjustable capacitor C1 and the differential input interface VT1 and the differential input interface VT2, respectively. Two adjustable capacitors C2 are connected in parallel across the two ends of the adjustable capacitor C1. An inductor L2 is connected to ground in parallel between the two adjustable capacitors C2. The symmetrical resonant network also includes an inductor L1 that forms a parallel resonant branch with the two adjustable capacitors C2. The adjustable group delay equalizer is configured to be used in conjunction with a vector network analyzer and a main control computer, and automatically optimizes the group delay parameters through the following steps: Step S1: Test the initial group delay data within the frequency band of the frequency converter channel to be compensated. The latency fluctuation of the test group was obtained. Represented as , and These represent the initial group delay data. The maximum and minimum values; Define target group delay fluctuation After obtaining the group delay equilibrium state, the state is as follows: ; Step S2: Testing After determining the frequency point, adjust the voltages of differential input interfaces VT1 and VT2, and change the capacitance value of adjustable capacitor C2 so that the center frequency of group delay compensation equals... Frequency points; Step S3: Adjust the voltage difference between differential input interface VT1 and differential input interface VT2 to change the capacitance value of adjustable capacitor C1, thereby adjusting the group delay amplitude at this frequency point; Step S4: Calculate the new test group latency and with The comparison is performed; if the result is better than the previous state, the voltages of differential input interfaces VT1 and VT2 are increased; otherwise, they are decreased. This yields the new test group delay. ; Indicates the number of comparisons and ; and These represent the new group latency data. The maximum and minimum values; Step S5: Repeat steps S2 to S4 to correct the parameters of adjustable capacitor C1 and adjustable capacitor C2 and optimize the group delay parameters. Step S6: Set the number of iterations and the group delay equalization circuit level used in the main control computer control software, configure the optimization strategy, and if the preset number of optimizations of each group delay equalization circuit level does not reach the target value, start the next adjustable group delay equalization circuit level for compensation. Repeat steps S1 to S5 until the target group delay is reached.

2. The group delay equalization circuit as described in claim 1, characterized in that, A filter capacitor C3 is connected in parallel to ground between the differential input interface VT1 and the resistor R1, and a filter capacitor C4 is connected in parallel to ground between the differential input interface VT2 and the resistor R2.

3. The group delay equalization circuit as described in claim 1, characterized in that, The adjustable capacitors C1 and C2 are varactor diodes, based on the group delay propagation response characteristics of the all-pass filter network. and approximate output waveform The center frequency of the group delay compensation is changed by adjusting the capacitance value of the adjustable capacitor C2, and the peak value of the group delay compensation is changed by adjusting the capacitance value of the adjustable capacitor C1.

4. The group delay equalization circuit as described in claim 3, characterized in that, The multi-stage cascaded adjustable group delay equalizer includes a control module and multiple stages of symmetrical resonant networks. The control module is connected to the drive module corresponding to each stage of the symmetrical resonant network. By selecting different equalization paths for the symmetrical resonant networks, the delay compensation amount of each symmetrical resonant network is controlled to achieve complex group delay compensation waveforms. The group delay frequency range and group delay value of each stage are calculated and calibrated based on the initial state being a straight-through state without group delay fluctuations. Specifically, the adjustable voltage range of the DAC is determined by the operating frequency range and the group delay value; the variable capacitance voltage control range is within 0V to 15V, and the DAC drive output voltage range covers 0V to 30V.

5. A group delay automatic equalization system, characterized in that, The system includes interconnected frequency conversion channels for optimizing group delay, a vector network analyzer for testing group delay, and an adjustable group delay equalizer in a group delay equalization circuit as described in any one of claims 1 to 4. It also includes a main control computer configured with control software. The main control computer is bidirectionally connected to the vector network analyzer to read the instrument's group delay data, and bidirectionally connected to the adjustable group delay equalizer to modify the equalization parameters through the read data.

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