Signal cycle jitter determination method and apparatus, electronic device, and storage medium
By calculating the zero-crossing time of the differential signal output signal of the MIPI interface C-PHY, the target zero-crossing time and clock frequency period are determined, solving the problem of the inability to quantify period jitter in the existing technology, and improving signal quality and circuit design reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XINXIANG MICRO (SHANGHAI) ELECTRONIC TECHNOLOGY CO LTD
- Filing Date
- 2024-11-28
- Publication Date
- 2026-05-29
AI Technical Summary
Existing technologies cannot effectively determine the period jitter of the C-PHY output signal of the MIPI interface, which makes it impossible to guide circuit optimization design and affects the upper limit of signal output speed.
By acquiring the C-PHY output signal from the MIPI transmitter, the zero-crossing times of the differential signals of the first, second, and third signals are calculated to determine the target zero-crossing time, and the period jitter is calculated based on the clock frequency period.
It achieves the quantization of the periodic jitter of the C-PHY output signal, guides circuit optimization design, and improves signal quality and circuit design reliability.
Smart Images
Figure CN122120165A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of communication interface technology, and in particular relates to a method, apparatus, electronic device and computer-readable storage medium for determining signal period jitter. Background Technology
[0002] The Mobile Industry Processor Interface (MIPI) is a serial communication interface used to connect various components within a mobile terminal device, enabling data transmission between these components. For example, a mobile phone's processor connects to the camera and display screen via the MIPI interface, and the camera can transmit captured image data to the processor through the MIPI interface.
[0003] The MIPI interface includes physical layer specifications such as D-PHY, C-PHY, and M-PHY. The jitter of the C-PHY output signal of the MIPI interface can determine the quality of the MIPI output signal. Significant jitter in the C-PHY output signal will affect the upper limit of the MIPI signal output speed. Therefore, to ensure the performance of the MIPI interface, the jitter immunity of the system or chip's receiver can be tested during the chip design phase to identify defects in the circuit design in advance and reduce the risk of chip fabrication failure.
[0004] Currently, oscilloscopes are typically used to measure the time interval error (TIE) jitter of the C-PHY output signal of the MIPI interface, thereby testing the jitter resistance of the MIPI interface. However, TIE jitter alone cannot determine the period jitter (PJ) of the C-PHY output signal, and therefore cannot guide circuit optimization design. Summary of the Invention
[0005] This application provides a method, apparatus, electronic device, and computer-readable storage medium for determining signal period jitter, which can determine the period jitter of the C-PHY output signal of the MIPI interface.
[0006] In a first aspect, embodiments of this application provide a method for determining signal period jitter, the method comprising:
[0007] Acquire the C-PHY output signal from the MIPI transmitter. The C-PHY output signal includes a first signal, a second signal, and a third signal.
[0008] Based on the first signal, the second signal, and the third signal, a first differential signal, a second differential signal, and a third differential signal are obtained. The first differential signal is the signal obtained by subtracting the first signal from the second signal, the second differential signal is the signal obtained by subtracting the second signal from the third signal, and the third differential signal is the signal obtained by subtracting the third signal from the first signal.
[0009] Multiple target zero-crossing times are determined from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal. The target zero-crossing time is the earliest zero-crossing time among the multiple zero-crossing times belonging to the same inversion point.
[0010] By subtracting the zero-crossing times of two targets with adjacent timing sequences, multiple clock frequency cycles can be obtained.
[0011] The period jitter of the C-PHY output signal is determined based on multiple clock cycles.
[0012] As can be seen from the above technical solution, after determining three differential signals based on the C-PHY output signal, the embodiment of this application determines the target zero-crossing time from the zero-crossing times of the three differential signals, and determines multiple clock frequency cycles based on multiple target zero-crossing times. Then, based on multiple clock frequency cycles, the period jitter of the C-PHY output signal can be determined, thus realizing the quantification of the period jitter of the C-PHY output signal.
[0013] In some possible implementations of the first aspect, the periodic jitter of the C-PHY output signal is determined based on multiple clock cycles, including:
[0014] Determine the ideal clock frequency period based on multiple clock frequency periods;
[0015] The jitter of multiple clock cycles is obtained by subtracting each clock cycle from the ideal clock cycle.
[0016] The periodic jitter of the C-PHY output signal is determined based on the jitter of multiple clock cycles.
[0017] In some possible implementations of the first aspect, the ideal clock frequency period is determined based on multiple clock frequency periods, including:
[0018] Determine the average value of multiple clock cycles;
[0019] The average value is determined as the ideal clock frequency period.
[0020] In some possible implementations of the first aspect, the periodic jitter of the C-PHY output signal is determined based on the jitter of multiple clock cycles, including:
[0021] The maximum value among the jitters of multiple clock cycles is determined as the periodic jitter of the C-PHY output signal.
[0022] In some possible implementations of the first aspect, multiple target zero-crossing times are determined from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal, including:
[0023] The zero-crossing times of the first differential signal are recorded in the first array, the zero-crossing times of the second differential signal are recorded in the second array, and the zero-crossing times of the third differential signal are recorded in the third array.
[0024] Merge the first, second, and third arrays, and sort the multiple zero-crossing moments in chronological order to obtain the first target array;
[0025] For multiple zero-crossing moments belonging to the same inversion point in the first target array, retain the target zero-crossing moment and remove the zero-crossing moments other than the target zero-crossing moment to obtain the second target array, which includes multiple target zero-crossing moments.
[0026] In some possible implementations of the first aspect, for multiple zero-crossing moments belonging to the same inversion point in the first target array, the target zero-crossing moment is retained, and the zero-crossing moments other than the target zero-crossing moment are removed to obtain the second target array, including:
[0027] Copy the first target array to obtain a copied array;
[0028] For the i-th element in the first target array, determine the difference between the i-th element and the (i-1)-th element in the first target array; if the difference is less than or equal to a preset threshold, the i-th position in the copied array will be the target value; if the difference is greater than the preset threshold, the i-th position in the copied array will remain unchanged.
[0029] Determine whether the i-th element of the first target array is the last element;
[0030] If not, after i = i + 1, return to the step of determining the difference between the i-th element and the (i-1)-th element in the first target array for the i-th element in the first target array;
[0031] If so, delete the elements in the copied array that are set to the target value, and obtain the second target array;
[0032] Where, the element is the zero-crossing moment, and the element in the copied array that has not been set to the target value is the target zero-crossing moment; if the difference is less than or equal to the preset threshold, the i-th element and the (i-1)-th element belong to the same reversal point; i is a positive integer greater than or equal to 2.
[0033] Secondly, embodiments of this application provide a signal period jitter determination device, comprising:
[0034] The signal acquisition module is used to acquire the C-PHY output signal of the MIPI transmitter. The C-PHY output signal includes a first signal, a second signal, and a third signal.
[0035] The differential processing module is used to obtain a first differential signal, a second differential signal, and a third differential signal based on the first signal, the second signal, and the third signal. The first differential signal is the signal obtained by subtracting the first signal from the second signal, the second differential signal is the signal obtained by subtracting the second signal from the third signal, and the third differential signal is the signal obtained by subtracting the third signal from the first signal.
[0036] The determination module is used to determine multiple target zero-crossing times from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal. The target zero-crossing time is the earliest zero-crossing time among the multiple zero-crossing times belonging to the same inversion point.
[0037] The difference module is used to subtract the zero-crossing times of two targets with adjacent timings to obtain multiple clock frequency cycles;
[0038] The period jitter determination module is used to determine the period jitter of the C-PHY output signal based on multiple clock cycles.
[0039] In some possible implementations of the second aspect, the period jitter determination module is specifically used for:
[0040] Determine the ideal clock frequency period based on multiple clock frequency periods;
[0041] The jitter of multiple clock cycles is obtained by subtracting each clock cycle from the ideal clock cycle.
[0042] The periodic jitter of the C-PHY output signal is determined based on the jitter of multiple clock cycles.
[0043] Thirdly, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method as described in any of the first aspects above.
[0044] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in any of the first aspects above.
[0045] Fifthly, embodiments of this application provide a computer program product that, when run on an electronic device, causes the electronic device to perform the method described in any one of the first aspects above.
[0046] It is understood that the beneficial effects of the second to fifth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description
[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0048] Figure 1 A schematic flowchart of a signal period jitter determination method provided in an embodiment of this application;
[0049] Figure 2 A schematic block diagram of the transmitting and receiving ends of a C-PHY circuit provided in an embodiment of this application;
[0050] Figure 3 This is a schematic diagram of the signal waveform provided in an embodiment of this application;
[0051] Figure 4 This is a schematic diagram of the signal waveform provided in an embodiment of this application;
[0052] Figure 5 A flowchart illustrating the process of determining the target zero-crossing time provided in the embodiments of this application;
[0053] Figure 6 A flowchart illustrating the zero-crossing time array processing provided in this application embodiment;
[0054] Figure 7 This is a schematic block diagram of the signal period jitter device provided in an embodiment of this application;
[0055] Figure 8 A schematic block diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation
[0056] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.
[0057] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.
[0058] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0059] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."
[0060] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0061] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0062] Please see Figure 1 This is a schematic flowchart of a signal period jitter determination method provided in an embodiment of this application. The method includes the following steps:
[0063] Step S101: Obtain the C-PHY output signal from the MIPI transmitter. The C-PHY output signal includes a first signal, a second signal, and a third signal.
[0064] In practical applications, the C-PHY output signal from the MIPI transmitter within a preset time period is acquired; the anti-jitter capability of the C-PHY output signal within the preset time period is tested to verify the overall quality of the MIPI output signal.
[0065] The C-PHY of the MIPI transmitter includes at least one data channel (or transmission link), and each data channel may include three data lines, each of which can be used to transmit data signals. These data signals can be image data signals.
[0066] For example, see Figure 2 The diagram shows a schematic block diagram of the C-PHY circuit's transmitter and receiver. The MIPI transmitter (MIPI TX) includes a MIPI parallel to serial (P2S) module and a MIPI data lane. The P2S module is used to convert parallel data into serial data.
[0067] After passing through the MIPIP2S module and the MIPI data channel, the image data outputs three signals, VA, VB, and VC, to the MIPI receiver (MIPI RX). The MIPI receiver performs decoding, clocking, and recovery processes based on the VA, VB, and VC signals to post-process the image data.
[0068] exist Figure 2 In C-PHY, the output signals include three signals: VA, VB, and VC. That is, the first signal, the second signal, and the third signal can be VA, VB, and VC, respectively.
[0069] Step S102: Based on the first signal, the second signal, and the third signal, obtain the first differential signal, the second differential signal, and the third differential signal. The first differential signal is the signal obtained by subtracting the first signal from the second signal, the second differential signal is the signal obtained by subtracting the second signal from the third signal, and the third differential signal is the signal obtained by subtracting the third signal from the first signal.
[0070] For example, see Figure 3 The illustrated signal waveform diagram includes the waveforms of the VA signal, the VB signal, and the VC signal; it also includes the waveforms of the VA-VB signal, the VB-VC signal, and the VC-VA signal.
[0071] This involves using an oscilloscope or similar device to acquire the C-PHY output signal from the MIPI transmitter, obtaining the VA, VB, and VC signal waveforms; and then copying the VA, VB, and VC signal waveforms within a preset time period from the oscilloscope or similar device to obtain, for example... Figure 3 The waveforms of the VA, VB, and VC signals are shown.
[0072] Differential processing is performed on the VA signal and the VB signal to obtain the VA-VB signal; differential processing is performed on the VB signal and the VC signal to obtain the VB-VC signal; differential processing is performed on the VC signal and the VA signal to obtain the VC-VA signal.
[0073] The waveforms of the VA-VB signal, VB-VC signal, and VC-VA signal can be as follows: Figure 3 As shown in the waveform diagrams of these three differential signals, the four high and low levels from top to bottom are defined as strong1, weak1, weak0, and strong0, respectively. The zero crossing is between weak1 and weak0.
[0074] By combining the different high and low levels of the three data signal lines, six wire states can be obtained, namely +x, -x, +y, -y, +z, and -z.
[0075] exist Figure 3 In this configuration, the first signal can be VA, the second signal can be VB, and the third signal can be VC. The first differential signal can be VA-VB, the second differential signal can be VB-VC, and the third differential signal can be VC-VA.
[0076] Step S103: Determine multiple target zero-crossing times from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal. The target zero-crossing time is the earliest zero-crossing time among the multiple zero-crossing times belonging to the same reversal point.
[0077] The zero-crossing point refers to the moment or time point when the differential signal curve crosses a zero. Each differential signal can have multiple zero-crossing points. For example, ... Figure 3 In the zero crossing, the waveform of the VC-VA signal will pass through zero crossing multiple times, with multiple zero-crossing moments.
[0078] After recording the zero-crossing times of the first, second, and third differential signals respectively, these three differential signals can be integrated into a zero-crossing time sequence according to their chronological order. This zero-crossing time sequence includes multiple zero-crossing times ordered chronologically, with the first zero-crossing time being the earliest and the last zero-crossing time being the latest.
[0079] After obtaining the sequence of zero-crossing moments, the difference between two adjacent zero-crossing moments can be used to determine whether they belong to the same inversion point. If the difference between two adjacent zero-crossing moments is less than or equal to a preset threshold, they are considered to belong to the same inversion point; conversely, if the difference between two adjacent zero-crossing moments is greater than the preset threshold, they are considered not to belong to the same inversion point. Based on this principle, multiple zero-crossing moments belonging to the same inversion point can be determined.
[0080] After identifying multiple zero-crossing moments belonging to the same reversal point, the earliest zero-crossing moment is determined from these multiple zero-crossing moments. This earliest zero-crossing moment is the target zero-crossing moment.
[0081] There will be multiple reversal points within a preset time period. The zero-crossing time of the target can be determined by the above process for each reversal point, thus obtaining multiple zero-crossing times of the target.
[0082] For example, see Figure 4 The diagram shown is a schematic representation of the signal waveform provided in an embodiment of this application. Figure 4 The top image shows the signal waveforms corresponding to the line state combinations +x, -x, and +y, while the bottom image shows the signal waveforms corresponding to the line state combinations -z, +x, and +y. That is, according to... Figure 3 The waveforms of the three differential signals shown are obtained under different line conditions, as follows: Figure 4 The signal waveform diagram is shown below.
[0083] against Figure 4 In the above figure, the first half of the curves BC, CA, and AB all pass through the zero point, and these three zero-crossing moments belong to the same reversal point. At this time, the zero-crossing moments of the BC and CA curves are the same, while the zero-crossing moment of the AB curve is earlier than that of the BC curve. Therefore, the zero-crossing moment of the AB curve is the target zero-crossing moment.
[0084] In the latter half, curve CA does not cross the zero point, while curves BC and AB both cross the zero point. Furthermore, the zero-crossing times of curves BC and AB belong to the same reversal point. At this point, curve BC crosses the zero point before curve AB, meaning that the zero-crossing time of curve BC is earlier. Therefore, the zero-crossing time of curve BC is the target zero-crossing time.
[0085] Among them, the BC curve refers to the waveform curve of the VB-VC signal, the AB curve refers to the waveform curve of the VA-VB signal, and the CA curve is the waveform curve of the VC-VA signal.
[0086] Similarly, regarding Figure 4 In the figure below, curves AB and CA in the first half do not pass through the zero point, only curve BC passes through the zero point. Therefore, for the reversal point of the first half, the zero-crossing time of curve BC is the target zero-crossing time.
[0087] In the latter half, curve CA does not cross the zero point, while curves AB and BC both cross the zero point. Furthermore, the zero-crossing times of curves AB and BC belong to the same reversal point. At this point, curve AB crosses the zero point before curve BC, meaning that the zero-crossing time of curve AB is earlier. Therefore, the zero-crossing time of curve AB is the target zero-crossing time.
[0088] Understandable Figure 4 The top and bottom images show the same waveform at different times.
[0089] Step S104: Subtract the zero-crossing times of two targets with adjacent timing sequences to obtain multiple clock frequency cycles.
[0090] As shown above, after obtaining the zero-crossing times of multiple targets, the zero-crossing times of multiple targets are sorted in chronological order, and then the difference between two adjacent zero-crossing times of targets in the time sequence is calculated to obtain multiple clock cycles (UI).
[0091] For example, such as Figure 4 As shown in the figure above, subtracting the zero-crossing time of the first half of the AB curve from the zero-crossing time of the second half of the BC curve yields the clock frequency period UI. CHAN .
[0092] Where, is the UI length of the current signal time. Figure 4 UI in AVERAGE It is the ideal UI of the signal. TRIGGER is the marker for the transition between each data, and the time between two markers is the clock frequency cycle.
[0093] Step S105: Determine the period jitter of the C-PHY output signal based on multiple clock frequency cycles.
[0094] In some embodiments, the ideal clock frequency period can be determined first based on multiple clock frequency periods; then, the difference between each clock frequency period and the ideal clock frequency period can be calculated to obtain the jitter of multiple clock frequency periods; finally, the periodic jitter of the C-PHY output signal can be determined based on the jitter of multiple clock frequency periods.
[0095] In determining the ideal clock frequency period based on multiple clock frequency periods, the average value of the multiple clock frequency periods can be determined first, and this average value can be used as the ideal clock frequency period (UI). AVERAGE Of course, in other embodiments, the ideal clock frequency period can also be determined in other ways, which are not limited here.
[0096] After determining the ideal clock frequency period, use UI_jitter CHAN(n) =|UI AVERAGE -UI CHAN(n) | This calculates the jitter of the clock cycle. Specifically, UI_jitter CHAN(n) It is the jitter of the nth clock cycle, UI CHAN(n) It is the nth clock cycle.
[0097] After determining the jitter UI_jitter across multiple clock cycles, the maximum value among these jitter values is defined as the periodic jitter PJ of the C-PHY output signal. Based on PJ, the overall quality of the MIPI C-PHY output signal can be determined, which in turn guides chip circuit design.
[0098] In this embodiment of the application, after determining three differential signals based on the C-PHY output signal, the target zero-crossing time is determined from the zero-crossing times of the three differential signals, and multiple clock frequency cycles are determined based on multiple target zero-crossing times. Then, the period jitter of the C-PHY output signal can be determined based on the multiple clock frequency cycles, thereby realizing the quantization of the period jitter of the C-PHY output signal.
[0099] In some embodiments, the zero-crossing times of the three differential signals can be recorded in an array, and multiple target zero-crossing times can be determined by integrating the array.
[0100] Based on the above embodiments, see Figure 5 The flowchart shown in this embodiment of the present application illustrates the process for determining the target zero-crossing time. The process of determining multiple target zero-crossing times from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal may include the following steps:
[0101] Step S501: Record the zero-crossing time of the first differential signal in the first array, the zero-crossing time of the second differential signal in the second array, and the zero-crossing time of the third differential signal in the third array.
[0102] Step S502: Merge the first array, the second array, and the third array, and sort the multiple zero-crossing moments in chronological order to obtain the first target array.
[0103] The first target array includes multiple zero-crossing moments, with the first zero-crossing moment being the earliest and the last zero-crossing moment being the latest.
[0104] Step S503: For multiple zero-crossing moments belonging to the same inversion point in the first target array, retain the target zero-crossing moment and remove the zero-crossing moments other than the target zero-crossing moment to obtain the second target array, which includes multiple target zero-crossing moments.
[0105] In some embodiments, see Figure 6 The flowchart shown illustrates the processing of the zero-crossing time array. First, the first target array is copied to obtain a copied array. The copied array is identical to the first target array, and the i-th element of the copied array is the same as the i-th element of the first target array. The elements in both the copied array and the first target array represent the zero-crossing times, and the elements are sorted in chronological order.
[0106] Then, for the i-th element in the first target array, determine the difference between the i-th element and the (i-1)-th element in the first target array; if the difference is less than or equal to a preset threshold, the i-th position in the copy array will be the target value; if the difference is greater than the preset threshold, the i-th position in the copy array will remain unchanged.
[0107] The target value and preset threshold can be set according to actual needs. For example, the target array can be 0, and the preset threshold can be 0.1 UI.
[0108] In this embodiment, if the difference between the i-th element and the (i-1)-th element is less than or equal to a preset threshold, then the i-th element and the (i-1)-th element are considered to belong to the same inversion point; conversely, if the difference between the i-th element and the (i-1)-th element is greater than the preset threshold, then the i-th element and the (i-1)-th element are considered not to belong to the same inversion point. i is a positive integer greater than or equal to 2.
[0109] Next, it is further determined whether the i-th element of the first target array is the last element. If not, after i = i + 1, the step of determining the difference between the i-th element and the (i-1)-th element in the first target array is returned; if yes, the element set to the target value in the copied array is deleted to obtain the second target array.
[0110] Elements in the copied array that are not set to the target value represent the target's zero-crossing point and should be retained; elements in the copied array that are set to the target array do not represent the target's zero-crossing point and should be removed. Figure 6 The process involves comparing the difference between two adjacent zero-crossing points with a set threshold. Points with a difference less than the threshold are discarded, while points with a difference greater than the threshold are retained.
[0111] Of course, the second target array can also be obtained in other ways. For example, in Figure 6 In this process, without obtaining a copy array, if the difference between the i-th element and the (i-1)-th element in the first target array is less than or equal to a preset threshold, the i-th element in the first target array can be marked as 0; conversely, if the difference is greater than the preset threshold, the i-th element in the first target array remains unchanged. After comparing the last element in the first target array, the elements marked as 0 in the first target array can be deleted, thus obtaining the second target array.
[0112] The second target array includes the zero-crossing times of multiple targets, and these zero-crossing times are sorted in chronological order.
[0113] In this embodiment of the application, the target zero-crossing time can be determined more conveniently from multiple zero-crossing times through the array processing procedure shown above.
[0114] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0115] Corresponding to the signal period jitter determination method described in the above embodiments, Figure 7 A schematic block diagram of the signal period jitter determination device provided in an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiment of this application are shown.
[0116] Reference Figure 7 The device includes:
[0117] The signal acquisition module 71 is used to acquire the C-PHY output signal of the MIPI transmitter. The C-PHY output signal includes a first signal, a second signal, and a third signal.
[0118] The differential processing module 72 is used to obtain a first differential signal, a second differential signal, and a third differential signal based on the first signal, the second signal, and the third signal. The first differential signal is the signal obtained by subtracting the first signal from the second signal, the second differential signal is the signal obtained by subtracting the second signal from the third signal, and the third differential signal is the signal obtained by subtracting the third signal from the first signal.
[0119] The determination module 73 is used to determine multiple target zero-crossing times from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal. The target zero-crossing time is the earliest zero-crossing time among the multiple zero-crossing times belonging to the same inversion point.
[0120] The difference module 74 is used to subtract the zero-crossing times of two targets with adjacent timings to obtain multiple clock frequency cycles;
[0121] The period jitter determination module 75 is used to determine the period jitter of the C-PHY output signal based on multiple clock frequency cycles.
[0122] In some possible implementations, the period jitter determination module 75 is specifically used to: determine the ideal clock frequency period based on multiple clock frequency periods; subtract each clock frequency period from the ideal clock frequency period to obtain the jitter of multiple clock frequency periods; and determine the period jitter of the C-PHY output signal based on the jitter of multiple clock frequency periods.
[0123] In some possible implementations, the cycle jitter determination module 75 is specifically used to: determine the average value of multiple clock frequency cycles; and determine the average value as the ideal clock frequency cycle.
[0124] In some possible implementations, the period jitter determination module 75 is specifically used to: determine the maximum value among the jitters of multiple clock cycles as the period jitter of the C-PHY output signal.
[0125] In some possible implementations, module 73 is specifically used for:
[0126] The zero-crossing times of the first differential signal are recorded in the first array, the zero-crossing times of the second differential signal are recorded in the second array, and the zero-crossing times of the third differential signal are recorded in the third array.
[0127] Merge the first, second, and third arrays, and sort the multiple zero-crossing moments in chronological order to obtain the first target array;
[0128] For multiple zero-crossing moments belonging to the same inversion point in the first target array, retain the target zero-crossing moment and remove the zero-crossing moments other than the target zero-crossing moment to obtain the second target array, which includes multiple target zero-crossing moments.
[0129] In some possible implementations, module 73 is specifically used for:
[0130] Copy the first target array to obtain a copied array;
[0131] For the i-th element in the first target array, determine the difference between the i-th element and the (i-1)-th element in the first target array; if the difference is less than or equal to a preset threshold, the i-th position in the copied array will be the target value; if the difference is greater than the preset threshold, the i-th position in the copied array will remain unchanged.
[0132] Determine whether the i-th element of the first target array is the last element;
[0133] If not, after i = i + 1, return to the step of determining the difference between the i-th element and the (i-1)-th element in the first target array for the i-th element in the first target array;
[0134] If so, delete the elements in the copied array that are set to the target value, and obtain the second target array;
[0135] Where, the element is the zero-crossing moment, and the element in the copied array that has not been set to the target value is the target zero-crossing moment; if the difference is less than or equal to the preset threshold, the i-th element and the (i-1)-th element belong to the same reversal point; i is a positive integer greater than or equal to 2.
[0136] It should be noted that the information interaction and execution process between the above-mentioned devices / modules are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.
[0137] Figure 8 This is a schematic block diagram of the structure of an electronic device provided in an embodiment of this application. Figure 8 As shown, the electronic device 8 of this embodiment includes: at least one processor 80 ( Figure 8 (Only one is shown in the diagram), memory 81, and computer program 82 stored in said memory 81 and executable on said at least one processor 80, which, when executed, implements the steps in any of the above method embodiments.
[0138] The electronic device may include, but is not limited to, a processor 80 and a memory 81. Those skilled in the art will understand that... Figure 8 This is merely an example of electronic device 8 and does not constitute a limitation on electronic device 8. It may include more or fewer components than shown, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.
[0139] The processor 80 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.
[0140] In some embodiments, the memory 81 may be an internal storage unit of the electronic device 8, such as a hard disk or memory of the electronic device 8. In other embodiments, the memory 81 may be an external storage device of the electronic device 8, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 8. Furthermore, the memory 81 may include both internal and external storage units of the electronic device 8. The memory 81 is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory 81 can also be used to temporarily store data that has been output or will be output.
[0141] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0142] Furthermore, the specific names of each functional unit and module are merely for ease of differentiation and are not intended to limit the scope of protection of this application. The specific working processes of the units and modules in the above system can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.
[0143] This application also provides an electronic device, which includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor, wherein the processor executes the computer program to implement the steps in any of the above method embodiments.
[0144] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.
[0145] This application provides a computer program product that, when run on an electronic device, enables the electronic device to perform the steps described in the various method embodiments above.
[0146] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.
[0147] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0148] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0149] In the embodiments provided in this application, it should be understood that the disclosed devices, electronic devices, and methods can be implemented in other ways. For example, the device / electronic device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings or direct couplings or communication connections may be through some interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.
[0150] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.
[0151] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for determining signal period jitter, characterized in that, include: Acquire the C-PHY output signal from the MIPI transmitter, wherein the C-PHY output signal includes a first signal, a second signal, and a third signal; Based on the first signal, the second signal, and the third signal, a first differential signal, a second differential signal, and a third differential signal are obtained. The first differential signal is the signal obtained by subtracting the first signal from the second signal. The second differential signal is the signal obtained by subtracting the second signal from the third signal. The third differential signal is the signal obtained by subtracting the third signal from the first signal. Multiple target zero-crossing times are determined from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal. The target zero-crossing time is the earliest zero-crossing time among the multiple zero-crossing times belonging to the same inversion point. By subtracting the zero-crossing times of two adjacent targets, multiple clock cycles are obtained. The period jitter of the C-PHY output signal is determined based on multiple clock cycles.
2. The method as described in claim 1, characterized in that, The period jitter of the C-PHY output signal is determined based on multiple clock frequency cycles, including: The ideal clock frequency period is determined based on the multiple clock frequency periods described. The jitter of multiple clock cycles is obtained by subtracting each of the clock cycles from the ideal clock cycle. The period jitter of the C-PHY output signal is determined based on the jitter of multiple clock frequency cycles.
3. The method as described in claim 2, characterized in that, Determining the ideal clock frequency period based on multiple clock frequency periods includes: Determine the average value of multiple clock frequency cycles; The average value is determined as the ideal clock frequency period.
4. The method as described in claim 2, characterized in that, Determining the periodic jitter of the C-PHY output signal based on the jitter of multiple clock frequency cycles includes: The maximum value among the jitter of multiple clock frequency cycles is determined as the period jitter of the C-PHY output signal.
5. The method according to any one of claims 1 to 4, characterized in that, Multiple target zero-crossing times are determined from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal, including: The zero-crossing times of the first differential signal are recorded in the first array, the zero-crossing times of the second differential signal are recorded in the second array, and the zero-crossing times of the third differential signal are recorded in the third array. The first array, the second array, and the third array are merged, and the multiple zero-crossing moments are sorted in chronological order to obtain the first target array; For multiple zero-crossing moments belonging to the same inversion point in the first target array, retain the target zero-crossing moments and remove the zero-crossing moments other than the target zero-crossing moments to obtain a second target array, which includes multiple target zero-crossing moments.
6. The method as described in claim 5, characterized in that, For multiple zero-crossing moments belonging to the same inversion point in the first target array, retain the target zero-crossing moment and remove the zero-crossing moments other than the target zero-crossing moment to obtain the second target array, including: Copy the first target array to obtain a copied array; For the i-th element in the first target array, determine the difference between the i-th element and the (i-1)-th element in the first target array; if the difference is less than or equal to a preset threshold, set the i-th position in the copy array to the target value; if the difference is greater than the preset threshold, the i-th position in the copy array remains unchanged. Determine whether the i-th element of the first target array is the last element; If not, after i = i + 1, return to the step of determining the difference between the i-th element and the (i-1)-th element in the first target array for the i-th element in the first target array; If so, delete the element in the copied array that is set to the target value to obtain the second target array; Wherein, the element is the zero-crossing time, and the element in the copy array that is not set to the target value is the target zero-crossing time; if the difference is less than or equal to the preset threshold, the i-th element and the (i-1)-th element belong to the same reversal point; i is a positive integer greater than or equal to 2.
7. A device for determining signal period jitter, characterized in that, include: The signal acquisition module is used to acquire the C-PHY output signal of the MIPI transmitter, wherein the C-PHY output signal includes a first signal, a second signal, and a third signal; The differential processing module is used to obtain a first differential signal, a second differential signal, and a third differential signal based on the first signal, the second signal, and the third signal. The first differential signal is the signal obtained by subtracting the first signal from the second signal, the second differential signal is the signal obtained by subtracting the second signal from the third signal, and the third differential signal is the signal obtained by subtracting the third signal from the first signal. The determination module is used to determine multiple target zero-crossing times from the zero-crossing times of the first differential signal, the second differential signal, and the third differential signal, wherein the target zero-crossing time is the earliest zero-crossing time among the multiple zero-crossing times belonging to the same inversion point. The difference module is used to subtract the zero-crossing times of two adjacent target points to obtain multiple clock frequency cycles; The period jitter determination module is used to determine the period jitter of the C-PHY output signal based on multiple clock frequency cycles.
8. The apparatus as claimed in claim 7, characterized in that, The periodic jitter determination module is specifically used for: The ideal clock frequency period is determined based on the multiple clock frequency periods described. The jitter of multiple clock cycles is obtained by subtracting each of the clock cycles from the ideal clock cycle. The period jitter of the C-PHY output signal is determined based on the jitter of multiple clock frequency cycles.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method as described in any one of claims 1 to 6.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 6.