A distributed interconnected access address mapping method, device, medium and product

Abstract

Embodiments of the present application disclose a distributed interconnected access address mapping method, device, medium and product. The method comprises: when a master node accesses a plurality of slave nodes in a distributed interconnected manner, obtaining an original access address; performing first address exchange processing on the original access address to rearrange each bit of the original access address and obtain a first exchanged address; performing multi-level hash processing on the first exchanged address according to the distributed structure of the slave nodes to obtain a hash discrete address; performing second address exchange processing on the hash discrete address to rearrange each bit of the hash discrete address and obtain a target access address, so that the master node accesses each slave node according to the target access address. Through the processing of "address exchange + multi-level hash + address exchange" on the original access address, the access address can be uniformly dispersed, and the access performance of the slave nodes is improved.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a distributed interconnection access address mapping method, device, medium, and product. Background Technology

[0002] With the development of computer technology, distributed structures are increasingly being used in data access to improve computing performance. For example, in a distributed interconnected world, a master node typically needs to perform distributed interconnection access to multiple slave nodes. Slave nodes can have a distributed structure with multiple access hierarchy domains.

[0003] In existing technologies, within a distributed interconnected world, access to slave nodes typically employs simple low-order address indexing. Under specific address access patterns, such as continuous address streams or cyclic access with a specific step size, these existing methods can easily lead to uneven address distribution. For example, they may cause some addresses on a slave node to be over-accessed, resulting in access conflicts, while other addresses remain idle, leading to a sharp drop in slave node performance.

[0004] Therefore, there is an urgent need to provide a distributed interconnection access address mapping method to improve the uniformity and dispersion of slave node address access and improve slave node performance. Summary of the Invention

[0005] This invention provides a distributed interconnection access address mapping method, device, medium, and product to uniformly discretize access addresses.

[0006] According to one aspect of the present invention, a method for mapping access addresses in a distributed interconnection is provided, the method comprising: When the master node performs distributed interconnection access to multiple slave nodes, the original access address is obtained; The original access address is subjected to a first address swapping process to rearrange the bits of the original access address to obtain a first swapped address; Based on the distributed structure of the slave nodes, the first exchange address is subjected to multi-level hashing to obtain a hash discrete address; The hash discrete address is subjected to a second address swapping process to rearrange the bits of the hash discrete address to obtain the target access address, so that the master node can access each of the slave nodes according to the target access address.

[0007] According to another aspect of the present invention, a distributed interconnection access address mapping apparatus is provided, the apparatus comprising: The original access address acquisition module is used to obtain the original access address when the master node performs distributed interconnection access to multiple slave nodes; The first address switching processing module is used to perform a first address switching process on the original access address to rearrange the bits of the original access address to obtain a first switched address. A multi-level hash processing module is used to perform multi-level hash processing on the first exchange address according to the distributed structure of the slave nodes to obtain a hash discrete address; The second address exchange processing module is used to perform a second address exchange processing on the hash discrete address to rearrange each bit of the hash discrete address to obtain a target access address, so that the master node can access each of the slave nodes according to the target access address.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one processor; and a memory communicatively connected to said at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the distributed interconnection access address mapping method according to any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the distributed interconnection access address mapping method according to any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the distributed interconnection access address mapping method described in any embodiment of the present invention.

[0011] The technical solution of this invention solves the problem of uniform discretization of access addresses by obtaining the original access address when the master node performs distributed interconnection access to multiple slave nodes; performing a first address exchange process on the original access address to rearrange the bits of the original access address to obtain a first exchange address; performing multi-level hashing processing on the first exchange address according to the distributed structure of the slave nodes to obtain a hash discrete address; and performing a second address exchange process on the hash discrete address to rearrange the bits of the hash discrete address to obtain a target access address, so that the master node can access each slave node according to the target access address. By performing "address exchange + multi-level hashing + address exchange" processing on the original access address, the access address can be uniformly discretized, improving the access performance of the slave nodes.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a flowchart of a distributed interconnection access address mapping method provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of a chip memory access structure provided in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of a first address switching processing circuit structure provided according to Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of a hash circuit structure provided in Embodiment 1 of the present invention; Figure 5 This is a flowchart of a distributed interconnection access address mapping method provided according to Embodiment 2 of the present invention; Figure 6 This is a schematic diagram of an off-center load correction process provided in Embodiment 2 of the present invention; Figure 7 This is a flowchart of another distributed interconnection access address mapping method provided according to Embodiment 2 of the present invention; Figure 8 This is a schematic diagram of a circuit structure for decrypting the first address exchange processing circuit according to Embodiment 2 of the present invention; Figure 9 This is a schematic diagram of the structure of a distributed interconnection access address mapping device according to Embodiment 3 of the present invention; Figure 10 This is a schematic diagram of the structure of an electronic device that implements the distributed interconnection access address mapping method of Embodiment 4 of the present invention. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1 This is a flowchart of a distributed interconnection access address mapping method according to Embodiment 1 of the present invention. This embodiment is applicable to situations where access addresses are uniformly discretized in a distributed interconnection world. The method can be executed by a distributed interconnection access address mapping device, which can be implemented in hardware and / or software. This distributed interconnection access address mapping device can be configured in electronic devices such as computers, mobile phones, smart devices, processors, or chips. Figure 1 As shown, the method includes: Step 110: When the master node performs distributed interconnection access to multiple slave nodes, obtain the original access address.

[0018] In a distributed interconnected world, one or more master nodes can access multiple slave nodes in a distributed interconnected manner. Slave nodes have a distributed structure. Optionally, the master node can be a chip, graphics processing unit (GPU), central processing unit (CPU), or vision processing unit (VPU); the slave node can be cache memory, memory, double data rate SDRAM (DDR), high bandwidth memory (HBM), or a protocol access port.

[0019] For example, a cache has a distributed structure, consisting of multiple independent cache slices, each slice containing multiple banks and sets. Memory has a distributed structure, consisting of multiple channels, each channel containing multiple bank groups and multiple banks. DDR has a distributed structure, consisting of multiple channels, each channel containing multiple ranks, multiple bank groups, and multiple banks. HBM has a distributed structure, consisting of multiple independent channels; each channel is divided into two pseudo-channels, each pseudo-channel containing several bank groups, each bank group containing multiple banks; the data storage units within each bank are organized in a row and column matrix. Protocol access ports use a distributed structure, consisting of multiple protocol channels, each protocol channel containing multiple independent access ports and multiple sub-ports.

[0020] The distributed interconnection access address mapping method provided in this embodiment of the invention can be applied to access nodes with distributed structures, such as cache, memory, DDR, HBM, or protocol access ports.

[0021] For example, Figure 2 This is a schematic diagram of a chip memory access structure according to Embodiment 1 of the present invention. Figure 2In this architecture, the master node can be an AI core, CPU, or VPU, etc. The master node can directly access distributed storage, meaning it can directly access slave nodes with a distributed structure. Figure 2 In this system, slave nodes can be caches or memory, etc. The master node accesses slave nodes through the Network on-Chip (NOC). For example, a cache consists of multiple banks, which can be located to the corresponding set via a group index, and data storage is completed in multiple ways within the set. Memory has different channels.

[0022] By processing the raw access addresses when the master node accesses the slave node, access domains in the distributed slave node structure can be accessed more evenly. An access domain can be a storage area or an interface, etc.

[0023] Step 120: Perform a first address swap on the original access address to rearrange the bits of the original access address to obtain the first swap address.

[0024] The first address swapping process can be a rearrangement of the bits of the original access address. In this embodiment of the invention, the first address swapping process can distribute the original access address, thereby homogenizing the results of subsequent multi-level hashing processes. The goal of a hash algorithm is to uniformly discretize the global address within the hash scope. However, the uniform discretization effect achieved by a hash algorithm for a specific input may be poor. To improve the uniform discretization effect of the hash algorithm for a specific input, the first address swapping process can be performed on the bits of the original access address.

[0025] In the first address exchange process, the address mapping relationship can be determined experimentally. For example, during initialization, the address mapping relationship can be randomly determined and used for the first address exchange of the original access addresses. Then, multi-level hashing is performed. In multi-level hashing, the optimal performance of uniform address discretization can be achieved by adjusting the hash algorithm. When determining the hash algorithm in the multi-level hashing process, its weaknesses can be identified, and the address mapping relationship can be adjusted based on these weaknesses to obtain the final address mapping relationship. Finally, the address mapping relationship can be fixed. In practical applications, the fixed address mapping relationship can be directly used for the first address exchange of the original access addresses. Through the first address exchange process, multi-level hashing can achieve uniform address discretization for different original access addresses.

[0026] In an optional embodiment of the present invention, the first address switching process can be implemented by hardware circuitry. Optionally, the first address switching process is performed on the original access address to rearrange the bits of the original access address to obtain the first switched address, including: constructing a crossbar switch network using N configuration registers and multiplexers, where N is the address bit width, each configuration register stores a location index, and the location indices in each configuration register are different; when performing the first address switching process on the original access address, the target location index of the current configuration register corresponding to the current bit of the first switched address is determined by the crossbar switch network; the target location index bit of the original access address is used as the current bit of the first switched address.

[0027] For example, Figure 3 This is a schematic diagram of a first address switching processing circuit structure provided according to Embodiment 1 of the present invention. Figure 3 As shown, for example, with an address width of 27 bits, 27 configuration registers can be configured. Each configuration register can store a location index. For example, in... Figure 3 The location index of configuration register 2 is 4. The location index in the configuration register can be determined according to the aforementioned address mapping relationship, the purpose of which is to improve the discreteness of address bits in the hash algorithm.

[0028] When performing the first address swapping process on the original access address, the target location index swizzle_index[i] of the current configuration register corresponding to the current bit i can be determined through the cross-connect network. The target location index bit addr_in[swizzle_index[i]] of the original access address is used as the current bit addr_swizzle[i] of the first swapped address. Here, addr_in represents the input original access address, addr_swizzle represents the first swapped address after the first address swapping process, and swizzle_index represents the location index set in the configuration register. That is, the address bit addr_swizzle[i] after the first address swapping process is driven by the swizzle_index[i] bit of the original access address. In other words, addr_swizzle[i] = addr_in[swizzle_index[i]]. For example, in... Figure 3 In the original access address, addr_swizzle[2] = addr_in[4], that is, the second bit of the first swizzle address is driven by the fourth bit of the original access address.

[0029] A multiplexer can determine the target location index of the current configuration register corresponding to the current bit in the first exchanged address, and select the target location index bit in the corresponding original access address based on the target location index. By ensuring that the location indices in each configuration register are different, the address mapping relationship in the first address exchange process is guaranteed to be one-to-one, avoiding information loss. If a configuration error exists in the software configuration, the hardware circuit can report an interrupt.

[0030] Step 130: Perform multi-level hashing on the first exchange address according to the distributed structure of the slave nodes to obtain the hash discrete address.

[0031] In multi-level hashing, each level of processing is performed on the distributed structure of the slave nodes. For example, when the slave node is a cache, the cache's distributed structure consists of multiple banks, and each bank contains multiple sets. Exemplarily, multi-level hashing could involve hashing the banks and then hashing the sets, achieving two levels of hashing. As another example, when the slave node is a memory, two levels of hashing could be achieved by hashing the channels and then hashing the banks.

[0032] Optionally, the first exchange address is subjected to multi-level hashing based on the distributed structure of the slave node to obtain a hash discrete address, including: determining multiple access hierarchy fields of the slave node and the index bit field of each access hierarchy field based on the distributed structure of the slave node; performing hashing on the index bit field of each access hierarchy field in the order of the access hierarchy fields, and concatenating the processing results to obtain the hash discrete address.

[0033] The access hierarchy domain can be a storage or interface domain at different levels in the distributed structure of the slave nodes. For example, when the slave node is a cache, the access hierarchy domain can include banks and sets. The index fields of banks and sets are different. For example, taking a 34-bit cache as an example, there can be 4 banks in the cache, indexed by 2 bits; there are 128 sets, indexed by 7 bits, with the lower 7 bits offset by 128 bytes per cache line. For example, bits [8:7] are used to index the banks, and bits [15:9] are used to index the sets; that is, the index field of the bank is bits [8:7], and the index field of the set is bits [15:9]. The distributed structure of the cache includes multiple banks, and each bank includes multiple sets. Therefore, the order of access hierarchy domains in the cache is bank first, then set. When performing multi-level hashing, hashing can be performed according to the order of access hierarchy domains, that is, the index field of the bank is hashed first, and then the index field of the set is hashed. For example, the access hierarchy field order for memory is channel first, then bank. The channel index field can be hashed first, followed by the bank index field. Similarly, the access hierarchy field order for DDR is channel first, then Rank, then bank. The channel index field can be hashed first, then the Rank index field, and finally the bank index field. Furthermore, when the slave node is HBM, the channel index field can be hashed first, followed by the bank index field. And when the slave node is a protocol access port, the index field of the access port group can be hashed first, followed by the index field of the access port within the access port group.

[0034] The technical solution of this invention achieves uniform address dispersion by performing multi-level hashing on the index segments of each access hierarchy domain separately, so that the index segments of each access hierarchy domain change. This avoids the situation where there are local changes when the index segments of each access hierarchy domain are hashed at the same time, such as the bank changing but the set not changing, which would result in poor uniform address dispersion.

[0035] In multi-level hashing, the hashing methods at each level can be the same or similar. For example, hash algorithms can be used at each level, and the choice of hash algorithm can be based on actual needs. For instance, an XOR network can be used for address discretization in multi-level hashing.

[0036] For example, Figure 4This is a schematic diagram of a hash circuit structure according to Embodiment 1 of the present invention. In the first exchange address, the bit field requiring hash processing, such as the index bit field, can be bitwise ANDed with the configuration coefficient, followed by XOR processing to obtain the hash discrete address. For example, Figure 4 The output bit j is composed of bits [26:0]. The value of the output bit j is the result of a bitwise AND operation between the values ​​of each input bit and the corresponding data in the hash mask, as shown by the configuration coefficients. Then, a XOR operation is performed to obtain the result. That is, addr_hashed[j] = XOR (hash mask[j][k] & addr_in[k]). Here, addr_hashed[j] represents the value of the output bit j, hash mask[j][k] represents the connection coefficient (0 or 1) between the j-th output bit and the k-th input bit, addr_in[k] represents the value of the input bit k, and & indicates a bitwise AND operation between the values ​​of each input bit and the corresponding data in the hash mask.

[0037] Figure 4 The hash circuit for bit [0] is shown. Figure 4 As shown, when determining the value of bit [0] in the hash discrete address, each input bit [26:0] can be ANDed with the corresponding data in the hash mask (hash mask[0][0] to hash mask[0]

[26] ) to obtain an intermediate result. The intermediate result is then XORed to obtain the value of bit [0] in the hash discrete address.

[0038] In multi-level hashing, the bits in the first exchange address can be processed in batches according to the distributed structure of the slave nodes, such as... Figure 4 The hash processing is illustrated. In this embodiment of the invention, considering that multi-level hashing may be required, and given that the hash configuration matrix (hash mask) is invertible, a full-rank square matrix is ​​used. By adjusting the hash mask or the hash algorithm used, uniform dispersion of hash discrete addresses can be achieved.

[0039] Step 140: Perform a second address swap process on the hash discrete address to rearrange each bit of the hash discrete address to obtain the target access address, so that the master node can access each slave node according to the target access address.

[0040] The goal of hash discretization is to uniformly discretize the global address access pattern across all target hardware components within the hash scope. Multi-level hashing increases the uniformity of discretization for any original access address and reduces the probability of conflicting accesses on physical hardware components. However, hash algorithms are inherently responsible for the entire group of target hardware components; the randomness of address patterns inevitably leads to certain unavoidable operating modes, resulting in a low probability of localized hardware component bias. To further address this low-probability localized hardware component bias, this embodiment of the invention performs a second address swapping process after multi-level hashing to rearrange the bits of the hashed discrete address.

[0041] The second address swapping process can be the same as or similar to the first address swapping process. The difference lies in that the first address swapping process rearranges the bits of the original access address before multi-level hashing; the second address swapping process rearranges the bits of the hashed discrete address after multi-level hashing. The first address swapping process aims to improve the input address before multi-level hashing by mapping it to a suitable input address, thus enhancing the uniformity of the multi-level hashing results. The second address swapping process aims to perform local bias mapping on the results after multi-level hashing, ultimately achieving uniform mapping on the hardware. By combining the first address swapping process, multi-level hashing, and the second address swapping process, a sandwich structure is formed, solving the problem of optimal uniform discretization for multiple master nodes accessing multiple slave nodes, given any address access pattern.

[0042] Optionally, a second address swapping process is performed on the hash discrete address to rearrange the bits of the hash discrete address. This includes: constructing a crossbar switch network using N configuration registers and multiplexers, where N is the address bit width, and each configuration register stores a location index, with each configuration register having a unique location index; during the second address swapping process, the crossbar switch network is used to determine the target location index of the current configuration register corresponding to the current bit of the second swapped address; and the target location index bit of the hash discrete address is used as the current bit of the second swapped address.

[0043] In the second address exchange process, the position indices in each configuration register can be determined experimentally. For example, after determining the address mapping relationship in the first address exchange process and the hash algorithm in the multi-level hash process, a targeted analysis can be conducted on the overall performance load situation to determine the load characteristics. Based on the load characteristics, the position indices in each configuration register in the second address exchange process can be determined to eliminate the load and improve the performance of uniform address discretization.

[0044] The second switching address can be directly used as the target access address, or in an optional implementation, the target access address can be obtained by further optimizing the biased load of the second switching address. The master node accesses each slave node according to the target access address, realizing discrete and uniform access of the master node to the slave nodes in the distributed structure, avoiding hardware component biased load conflict access, and improving the overall performance in multiple scenarios.

[0045] The technical solution of this embodiment obtains the original access address when the master node performs distributed interconnection access to multiple slave nodes; performs a first address exchange process on the original access address to rearrange the bits of the original access address to obtain a first exchange address; performs multi-level hashing on the first exchange address according to the distributed structure of the slave nodes to obtain a hash discrete address; and performs a second address exchange process on the hash discrete address to rearrange the bits of the hash discrete address to obtain a target access address, so that the master node can access each slave node according to the target access address. This solves the problem of uniform discretization of access addresses. By performing a sandwich structure processing of "address exchange + multi-level hashing + address exchange" on the original access address, the access address can be uniformly discretized, improving the access performance of slave nodes.

[0046] Example 2 Figure 5 This is a flowchart of a distributed interconnection access address mapping method according to Embodiment 2 of the present invention. This embodiment is a further addition and refinement of the above technical solution, and the technical solution in this embodiment can be combined with various optional solutions in one or more of the above embodiments. Figure 5 As shown, the method includes: Step 510: When the master node performs distributed interconnection access to multiple slave nodes, obtain the original access address.

[0047] Optionally, the master node can be a chip, a graphics processing unit (GPU), a central processing unit (CPU), or a visual processing unit (VPU); the slave node can be a cache, memory, double data rate memory (DDR), high bandwidth memory (HBM), or a protocol access port.

[0048] Step 520: Perform a first address swap on the original access address to rearrange the bits of the original access address to obtain the first swap address.

[0049] Optionally, a first address swapping process is performed on the original access address to rearrange the bits of the original access address to obtain a first swapped address. This includes: constructing a crossbar switch network using N configuration registers and multiplexers, where N is the address bit width, and each configuration register stores a location index, with each configuration register having a unique location index; during the first address swapping process on the original access address, the target location index of the current configuration register corresponding to the current bit of the first swapped address is determined using the crossbar switch network; and the target location index bit of the original access address is used as the current bit of the first swapped address.

[0050] Step 530: Perform multi-level hashing on the first exchange address according to the distributed structure of the slave nodes to obtain the hash discrete address.

[0051] Optionally, the first exchange address is subjected to multi-level hashing based on the distributed structure of the slave node to obtain a hash discrete address, including: determining multiple access hierarchy fields of the slave node and the index bit field of each access hierarchy field based on the distributed structure of the slave node; performing hashing on the index bit field of each access hierarchy field in the order of the access hierarchy fields, and concatenating the processing results to obtain the hash discrete address.

[0052] Step 540: Perform a second address swapping process on the hash discrete address to rearrange the bits of the hash discrete address to obtain the second swapped address.

[0053] Optionally, a second address swapping process is performed on the hash discrete address to rearrange the bits of the hash discrete address to obtain the second swapped address. This includes: constructing a crossbar switch network using N configuration registers and multiplexers, where N is the address bit width, and each configuration register stores a location index, with each configuration register having a unique location index; during the second address swapping process, the crossbar switch network is used to determine the target location index of the current configuration register corresponding to the current bit of the second swapped address; and the target location index bit of the hash discrete address is used as the current bit of the second swapped address.

[0054] Step 550: Within a preset time window, count the number of times each bit of the second exchange address is flipped.

[0055] The preset time window can be measured in clock cycles. The length of the preset time window can be adjusted according to actual needs. A bit flip can be either from 0 to 1 or from 1 to 0, both of which can be considered a flip.

[0056] Step 560: Perform the off-load correction process of the second switching address according to the number of flips of each bit to obtain the target access address, so that the master node can access each slave node according to the target access address.

[0057] Within a preset time window, the number of flips for each bit can be counted and sorted. When performing the second address offset correction process based on the number of flips for each bit, bits with a flip count higher than a first preset value can be swapped with bits with a flip count lower than a second preset value. The second preset value is lower than the first preset value. By swapping bits that originally flipped less frequently with bits that flipped more frequently, dynamic address changes can be achieved, resulting in a more uniform and discrete use of the address.

[0058] During off-center load correction, sensitive bits, also known as preset key bits, can be set for the bits. When the number of flips of the preset key bit is less than the first preset number of flips, non-preset key bits with a number of flips greater than the second preset number of flips can be swapped to solve the local off-center load problem and achieve the effect of uniform address discretization. The second preset number of flips is greater than the first preset number of flips.

[0059] Optionally, the second switching address is subjected to off-load correction processing based on the number of flips of each bit to obtain the target access address, including: obtaining a preset key bit and a preset off-load threshold; determining a preset number of first candidate bits with the lowest flip frequency based on the number of flips of each bit, and determining the off-load quantity when the first candidate bit is the preset key bit; when the off-load quantity is greater than or equal to the preset off-load threshold, determining a second candidate bit with the highest flip frequency based on the number of flips of each bit, wherein the second candidate bit is not the preset key bit; and performing address swapping based on the preset key bit and the second candidate bit in the first candidate bit of the second switching address to obtain the target access address.

[0060] For example, Figure 6 This is a schematic diagram of an off-center load correction process provided according to Embodiment 2 of the present invention. Figure 6 As shown, a preset key bit position can be set to bit position [9:4], a total of 6 bits. The preset off-load threshold can be a value less than or equal to the preset number of key bits. In the off-load correction process, the number of flips of each bit can be sorted to determine the first candidate bit with the lowest preset number of flips. For example, in Figure 6The six first candidate bits with the worst flip frequency can be identified. The number of offset bits when the first candidate bits are preset key bits is determined. That is, the number of times the six bits with the worst flip frequency fall within the preset key bits is determined as the offset number. Offset correction processing can be performed when the offset number is greater than or equal to a preset offset threshold; otherwise, offset correction processing is not performed.

[0061] In the off-center load correction process, the second candidate bit with the highest flip frequency can be determined based on the number of flips of each bit; wherein, the second candidate bit is not a preset key bit. That is, based on the number of flips of each bit, the number of second candidate bits with the highest flip frequency that do not fall on the preset key bit is determined.

[0062] The preset critical bit in the first candidate bit position can be swapped with the second candidate bit position to achieve local off-center load correction. Multiple bit positions can be used for address swapping. For example, first-level, second-level, and third-level address swapping can be employed. The first-level address swapping is a conservative approach, with fewer bits swapped than the second-level address swapping. The second-level address swapping is a neutral approach, with more bits swapped than the first-level address swapping but fewer than the third-level address swapping. The third-level address swapping is an aggressive approach, with more bits swapped than the second-level address swapping.

[0063] For example, Figure 6 There are a total of 6 preset critical bits. Among them, 4 of the 6 bits with the lowest flip frequency are preset critical bits: bits 4, 5, 7, and 8. The flip frequency is bit 4 > bit 5 > bit 7 > bit 8. The 4 non-preset critical bits with the highest flip frequency are bit 24 > bit 22 > bit 21 > bit 17. During the first-tier address swap, only one of the second-highest flip frequency alternative bits can be swapped with the preset critical bit with the lowest flip frequency, i.e., bit 24 can be swapped with bit 8. During the second-tier address swap, N of the second-highest flip frequency alternative bits can be swapped with the N preset critical bits with the lowest flip frequency. N is greater than 1 and less than the off-center load, and is a configurable parameter. For example, when N is 2, bit 24 can be swapped with bit 8, and bit 22 can be swapped with bit 7. During the third-level address swap, the second alternative bit with the highest off-load number flip frequency can be swapped with the preset key bit with the lowest off-load number flip frequency. Specifically, bit 24 is swapped with bit 8, bit 22 is swapped with bit 7, bit 21 is swapped with bit 5, and bit 17 is swapped with bit 4.

[0064] After address swapping, the target access address is obtained, and the master node can use the target access address to access the slave node. After the address swapping is completed, the number of bit flips can be counted again in the next preset time window to correct for off-load and ensure that the distributed structure of the slave nodes is accessed in a discrete and uniform manner.

[0065] Based on the above implementation method, optionally, after performing the off-load correction processing of the second exchange address according to the number of flips of each bit to obtain the target access address, the method further includes: when recovering the original access address from the slave node, performing de-off-load correction processing of the target access address according to the off-load correction processing parameters to obtain the second exchange address; performing de-second address exchange processing on the second exchange address according to the second address exchange processing parameters to obtain the hash discrete address; performing de-multi-level hash processing on the hash discrete address according to the multi-level hash processing parameters to obtain the first exchange address; and performing de-first address exchange processing on the first exchange address according to the first address exchange processing parameters to obtain the original access address.

[0066] Figure 7 This is a flowchart of another distributed interconnection access address mapping method provided according to Embodiment 2 of the present invention. Figure 7 As shown, the distributed interconnection access address mapping method can include a forward path and a reverse path. The forward path can include a first address swap (pre-bit swizzle), multi-level hashing, and a second address swap (post-bit swizzle) of the original access address (addr_in). The forward path can also include a load offset correction process (load offset sensor). The forward path can improve the uniformity of access address distribution and enhance distributed performance. The reverse path can include de-swapping the second address swap (post-bit de-swizzle), de-hashing the multi-level hash, and de-swapping the first address swap (pre-bit de-swizzle) of the target access address (addr_hashed). When the forward path includes load offset correction, the reverse path can further perform address swapping based on the address swaps in the load offset correction process to resolve the load offset correction.

[0067] For example, such as Figure 2 In the chip access shown, the cache needs to be written back to the lower-level memory. At this point, the original access address needs to be restored, which can be done as follows: Figure 7 The reverse path is processed based on the forward path shown. Figure 2 In this case, memory does not need to be written back to the lower-level storage, and the original access address does not need to be restored. At this time, only the following can be executed: Figure 7The forward path processing is shown, but the reverse path processing is not performed.

[0068] Decomposing the second address swap is the inverse operation of the second address swap. Decomposing the first address swap is the inverse operation of the first address swap. Decomposing the second address swap is similar to or the same as decomposing the first address swap. The following explanation uses the decomposition of the first address swap as an example. Figure 8 This is a schematic diagram of a circuit structure for decrypting the first address exchange processing according to Embodiment 2 of the present invention. In the decryption of the first address exchange processing, an inverse operation can be performed based on the position index configured during the first address exchange processing. For example, if index[2]=4, swapping bit 4 to bit 2 will complete the decryption of the first address exchange processing. That is, it satisfies addr_in[swizzle_index[i]] = addr_swizzle[i]. Wherein, addr_in[swizzle_index[i]] is the swizzle_index[i]th bit of the input first exchange address, and addr_swizzle[i] is the i-th bit of the output original access address. That is, an inverse operation is performed based on the position index, and the swizzle_index[i]th bit of the first exchange address is used as the i-th bit of the original access address. Based on this exchange relationship, the following can be generated: Figure 8 The circuit shown is the first address switching processing circuit.

[0069] In another implementation of the first address exchange process, the same circuit as the first address exchange process can be used, with a position index that is the reverse of the position index in the first address exchange process. The circuit for the second address exchange process is the same as the circuit for the first address exchange process, and will not be described again here.

[0070] The circuit for demultiplexing hash processing is identical in structure to that used in multimultiplexing hash processing. In demultiplexing hash processing, the corresponding bits can be processed again using the same hash mask as in multimultiplexing hash processing to achieve the desired result.

[0071] The technical solution of this invention solves the problem of uniform discretization of access addresses by obtaining the original access address when the master node performs distributed interconnection access to multiple slave nodes; performing a first address exchange process on the original access address to rearrange the bits of the original access address to obtain a first exchange address; performing multi-level hashing on the first exchange address according to the distributed structure of the slave nodes to obtain a hash discrete address; performing a second address exchange process on the hash discrete address to rearrange the bits of the hash discrete address to obtain a second exchange address; counting the number of flips of each bit of the second exchange address within a preset time window; and performing off-load correction processing on the second exchange address according to the number of flips of each bit to obtain a target access address, so that the master node can access each slave node according to the target access address. This solves the problem of uniform discretization of access addresses. By performing a sandwich structure processing of "address exchange + multi-level hashing + address exchange" on the original access address, combined with off-load correction processing, the access address can be uniformly discretized, avoiding local off-load and improving the access performance of slave nodes.

[0072] For example, consider a 34-bit cache access. In this 34-bit configuration, bits [6:0] represent the address offset; bits [8:7] are used to index the bank; bits [15:9] are used to index the set; and bits [33:16] represent the cache tag. In distributed interconnected access address mapping, since bits [6:0] represent the address offset, they do not cause changes to the set and can be left unprocessed. In the forward path, the bits [33:7] in the original access address can be swapped to obtain the first swapped address addr_swizzle[33:7]. Bits [8:7] in addr_swizzle[33:7] are used to index the bank, enabling bank hashing in multi-level hashing. Bits [15:9] in addr_swizzle[33:7] are used to index the set, enabling set hashing in multi-level hashing. By hashing bits [8:7] and [15:9] in addr_swizzle[33:7] sequentially, the hashed discrete address addr_hashed[33:7] can be obtained. addr_hashed[33:7] can then undergo a second address swap to obtain a second swapped address. This second swapped address can be concatenated with bits [6:0] to form the target access address. Furthermore, based on the number of flips in bits [33:7], bias correction processing can be performed to achieve uniform address discretization. Additionally, reverse path processing can be performed based on the forward path processing to obtain the original access address.

[0073] By processing the original access address using a sandwich structure of "address swapping + multi-level hashing + address swapping" and combining it with off-center load correction, the access address can be evenly discretized, avoiding local off-center loads and improving the access performance of slave nodes.

[0074] Example 3 Figure 9 This is a schematic diagram of the structure of a distributed interconnected access address mapping device according to Embodiment 3 of the present invention. Figure 9 As shown, the device includes: a raw access address acquisition module 910, a first address exchange processing module 920, a multi-level hash processing module 930, and a second address exchange processing module 940. Wherein: The original access address acquisition module 910 is used to acquire the original access address when the master node performs distributed interconnection access to multiple slave nodes; The first address exchange processing module 920 is used to perform a first address exchange processing on the original access address, so as to rearrange each bit of the original access address to obtain the first exchanged address; The multi-level hash processing module 930 is used to perform multi-level hash processing on the first exchange address according to the distributed structure of the slave nodes to obtain a hash discrete address; The second address exchange processing module 940 is used to perform a second address exchange processing on the hash discrete address to rearrange each bit of the hash discrete address to obtain the target access address, so that the master node can access each slave node according to the target access address.

[0075] Optionally, the device may also include: an off-center load correction processing module; The off-load correction processing module is used to perform a second address swapping process on the hash discrete address to rearrange each bit of the hash discrete address to obtain a second swapped address; within a preset time window, it counts the number of flips of each bit of the second swapped address; based on the number of flips of each bit, it performs off-load correction processing on the second swapped address to obtain the target access address.

[0076] Optional, the off-center load correction processing module includes: The parameter acquisition unit is used to acquire the preset key bits and the preset offload threshold. The first candidate bit determination unit is used to determine a preset number of first candidate bits with the lowest flip frequency based on the number of flips of each bit, and to determine the number of off-center bits when the first candidate bit is a preset key bit. The second candidate bit determination unit is used to determine the second candidate bit with the highest flip frequency of the off-load quantity based on the flip number of each bit when the off-load quantity is greater than or equal to the preset off-load threshold. The second candidate bit is not a preset key bit. The off-center load correction processing unit is used to perform address swapping based on the preset key bit and the second alternative bit in the first alternative bit of the second swap address to obtain the target access address.

[0077] Optionally, the device may also include: The off-load correction processing module is used to perform off-load correction processing on the second exchange address based on the number of flips of each bit to obtain the target access address. Then, when the slave node restores the original access address, it performs off-load correction processing on the target access address based on the off-load correction processing parameters to obtain the second exchange address. The second address exchange processing module is used to de-exchange the second exchanged address according to the second address exchange processing parameters to obtain a hash discrete address. The multi-level hash processing module is used to perform multi-level hash processing on the hash discrete address according to the multi-level hash processing parameters to obtain the first exchange address; The first address exchange processing module is used to perform first address exchange processing on the first exchanged address according to the first address exchange processing parameters to obtain the original access address.

[0078] Optionally, the first address switching processing module 920 includes: The cross switch network generation unit is used to construct a cross switch network through N configuration registers and multiplexers, where N is the address width, each configuration register stores a position index, and the position indices in each configuration register are different. The target location index determination unit is used to determine the target location index of the current configuration register corresponding to the current bit of the first exchanged address through a crossbar switch network when performing the first address exchange process on the original access address. The first address exchange processing unit is used to use the target location index bit of the original access address as the current bit of the first exchange address.

[0079] Optional, the multi-level hash processing module 930 includes: The index bit field determination unit is used to determine multiple access hierarchy fields of the slave node and the index bit field of each access hierarchy field based on the distributed structure of the slave node. The multi-level hash processing unit is used to perform hash processing on the index segments of each access hierarchy field according to the order of access hierarchy fields, and then concatenate the processing results to obtain the hash discrete address.

[0080] Optionally, the master node can be a chip, a graphics processing unit (GPU), a central processing unit (CPU), or a visual processing unit (VPU); the slave node can be a cache, memory, double data rate memory (DDR), high bandwidth memory (HBM), or a protocol access port.

[0081] The distributed interconnection access address mapping device provided in the embodiments of the present invention can execute the distributed interconnection access address mapping method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0082] Example 4 Figure 10 This is a schematic diagram of the structure of an electronic device implementing the distributed interconnection access address mapping method of Embodiment 4 of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0083] like Figure 10 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) or random access memory (RAM), communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. Input / output (I / O) interfaces are also connected to the bus 14.

[0084] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0085] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as distributed interconnect access address mapping methods.

[0086] In some embodiments, the distributed interconnect access address mapping method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the distributed interconnect access address mapping method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the distributed interconnect access address mapping method by any other suitable means (e.g., by means of firmware).

[0087] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0088] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0089] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0090] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0091] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0092] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0093] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0094] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A distributed interconnection access address mapping method, characterized in that, include: When the master node performs distributed interconnection access to multiple slave nodes, the original access address is obtained; The original access address is subjected to a first address swapping process to rearrange the bits of the original access address to obtain a first swapped address; Based on the distributed structure of the slave nodes, the first exchange address is subjected to multi-level hashing to obtain a hash discrete address; The hash discrete address is subjected to a second address swapping process to rearrange the bits of the hash discrete address to obtain the target access address, so that the master node can access each of the slave nodes according to the target access address.

2. The method according to claim 1, characterized in that, A second address swapping process is performed on the hash discrete address to rearrange the bits of the hash discrete address to obtain the target access address, including: The hash discrete address is subjected to a second address swapping process to rearrange the bits of the hash discrete address to obtain a second swapped address; Within a preset time window, count the number of times each bit of the second exchange address is flipped; The second exchange address is subjected to off-load correction processing based on the number of flips of each bit to obtain the target access address.

3. The method according to claim 2, characterized in that, The second exchanged address undergoes off-load correction processing based on the number of bit flips for each bit to obtain the target access address, including: Obtain the preset key bits and preset offload threshold; Based on the number of flips of each bit, a preset number of first candidate bits with the lowest flip frequency are determined, and the number of off-center bits when the first candidate bit is a preset key bit is determined. When the number of off-loads is greater than or equal to the preset off-load threshold, the second candidate bit with the highest flip frequency of the off-load number is determined according to the number of flips of each bit. The second candidate bit is not a preset key bit. The target access address is obtained by exchanging the preset key bit in the first candidate bit of the second exchange address and the second candidate bit.

4. The method according to claim 2, characterized in that, After performing off-load correction processing on the second exchanged address based on the number of bit flips for each bit to obtain the target access address, the process further includes: When restoring the original access address from the node, the target access address is de-biased and corrected according to the bias correction processing parameters to obtain the second switching address; The second address is de-switched according to the second address switching parameters to obtain a hash discrete address. The hash discrete address is subjected to multi-level hashing based on the multi-level hashing parameters to obtain the first exchange address; The first address is de-switched according to the first address switching processing parameters to obtain the original access address.

5. The method according to claim 1, characterized in that, Perform a first address swapping process on the original access address to rearrange the bits of the original access address to obtain a first swapped address, including: A crossbar switch network is formed by N configuration registers and multiplexers, where N is the address width, each configuration register stores a location index, and the location indices in each configuration register are different. When performing the first address swapping process on the original access address, the target location index of the current configuration register corresponding to the current bit of the first swapped address is determined through the crossbar switch network. Use the target location index bit of the original access address as the current bit of the first exchange address.

6. The method according to claim 1, characterized in that, Based on the distributed structure of the slave nodes, the first exchange address is subjected to multi-level hashing to obtain a hash discrete address, including: Based on the distributed structure of the slave nodes, determine multiple access hierarchy domains of the slave nodes, as well as the index bit field of each access hierarchy domain; The index segments of each access hierarchy are hashed according to the order of the access hierarchy, and the processing results are concatenated to obtain the hash discrete address.

7. The method according to claim 1, characterized in that, The master node is a chip, graphics processing unit (GPU), central processing unit (CPU), or visual processing unit (VPU); the slave node is a cache, memory, double data rate memory (DDR), high bandwidth memory (HBM), or a protocol access port.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to said at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the distributed interconnection access address mapping method according to any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed by a processor, implement the distributed interconnection access address mapping method according to any one of claims 1-7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the distributed interconnection access address mapping method according to any one of claims 1-7.

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