Memory device and method of forming the same

Abstract

Some embodiments of a memory device and a method of manufacturing the memory device are provided. One of the memory devices includes an array of memory cells in a memory array region and a plurality of word lines extending from the memory array region to a connection region in a first direction. The memory cells include a semiconductor body. In the connection region, the word lines are interconnected to connect with the plurality of word lines extending in a third direction. The plurality of word lines includes a first word line and a second word line arranged in a second direction and between two rows of the semiconductor bodies. In the second direction, a first distance between the first word line and the second word line in the connection region is greater than a second distance between the first word line and the second word line in the memory array region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to international application PCT / CN2024 / 134870, filed on November 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to the field of semiconductor technology, and more specifically to semiconductor devices and methods of manufacturing thereof. Background Technology

[0004] Planar memory cells have traditionally shrunk thanks to advancements in process technology, circuit design, programming algorithms, and manufacturing techniques. However, as the feature sizes of these memory cells approach their physical limits, continuing planar processes becomes increasingly challenging and expensive. Consequently, the achievable storage density of planar memory cells is nearing its maximum capacity.

[0005] To overcome these density limitations, three-dimensional (3D) memory architectures have been introduced. The innovative approach of 3D memory architecture offers promising solutions for achieving higher storage densities and addressing the inherent constraints of planar memory cells. Summary of the Invention

[0006] This article discloses some implementations of 3D storage devices and methods for forming them.

[0007] In some aspects, a memory device is provided within a memory device. The memory device may include an array of memory cells in a memory array region and a plurality of word lines extending in a first direction from the memory array region to a connection region. The memory cells may include semiconductor bodies. In the connection region, word line interconnects may extend upward in a third direction to connect to the plurality of word lines. The plurality of word lines may include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor bodies. In the second direction, a first distance between the first word line and the second word line in the connection region may be greater than a second distance between the first word line and the second word line in the memory array region.

[0008] In some embodiments, in the third direction, one of the word line interconnects may extend through a first dielectric layer and a second dielectric layer of the stacked structure in the connection region to connect to a corresponding word line among the plurality of word lines. The first dielectric layer may be different from the second dielectric layer.

[0009] In some embodiments, one of the memory cells may further include a storage element. A third dielectric layer may be arranged laterally and generally horizontally relative to the third direction, wherein the electrode structure of the storage element may be connected to a corresponding semiconductor body in the semiconductor body.

[0010] In some embodiments, the third dielectric layer may include a silicon boron nitride layer.

[0011] In some implementations, the third dielectric layer may extend over the storage array region without extending over the connection region.

[0012] In some embodiments, a memory cell in the memory cell array may include a storage element, the storage element including an electrode structure having a first end and a second end connected to one of the semiconductor bodies. A word line interconnect in the word line interconnect may include a third end and a fourth end connected to the first word line. The second end of the electrode structure may be substantially flush with the fourth end of the word line interconnect.

[0013] In some embodiments, the surface area of ​​the second end of the electrode structure may be substantially the same as the surface area of ​​the fourth end of the word line interconnection.

[0014] In some embodiments, in the third direction, the length of the word line interconnect can be greater than the length of the electrode structure of the storage device.

[0015] In some implementations, the storage array region may include a first sub-storage region and a second sub-storage region. One of the plurality of word lines may extend from the first sub-storage region to the second sub-storage region in the first direction. The connection region may be arranged between the first sub-storage region and the second sub-storage region.

[0016] In some embodiments, the two rows of the semiconductor body may include a first row and a second row of the semiconductor body. The storage device may also include an isolation structure disposed between the second row and the third row of the semiconductor body and configured to isolate the second row from the third row of the semiconductor body.

[0017] In some implementations, in the second direction, the first end of the first character line may be substantially flush with the second end of the second character line.

[0018] In some embodiments, the first semiconductor structure may include the memory cell array and the plurality of word lines. The memory device may also include peripheral circuitry disposed in the second semiconductor structure. The first semiconductor structure may be bonded to the second semiconductor structure. The plurality of word lines in the first semiconductor structure may be electrically coupled to the peripheral circuitry of the second semiconductor structure.

[0019] In some aspects, another storage device is provided. The storage device may include an array of memory cells in a memory array region. A memory cell may include a semiconductor body. Multiple word lines may extend from the memory array region to a connection region in a first direction. In the connection region, word line interconnects may extend upward in a third direction to connect with the multiple word lines. The third direction may be perpendicular to the first direction. The multiple word lines may include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor body. The second direction may be perpendicular to both the first direction and the third direction. In the second direction, a first distance between the first word line and the second word line in the connection region may be different from a second distance between the first word line and the second word line in the memory array region. In the second direction, a first end of the first word line may be substantially flush with a second end of the second word line.

[0020] In some implementations, the first distance may be greater than the second distance.

[0021] In some embodiments, in the third direction, one of the word line interconnects may extend through a first dielectric layer and a second dielectric layer in the stacked structure of the connection region to connect to a corresponding word line among the plurality of word lines. The first dielectric layer may be different from the second dielectric layer.

[0022] In some embodiments, one of the memory cells may further include a storage element. A third dielectric layer may be arranged laterally and generally horizontally relative to the third direction, wherein the electrode structure of the storage element may be connected to a corresponding semiconductor body in the semiconductor body.

[0023] In some embodiments, the third dielectric layer may include a silicon boron nitride layer.

[0024] In some implementations, the third dielectric layer may extend over the storage array region without extending over the connection region.

[0025] In some embodiments, one of the memory cells may include a storage element, the storage element including an electrode structure having a first end and a second end connected to one of the semiconductor bodies. One of the word line interconnects may include a third end and a fourth end connected to the first word line. The second end of the electrode structure may be substantially flush with the fourth end of the word line interconnect.

[0026] In some embodiments, the surface area of ​​the second end of the electrode structure may be substantially the same as the surface area of ​​the fourth end of the word line interconnection.

[0027] In some embodiments, in the third direction, the length of the word line interconnect can be greater than the length of the electrode structure.

[0028] In some implementations, the storage array region may include a first sub-storage region and a second sub-storage region. One of the plurality of word lines may extend from the first sub-storage region to the second sub-storage region in the first direction. The connection region may be arranged between the first sub-storage region and the second sub-storage region.

[0029] In some embodiments, the two rows of the semiconductor body may include a first row and a second row of the semiconductor body. The storage device may also include an isolation structure disposed between the second row and the third row of the semiconductor body and configured to isolate the second row from the third row of the semiconductor body.

[0030] In some embodiments, the first semiconductor structure may include the memory cell array and the plurality of word lines. The memory device may also include peripheral circuitry disposed in the second semiconductor structure. The first semiconductor structure may be bonded to the second semiconductor structure. The plurality of word lines in the first semiconductor structure may be electrically coupled to the peripheral circuitry in the second semiconductor structure.

[0031] In some aspects, a method for forming a memory device is provided. The method may include: forming an array of memory cells in a memory array region, each memory cell including a semiconductor body; and forming a plurality of word lines extending from the memory array region to a connection region in a first direction. In the connection region, word line interconnects may extend in a third direction to connect to the plurality of word lines. The third direction may be perpendicular to the first direction. The plurality of word lines may include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor body. The second direction may be perpendicular to both the first direction and the third direction. In the second direction, a first distance between the first word line and the second word line in the connection region may be greater than a second distance between the first word line and the second word line in the memory array region.

[0032] In some embodiments, forming the plurality of word lines including the first word line and the second word line may include: forming a conductive layer between and connecting the two rows of the semiconductor body; and removing a portion of the conductive layer to split the conductive layer into the first word line and the second word line. In the second direction, a first end of the first word line may be substantially flush with a second end of the second word line.

[0033] In some embodiments, the method may include: forming a plurality of bit lines connected to the semiconductor body at a first side of the semiconductor body; and forming word line interconnects at a second side of the semiconductor body opposite to the first side in the interconnection region, the word line interconnects extending upward on the third side to connect to the plurality of word lines.

[0034] In some embodiments, the word line interconnect formed extending upward in the third party to connect with the plurality of word lines may include: forming a plurality of vias extending upward in the third party, wherein the plurality of vias includes a first via in the memory array region and a second via extending upward in the third party through the stack structure to reach the first word line in the connection region, wherein the length of the second via in the third party may be greater than the length of the first via; and filling the second via with one or more conductive materials to contact the first word line, thereby forming one word line interconnect in the word line interconnect.

[0035] In some embodiments, the method may further include: forming a first dielectric layer and a second dielectric layer on top of the first dielectric layer, the stacked structure including the first dielectric layer and the second dielectric layer. Forming the plurality of vias may include: forming a second via in the connection region, the second via extending through the second dielectric layer and the first dielectric layer to reach the first word line.

[0036] In some implementations, forming the plurality of vias extending upward from the third party may include: simultaneously forming the first via in the storage array region and forming the second via in the connection region.

[0037] In some embodiments, the method may further include: forming an electrode structure of a storage device, the electrode structure of the storage device being connected to a first semiconductor body in the semiconductor body, the first semiconductor body corresponding to a first channel via in the storage array region. The electrode structure of the storage device and the word line interconnects may be arranged on the same side of the first semiconductor body.

[0038] In some embodiments, the method may further include forming a third dielectric layer in the memory array region. Forming the plurality of vias may include forming a first via in the memory array region, the first via extending through the stacked structure and stopping at the third dielectric layer, the first via corresponding to the first semiconductor body.

[0039] In some embodiments, the third dielectric layer may include a silicon boron nitride layer.

[0040] In some embodiments, the storage device may include the electrode structure having a first end and a second end connected to the first semiconductor body. The word line interconnect may include a third end and a fourth end connected to the first word line. The surface area of ​​the second end of the electrode structure may be substantially the same as the surface area of ​​the fourth end of the word line interconnect.

[0041] In some embodiments, in the second direction, the second end of the electrode structure may be substantially flush with the fourth end that is interconnected with the word line.

[0042] In some embodiments, in the third direction, the length of the word line interconnect can be greater than the length of the electrode structure.

[0043] In some embodiments, the two rows of the semiconductor body may include a first row and a second row of the semiconductor body. The method may further include forming an isolation structure disposed between the second row and a third row of the semiconductor body. The isolation structure may be configured to isolate the second row from the third row of the semiconductor body.

[0044] In some embodiments, the method may further include: forming a first semiconductor structure, the first semiconductor structure including the memory cell array and the plurality of word lines; forming a second semiconductor structure including peripheral circuitry; and bonding the first semiconductor structure to the second semiconductor structure, wherein the plurality of word lines in the first semiconductor structure may be electrically coupled to the peripheral circuitry in the second semiconductor structure. Attached Figure Description

[0045] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate some embodiments of the present disclosure, and together with the specification, serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0046] Figure 1 A schematic diagram of an exemplary memory device including peripheral circuitry and an array of memory cells with vertical transistors, according to some aspects of this disclosure, is shown.

[0047] Figure 2A A schematic plan view of exemplary word lines in a memory device having vertical transistors according to some aspects of this disclosure is shown.

[0048] Figure 2B A schematic cross-sectional view of an exemplary word line in a memory device having vertical transistors according to some aspects of this disclosure is shown.

[0049] Figure 3 A schematic diagram of an exemplary system having one or more storage devices is shown, according to some aspects of this disclosure.

[0050] Figure 4A A schematic diagram of a cross-section of an exemplary 3D storage device according to some aspects of this disclosure is shown.

[0051] Figure 4B A schematic diagram of a cross-section of another exemplary 3D storage device according to some aspects of this disclosure is shown.

[0052] Figure 5 A perspective view of an exemplary storage device implementing a front-side word line solution according to some aspects of this disclosure is shown.

[0053] Figure 6 A flowchart illustrating an exemplary method for forming individual word lines in a storage device, according to some aspects of this disclosure, is shown.

[0054] Figures 7A to 7D A schematic plan view of a storage device during various manufacturing processes for forming exemplary individual word lines, according to some aspects of this disclosure, is shown.

[0055] Figures 8A to 8D A schematic side view is shown illustrating an exemplary manufacturing process performed from the front side of a storage device, according to some aspects of this disclosure.

[0056] Figures 9A to 9D A schematic side view is shown illustrating other exemplary manufacturing processes performed from the back side of the storage device, illustrating some aspects of this disclosure.

[0057] Figure 10 A flowchart illustrating an exemplary method for forming word line interconnects in a storage device, according to some aspects of this disclosure, is shown.

[0058] Figure 11A A schematic cross-sectional view of a storage device during a manufacturing process for forming an exemplary channel hole, according to some aspects of this disclosure, is shown.

[0059] Figure 11B A schematic diagram of an exemplary mask for forming a channel hole is shown, according to some aspects of this disclosure.

[0060] Figure 12A A schematic plan view of a memory device during a manufacturing process for forming an exemplary word line interconnect, according to some aspects of this disclosure, is shown.

[0061] Figures 12B to 12C A schematic cross-sectional view of a memory device during a manufacturing process for forming an exemplary word line interconnect, according to some aspects of this disclosure, is shown.

[0062] Figure 13A A schematic plan view of another memory device during a manufacturing process for forming other exemplary word line interconnects, according to some aspects of this disclosure, is shown.

[0063] Figures 13B to 13C A schematic cross-sectional view of a memory device during a manufacturing process for forming other exemplary word line interconnects, according to some aspects of this disclosure, is shown.

[0064] Figure 14 A schematic plan view of another storage device having word lines and word line interconnections according to some aspects of this disclosure is shown.

[0065] Figure 15 A schematic cross-sectional view is shown of another storage device having word lines and word line interconnections according to some aspects of this disclosure.

[0066] Some embodiments of this disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0067] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of this disclosure. It will be apparent to those skilled in the art that this disclosure can also be used in a variety of other applications.

[0068] It should be noted that references to "some embodiments," "exemplary embodiments," "other embodiments," "some examples," etc., in the specification indicate that the described embodiments may include specific features, structures, or characteristics, but each embodiment may not necessarily include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments (whether explicitly described or not) is within the knowledge of those skilled in the art.

[0069] Generally, terms can be understood at least partially from their use in context. For example, depending at least partially on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partially on the context, terms such as "a," "an," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the terms "based on" and "according to" can be understood not necessarily to express an exclusive set of factors, but can, at least partially on the context, allow for the presence of other factors that are not necessarily explicitly described.

[0070] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also “on” with an intermediate feature or layer; and “above” or “on top of” means not only “above” or “on top of” but also “above” or “on top of” without an intermediate feature or layer (i.e., directly on).

[0071] Furthermore, for ease of description, spatially relative terms (e.g., "below," "below," "down," "above," "up," etc.) may be used herein to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0072] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0073] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or at the top and bottom surfaces of a continuous structure. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (in which interconnect lines and / or vertical interconnect channel "VIA" contacts are formed) and one or more dielectric layers.

[0074] As used herein, the terms “nominal / nominally” and “substantially / basically” refer to the expected or target value of a characteristic or parameter of a component or process operation set during the design phase of a product or process, and the range of values ​​higher and / or lower than that expected value. The range of values ​​may be attributable to slight variations in manufacturing processes or tolerances. As used herein, the terms “about” and “approximately” indicate that the value of a given quantity may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the terms “about” and “approximately” may indicate that the value of a given quantity varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0075] As used herein, the term "three-dimensional (3D) memory device" can refer to a semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string," such as a NAND memory string) on ​​a laterally oriented substrate such that the memory string extends vertically relative to the substrate. As used herein, the term "memory string" can refer to a vertically oriented string of memory cell transistors connected in series on a laterally oriented substrate such that the memory cell transistor string extends vertically relative to the substrate. As used herein, the term "vertical / perpendicularly" can refer to a direction perpendicular to the lateral surface of the substrate.

[0076] In memory technologies such as Dynamic Random Access Memory (DRAM), Phase-Change Memory (PCM), and Ferroelectric DRAM (FRAM), transistors are typically used as switching or selection devices. However, planar transistors in conventional memory cells typically have a horizontal structure, where word lines are buried in the substrate and bit lines are above the substrate. This lateral arrangement of the source and drain of planar transistors increases their footprint. Furthermore, planar transistor design complicates the organization of interconnect structures, including the arrangement of word lines and bit lines, which can limit the spacing of these lines, thus increasing manufacturing complexity and reducing production yield.

[0077] To address these issues, vertical transistors are introduced to replace conventional planar transistors as switching and selection devices in memory devices such as DRAM, PCM, and FRAM. Memory cell arrays with vertical transistors can each include a semiconductor structure extending in the vertical direction, as well as a gate structure.

[0078] Figure 1 A schematic diagram of an exemplary memory device 100, including peripheral circuitry 101 and an array 103 (or “memory cell array”) of memory cells having vertical transistors 104, is shown according to some aspects of this disclosure. In some embodiments, the memory device 100 may include a memory cell array 103 having memory cells 102, and the memory cells 102 may include vertical transistors 104 and storage elements (e.g., capacitors) 106 coupled to the vertical transistors 104. In some cases, the memory cell array 103 may be a DRAM cell array, and the storage element may be a capacitor 106 configured to store charge in the DRAM cells.

[0079] like Figure 1As shown, the memory cells 102 can be organized as a two-dimensional (2D) memory cell array 103 with multiple rows and columns. The memory device 100 may include word lines 108 and bit lines 110. Word lines 108 can be configured to electrically couple the memory cell array 103 to peripheral circuitry 101 to control the switching of vertical transistors 104. Word lines 108 can be configured in a first lateral direction (i.e., Figure 1 The bit line 110 extends in the horizontal direction (referred to as the word line direction) to connect to the corresponding vertical transistor 104 in a row of the memory cell array 103. Alternatively, the bit line 110 can be configured to couple the memory cell array 103 to peripheral circuitry 101 to send data to and / or receive data from memory cells 102. The bit line 110 can also extend in a second lateral direction (i.e., Figure 1 The vertical transistors 104 extend in the vertical direction (referred to as the bit line direction) of the memory cell array 103 to connect to the corresponding vertical transistors 104 in a column. In some examples, the gate of the vertical transistor 104 may be connected to the corresponding word line 108. One of the source and drain of the vertical transistor 104 may be connected to the corresponding bit line 110, and the other of the source and drain of the vertical transistor 104 may be connected to the capacitor 106, such as... Figure 1 As shown.

[0080] like Figure 1 As shown in the left box, in some examples, the vertical transistor 104-1 (such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET)) can replace a conventional planar transistor with a pass transistor for the memory cell 102 to reduce the area occupied by the pass transistor, coupling capacitance, and interconnect wiring complexity. In some embodiments, unlike planar transistors where the active region is formed in a substrate, the vertical transistor 104-1 may include a semiconductor body 120 extending vertically (in the z-direction) above a substrate (not shown) and a gate structure 122 contacting one or more sides of the semiconductor body 120. In some embodiments, the gate structure 122 of the vertical transistor 104-1 may contact one side of the semiconductor body 120, such as... Figure 1 As shown.

[0081] Gate structure 122 may include a gate dielectric 124 on the side of semiconductor body 120. In some examples, gate structure 122 may also include a gate electrode 126 on and in contact with the gate dielectric 124 on the side of gate electrode 126. Gate dielectric 124 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material. Gate electrode 126 may include any suitable conductive material, such as polysilicon, metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicide.

[0082] It is understood that, in some examples, the gate electrode 126 and word line 108 shown in the memory cell array 103 can be a continuous conductive structure. In other words, the gate electrode 126 can be considered as a portion of the word line 108 forming the gate structure 122, or the word line 108 can be considered as an extension of the gate electrode 126 for coupling with the peripheral circuitry 101. It is also understood that, although the semiconductor body 120 is in Figure 1 While shown as a cuboid shape, the semiconductor body 120 can have any suitable 3D shape, such as a polyhedral or cylindrical shape. This disclosure does not limit this.

[0083] like Figure 1 As shown, the vertical transistor 104-1 may further include a pair of source and drain electrodes (S / D, doped regions, also referred to as source and drain electrodes) formed at its two ends in the vertical direction (z-direction). A gate structure 122 may be formed between the source and drain electrodes. As a result, when the gate voltage applied to the gate electrode 126 of the gate structure 122 can be higher than the threshold voltage of the vertical transistor 104-1, a channel (not shown) of the vertical transistor 104-1 can be vertically formed in the semiconductor body 120 between the source and drain electrodes.

[0084] like Figure 1 As shown, storage device 106-1 can be coupled to one of the source / drain terminals of vertical transistor 104-1. In some examples, storage device 106-1 may include any device capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM and FRAM cells, and PCM elements for PCM cells. In some embodiments, vertical transistor 104-1 can control the selection and / or state switching of the corresponding storage device 106-1 coupled to vertical transistor 104-1. In some cases, vertical transistor 104-1 and storage device 106-1 may be misaligned in the z-direction, such as... Figure 1As shown, for example, to facilitate routing of word line 108, a more compact memory device 100 can be achieved. However, in some cases, vertical transistor 104-1 and memory device 106-1 may be aligned in the z-direction. This disclosure does not limit this.

[0085] Peripheral circuitry 101 can be coupled to memory cell array 103 via bit line 110, word line 108, and any other suitable conductive wiring. Peripheral circuitry 101 (or “control and sensing circuitry”) can include any suitable digital, analog, and / or mixed-signal circuitry used to facilitate operation of the memory cell array by applying voltage and / or current signals to memory cells 102 via word line 108 and bit line 110, and sensing voltage and / or current signals from memory cells 102 via word line 108 and bit line 110. For example, peripheral circuitry 101 can include one or more of the following: page buffer, decoder (e.g., row decoder and column decoder), sense amplifier, driver (e.g., word line driver), input / output (I / O) circuitry, charge pump, voltage source or voltage generator, current or voltage reference, any portion (e.g., sub-circuit) of the aforementioned functional circuitry, or any active or passive component of the circuitry (e.g., transistor, diode, resistor, or capacitor). According to some implementations, the peripheral circuit 101 may use complementary metal-oxide-semiconductor (CMOS) technology, which may be implemented using logic processes (e.g., various technology nodes).

[0086] Figure 2A A schematic plan view of an exemplary word line 202 in a memory device 200 having a vertical transistor 204, according to some aspects of this disclosure, is shown. Figure 2B A schematic cross-sectional view of an exemplary word line 203 in a memory device 201 having a vertical transistor 205, according to some aspects of this disclosure, is shown. Memory devices 200 and 201 may be 3D memory devices. Figure 2A A partial plan view of the 3D storage device 200 is provided, while Figure 2B A partial cross-sectional view of the 3D storage device 201 is provided. Figure 2B It can be along the word line (such as...) Figure 2A The cross-sectional view of the character line 202 in the image. It should be noted that... Figure 2B Certain components (such as vertical transistor 205) are depicted in the cross-section, but these components may not be directly located on the cross-section. These components may be at different distances relative to word line 203. They are included in the cross-sectional view only to show the spatial relationship between these components and word line 203 for illustrative purposes.

[0087] In such Figure 2AIn some embodiments shown, the vertical transistors 204 can be arranged in an array, and storage devices 206 corresponding to each vertical transistor 204 can be formed. In some embodiments, the vertical transistor 204 may include a semiconductor body and a gate structure located on one side of the semiconductor body, such as... Figure 1 As shown. The gate structures of the vertical transistors 204 in a row (i.e., the x-direction or word line direction) of the memory cell array can be electrically coupled to extend and form word lines 202. In some cases, multiple gate structures in a row of the memory cell array can be connected, for example, through a continuous conductive layer, and the conductive layer can be in the word line direction (i.e., Figure 2A It extends in the x direction to form a word line 202 corresponding to the row of the vertical transistor 204.

[0088] In the manufacturing process, a continuous conductive layer corresponding to the two rows of vertical transistors 204 in the memory cell array can be formed. In some embodiments, the conductive layer can be formed. A portion of the conductive layer can then be removed (e.g., by forming a notch 208), and the conductive layer can be separated into a pair of individual word lines 202-1 and 202-2, as shown below. Figure 2A As shown, word lines 202-1 and 202-2 can independently control a row of vertical transistors 204. Therefore, the memory device 200 can include multiple word lines 202, each extending along a first lateral direction. Subsequently, word line interconnects 210 corresponding to the word lines 202 can be formed, which realize electrical connections between the word lines 202 and the peripheral circuitry 101, thereby facilitating signal transmission on the memory device 200.

[0089] In some implementations, to form word line interconnects connected to word lines, the memory device 201 having word lines 203 connecting a row of vertical transistors 205 can be flipped (e.g., Figure 2B (As shown) to access its back side. Then, vias extending downwards from the back side of the memory device 201 to reach the corresponding word lines 203 can be created. A conductive material, such as tungsten, can then be deposited into the vias to form word line interconnects 207, such as... Figure 2B As shown.

[0090] However, these processes impose significant constraints on the routing direction of word lines 203. Restricting word lines 203 to specific paths reduces overall design flexibility, making it difficult to optimize layout for the performance or density of memory devices 201. Furthermore, this back-side approach imposes further constraints on how a semiconductor structure with an array of memory cells can be bonded to another semiconductor structure. The reliance on back-side processes for word-line pickup complicates the integration of routing and bonding, thereby increasing manufacturing complexity. As the demand for higher density and performance continues to grow, these constraints could lead to increased manufacturing challenges and potentially hinder advancements in semiconductor technology.

[0091] To address one or more of the aforementioned problems, this disclosure provides a solution in which a mask can be used to separate consecutive conductive layers in a memory cell array. By positioning the mask, conductive material in portions of the conductive layers can be removed, and one or more dielectric materials can then be filled in to form a pair of separate word lines to control vertical transistors in corresponding rows. Furthermore, vias present in the interconnect regions can be utilized as word line interconnects. For example, these vias can be formed vertically (i.e., in the z-direction) to extend downwards to contact corresponding word lines from the front side of the semiconductor structure with word lines. This method of leading word lines from the front side achieves greater flexibility because it simplifies the positioning process and minimizes the need to form additional vias on the back side.

[0092] Figure 3 A schematic diagram of an exemplary system 300 having one or more storage devices 306 according to some aspects of this disclosure is shown. System 300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 3 As shown, system 300 may include a host 302 and a storage system 304 having one or more storage devices 306 and a memory controller 308. The host 302 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-a-chip (SoC), such as an application processor (AP). The host 302 may be configured to send data to or receive data from the storage device 306.

[0093] The memory device 306 can be any memory device disclosed in this disclosure, such as a 3D memory device (e.g., DRAM, PCM, FRAM). In some embodiments, the memory device 306 may include an array of memory cells (each memory cell including a vertical transistor) and may also implement a front-side word line solution, as described in detail below.

[0094] According to some implementations, the memory controller 308 may be coupled to the storage device 306 and the host 302, and may be configured to control the storage device 306. The memory controller 308 may manage data stored in the storage device 306 and communicate with the host 302. The memory controller 308 may be configured to control the operation of the storage device 306, such as read, write, and refresh operations. The memory controller 308 may also be configured to manage various functions related to data stored in or to be stored in the storage device 306, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management.

[0095] Figure 4A A schematic cross-sectional view of an exemplary 3D memory device 400 according to some aspects of this disclosure is shown. The 3D memory device 400 may represent an example of a bonded chip. Components of the 3D memory device 400 (e.g., memory cell arrays and peripheral circuitry) may be formed separately on different substrates and then combined to form a bonded chip. The 3D memory device 400 may include a first semiconductor structure 402 comprising peripheral circuitry including a memory cell array. In some embodiments, the 3D memory device 400 may also include a second semiconductor structure 404 comprising a memory cell array. In some embodiments, the second semiconductor structure 404 may include a memory cell array capable of using vertical transistors as switching and selection devices. In some embodiments, the memory cell array may include a DRAM cell array. For ease of description, in some cases, a DRAM cell array may be used as an example in this disclosure for describing a memory cell array.

[0096] The second semiconductor structure 404 may be a DRAM device, wherein memory cells are provided in the form of an array of DRAM cells. In some embodiments, a DRAM cell may include a capacitor for storing data bits as positive or negative charges, and one or more vertical transistors for controlling access to the capacitor. In some examples, a DRAM cell may include a transistor and a capacitor and have a 1T1C structure.

[0097] like Figure 4A As shown, the 3D memory device 400 also includes components perpendicularly between the first semiconductor structure 402 and the second semiconductor structure 404 (in the vertical direction, for example, Figure 4AThe bonding interface 406 (in the z-direction) is used. In some embodiments, the first semiconductor structure 402 and the second semiconductor structure 404 can be fabricated separately (and in some embodiments, in parallel) such that the thermal budget for fabricating one of the first semiconductor structure 402 and the second semiconductor structure 404 does not limit the process for fabricating the other of the first semiconductor structure 402 and the second semiconductor structure 404. Furthermore, compared to long-distance (e.g., millimeter or centimeter-level) chip-to-chip data buses on a circuit board (such as a printed circuit board (PCB)), multiple interconnects (e.g., bonding contacts) can be formed via the bonding interface 406 to provide direct, short-distance (e.g., micrometer-level) electrical connections between the first semiconductor structure 402 and the second semiconductor structure 404, thereby eliminating chip interface latency and achieving high-speed I / O throughput with reduced power consumption. Data transfer between the memory cell array in the second semiconductor structure 404 and the peripheral circuitry in the first semiconductor structure 402 can be performed via the interconnects (e.g., bonding contacts) on the bonding interface 406. By vertically integrating the first semiconductor structure 402 and the second semiconductor structure 404, the chip size can be reduced and the memory cell density can be increased.

[0098] It is understood that the relative positions of the stacked first semiconductor structure 402 and the second semiconductor structure 404 are unrestricted. Therefore, Figure 4B A schematic cross-sectional view of another exemplary 3D storage device 401 according to some embodiments is shown. Unlike Figure 4A The 3D memory device 400 (in which a second semiconductor structure 404 including a memory cell array is above a first semiconductor structure 402 including peripheral circuitry) is in Figure 4B In the 3D memory device 401, a first semiconductor structure 402 including peripheral circuitry is positioned above a second semiconductor structure 404 including an array of memory cells. According to some embodiments, a bonding interface 406 is vertically formed between the first semiconductor structure 402 and the second semiconductor structure 404 in the 3D memory device 401, and the first semiconductor structure 402 and the second semiconductor structure 404 are vertically combined by bonding (e.g., hybrid bonding). Hybrid bonding (also known as “metal / dielectric hybrid bonding”) is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal (e.g., copper-to-copper) bonding and dielectric-to-dielectric (e.g., silicon oxide-to-silicon oxide) bonding.

[0099] Figure 5A perspective view of an exemplary memory device 500 implementing a front-side word line solution according to some aspects of this disclosure is shown. The front-side word line solution provides a method for picking up / routing word lines from the front side of a semiconductor structure to achieve electrical connections between word lines and peripheral circuitry. In this disclosure, the terms "word line picking up" and "word line routing" are used to refer to certain processes of positioning word lines and forming word line interconnects (e.g., in connection regions) to make electrical connections through direct contact with the word lines.

[0100] It should be noted that, Figure 5 The x-axis, y-axis, and z-axis are included to further illustrate the spatial relationships of the components in the memory device 500. The substrate (not shown) of the memory device 500 may include two lateral surfaces extending laterally in the xy-plane: a top surface on the front side of the wafer on which semiconductor devices are formed; and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x-axis and y-axis.

[0101] As used herein, when a substrate is positioned in the lowest plane of a 3D memory device in the z-direction, one component (e.g., a layer or device) of the 3D memory device can be defined "above," "over," or "below" another component (e.g., a layer or device) of the 3D memory device in the z-direction (a direction perpendicular to the xy-plane, e.g., the thickness direction of the substrate) relative to the substrate of the 3D memory device. Therefore, in this disclosure, the term "front side" is used to refer to... Figure 5 In this context, the term "side facing the positive z-direction" refers to the side oriented in the positive z-direction, while the term "back side" refers to the opposite side oriented in the negative z-direction. Throughout this disclosure, the same concepts are applied to describe spatial relationships. Furthermore, in the description of this disclosure, the term "depth" may be used to indicate a distance or length along the z-direction relative to the top or bottom surface of a reference item (e.g., a substrate).

[0102] like Figure 5 As shown, the memory device 500 may include a plurality of memory cells 508. In some embodiments, the memory cells 508 may be organized as a 2D array having multiple rows and columns. The memory cells 508 in the array may include vertically stacked transistors 510 and memory cells 512 relative to the z-direction. In some embodiments, the memory device 500 may also include word lines 502 and bit lines 514. The word lines 502 may extend in a first lateral direction (i.e., the x-direction or word line direction), and the bit lines 514 may extend in a second lateral direction (i.e., the y-direction or bit line direction). The bit lines 514 may be configured to electrically couple the array of memory cells 508 to peripheral circuitry via bit line interconnects 516. In some embodiments, the bit line interconnects 516 may be formed using vias in the connection region 506.

[0103] In some embodiments of this disclosure, two word lines 502 can be formed by removing a portion of a conductive layer, thereby turning the conductive layer into two independent conductive lines. By splitting the conductive layer along the y-direction, the end of word line 502-1 can be substantially flush with the end of another word line 502-2 in the x-direction, such as... Figure 5 As shown. The distance in the y-direction between a pair of adjacent word lines formed by the same conductive layer can be different in the connection region 506 and the storage region. Details will be provided in the following description.

[0104] Consistent with the scope of this disclosure, word line interconnects 504 can be formed by utilizing a channel via created in the connection region 506, extending the depth of the channel via in the z-direction until reaching the word line 502. Subsequently, the channel via can be filled with one or more conductive materials to form the word line interconnect 504 connecting the word lines 502, such as... Figure 5 As shown, word line 502 can electrically couple vertical transistor 510 to peripheral circuitry via word line interconnect 504.

[0105] In some embodiments, the memory device 500 may further include one or more through-silicon contacts (TSCs) 518 in the connection region 506. A TSC 518 (also known as a through-silicon via) is a vertical electrical connection used for integration in a 3D memory device. TSCs enhance signal integrity by minimizing interference. In some embodiments, the memory cells 508 in the memory array region may also be organized into multiple sub-memory regions 520, such as... Figure 5 As shown. In some cases, memory cells 508 in a sub-memory region 520 may be defined by a partition wall 522, but this disclosure is not limited to this. In some embodiments, word lines 502 may extend laterally (in the x-direction) from one sub-memory region 520 to another sub-memory region 520. In some embodiments, a connection region 506 may be arranged between two adjacent sub-memory regions 520.

[0106] In some embodiments, word lines 502 may extend in the x-direction, and bit lines 514 may extend in the y-direction. Therefore, in the connection region 506, word line interconnects 504 may be arranged in the y-direction to pick up word lines 502 arranged in the x-direction. In some embodiments, in the connection region 506, bit line interconnects 516 may be arranged in the x-direction to pick up bit lines 514 arranged in the y-direction. In some embodiments, a TSC may be formed at the intersection of word line interconnects 504 and bit line interconnects 516.

[0107] Figure 6 A flowchart of an exemplary method 600 for forming individual word lines in a storage device, according to some aspects of this disclosure, is shown. Figures 7A to 7DA schematic plan view of a memory device 700 during various manufacturing processes for forming exemplary individual word lines, according to some aspects of this disclosure, is shown. Figures 8A to 8D A schematic side view showing an exemplary manufacturing process performed from the front side of the storage device is shown. Figures 9A to 9D A schematic side view showing other exemplary manufacturing processes performed from the back side of the storage device is shown.

[0108] To form individual word lines in the memory device, method 600 may begin with operation 602. At operation 602, multiple conductive layers 702 may be formed in the semiconductor structure of the memory device 700, such as... Figure 7A As shown. In some embodiments, conductive layer 702 may comprise any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. In some examples, conductive layer 702 may comprise tungsten (W).

[0109] In some embodiments, the conductive layer 702 formed in the memory device 700 may correspond to two rows of vertical transistors 704. For example, as Figure 7A As shown, the conductive layer 702 can be arranged between two rows of vertical transistors 704. Figures 7A to 7C The rectangular frame with reference numeral 704 in the figure can represent the semiconductor body of a vertical transistor (e.g., Figure 1 (Semiconductor body 120 in the image). In some cases, the conductive layer 702 may be arranged between two rows of the semiconductor body of the vertical transistor 704. In some examples, the conductive layer 702 may be formed as a ring structure in plan view. In this disclosure, the term "ring" is used to describe a continuous and uninterrupted path for forming a closed structure of the conductive layer 702. The choice of a ring-shaped conductive layer may be an option to facilitate the manufacturing process, but this disclosure is not limiting. In other embodiments, the conductive layer 702 may be continuous in the memory array region 706 and the interconnect region 708 in plan view, but discontinuous in the separation region 710. By removing the discontinuous portion of the conductive layer 702 in the separation region 710 using other suitable processes, two separate word lines can be formed.

[0110] In some embodiments, the conductive layer 702 may extend on the memory device 700 in a lateral direction (i.e., the x-direction; word line direction). In some examples, the conductive layer 702 may extend in the x-direction from the memory array region 706 to the connection region 708. A portion of the conductive layer 702 (e.g., a corner portion of the conductive layer 702) may be disposed in a separation region 710 adjacent to the memory array region 706. In some embodiments, the configuration of the conductive layer 702 in the connection region 708 may differ from the configuration of the conductive layer 702 in the memory array region 706, such as... Figure 7A As shown. Details will be described below.

[0111] Figure 8A A cross-sectional view (e.g., along section line AA) is provided for describing a storage device (e.g., storage device 700) for subsequent front-side word line solutions, while Figure 9A A flip-out perspective view of a memory device 700 is presented, showing a fabrication process in which two separate word lines are executed from the back side by displaying a substrate 712 on top. In some embodiments consistent with the core of this disclosure, the substrate 712 may be fabricated first, and then one or more dielectric layers 714 (e.g., including a silicon oxide layer) may be deposited on the substrate 712. Within the one or more dielectric layers 714, vertical transistors 704, each having a semiconductor body and a gate structure, and a continuous / annular conductive layer 702 connecting two rows of gate structures in the memory array region 706 may be formed. In some embodiments, the conductive layer 702 may be disposed between the two rows of semiconductor bodies of the vertical transistors 704 in the memory array region 706.

[0112] Method 600 can proceed to operations 604 and 606, wherein a mask 716 can be applied to remove unwanted portions of the separation region 710. In some embodiments, the width of the mask 716 in the x-direction can be approximately 100 nm, and the corner portions of the conductive layer 702 in the separation region 710 can be covered within the mask 716, such as... Figure 7B As shown. Based on mask 716, portions of one or more dielectric layers 714 can be removed sequentially at operation 604, and portions of conductive layer 702 can be removed at operation 606, as... Figure 7B and 7CAs shown. In some examples, at operations 604 and 606, portions of the conductive layer 702 and one or more dielectric layers 714 can be removed using wet etching and / or dry etching (such as DRIE). For example, one or more etchants can be applied to one or more dielectric layers 714 and the conductive layer 702. The etchant can include any suitable etchant capable of selectively etching one or more dielectric layers 714 relative to the conductive layer 702. Thus, one or more dielectric layers 714 within the conductive layer 702 in the mask 716 can be selectively removed. Subsequently, the conductive layer 702 in the mask 716 can then be removed, thereby forming an opening 718.

[0113] In some implementations, the removal process can be performed from the front side of the semiconductor structure opposite to the substrate 712, such as Figure 8B and Figure 8C As shown. Therefore, the substrate 712 can be held at the bottom, as... Figure 8B and Figure 8C As shown. In other embodiments, the removal process can be performed from the back side of the semiconductor structure (e.g., applying one or more etchants to the substrate 712). Therefore, the substrate 712 can also be removed together with portions of one or more dielectric layers 714, such as... Figure 9B and Figure 9C As shown. This disclosure does not limit this.

[0114] Method 600 can proceed to operation 608, in which the dielectric layer 720 can be filled into the opening 718, such as Figure 7D , Figure 8D and Figure 9D As shown. In some embodiments, dielectric layer 720 may be the same as one or more dielectric layers 714. For example, both the first dielectric layer 714 and the second dielectric layer 720 may comprise a silicon oxide layer, while in other examples they may be different.

[0115] Consistent with the core of this disclosure, conductive layer 702 may include a first portion extending in the x-direction corresponding to a first row of semiconductor bodies perpendicular to the transistors, and a second portion extending in the x-direction corresponding to a second row of semiconductor bodies perpendicular to the transistors. In some embodiments, conductive layer 702 may further include a third portion, which is a bottom layer 707 connecting the first and second portions, such as... Figure 8AAs shown. The bottom layer 707 may extend laterally through the memory array region 706 within one or more dielectric layers 714. In some embodiments, the bottom layer 707 of the conductive layer 702 may be completely removed before or after the formation of the memory device, and this disclosure is not limiting in this regard. For example, a certain thickness of the semiconductor structure, including the substrate and the bottom layer 707, may be removed from the back side after the formation of the memory device. Thus, two separate and adjacent word lines 722-1 and 722-2 may be formed using the same conductive layer.

[0116] In some implementations, word lines 722-1 and 722-2 can be arranged between two rows of the semiconductor body of the vertical transistor 704. In some examples, in the second lateral direction (i.e., the y-direction; bit line direction), the first distance d1 between the first word line 722-1 and the second word line 722-2 in the connection region 708 can be greater than the second distance d2 between the first word line 722-1 and the second word line 722-2 in the memory array region 706, such as... Figure 7D As shown. In some embodiments, the second distance d2 can abruptly change to the first distance d1 within the connection region 708, such as... Figure 7D As shown. However, in other embodiments, the transition can occur gradually with a slope or a smooth curve, wherein the second distance d2 slowly changes to the first distance d1. This disclosure is not limiting in this respect.

[0117] For ease of explanation, Figures 7A to 7D , Figures 8A to 8D and Figures 9A to 9D Only certain components are depicted in this diagram. It will be understood that the memory device 700 may include other components, such as an isolation structure 724 configured to electrically isolate two rows of vertical transistors 704. By placing the isolation structure 724 between memory cells (e.g., between the semiconductor bodies of the vertical transistors), electrical isolation of the vertical transistors can be ensured, thereby maintaining the integrity of switching operation. In some embodiments, other suitable components may be included in these figures. This disclosure is not limiting in this regard. Since the memory device 700 has independent word lines 722, word line interconnects may be formed accordingly.

[0118] Figure 10 A flowchart of an exemplary method 1000 for forming word line interconnects in a storage device, according to some aspects of this disclosure, is shown. Figure 11A A schematic cross-sectional view of a storage device 1100 during a manufacturing process for forming an exemplary channel hole, according to some aspects of this disclosure, is shown. The storage device 1100 may be an example of a storage device 700, and can be described with respect to... Figure 6 The described method forms word line 1104.

[0119] Method 1000 begins with operation 1002. At operation 1002, a stop layer 1102 may be formed over the transistor structure in the memory array region 706. In some cases, the formation of the stop layer 1102 may be constrained within the memory array region 706 of the memory device 1100. In some embodiments, the stop layer 1102 may extend laterally over the memory array region 706 without extending into the connection region 708. In some embodiments, the stop layer 1102 may cover a portion of the connection region 708, leaving another portion of the connection region 708 uncovered. In some embodiments, the stop layer 1102 may extend over both the memory array region 706 and the connection region 708. This disclosure is not limited in this respect, as long as the stop layer 1102 covers the memory array region 706.

[0120] In some embodiments, the stop layer 1102 may include a dielectric layer. For example, the stop layer 1102 may include at least one of a silicon boron nitride layer or a silicon nitride layer. In some embodiments, the stop layer 1102 may extend laterally over the memory array region 706 without extending into the connection region 708. In subsequent manufacturing processes, the stop layer 1102 may serve as a stop layer to prevent vias in the memory array region 706 from penetrating the layers beneath the stop layer 1102. Therefore, a via formed laterally in the memory array region 706 may have a smaller length (or depth) z1 in the z-direction compared to the length (or depth) z2 of a via in the connection region 708 where the stop layer 1102 is not present.

[0121] Method 1000 can proceed to operation 1004. At operation 1004, a stacked structure 1108 can be formed in the connection region 708 and the storage array region 706, such as... Figure 11AAs shown. In some embodiments, the stacked structure 1108 may include multiple dielectric layers, including a first dielectric layer and a second dielectric layer. In some examples, the stacked structure 1108 may include a silicon nitride layer, a silicon carbonitride layer, and / or a silicon oxide layer. For example, the stacked structure 1108 may include a first silicon oxide layer, a silicon carbonitride layer stacked on the first silicon oxide layer, a second silicon oxide layer stacked on the silicon carbonitride layer, and a silicon nitride layer stacked on the second silicon oxide layer. In some embodiments, the stacked structure 1108 may extend laterally over the memory array region 706 and the interconnect region 708. In some embodiments, the stacked structure 1108 in the memory array region 706 may be removed in a subsequent manufacturing process, while the stacked structure 1108 may be retained in the interconnect region 708. For example, one or more layers of the stacked structure 1108 in the memory array region 706 may be removed sequentially using wet etching and / or dry etching (such as DRIE). In some implementations, the stacked structure 1108 can be completely removed in the storage array region 706 in a subsequent process to form components of the storage device, such as capacitor dielectrics and electrode structures.

[0122] Method 1000 can proceed to operation 1006. In operation 1006, multiple vias 1110 can be formed in the storage array region 706 and the connection region 708, such as... Figure 11A As shown. In some embodiments, a mask 1101 (e.g., a hard mask) covering both the memory array region 706 and the interconnect region 708 of the memory device 1100 can be formed on the stacked structure 1108, such as Figure 11B As shown. In some examples, mask 1101 may include polysilicon and / or silicon oxide. Mask 1101 may include multiple uncovered portions configured to form a channel via 1110 in memory array region 706 or a channel via 1110 in interconnect region 708. In some examples, the uncovered portions of mask 1101 may include circles, and these circles may have the same area. Thus, the surface area of ​​the ends of the channel via may be the same.

[0123] At operation 1006, a portion of the stacked structure 1108 can be removed from the top of the memory device 1100, for example, using a mask 1101. In some embodiments, to form the vias, the stacked structure 1108 can be patterned using photolithography followed by wet etching and / or dry etching. As a result, portions of the stacked structure 1108 corresponding to the vias (e.g., portions of the first and second dielectric layers) in both the memory array region 706 and the interconnect region 708 can be removed. The mask 1101 can then be removed from the stacked structure 1108. In some embodiments, a stop layer 1102 can be used as a stop layer to prevent the removal process in the memory array region 706 from continuing further upon encountering the stop layer 1102. In other words, the removal process in the memory array region 706 is stopped due to the presence of the stop layer 1102.

[0124] In some embodiments, the stop layer 1102 may be formed to extend over both the memory array region 706 and the connection region 708. Therefore, the vias 1110 in the memory array region 706 and the connection region 708 may initially be formed to stop at the stop layer 1102 to have the same length. Subsequently, the stop layer 1102 and other layers in the vias 1110 of the connection region 708 may be further removed. As a result, the vias 1110 in the connection region 708 may have a longer length than the vias 1110 in the memory array region 706.

[0125] In some embodiments, after reaching the stop layer 1102, the stop layer 1102 within the via 1110 can be further removed to ensure that the via exposes the corresponding vertical transistor 1106 below. In some examples, the source node contact (SNC) structure 1112 of the vertical transistor 1106 can be exposed in the via 1110 of the memory array region 706. In some embodiments, the stop layer 1102 may include a third dielectric layer, and the third dielectric layer within the via 1110 of the memory array region 706 can be removed. In some embodiments, the SNC structure 1112 can be configured to couple the vertical transistor 1106 to a storage device subsequently formed in the via 1110 of the memory array region 706. For example, the via in the memory array region 706 can then be filled with one or more conductive materials to form the electrode structure of the storage device. The electrode structure of the storage device can be configured to have an electrical connection with the SNC structure 1112 of the vertical transistor 1106. The SNC structure 1112 may be disposed on top of the semiconductor body of the corresponding vertical transistor 1106 and includes a conductive layer in contact with the corresponding electrode structure formed later. In some embodiments, the SNC structure 1112 may be arranged in an array and disposed in one or more dielectric layers below the stop layer 1102.

[0126] Therefore, in the z-direction, the length (or depth) z1 of the channel hole 1110 in the storage array region 706 can be smaller than the length (or depth) z2 of the channel hole 1110 in the connection region 708 where the stop layer 1102 does not exist, such as... Figure 11A As shown. In some embodiments, the via 1110 in the connection region 708 may have sufficient length / depth in the z-direction to allow the word line 1104 to be reached. In some embodiments, a portion of the via in the connection region 708 may be configured to form a bit line interconnect in the connection region 708. The bit line interconnect may be configured to couple the bit line to a bit line contact formed subsequently.

[0127] In some embodiments, vias 1110 for forming storage devices in memory array region 706 and vias 1110 for forming word line interconnects in connection region 708 can be formed simultaneously. In some embodiments, vias 1110 for forming storage devices in memory array region 706, vias 1110 for forming word line interconnects in connection region 708, and vias 1110 for forming bit line interconnects in connection region 708 can be formed simultaneously. In some embodiments, the circles in mask 1101 can be of the same size. Therefore, as... Figure 11A As shown, on the side away from word line 1104, the surface area of ​​the end of a channel hole 1110 used to form a storage element in storage array region 706 can be the same as the surface area of ​​the end of another channel hole 1110 used to form word line interconnection in connection region 708.

[0128] Figure 12A A schematic plan view of a memory device 1200 during a manufacturing process for forming an exemplary word line interconnect, according to some aspects of this disclosure, is shown. Method 1000 can proceed to operation 1008, in which a channel via 1110 in memory array region 706 can be formed Figure 12A The storage device 1202 in the connection area 708 can form word line interconnects 1204 based on the channel holes 1110 in the connection area 708.

[0129] In some embodiments, the storage device 1202 may include a capacitor. For example, in Figure 11A In the channel vias 1110 of the storage array region 706, electrode structures for capacitors can be formed (e.g., Figure 15 The first electrode structure 1518 in the memory array 1202). The electrode structure may be an electrode coupled to the corresponding semiconductor body of the storage device 1202. In some embodiments, one or more conductive layers may be deposited into the channel vias 1110 in the memory array region 706 using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof). Figure 11A The electrode structure can be formed by filling the channel holes 1110 in the memory array region 706 with titanium nitride (TiN). The formed electrode structure can be configured to interact with... Figure 11A The SNC structure 1112 in the middle makes direct contact to couple the storage device 1202 to the source of the corresponding vertical transistor. Subsequently, another electrode and capacitor dielectric can be formed to act as a capacitor in contact with the semiconductor body of the vertical transistor.

[0130] In some implementations, the bit line ( Figure 5 Storage device 1202 is formed on the side opposite the semiconductor body of the vertical transistor (as shown). In some examples, bit lines may be coupled to the drain of the vertical transistor, while storage device 1202 may be coupled to the source of the vertical transistor. In some embodiments, memory device 1200 may include a separation region 710, in which the conductive layer is subsequently split to form two separate word lines 1206, such as... Figure 12A As shown. The separation region 710 can be arranged at the boundary of the storage array region 706. It is understood that, for ease of description in this disclosure, the separation region 710 can be divided from the storage array region 706. In some descriptions, the separation region 710 can be regarded as part of the storage array region 706 or the connection region 708.

[0131] In some implementations, at operation 1008, the word line interconnect 1204 can be formed based on the via 1110 in the connection region 708. For example, the via 1110 in the connection region 708 can have a greater depth than the via 1110 in the memory array region 706, until it encounters the word line 1104. One or more conductive materials can be deposited into the via 1110 in the connection region 708 to form the word line interconnect 1204, such as... Figure 12AAs shown. One or more conductive materials may include metals (e.g., tungsten) or metal compounds, wherein a portion of the channel via 1110 in the connection region 708 is filled using one or more thin-film deposition processes (including, but not limited to, CVD, PVD, ALD, or any combination thereof). In some embodiments, a planarization process (e.g., chemical mechanical planarization, CMP) may be performed after the formation of the word line interconnect 1204 to remove residual material, such that the top surface of the word line interconnect 1204 is substantially flush with the top surface of the storage device 1202. In some embodiments, the formation of the word line interconnect 1204 in the connection region 708 and the formation of the electrode structure of the storage device 1202 in the memory array region 706 may be performed simultaneously. In some embodiments, the formation of the word line interconnect 1204 in the connection region 708, the formation of the electrode structure of the storage device 1202 in the memory array region 706, and the formation of the bit line contacts in the connection region 708 may be performed simultaneously.

[0132] In some embodiments, the storage device 1200 may include an isolation structure 1210, which may be configured to isolate two rows of storage cells (e.g., electrically). For example, the isolation structure 1210 may be configured to be disposed between two rows of semiconductor bodies of vertical transistors to isolate these vertical transistors (e.g., electrically). Vertical transistors are part of the signal path and are sensitive to interference. In some cases, electrical noise or interference between adjacent vertical transistors may cause unwanted switching, leakage, or malfunctioning operation, which may corrupt the stored data in the storage device 1202. By placing the isolation structure 1210 between storage cells (e.g., between vertical transistors), it is ensured that the vertical transistors remain electrically isolated, thereby maintaining the integrity of switching operation.

[0133] Figures 12B to 12C A schematic cross-sectional view of a memory device 1200 during a manufacturing process for forming an exemplary word line interconnect 1204, according to some aspects of this disclosure, is shown. Figure 12B It shows along Figure 12A The cross-sectional view 1201, with section lines 12B-12B, represents a cross-sectional view of the memory array region 706. The memory device 1200 may include memory device 1202 and word line 1206, such as... Figure 12B The cross-sectional view is shown in Figure 1201. Figure 12B As shown, word line 1206 and storage device 1202 are not in contact and are not electrically coupled within storage array region 706. In some embodiments, to achieve this, the length of the channel aperture corresponding to storage device 1202 can be controlled. For example, as Figure 12BAs shown, the stop layer 1212 can be arranged to control the channel vias in the memory array region 706 to not exceed a certain length. In some embodiments, the stop layer 1212 can be arranged laterally and generally horizontally relative to the z-direction, wherein the storage element 1202 is connected to the semiconductor body of the vertical transistor.

[0134] on the other hand, Figure 12C It shows along Figure 12A The cross-sectional view 1203 is shown along section lines 12C-12C. Cross-sectional view 1203 may represent a cross-sectional view within the connection region 708. The storage device 1200 may include word line interconnects 1204 and word lines 1206, such as... Figure 12C The cross-sectional view is shown in Figure 1203. Figure 12C In this configuration, word line interconnect 1204 and word line 1206 can be electrically connected in connection region 708. In some embodiments, for this purpose, control can be implemented. Figure 12B The stop layer 1212 in the storage array region 706 does not extend to Figure 12C The connection region 708 in the memory array. Therefore, the via corresponding to the word line interconnect 1204 can have a longer length (depth in the z-direction) than the via corresponding to the storage device 1202 in the memory array region 706. Figure 12A As shown, in some embodiments, the two word line interconnects 1204 can be aligned on section lines 12C-12C. Therefore, in Figure 12C In the cross-sectional view 1203, two word line interconnects 1204 can be connected to two word lines 1206 respectively, but this disclosure is not limited thereto. In some embodiments, more than one word line interconnect 1204 can be arranged in the connection area 708 along a word line 1206, for example, two or four word line interconnects 1204 corresponding to a word line 1206 in the connection area 708.

[0135] Figure 13A A schematic plan view of another memory device 1300 during a manufacturing process for forming other exemplary word line interconnects 1304, according to some aspects of this disclosure, is shown. In some embodiments, the memory device 1300 may include word line interconnects 1304 that are misaligned on section lines 13C-13C, such as... Figure 13A As shown. In some embodiments, in the storage array region 706, the storage device 1300 may have a configuration similar to... Figure 12B Those structures that are identical (or similar) in construction. Therefore, storage device 1300 may include storage device 1302 and word line 1306, such as Figure 13B The cross-sectional view is shown in Figure 1301. Figure 13BAs shown, word line 1306 and storage device 1302 do not contact each other in storage array region 706. In some embodiments, stop layer 1312 may be arranged laterally and generally horizontally relative to the z-direction, wherein storage device 1302 is connected to the semiconductor body of vertical transistor.

[0136] On the other hand, such as Figure 13C As shown in cross-sectional view 1303, storage device 1200 may include word line interconnects 1304 and word lines 1306. In some embodiments, word line interconnects 1304 and word lines 1306 may be electrically connected in connection region 708. Due to misalignment of the two word line interconnects 1304, only one word line interconnect 1304 is depicted connected to word line 1306, as shown. Figure 13C As shown.

[0137] In some embodiments, the memory device 1300 may include an isolation structure 1310, and the isolation structure 1310 may be configured to electrically isolate two rows of memory cells. For example, the isolation structure 1310 may be configured to be disposed between two rows of semiconductor bodies of vertical transistors to electrically isolate these vertical transistors.

[0138] Figure 14 A schematic plan view of another memory device 1400 having word lines 1406 and word line interconnects 1404 according to some aspects of this disclosure is shown. For ease of illustration, Figure 14 Only two separate regions 710 and a memory array region 706 located between the two separate regions 710 are shown. In some embodiments, word line interconnects 1404 may be formed to extend in the z-direction for electrical connection with word lines 1406. Word lines 1406 may be formed to connect to the semiconductor body of vertical transistors 1408 and may form memory devices 1402 corresponding to vertical transistors 1408. In some embodiments, two adjacent word lines may be formed by splitting the conductive layer by removing corner portions of the conductive layer in the separate regions 710, such as... Figure 14 As shown. In some embodiments, the first word line 1406-1 and the second word line 1406-2 may be arranged between two rows of the semiconductor body of the vertical transistor 1408. In some examples, the ends of the first word line 1406-1 and the ends of the second word line 1406-2 are substantially flush, such as... Figure 14 As shown.

[0139] Figure 15 A schematic cross-sectional view of another storage device 1500 having word lines 1502 and word line interconnects 1504 according to some aspects of this disclosure is shown. Figure 15A cross-sectional view along word line 1502 can be shown. In some embodiments, word line interconnects 1504 may be formed to extend in the z-direction through stack structure 1506, thereby connecting to word line 1502, as shown. Figure 15 As shown. In some embodiments, the stacked structure 1506 may include multiple dielectric layers, including a silicon nitride layer, a silicon carbonitride layer, and / or a silicon oxide layer. In some examples, the stacked structure 1506 may include a first silicon oxide layer 1508, a silicon carbonitride layer 1510 stacked on the first silicon oxide layer 1508, a second silicon oxide layer 1512 stacked on the silicon carbonitride layer 1510, and a silicon nitride / silicon carbonitride layer 1524 stacked on the second silicon oxide layer 1512.

[0140] In some embodiments, the storage device 1500 may include a stop layer 1516 that extends laterally over the storage array region 706 but not into the connection region 708, such as... Figure 15 As shown. In the manufacturing process, the channel hole corresponding to the corresponding storage device (e.g., the first electrode structure 1518 of the storage device) can be stopped before the stop layer 1516 and has a length smaller than the length of the channel hole corresponding to the word line interconnect 1504. Subsequently, the first electrode structure 1518 can be formed above the semiconductor body 1520 of the vertical transistor in the channel hole of the storage array region 706, as shown. Figure 15 As shown. In some embodiments, the first electrode structure 1518 may be arranged to contact the SNC structure 1522 of the corresponding vertical transistor, such as... Figure 15 As shown. In some embodiments, the storage device 1500 may further include a second electrode structure 1507 and a dielectric 1505 located between the first electrode structure 1518 and the second electrode structure 1507, thereby forming a capacitor that serves as a storage device.

[0141] It should be noted that, Figure 15 Certain components (such as semiconductor body 1520) are depicted in the cross-section, but they may not be directly located on the cross-section. These components may be at different distances relative to word line 1502. They are included in the cross-sectional view merely to illustrate the spatial relationship between these components and word line 1502 for illustrative purposes.

[0142] In some examples, the second electrode structure 1507 may include one or more conductive layers (e.g., a titanium nitride layer). In some embodiments, the dielectric 1505 may include one or more dielectric materials, such as silicon oxide, silicon nitride, or high-k dielectrics, including but not limited to aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), tantalum oxide (Ta₂O₅), zirconium oxide (ZrO₂), titanium oxide (TiO₂), or any combination thereof. In some embodiments, one or more conductive layers and one or more dielectric layers may be disposed on the storage device.

[0143] In some embodiments, on the side away from word line 1502, the surface area of ​​the end of a portion of the storage element in storage array region 706 (e.g., the first electrode structure 1518) may be the same as the surface area of ​​the end of word line interconnect 1504 in connection region 708.

[0144] In some embodiments, the memory device 1500 may include one or more interlayer dielectric (ILD) layers containing various local contacts (such as bit line contacts) that interact with the memory cells of the 1T1C structure. The local contacts may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer may include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0145] In some embodiments, the storage device 1500 may include word line contacts 1514, which may be formed corresponding to word line interconnects 1504 and configured to route / pick up word lines 1502 for connection to peripheral circuitry. In some embodiments, the storage device 1500 may include bit lines and bit line contacts configured to route / pick up bit lines for connection to peripheral circuitry.

[0146] In some embodiments, the memory device 1500 can be formed in the first semiconductor structure, and the peripheral circuitry can be formed separately or independently in the second semiconductor structure. Subsequently, for example, according to... Figure 4A or Figure 4B The first semiconductor structure and the second semiconductor structure are bonded in a manner that allows the memory device 1500 in the first semiconductor structure to be electrically connected to peripheral circuitry in the second semiconductor structure via word line contacts 1514, word line interconnects 1504, bit lines, bit line contacts, etc. Therefore, by applying various voltages to the word lines 1502 and bit lines, for example, via peripheral circuitry, the memory device 1500 can be controlled by a memory controller (e.g., ...). Figure 3 The memory controller 308 in the memory is controlled.

[0147] Therefore, this disclosure provides various solutions in which individual word lines can be formed using conductive layers, and word line interconnects can be formed using vias in the interconnect regions. At the heart of this disclosure, word line interconnects can be formed from the front side of the memory device. This method of leading word lines from the front side achieves greater flexibility because it simplifies the positioning process and minimizes the need for additional vias formed on the back side.

[0148] The foregoing description of specific embodiments will reveal the general nature of this disclosure. Without departing from the overall concept of this disclosure, others can easily modify and / or adapt these specific embodiments for various applications by applying knowledge in the art, without excessive experimentation. Therefore, based on the teachings and guidance provided herein, such modifications and adjustments are intended to be within the meaning and scope of equivalents of the disclosed embodiments. It should be understood that the wording or terminology herein is for descriptive rather than limiting purposes, and that the terminology or terminology in this specification should be interpreted by those skilled in the art based on the teachings and guidance.

[0149] The embodiments of this disclosure have been described above using functional building blocks that illustrate implementations of specific functions and their relationships. For ease of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specific functions and their relationships are properly performed.

[0150] The summary and abstract may set forth one or more, but not all, exemplary embodiments of this disclosure as conceived by the inventors, and are therefore not intended to limit this disclosure and the appended claims in any way.

[0151] The breadth and scope of this disclosure should not be limited by any of the embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A storage device, comprising: An array of memory cells in a memory array region, wherein each memory cell includes a semiconductor body; as well as Multiple word lines extending from the storage array region to the connection region in a first direction. in: In the connection area, word line interconnects extend upward in a third direction to connect with the plurality of word lines, the third direction being perpendicular to the first direction; The plurality of word lines include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor body, the second direction being perpendicular to the first direction and the third direction; and In the second direction, the first distance between the first word line and the second word line in the connection region is greater than the second distance between the first word line and the second word line in the storage array region.

2. The storage device according to claim 1, wherein: In the third direction, one of the word line interconnects extends through a first dielectric layer and a second dielectric layer of the stacked structure in the connection region to connect with a corresponding word line among the plurality of word lines, wherein the first dielectric layer and the second dielectric layer are different.

3. The storage device according to claim 1 or claim 2, wherein: One of the storage units further includes a storage component; and The third dielectric layer is arranged laterally and is generally horizontal relative to the third direction, wherein the electrode structure of the storage device is connected to the corresponding semiconductor body in the semiconductor body.

4. The storage device according to claim 3, wherein: The third dielectric layer includes a silicon boron nitride layer.

5. The storage device according to claim 3, wherein: The third dielectric layer extends over the storage array region but not over the connection region.

6. The storage device according to any one of claims 1-5, wherein: One of the memory cells in the memory cell array includes a storage element, the storage element including an electrode structure having a first end and a second end connected to one of the semiconductor bodies in the semiconductor body; One of the word line interconnects includes a third end and a fourth end connected to the first word line; and The second end of the electrode structure is substantially flush with the fourth end, which is interconnected with the word line.

7. The storage device according to claim 6, wherein: The surface area of ​​the second end of the electrode structure is substantially the same as the surface area of ​​the fourth end interconnected by the word lines.

8. The storage device according to claim 6, wherein: In the third direction, the length of the word line interconnect is greater than the length of the electrode structure of the storage device.

9. The storage device according to any one of claims 1-8, wherein: The storage array region includes a first sub-storage region and a second sub-storage region; and One of the multiple word lines extends from the first sub-storage area to the second sub-storage area in the first direction, and the connecting area is arranged between the first sub-storage area and the second sub-storage area.

10. The storage device according to any one of claims 1-9, wherein: The two rows of the semiconductor body include a first row of the semiconductor body and a second row of the semiconductor body; and The storage device further includes an isolation structure disposed between the second row and the third row of the semiconductor body and configured to isolate the second row of the semiconductor body from the third row of the semiconductor body.

11. The storage device according to any one of claims 1-10, wherein: In the second direction, the first end of the first character line is substantially flush with the second end of the second character line.

12. The storage device according to any one of claims 1-11, wherein: The first semiconductor structure includes the memory cell array and the multiple word lines; and The storage device also includes peripheral circuitry arranged in the second semiconductor structure. in: The first semiconductor structure is bonded to the second semiconductor structure; and The multiple word lines in the first semiconductor structure are electrically coupled to the peripheral circuit of the second semiconductor structure.

13. A storage device comprising: An array of memory cells in a memory array region, wherein each memory cell includes a semiconductor body; as well as Multiple word lines extending from the storage array region to the connection region in a first direction. in: In the connection area, word line interconnects extend upward in a third direction to connect with the plurality of word lines, the third direction being perpendicular to the first direction; The plurality of word lines include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor body, the second direction being perpendicular to the first direction and the third direction; and In the second direction, the first distance between the first word line and the second word line in the connection area is different from the second distance between the first word line and the second word line in the storage array area. In the second direction, the first end of the first word line and the second end of the second word line are substantially flush.

14. The storage device according to claim 13, wherein: The first distance is greater than the second distance.

15. The storage device according to claim 13 or claim 14, wherein: In the third direction, one of the word line interconnects extends through a first dielectric layer and a second dielectric layer in the stacked structure of the connection region to connect with a corresponding word line among the plurality of word lines, wherein the first dielectric layer and the second dielectric layer are different.

16. The storage device according to any one of claims 13-15, wherein: One of the storage units further includes a storage component; and The third dielectric layer is arranged laterally and is generally horizontal relative to the third direction, wherein the electrode structure of the storage device is connected to the corresponding semiconductor body in the semiconductor body.

17. The storage device according to claim 16, wherein: The third dielectric layer includes a silicon boron nitride layer.

18. The storage device according to claim 16, wherein: The third dielectric layer extends over the storage array region but not over the connection region.

19. The storage device according to any one of claims 13-18, wherein: One of the storage units includes a storage element, the storage element including an electrode structure having a first end and a second end connected to one of the semiconductor bodies; One of the word line interconnects includes a third end and a fourth end connected to the first word line; and The second end of the electrode structure is substantially flush with the fourth end, which is interconnected with the word line.

20. The storage device according to claim 19, wherein: The surface area of ​​the second end of the electrode structure is substantially the same as the surface area of ​​the fourth end interconnected by the word lines.

21. The storage device according to claim 19, wherein: In the third direction, the length of the word line interconnect is greater than the length of the electrode structure of the storage device.

22. The storage device according to any one of claims 13-21, wherein: The storage array region includes a first sub-storage region and a second sub-storage region; and One of the multiple word lines extends from the first sub-storage area to the second sub-storage area in the first direction, and the connecting area is arranged between the first sub-storage area and the second sub-storage area.

23. The storage device according to any one of claims 13-22, wherein: The two rows of the semiconductor body include a first row of the semiconductor body and a second row of the semiconductor body; and The storage device further includes an isolation structure disposed between the second row and the third row of the semiconductor body and configured to isolate the second row of the semiconductor body from the third row of the semiconductor body.

24. The storage device according to any one of claims 13-23, wherein: The first semiconductor structure includes the memory cell array and the multiple word lines; and The storage device also includes peripheral circuitry arranged in the second semiconductor structure. in: The first semiconductor structure is bonded to the second semiconductor structure; and The multiple word lines in the first semiconductor structure are electrically coupled to the peripheral circuits in the second semiconductor structure.

25. A method for forming a storage device, comprising: An array of memory cells is formed in the memory array region, and each memory cell includes a semiconductor body; as well as Multiple word lines are formed extending from the storage array region to the connection region in a first direction. in: In the connection area, word line interconnects extend upward in a third direction to connect with the plurality of word lines, the third direction being perpendicular to the first direction; The plurality of word lines include a first word line and a second word line arranged in a second direction and between two rows of the semiconductor body, the second direction being perpendicular to the first direction and the third direction; and In the second direction, the first distance between the first word line and the second word line in the connection region is greater than the second distance between the first word line and the second word line in the storage array region.

26. The method of claim 25, wherein, The plurality of character lines, including the first character line and the second character line, include: A conductive layer formed between the two rows of the semiconductor body and connecting the two rows of the semiconductor body; and A portion of the conductive layer is removed to split the conductive layer into a first word line and a second word line, wherein, in the second direction, a first end of the first word line and a second end of the second word line are substantially flush.

27. The method according to claim 25 or claim 26, further comprising: Multiple bit lines connected to the semiconductor body are formed on a first side of the semiconductor body; as well as The word line interconnect is formed in the connection region on a second side of the semiconductor body opposite to the first side, and the word line interconnect extends upward on the third side to connect with the plurality of word lines.

28. The method according to any one of claims 25-27, wherein, The word line interconnection formed by extending upward from the third party to connect with the plurality of word lines includes: A plurality of vias are formed extending upward in the third direction, wherein the plurality of vias includes a first via in the memory array region and a second via, the second via extending upward in the third direction through the stacking structure to reach the first word line in the connection region, and the length of the second via in the third direction is greater than the length of the first via; and The second channel hole is filled with one or more conductive materials to contact the first word line, thereby forming one of the word line interconnects.

29. The method of claim 28, further comprising: A first dielectric layer and a second dielectric layer are formed on top of the first dielectric layer, the stacked structure comprising the first dielectric layer and the second dielectric layer, wherein: Forming the plurality of vias includes: forming a second via in the connection region, the second via extending through the second dielectric layer and the first dielectric layer to reach the first word line.

30. The method according to claim 28, wherein, The plurality of channel holes formed extending upward from the third party include: Simultaneously, the first channel hole is formed in the storage array region and the second channel hole is formed in the connection region.

31. The method of claim 28, further comprising: An electrode structure is formed for a storage device, the electrode structure of the storage device being connected to a first semiconductor body in the semiconductor body, the first semiconductor body in the semiconductor body corresponding to a first channel via in the storage array region, and the electrode structure of the storage device and the word line interconnect being arranged on the same side of the first semiconductor body.

32. The method of claim 31, further comprising: A third dielectric layer is formed in the storage array region. in: Forming the plurality of vias includes: forming a first via in the memory array region, the first via extending through the stacked structure and stopping at the third dielectric layer, the first via corresponding to the first semiconductor body.

33. The method according to claim 32, wherein: The third dielectric layer includes a silicon boron nitride layer.

34. The method according to claim 31, wherein: The storage device includes the electrode structure, the electrode structure having a first end connected to the first semiconductor body and a second end; The word line interconnect includes a third end and a fourth end connected to the first word line; and The surface area of ​​the second end of the electrode structure is substantially the same as the surface area of ​​the fourth end interconnected by the word lines.

35. The method according to claim 34, wherein: In the second direction, the second end of the electrode structure is substantially flush with the fourth end that is interconnected with the word line.

36. The method according to claim 31, wherein: In the third direction, the length of the word line interconnect is greater than the length of the electrode structure of the storage device.

37. The method according to any one of claims 25-36, wherein: The two rows of the semiconductor body include a first row of the semiconductor body and a second row of the semiconductor body; and The method further includes forming an isolation structure disposed between a second row and a third row of the semiconductor body, the isolation structure being configured to isolate the second row of the semiconductor body from the third row of the semiconductor body.

38. The method according to any one of claims 25-37, further comprising: A first semiconductor structure is formed, the first semiconductor structure including the memory cell array and the plurality of word lines; Forming a second semiconductor structure including peripheral circuitry; as well as The first semiconductor structure is bonded to the second semiconductor structure, wherein the plurality of word lines in the first semiconductor structure are electrically coupled to the peripheral circuits in the second semiconductor structure.

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