Semiconductor structure and method of manufacturing the same, electronic device

Abstract

Embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof and an electronic device, and are used to solve how to improve the isolation of a bit line. The method comprises: providing a substrate, the substrate comprising semiconductor patterns and first dielectric layers arranged alternately, the semiconductor patterns comprising semiconductor lines extending along a second direction and a plurality of semiconductor columns spaced apart along the second direction and each connected to the semiconductor lines, first grooves exposing the semiconductor lines being formed between adjacent first dielectric layers; forming a bit line structure in the first grooves, the bit line structure comprising a bit line and second dielectric layers, the bit line being located between the semiconductor lines and the second dielectric layers; removing part of the first dielectric layers to form second grooves extending along the second direction; and forming an isolation structure located at least in the second grooves, the isolation structure having air gaps extending along the second direction, the air gaps having a size in a third direction greater than a size of the bit line in the third direction. In this way, a better isolation effect of the bit line is achieved.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more particularly to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Technology

[0002] As DRAM storage density continues to increase, bit line size continues to shrink, resulting in parasitic capacitance between bit lines having an increasingly significant impact on device read speed, signal quality, and overall performance.

[0003] To suppress parasitic capacitance between bit lines, the industry commonly employs a scheme of forming an isolation structure with an air gap between adjacent bit lines, thereby reducing the equivalent dielectric constant by introducing an isolation dielectric with a lower dielectric constant. However, the process for forming the isolation structure with the air gap still needs further optimization and improvement. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, a method for manufacturing the same, and an electronic device.

[0005] The technical solution of this disclosure embodiment is implemented as follows: On one hand, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a substrate, the substrate including a semiconductor pattern and a first dielectric layer alternately arranged along a first direction, wherein the semiconductor pattern includes semiconductor lines extending along a second direction and a plurality of semiconductor pillars spaced apart along the second direction and each connected to a first end of the semiconductor lines, a first trench exposing a second end of the semiconductor lines is formed between adjacent first dielectric layers, the second end and the first end are opposite each other along a third direction, the second direction and the first direction intersect and are both perpendicular to the third direction; forming a bit line structure in the first trench, wherein the bit line structure includes a bit line and a second dielectric layer, the bit line being located between the semiconductor lines and the second dielectric layer; removing a portion of the first dielectric layer to form a second trench extending along the second direction, wherein the second trench exposes the semiconductor lines and the sidewalls of the bit line structure; forming an isolation structure at least located within the second trench, wherein the isolation structure has an air gap extending along the second direction, the size of the air gap in the third direction being larger than the size of the bit line in the third direction.

[0006] In some embodiments, forming an isolation structure at least within the second trench includes: forming a third dielectric layer covering the inner wall of the second trench and the surface of the second dielectric layer; forming a sacrificial layer on the third dielectric layer within the second trench to fill the second trench; forming a fourth dielectric layer covering the sacrificial layer and the surface of the third dielectric layer; and removing the sacrificial layer to form the air gap at the location where the sacrificial layer was removed.

[0007] In some embodiments, the process for removing the sacrificial layer includes an ashing process.

[0008] In some embodiments, the material of the sacrificial layer includes a carbon material.

[0009] In some embodiments, forming a bit line structure in the first trench includes: forming the bit line on the semiconductor line; and forming a second dielectric layer on the bit line.

[0010] In some embodiments, there is a height difference between the surface of the isolation structure away from the first dielectric layer and the surface of the bit line away from the semiconductor line, wherein the height difference is greater than 0.

[0011] On the other hand, embodiments of this disclosure provide a semiconductor structure comprising: a plurality of semiconductor patterns, a first dielectric layer, a bit line structure, and an isolation structure; the plurality of semiconductor patterns are spaced apart along a first direction, wherein each semiconductor pattern includes semiconductor lines extending along a second direction and a plurality of semiconductor pillars spaced apart along the second direction and each connected to a first end of the semiconductor lines; the first dielectric layer is located between adjacent semiconductor pillars in the first direction; the bit line structure extends along the second direction and connects to a second end of the semiconductor lines, wherein the bit line structure includes a bit line and a second dielectric layer, the bit line is located between the semiconductor lines and the second dielectric layer, the second end and the first end are opposite each other in a third direction, the second direction and the first direction intersect and are both perpendicular to the third direction; the isolation structure is located at least between adjacent bit line structures in the first direction and between adjacent semiconductor lines in the first direction, wherein the isolation structure has an air gap extending along the second direction, the size of the air gap in the third direction being larger than the size of the bit line in the third direction.

[0012] In some embodiments, the isolation structure further includes a third dielectric layer covering the sidewalls of the semiconductor line, the sidewalls of the bit line structure, the surface away from the semiconductor line, and the surface of the first dielectric layer near the air gap.

[0013] In some embodiments, the semiconductor structure further includes a fourth dielectric layer that covers the air gap and the third dielectric layer on the surface of the bit line structure.

[0014] In another aspect, embodiments of this disclosure also provide an electronic device, the electronic device comprising: a processor; and a memory electrically connected to the processor, the memory comprising the semiconductor structure described in any of the above embodiments.

[0015] In this embodiment, a second dielectric layer is formed on the bit line, and then an isolation structure is formed between adjacent bit lines and between adjacent second dielectric layers. Because the isolation structure has an air gap extending along a second direction, and the size of the air gap in the third direction is larger than the size of the bit line in the third direction, the top of the air gap is higher than the top of the bit line, thereby achieving a better isolation effect on the bit line. Attached Figure Description

[0016] Figure 1 This is an example providing a schematic diagram of a substrate after it has been formed; Figure 2 This is an example of a schematic diagram showing the formation of bitline trenches; Figure 3 This is a schematic diagram illustrating the formation of a doped polycrystalline silicon material layer as an example. Figure 4 This is a schematic diagram illustrating the formation of a doped semiconductor layer as an example. Figure 5 This is an example of a schematic diagram showing the formation of an isolation trench; Figure 6 This is an example of a schematic diagram showing the etching of a doped semiconductor layer; Figure 7 This is an example of a schematic diagram showing the formation of a nitrogen oxide layer; Figure 8 This is an example of a schematic diagram showing the formation of a barrier material layer; Figure 9 This is an example of a schematic diagram showing the formation of a barrier layer; Figure 10 This is an example providing a schematic diagram of a bitline contact after it has been formed; Figure 11 This is an example diagram showing the result after removing the barrier layer; Figure 12 This is an example of a schematic diagram showing the formation of a protective layer; Figure 13 This is a schematic diagram illustrating an example of a deposited sacrificial material; Figure 14 This is an example diagram illustrating the formation of a sacrificial layer; Figure 15 This is a schematic diagram illustrating the formation of a dielectric material layer as an example. Figure 16 This is a schematic diagram illustrating the formation of an air gap as an example. Figure 17 This is a schematic flowchart of a semiconductor structure manufacturing method provided in an embodiment of this disclosure; Figure 18 This is a schematic diagram of an embodiment of the present disclosure after the formation of an initial substrate; Figure 19 This is a schematic diagram of a first trench formed according to an embodiment of this disclosure; Figure 20 This is a schematic diagram of a semiconductor line formed according to an embodiment of the present disclosure; Figure 21 This is a schematic diagram of a bit line formed according to an embodiment of the present disclosure; Figure 22 This is a schematic diagram of a second dielectric material layer after being formed, provided in an embodiment of this disclosure; Figure 23 This is a schematic diagram of a second dielectric layer after being formed, provided in an embodiment of this disclosure; Figure 24 This is a schematic diagram of a second trench formed according to an embodiment of this disclosure; Figure 25 This is a schematic diagram of a third dielectric layer after being formed, provided in an embodiment of this disclosure; Figure 26 This is a schematic diagram of a sacrificial material after deposition, provided in an embodiment of this disclosure; Figure 27 This is a schematic diagram of a sacrificial layer after its formation, provided in an embodiment of this disclosure; Figure 28 This is a schematic diagram of a fourth dielectric layer formed according to an embodiment of the present disclosure; Figure 29 This is a schematic diagram of an air gap formed according to an embodiment of the present disclosure; Figure 30 This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 31 This is a schematic block diagram of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0017] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0024] Before introducing the embodiments of this disclosure, the various directions that may be involved in the following text are defined. The direction perpendicular to the main surface of the substrate is defined as the third direction (denoted as direction D3 in the figures). In a plane parallel to the main surface of the substrate, an intersecting first direction (denoted as direction D1 in the figures) and a second direction (denoted as direction D2 in the figures) are defined. The angle between direction D1 and direction D2 can be acute, right, or obtuse. For ease of understanding, the following explanation will use the example of a right angle between direction D1 and direction D2, meaning that any two of directions D1, D2, and D3 are perpendicular to each other.

[0025] Figures 1 to 16 This is a schematic diagram illustrating a semiconductor structure manufacturing process as an example. Figures 1 to 16 These are all three-dimensional structural diagrams of semiconductor structures during the manufacturing process. The following will combine... Figures 1 to 16An example of a method for manufacturing a semiconductor structure is provided.

[0026] Reference Figure 1 As shown, a substrate is provided, comprising semiconductor patterns 102 and a first dielectric layer 104 alternately arranged along a first direction D1. The semiconductor patterns 102 include a first portion 106 extending along a second direction D2 and second portions 108 spaced apart along the second direction D2 and each connected to a first end of the first portion 106. The second end surface of the first portion 106 is flush with the surface of the first dielectric layer 104. The second end and the first end of the first portion 106 are opposite each other along a third direction D3. The second direction D2 intersects the first direction D1 and is perpendicular to the third direction D3. Here, the second portion 108 can be a semiconductor pillar or part of a semiconductor pillar for forming an active region of a transistor.

[0027] In each semiconductor pattern 102, a first portion 106 extends along a second direction D2, and each second portion 108 extends along a third direction D3. It should be noted that, although... Figure 1 Although not shown, insulating material may be filled between adjacent second portions 108 on the second direction D2 to achieve isolation between adjacent second portions 108. In some embodiments, the semiconductor pattern 102 further includes a third portion connected one-to-one with a plurality of second portions 108. The third portion extends along the third direction D3 and is located on the side of the second portion 108 on the third direction D3 away from the first portion 106. The second portions 108 and the third portion together form a semiconductor pillar. Each second portion 108 and its corresponding third portion form an active region of a transistor. The active region may include a source, a channel, and a drain arranged along the third direction D3. The second portion 108 is used to form one of the source and drain and is coupled to a bit line. The third portion is used to form the other of the source and drain and is coupled to a capacitor. The third portion is also used to form a channel and is coupled to a gate (or word line).

[0028] In some embodiments, the semiconductor pattern 102 can be formed on a substrate. Exemplarily, the substrate has a first surface and a second surface opposite each other along a third direction D3. The first surface of the substrate is etched to form a plurality of semiconductor patterns 102 arranged along a first direction D1 on the first surface of the substrate. Each semiconductor pattern 102 includes a first portion 106 extending along a second direction D2, a plurality of second portions 108 spaced apart along the second direction D2 and all connected to the first portion 106, and a third portion connected to the second portions 108. After forming the semiconductor pattern 102, a first dielectric layer 104 is filled between adjacent semiconductor patterns 102 in the first direction D1, such that the first dielectric layer 104 is located at least between two adjacent first portions 106 in the first direction D1. Then, a transistor structure can be formed based on each second portion 108 and the third portion, and a capacitor correspondingly connected to each transistor structure can be formed. Each transistor structure and its corresponding connected capacitor constitute a memory cell, thus forming a plurality of memory cells arranged in an array along the first direction D1 and the second direction D2 on the first surface of the substrate. After forming the memory cells, the entire three-dimensional structure is flipped so that the second side of the substrate faces upward. Then, a chemical mechanical planarization (CMP) process can be used to thin the second side of the substrate until the first dielectric layer 104 is exposed. In this way, the remaining substrate forms a plurality of semiconductor patterns 102 arranged along the first direction D1. The plurality of semiconductor patterns 102 are isolated from each other by the first dielectric layer 104, and the top surface of the semiconductor patterns 102 is flush with the top surface of the first dielectric layer 104.

[0029] The substrate material may include elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs), or indium phosphide (InP), etc.), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS), or cadmium telluride (CdTe), etc.), organic semiconductor materials, or other semiconductor materials known in the art. It is understood that since the semiconductor pattern 102 is formed based on the substrate, the material of the semiconductor pattern 102 may be the same as the material of the substrate. For ease of understanding, the following description will use silicon as an example for the semiconductor pattern 102.

[0030] The material of the first dielectric layer 104 includes an insulating material, such as an oxide, and more specifically, the first dielectric layer 104 may include silicon oxide.

[0031] The formation process of the first dielectric layer 104 includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0032] Reference Figure 2 As shown, the semiconductor pattern 102 is etched to remove at least a first portion 106 of the semiconductor pattern 102, forming a bit line trench 110 located between adjacent first dielectric layers 104. The bit line trench 110 extends along the second direction D2 and exposes a portion of the side surface of the first dielectric layer 104.

[0033] Here, the bit line trench 110 is used to define the formation area of ​​the bit line structure. In this embodiment of the present disclosure, the etching depth of the bit line trench 110 can be determined according to actual design requirements, thereby obtaining a bit line structure with the required dimensions.

[0034] The forming process of bit line trench 110 includes, but is not limited to, dry etching, wet etching, or a combination thereof.

[0035] Reference Figure 3 As shown, a doped polysilicon material layer 112 is formed in the bit line trench 110 and on the surface of the first dielectric layer 104, such that the doped polysilicon material layer 112 fills the bit line trench 110.

[0036] The material of the doped polycrystalline silicon material layer 112 includes doped polycrystalline silicon. Furthermore, the doping elements in the doped polycrystalline silicon material layer 112 may include N-type doping elements, such as phosphorus, arsenic, and antimony. The doping elements in the doped polycrystalline silicon material layer 112 may also include P-type doping elements, such as boron, aluminum, gallium, and indium.

[0037] The formation process of the doped polycrystalline silicon material layer 112 includes, but is not limited to, epitaxial growth, CVD, PVD, ALD, or any combination thereof.

[0038] In some embodiments, the polycrystalline silicon in the doped polycrystalline silicon material layer 112 can be induced to transform into monocrystalline silicon using a pulsed laser annealing (PLA) process, thereby forming an initial doped semiconductor layer.

[0039] PLA (Plastic Argumentation) is an advanced rapid thermal annealing technology. It utilizes a high-energy pulsed laser beam (nanosecond to millisecond pulse width) to directly irradiate the wafer surface, which can heat the material on the wafer surface to the melting point or high temperature in a very short time, followed by rapid cooling to achieve non-equilibrium solid-phase or liquid-phase epitaxial recrystallization.

[0040] In this embodiment, a high-energy pulsed laser beam is used to scan and irradiate the surface of the doped polycrystalline silicon material layer 112 with a nanosecond-level pulse width. This causes the doped polycrystalline silicon material layer 112 to absorb light energy and heat up to above its melting point in a very short time, forming a thin liquid phase melting zone. The remaining semiconductor pattern 102 located below the doped polycrystalline silicon material layer 112 is used as a seed crystal. During the rapid cooling process, the molten silicon is epitaxially recrystallized along the original crystal direction, thereby converting the polycrystalline silicon in the doped polycrystalline silicon material layer 112 into high-lattice-quality single-crystal silicon to form the initial doped semiconductor layer.

[0041] Reference Figure 4 As shown, the initial doped semiconductor layer outside the bit line trench 110 is removed, so that the remaining initial doped semiconductor layer within the bit line trench 110 forms a doped semiconductor layer 114. The top surface of the doped semiconductor layer 114 is flush with the top surface of the first dielectric layer 104. The doped semiconductor layer 114 is used to form the bit line structure.

[0042] The removal process of the initial doped semiconductor layer includes, but is not limited to, the CMP process.

[0043] Reference Figure 5 As shown, a portion of the first dielectric layer 104 is removed to form an isolation trench 116 located between adjacent doped semiconductor layers 114 in the first direction D1. The isolation trench 116 exposes the sidewalls of the doped semiconductor layers 114.

[0044] The process for forming the isolation trench 116 includes, but is not limited to, dry etching.

[0045] In some embodiments, after the isolation trench 116 is formed, the doped semiconductor layer 114 can be etched (also known as trimmed) based on the isolation trench 116 to reduce the size of the doped semiconductor layer 114 in the first direction D1, while increasing the distance between adjacent bit line structures in the first direction D1, as shown in the figure. Figure 6 As shown. In this way, the coupling between adjacent bit line structures can be reduced.

[0046] The etching process for the doped semiconductor layer 114 includes, but is not limited to, wet etching.

[0047] Reference Figure 7 As shown, oxynitride layers 118 are formed on the top and side surfaces of the doped semiconductor layer 114.

[0048] In one example, the method for forming the oxynitride layer 118 includes: annealing the substrate with nitrous oxide (N₂O) to introduce nitrogen atoms at the interface between the top surface and the side surface of the doped semiconductor layer 114, thereby forming silicon oxynitride (SiON) (i.e., the oxynitride layer) on the top surface and the side surface of the doped semiconductor layer 114. The oxynitride layer 118 can effectively suppress the diffusion of dopant ions in the doped semiconductor layer 114 to the outside, thereby reducing leakage current. It should be noted that since the material of the oxynitride layer 118 and the material of the first dielectric layer 104 are both insulating materials, therefore Figure 7 The interface between the oxynitride layer 118 and the first dielectric layer 104 is not distinguished.

[0049] Reference Figure 8 and Figure 9 As shown, a barrier material layer 120 is formed within the isolation trench 116 and on the surface of the oxide nitride layer 118, such that the barrier material layer 120 fills the isolation trench 116. Subsequently, the barrier material layer 120 outside the isolation trench 116 is removed using a CMP process, and the oxide nitride layer 118 on the top surface of the doped semiconductor layer 114 is simultaneously removed, so that the remaining barrier material layer 120 within the isolation trench 116 forms a barrier layer 122, while exposing the top surface of the doped semiconductor layer 114. The barrier layer 122 is used to prevent metal elements in the metal layer from diffusing into the first dielectric layer 104 during subsequent bit line contact formation processes.

[0050] The material of the barrier layer 122 includes, but is not limited to, titanium nitride. The process for forming the barrier layer 122 includes, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0051] Reference Figure 10 As shown, a bit line contact 124 extending along the second direction D2 is formed on the top surface of the doped semiconductor layer 114 using a self-aligned silicide process. Here, the bit line contact 124 can be used as a bit line alone or as part of a bit line.

[0052] In some embodiments, the method of forming bit line contact 124 includes: forming a metal layer on the surface of doped semiconductor layer 114, the surface of oxynitride layer 118 and the surface of barrier layer 122; performing an annealing process on the substrate on which the metal layer is formed, so that the metal atoms of the metal layer diffuse into and combine with the silicon atoms of doped semiconductor layer 114 under thermal drive to form a low-resistance stable metal silicide (i.e., bit line contact 124).

[0053] Reference Figure 11 As shown, the barrier layer 122 is removed using a back-etching process to reopen the isolation trench 116 and expose the oxynitride layer 118 located on the side of the doped semiconductor layer 114.

[0054] The process for removing the barrier layer 122 includes, but is not limited to, wet etching.

[0055] Reference Figure 12 As shown, a protective layer 126 is formed covering the surface of the oxynitride layer 118 and the surface of the bit line contact 124. Here, the material of the protective layer 126 includes nitrides or oxides, such as silicon nitride or silicon oxide. The protective layer 126 is used to prevent metal elements in the bit line contact 124 from diffusing into the sacrificial layer after the subsequent formation of the sacrificial layer.

[0056] Reference Figure 13 and Figure 14 As shown, sacrificial material 128 is deposited within the isolation trench 116 and on the surface of the protective layer 126 to fill the isolation trench 116. Subsequently, the sacrificial material 128 outside the isolation trench 116 is removed using a CMP process, leaving the remaining sacrificial material 128 within the isolation trench 116 as the sacrificial layer 130. At this point, the surface of the sacrificial layer 130 is flush with the surface of the protective layer 126 located on top of the doped semiconductor layer 114.

[0057] The sacrificial layer 130 is made of carbon materials. The formation process of the sacrificial layer includes, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0058] Reference Figure 15 As shown, a dielectric material layer 132 is formed on the surfaces of the sacrificial layer 130 and the protective layer 126. In some embodiments, the material of the dielectric material layer 132 includes silicon nitride or silicon carbonitride.

[0059] The formation process of the dielectric material layer 132 includes, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0060] Reference Figure 16 As shown, after forming the dielectric material layer 132, the sacrificial layer 130 is removed using an ashing process to form an air gap 134 extending along the second direction D2 at the removal location of the sacrificial layer 130. Here, the air gap 134 utilizes its low dielectric constant (k approximately equal to 1) close to the theoretical limit to effectively reduce parasitic capacitance and signal crosstalk between adjacent bit line structures, thereby improving sensing margin and data transmission speed.

[0061] However, the above-mentioned schemes have certain drawbacks: First, the energy inhomogeneity of the PLA process can lead to the diffusion of dopants, resulting in bit line leakage. Second, the PLA process cannot form a gradually changing junction with a dopant gradient at the source and bit lines. Third, during the bit line formation process, polysilicon material needs to be deposited in trenches with a large aspect ratio, but deposition processes such as PVD are difficult to achieve high aspect ratio trench filling. Fourth, the top of the bit line structure formed by this scheme is higher than or flush with the top of the isolation structure with an air gap, resulting in poor isolation effect of the isolation structure on the bit lines.

[0062] Based on at least one of the above-mentioned technical problems, this disclosure provides a method for manufacturing a semiconductor structure.

[0063] Figure 17 This is a schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure. It should be noted that... Figure 17 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 17 The steps shown can be rearranged in order according to actual needs. (Refer to...) Figure 17 As shown, the manufacturing method includes at least the following steps: Step S102: Provide a substrate, the substrate including semiconductor patterns and a first dielectric layer arranged alternately along a first direction, wherein the semiconductor pattern includes semiconductor lines extending along a second direction and a plurality of semiconductor pillars arranged at intervals along the second direction and all connected to the first ends of the semiconductor lines, a first trench is formed between adjacent first dielectric layers to expose the second ends of the semiconductor lines, the second ends and the first ends are opposite to each other along a third direction, the second direction and the first direction intersect and are both perpendicular to the third direction; Step S104: A bit line structure is formed in the first trench, wherein the bit line structure includes a bit line and a second dielectric layer, located between the semiconductor line and the second dielectric layer; Step S106: Remove a portion of the first dielectric layer to form a second trench extending along the second direction, wherein the second trench exposes the sidewalls of the semiconductor line and bit line structure; Step S108: Form an isolation structure located at least within the second trench, wherein the isolation structure has an air gap extending along a second direction, the size of the air gap in the third direction being larger than the size of the bit line in the third direction.

[0064] In this embodiment, a second dielectric layer is formed on the bit lines, and then an isolation structure is formed between adjacent bit lines and between adjacent second dielectric layers. Because the isolation structure has an air gap extending along a second direction, and the size of the air gap in the third direction is larger than the size of the bit lines in the third direction, the top of the air gap is higher than the top of the bit lines, thereby achieving a better isolation effect on the bit lines.

[0065] Figures 18 to 29 This is a schematic diagram of a semiconductor structure manufacturing process provided in an embodiment of this disclosure. Figures 18 to 29 These are all three-dimensional structural diagrams of semiconductor structures during the manufacturing process. The following will combine... Figure 17 , Figures 18 to 29 An exemplary method for manufacturing a semiconductor structure is described in accordance with embodiments of this disclosure.

[0066] Reference Figure 20 As shown, step S102 is performed: a substrate is provided, the substrate including a semiconductor pattern 202 and a first dielectric layer 204 arranged alternately along a first direction, wherein the semiconductor pattern 202 includes semiconductor lines 206 extending along a second direction D2 and a plurality of semiconductor pillars 208 arranged at intervals along the second direction D2 and all connected to the first ends of the semiconductor lines 206, a first trench 210 is formed between adjacent first dielectric layers 204 to expose the second ends of the semiconductor lines 206, the second ends and the first ends are opposite each other along a third direction D3, the second direction D2 and the first direction D1 intersect and are both perpendicular to the third direction D3.

[0067] Figures 18 to 20 To form a process step diagram for the substrate, it can be based on Figure 20 The substrate in the process performs subsequent process steps. The following section combines... Figures 18 to 20 The formation process of the substrate is explained in detail.

[0068] Reference Figure 18 As shown, an initial substrate is provided, comprising an initial semiconductor pattern 212 and a first dielectric layer 204 alternately arranged along a first direction D1. The initial semiconductor pattern 212 includes a first portion 214 extending along a second direction D2 and second portions 216 spaced apart along the second direction D2 and connected to the first ends of the first portion 214. The surface of the second end of the first portion 214 is flush with the surface of the first dielectric layer 204. The second end and the first end are opposite each other along a third direction D3. The second direction D2 intersects the first direction D1 and is perpendicular to the third direction D3.

[0069] Here, the second part 216 can be the semiconductor pillar 208 or a portion thereof. The initial semiconductor pattern 212 and the first dielectric layer 204 in the initial substrate can be referred to the above description respectively. Figure 1The relevant descriptions of the semiconductor pattern 102 and the first dielectric layer 104 in the substrate will not be repeated here.

[0070] Reference Figure 19 As shown, the initial semiconductor pattern 212 is etched to remove at least a first portion 214 of the initial semiconductor pattern 212 and form a first trench 210 located between adjacent first dielectric layers 204. The first trench 210 extends along a second direction D2 and exposes a portion of the sidewalls of the first dielectric layer 204. The first trench 210 is used to define the formation region of the bit line structure.

[0071] Here, removing at least the first portion 214 of the initial semiconductor pattern 212 means removing the first portion 214 of the initial semiconductor pattern 212, or removing the first portion 214 of the initial semiconductor pattern 212 and a portion of the semiconductor pillars 208.

[0072] The process for forming the first trench 210 includes, but is not limited to, dry etching.

[0073] Reference Figure 20 As shown, using an epitaxial process, a semiconductor line 206 extending along a second direction D2 is formed within the first trench 210 based on the bottom surface of the first trench 210. The semiconductor line 206 has a first end and a second end opposite to each other along a third direction D3, wherein the first end of the semiconductor line 206 is connected to a plurality of semiconductor pillars 208 spaced apart along the second direction D2.

[0074] Here, the material of semiconductor line 206 includes doped single-crystal silicon. The doping elements in semiconductor line 206 may include N-type doping elements, such as phosphorus, arsenic, and antimony. The doping elements in semiconductor line 206 may also include P-type doping elements, such as boron, aluminum, gallium, and indium.

[0075] In some embodiments, during the process of forming the semiconductor line 206, the flow rate of the dopant gas can be changed in real time to continuously control the doping concentration during epitaxial growth, thereby obtaining a semiconductor line 206 with a doping concentration gradient. For example, by controlling the doping concentration during epitaxial growth, the elemental doping concentration of the semiconductor line 206 in the region far from the semiconductor pillar 208 is higher than that in the region near the semiconductor pillar 208, thereby achieving the technical effect of reducing series resistance and improving device performance.

[0076] Reference Figure 20 As shown, it is important to emphasize that the epitaxially formed semiconductor line 206 does not completely fill the first trench 210, but only fills a portion of it. Therefore, some areas within the first trench 210 remain unfilled.

[0077] refer to Figure 18As shown, in some embodiments, the size of the first portion 214 of the initial semiconductor pattern 212 in the first direction D1 is smaller than the size of the second portion 216 of the initial semiconductor pattern 212 in the first direction D1. Thus, after removing the first portion 214 of the initial semiconductor pattern 212 and a portion of the semiconductor pillar 208, a first trench 210 with a structure narrower at the top and wider at the bottom is formed. Furthermore, the semiconductor line 206 formed within the first trench 210 also has a structure narrower at the top and wider at the bottom that matches the first trench 210. In other words, the size of the semiconductor line 206 in the first direction D1 is larger than the size of the semiconductor line 206 in the first direction D1 at a position away from the semiconductor pillar 208.

[0078] In this embodiment, the semiconductor line 206 within the first trench 210 is formed using an epitaxial process instead of a PLA process, avoiding bit line leakage caused by the uneven energy distribution of the PLA process. Furthermore, the epitaxial growth process utilizes multidirectional vapor-phase reactions to achieve excellent step coverage and void-free trench filling capabilities, enabling the formation of high-quality single-crystal silicon (i.e., semiconductor line 206) within the first trench 210 with a high aspect ratio. Simultaneously, precise control of in-situ doping allows for the formation of a gradually changing junction with varying dopant element gradients at the source and bit lines, thereby reducing series resistance.

[0079] Reference Figure 23 As shown, step S104 is performed: a bit line structure 218 is formed in the first trench 210, wherein the bit line structure 218 includes a bit line 220 and a second dielectric layer 222, and the bit line 220 is located between the semiconductor line 206 and the second dielectric layer 222.

[0080] In some embodiments, step S104 above includes: Step S402: Form bit line 220 on semiconductor line 206; Step S404: Form a second dielectric layer 222 on bit line 220.

[0081] Figures 21 to 23 To illustrate the process steps for forming bitline structure 218, see the diagram below. Figures 21 to 23 The formation process of bit line structure 218 is explained in detail.

[0082] Reference Figure 21 As shown, step S402 is performed: bit line 220 is formed on semiconductor line 206.

[0083] For example, using a self-aligned silicide process, a bit line 220 extending in the second direction D2 is formed above a semiconductor line 206 within a first trench 210.

[0084] In one example, the self-aligned silicide process for forming bit line 220 specifically includes: forming a metal layer on the surface of semiconductor line 206 and first dielectric layer 204. Here, the material of the metal layer includes, but is not limited to, nickel, cobalt, platinum, titanium, tungsten, molybdenum, etc. The metal layer formation process includes, but is not limited to, PVD, CVD, ALD, or any combination thereof. After forming the metal layer, an annealing process is performed on the substrate with the metal layer to react the metal layer with semiconductor line 206, thereby generating bit line 220 extending along the second direction D2 on top of semiconductor line 206. Here, bit line 220 is formed through a solid-phase diffusion reaction between semiconductor line 206 and metal layer. Specifically, an annealing process is performed on the substrate with the metal layer to allow metal atoms in the metal layer to diffuse into and combine with silicon atoms in semiconductor line 206 under thermal drive, forming a low-resistivity stable metal silicide (i.e., bit line 220). After forming bit line 220, the unreacted metal layer is removed to expose the surface of bit line 220.

[0085] Reference Figure 22 and Figure 23 As shown, after bit line 220 is formed, step S404 is performed: a second dielectric layer 222 is formed on bit line 220.

[0086] For example, refer to Figure 22 As shown, a second dielectric material layer 224 is formed on the surface of bit line 220 and the first dielectric layer 204 to fill the first trench 210. Then, the second dielectric material layer 224 outside the first trench 210 is removed, so that the remaining second dielectric material layer 224 within the first trench 210 is formed as the second dielectric layer 222. (Refer to...) Figure 23 As shown. At this time, the top of the second dielectric layer 222 is flush with the top of the first dielectric layer 204. The second dielectric layer 222 and the bit line 220 together form the bit line structure 218.

[0087] The process for forming the second dielectric material layer 224 includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0088] The removal process of the second dielectric material layer 224 includes, but is not limited to, etching processes.

[0089] Reference Figure 24 As shown, step S106 is performed: a portion of the first dielectric layer 204 is removed to form a second trench 226 extending along the second direction D2, wherein the second trench 226 exposes the sidewalls of the semiconductor line 206 and the bit line structure 218.

[0090] In some embodiments, the process for forming the second trench 226 includes, but is not limited to, dry etching.

[0091] Reference Figure 29As shown, step S108 is performed: forming an isolation structure 228 located at least within the second trench 226, wherein the isolation structure 228 has an air gap 230 extending along the second direction D2, and the size of the air gap 230 in the third direction D3 is greater than the size of the bit line 220 in the third direction D3.

[0092] In some embodiments, step S108 above includes: Step S802: Form a third dielectric layer 232 covering the inner wall of the second trench 226 and the surface of the second dielectric layer 222; Step S804: A sacrificial layer 234 is formed on the third dielectric layer 232 located in the second trench 226 to fill the second trench 226; Step S806: Form a fourth dielectric layer 236 covering the surface of the third dielectric layer 232 covering the surface of the sacrificial layer 234 and the second dielectric layer 222; Step S808: Remove the sacrificial layer 234 to form an air gap 230 at the location where the sacrificial layer 234 was removed.

[0093] Figures 25 to 29 The process steps for forming the isolation structure 228 are shown below. Figures 25 to 29 The formation process of the isolation structure 228 is explained in detail.

[0094] Reference Figure 25 As shown, step S802 is performed: a third dielectric layer 232 is formed covering the inner wall of the second trench 226 and the surface of the second dielectric layer 222.

[0095] Here, at least a portion of the third dielectric layer 232 covers the sidewall of the bit line 220 to prevent metal elements in the bit line 220 from diffusing into the sacrificial layer 234 after the sacrificial layer 234 is subsequently formed, thus preventing the sacrificial layer 234 from becoming contaminated.

[0096] The material of the third dielectric layer 232 includes oxides, such as silicon oxide.

[0097] The process for forming the third dielectric layer 232 includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0098] Reference Figure 27 As shown, step S804 is performed: a sacrificial layer 234 is formed on the third dielectric layer 232 located in the second trench 226 to fill the second trench 226.

[0099] Figures 26 to 27 The process steps for forming sacrificial layer 234 are shown below. Figures 26 to 27 The formation process of the sacrificial layer 234 is explained in detail.

[0100] Reference Figure 26As shown, sacrificial material 235 is deposited in the second trench 226 and on the surface of the third dielectric layer 232 located on top of the second dielectric layer 222, so that the sacrificial material 235 fills the second trench 226.

[0101] The deposition process of sacrificial material 235 includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0102] Reference Figure 27 As shown, the sacrificial material 235 located outside the second trench 226 is removed so that the remaining sacrificial material 235 located inside the second trench 226 becomes the sacrificial layer 234, while exposing the surface of the third dielectric layer 232 located on top of the second dielectric layer 222.

[0103] The removal process of sacrificial material 235 includes, but is not limited to, the re-etching process.

[0104] In some embodiments, the material of the sacrificial layer 234 includes a carbon material.

[0105] In a specific example, a spin-on hard mask (SOH) can be used as the material for the sacrificial layer 234. Here, the specific materials for SOH mainly fall into two categories: carbon-rich spin-on organic polymers (C-SOH / SOC) and modified silicon-containing polymers (Si-SOH). The former includes aromatic polycyclic polymers (naphthalene, anthracene derivatives) and amorphous carbon-based materials with a carbon content >90%, which can be thermally decomposed at temperatures between 300°C and 400°C or completely removed via oxygen plasma ashing. The latter includes modified variants of methylsilsesquioxane (MSQ) and hydrosilsesquioxane (HSQ), which can also be removed by thermal decomposition or plasma ashing. Both types of materials possess excellent high aspect ratio gap-filling capabilities and clean, residue-free removal characteristics, making them suitable as sacrificial layers for forming air gaps.

[0106] Reference Figure 28 As shown, step S806 is performed: a fourth dielectric layer 236 is formed covering the surface of the third dielectric layer 232 over the sacrificial layer 234 and the second dielectric layer 222. Here, since both the material of the fourth dielectric layer 236 and the material of the third dielectric layer 232 are insulating materials, no distinction is made between their interface.

[0107] The material of the fourth dielectric layer 236 includes, but is not limited to, at least one of silicon nitride (SiN / Si3N4), silicon carbonitride (SiCN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbonate (SiOC), and silicon oxycarbonate (SiOCN).

[0108] The process for forming the fourth dielectric layer 236 includes, but is not limited to, PVD, CVD, ALD, or any combination thereof.

[0109] Reference Figure 29 As shown, step S808 is performed: the sacrificial layer 234 is removed to form an air gap 230 at the location where the sacrificial layer 234 is removed.

[0110] In some embodiments, the process of removing the sacrificial layer 234 includes an ashing process.

[0111] In this embodiment of the disclosure, when the material of the sacrificial layer 234 is carbon material, the sacrificial layer 234 can be removed by an ashing process. The ashing process can remove the sacrificial layer 234 with a high selectivity and without residual damage, which is conducive to forming a high-quality air gap 230.

[0112] In some embodiments, there is a height difference H between the surface of the isolation structure 228 facing away from the first dielectric layer 204 and the surface of the bit line 220 facing away from the semiconductor line 206, wherein the height difference H is greater than 0. That is, the surface of the isolation structure 228 facing away from the first dielectric layer 204 is higher than the surface of the bit line 220 facing away from the semiconductor line 206, such as... Figure 29 As shown.

[0113] In one specific embodiment, the top of the air gap 230 is higher than the top of the bit line 220. That is, the air gap 230 is located not only between adjacent bit lines 220 in the second direction D2, but also between adjacent second dielectric layers 222 in the second direction D2. Thus, compared to the above... Figures 1 to 16 The isolation structure 228 in the present embodiment can achieve better isolation of adjacent bit lines 220.

[0114] Based on a concept similar to the manufacturing method described above, this disclosure provides a semiconductor structure.

[0115] Reference Figure 30 As shown, Figure 30This is a three-dimensional structural diagram of a semiconductor structure provided in an embodiment of the present disclosure. The semiconductor structure includes: a plurality of semiconductor patterns 202, a first dielectric layer 204, a bit line structure 218, and an isolation structure 228. The plurality of semiconductor patterns 202 are arranged at intervals along a first direction D1. Each semiconductor pattern 202 includes semiconductor lines 206 extending along a second direction D2 and a plurality of semiconductor pillars 208 arranged at intervals along the second direction D2 and each connected to a first end of a semiconductor line 206. The first dielectric layer 204 is located between adjacent semiconductor pillars 208 in the first direction D1. The bit line structure 218 extends along the second direction D2 and connects to the second end of a semiconductor line 206. The bit line structure 218 includes bit lines 220 and a second dielectric layer 222. 220 is located between semiconductor line 206 and second dielectric layer 222, with the second end and the first end facing each other along the third direction D3, the second direction D2 and the first direction D1 intersecting and both perpendicular to the third direction D3; the isolation structure 228 is located at least between adjacent bit line structures 218 on the first direction D1 and between adjacent semiconductor lines 206 on the first direction D1, wherein the isolation structure 228 has an air gap 230 extending along the second direction D2, and the size of the air gap 230 on the third direction D3 is larger than the size of the bit line 220 on the third direction D3.

[0116] Here, the isolation structure 228 being located at least between adjacent bit line structures 218 and adjacent semiconductor lines 206 in the first direction D1 means that the isolation structure 228 is not only located between adjacent bit line structures 218 and adjacent semiconductor lines 206 in the first direction D1, but also located at other positions in the semiconductor structure.

[0117] In some embodiments, the isolation structure 228 further includes a third dielectric layer 232, which covers the sidewalls of the semiconductor line 206, the sidewalls of the bit line structure 218, the surface away from the semiconductor line 206, and the surface of the first dielectric layer 204 near the air gap 230. It is understood that, since the third dielectric layer 232 is part of the isolation structure 228, the isolation structure 228 is also located on the surface of the second dielectric layer 222 on the side away from the bit line.

[0118] The semiconductor pattern 202, the first dielectric layer 204, the bit line structure 218, and the isolation structure 228 can be referred to the relevant descriptions of the semiconductor pattern 202, the first dielectric layer 204, the bit line structure 218, and the isolation structure 228 in the above method embodiments, and will not be repeated here.

[0119] In this embodiment, a second dielectric layer 222 is provided on the bit line 220, and an isolation structure 228 is provided between adjacent bit line structures 218 and between adjacent semiconductor lines 206 in the first direction D1. Since the isolation structure 228 has an air gap 230 extending along the second direction D2, and the size of the air gap 230 in the third direction D3 is larger than the size of the bit line 220 in the third direction D3, the top of the air gap 230 is higher than the top of the bit line 220, thereby achieving a better isolation effect for the bit line 220.

[0120] In some embodiments, the semiconductor structure further includes a fourth dielectric layer 236, which covers the air gap 230 and the surface of the third dielectric layer 232 on the bit line structure 218. The description of the fourth dielectric layer 236 in the above method embodiments is provided and will not be repeated here.

[0121] The semiconductor structure provided in this disclosure can constitute part or all of a chip. The chip can be various functional chips known in the art, such as memory chips, logic chips, interface chips, power chips, artificial intelligence chips, computing chips, and sensor chips.

[0122] In this embodiment of the disclosure, the semiconductor structure can be manufactured using the manufacturing method in any of the above embodiments. The technical effects that can be achieved by the manufacturing methods in the foregoing embodiments can also be achieved by the semiconductor structure shown in this embodiment of the disclosure, and will not be repeated here.

[0123] Based on a concept similar to the semiconductor structure described above, this disclosure provides an electronic device.

[0124] Figure 31 This is a schematic block diagram of an electronic device 300 provided in an embodiment of this disclosure. (Refer to...) Figure 31 As shown, the electronic device includes a processor 302 and a memory 304 electrically connected to the processor 302; the memory 304 includes the semiconductor structure in any of the above embodiments.

[0125] Electronic device 300 can be a terminal or other devices besides a terminal. For example, electronic device 300 may include mobile phones, tablets, laptops, handheld computers, in-vehicle electronic devices, mobile internet devices (MIDs), augmented reality (AR) / virtual reality (VR) devices, robots, wearable devices, ultra-mobile personal computers (UMPCs), netbooks, or personal digital assistants (PDAs), etc. It can also be servers, network attached storage (NAS), personal computers (PCs), televisions (TVs), ATMs, or self-service machines, etc.

[0126] Processor 302 typically controls the overall operation of an electronic device. As an example, processor 302 may include a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0127] The memory 304 is configured to store instructions and applications executable by the processor 302, and may also cache data to be processed or already processed (e.g., image data, audio data, voice communication data, and video communication data) in the processor 302 and various modules in the electronic device 300. Data can be transferred between the memory 304 and the processor 302 via a bus. As an example, the memory 304 may include DRAM, dual data rate synchronous dynamic random access memory (DDR), DDR2, DDR3, DDR4, DDR5, LPDDR, GDDR, flash memory, static random-access memory (SRAM), etc.

[0128] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0129] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a semiconductor pattern and a first dielectric layer alternately arranged along a first direction, wherein the semiconductor pattern comprises semiconductor lines extending along a second direction and a plurality of semiconductor pillars spaced apart along the second direction and each connected to a first end of the semiconductor lines, a first trench is formed between adjacent first dielectric layers to expose a second end of the semiconductor lines, the second end and the first end are opposite to each other along a third direction, the second direction and the first direction intersect and are both perpendicular to the third direction; A bit line structure is formed in the first trench, wherein the bit line structure includes a bit line and a second dielectric layer, and the bit line is located between the semiconductor line and the second dielectric layer; A portion of the first dielectric layer is removed to form a second trench extending along the second direction, wherein the second trench exposes the sidewalls of the semiconductor line and the bit line structure; An isolation structure is formed at least within the second trench, wherein the isolation structure has an air gap extending along the second direction, the size of the air gap in the third direction being larger than the size of the bit line in the third direction.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The formation of the isolation structure at least within the second trench includes: A third dielectric layer is formed that covers the inner wall of the second trench and the surface of the second dielectric layer; A sacrificial layer is formed on the third dielectric layer located within the second trench to fill the second trench; A fourth dielectric layer is formed that covers the surface of the third dielectric layer and the surface of the sacrificial layer and the second dielectric layer; The sacrificial layer is removed to form the air gap at the location where the sacrificial layer was removed.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The process for removing the sacrificial layer includes an ashing process.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The material of the sacrificial layer includes carbon materials.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The step of forming a bitline structure in the first trench includes: The bit line is formed on the semiconductor line; The second dielectric layer is formed on the bit line.

6. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, There is a height difference between the surface of the isolation structure away from the first dielectric layer and the surface of the bit line away from the semiconductor line, wherein the height difference is greater than 0.

7. A semiconductor structure, obtained by the manufacturing method of the semiconductor structure according to any one of claims 1 to 6, characterized in that, include: Multiple semiconductor patterns are arranged at intervals along a first direction, wherein each semiconductor pattern includes semiconductor lines extending along a second direction and multiple semiconductor pillars arranged at intervals along the second direction and each connected to a first end of the semiconductor lines. A first dielectric layer is located between adjacent semiconductor pillars in the first direction; Bit line structure, the bit line structure extends along the second direction and connects to the second end of the semiconductor line, wherein the bit line structure includes a bit line and a second dielectric layer, the bit line is located between the semiconductor line and the second dielectric layer, the second end and the first end are opposite each other along a third direction, the second direction and the first direction intersect and are both perpendicular to the third direction; An isolation structure is located at least between adjacent bit line structures and between adjacent semiconductor lines in the first direction, wherein the isolation structure has an air gap extending in the second direction, the size of the air gap in the third direction being larger than the size of the bit line in the third direction.

8. The semiconductor structure according to claim 7, characterized in that, The isolation structure also includes: A third dielectric layer covers the sidewalls of the semiconductor line, the sidewalls of the bit line structure, the surface away from the semiconductor line, and the surface of the first dielectric layer near the air gap.

9. The semiconductor structure according to claim 8, characterized in that, The semiconductor structure also includes: A fourth dielectric layer, which covers the air gap and the surface of the bit line structure of the third dielectric layer.

10. An electronic device, characterized in that, include: processor; as well as A memory electrically connected to the processor, the memory comprising the semiconductor structure of any one of claims 7 to 9.

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