A semiconductor device and a method of fabricating the same

Abstract

The application belongs to the technical field of semiconductor manufacturing, and provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a shielding gate, a gate, a body region, an injection region and a deep buried layer. The epitaxial layer is located on the front surface of the substrate. A plurality of grooves are arranged in the epitaxial layer. The shielding gate and the gate are arranged at intervals and located in the grooves. The body region is located on the side of the epitaxial layer away from the substrate. The injection region is located on the side of the body region away from the epitaxial layer. The deep buried layer is located in the epitaxial layer and on the opposite sides of the grooves along a first direction. By introducing the deep buried layer, a depleted electric field shielding layer can be formed on both sides below the grooves, thereby avoiding the concentration of the electric field in the weak areas such as the bottom of the grooves, reducing the peak electric field around the shielding gate, making the electric field distribution in the device more uniform, and improving the breakdown voltage of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Power semiconductor devices are core components used in power conversion and control circuits. In the field of power semiconductors, trench MOSFETs have become the mainstream choice for medium and low voltage applications due to their advantages such as high cell density and low on-resistance (Rdson). To further optimize device performance, shielded gate trench (SGT) technology has emerged. SGT MOSFETs introduce a shielded gate connected to the source below the traditional trench gate. This structure can effectively shield the strong electric field below the gate when the device is turned off, thereby significantly improving the device's breakdown voltage (BV) and reducing the gate drain charge (Qgd), thus improving switching characteristics.

[0003] As application systems place increasingly stringent demands on power density, efficiency, and reliability, existing SGT MOSFET technology still faces numerous challenges. One of these is the optimization of charge balance and electric field distribution: in high-voltage applications, how to optimize the charge balance between the shield gate and the trench sidewalls to achieve a more ideal lateral and longitudinal electric field distribution, thereby reducing on-resistance and improving avalanche withstand capability while ensuring high breakdown voltage. However, in traditional SGT MOSFET structures, the electric field is highly concentrated at the bottom of the trench when subjected to high voltage, which can easily lead to premature breakdown and other problems, reducing the device's operational reliability and lifespan.

[0004] Therefore, the present invention aims to provide an improved SGT MOSFET device structure to alleviate the electric field distribution problem existing in the prior art, so as to meet the needs of next-generation high-efficiency, high-density power conversion systems. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a semiconductor device and its fabrication method, which can effectively improve the electric field distribution problem of the existing SGT MOSFET device and meet the needs of the next generation of high-efficiency, high-density power conversion systems.

[0006] To achieve the above and other related objectives, this application provides a semiconductor device, comprising:

[0007] A substrate has a front side and a back side disposed opposite to each other, and a first direction and a second direction are defined, wherein the first direction is parallel to the front side of the substrate and perpendicular to the second direction, and the second direction is perpendicular to the front side of the substrate.

[0008] An epitaxial layer of a first conductivity type is formed on the front side of the substrate, and a plurality of trenches are provided in the epitaxial layer;

[0009] A shielding gate and a gate are located within the trench, with the gate spaced apart on the side of the shielding gate away from the substrate;

[0010] A body region of the second conductivity type is formed on the side of the epitaxial layer away from the substrate;

[0011] An implantation region of the first conductivity type is formed on the side of the body region away from the epitaxial layer and covers a portion of the surface of the body region;

[0012] The second type of conductive buried layer is located within the epitaxial layer and is situated on opposite sides of the trench along the first direction.

[0013] Optionally, the distance between the surface of the buried layer away from the substrate and the substrate is less than the distance between the shielding gate and the substrate, and the distance between the buried layer and the substrate is not less than 1 μm.

[0014] Optionally, the deep buried layer includes M buried layers, denoted as the 1st to the Mth buried layers, which are distributed sequentially at intervals along the second direction and gradually move away from the substrate, where M is a positive integer.

[0015] Optionally, the first to M buried layers are formed by ion implantation. When M is 1, the implantation energy and implantation dose of the first buried layer are greater than or equal to the implantation energy and implantation dose of the first buried layer when M is greater than 1. And when M is greater than 1, the implantation energy and implantation dose of the first buried layer are greater than or equal to the implantation energy and implantation dose of the second to M buried layers.

[0016] Optionally, when M is 1, the first buried layer is formed by boron ion implantation, with an implantation energy of 40 keV to 60 keV and an implantation dose of 1E13cm. -2 ~5E13cm -2 ;

[0017] When M is 3, the first to M buried layers are all formed by B ion implantation. The implantation energy of the first buried layer is 30 keV to 45 keV, and the implantation dose is 7E12cm. -2 ~2E13cm -2 The injection energy for the second to M buried layers was 20 keV to 35 keV, and the injection dose was 5E12cm. -2 ~1E13cm -2 .

[0018] Optionally, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked together, the first epitaxial layer being located between the second epitaxial layer and the substrate, and the buried layer being located within the first epitaxial layer;

[0019] Wherein, the thickness of the first epitaxial layer is greater than the distance between the shielding gate and the substrate, and the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer.

[0020] Optionally, the doping concentration of the first epitaxial layer is 1E16cm. -3 ~8E16cm -3 The doping concentration of the second epitaxial layer is 7E15cm. -3 ~2.5E16cm -3 .

[0021] Optionally, the deep buried layer includes M buried layers, denoted as the 1st to the Mth buried layers, which are distributed sequentially at intervals along the second direction and gradually move away from the substrate, where M is a positive integer;

[0022] When M is 1, the thickness of the first epitaxial layer is 5um to 8.5um, the thickness of the second epitaxial layer is 4um to 7.5um, the depth of the trench is 7um to 12um, the width of the first buried layer along the first direction is 0.4um to 0.7um, and the thickness of the first buried layer is 0.5um to 0.8um.

[0023] When M is 3, the thickness of the first epitaxial layer is 5um-8.5um, the thickness of the second epitaxial layer is 4um-7.5um, the depth of the trench is 7um-12um, the width of the first to M buried layers along the first direction is 0.4um-0.7um, the thickness of the first to M buried layers is 0.3um-0.5um, the surface of the i-th buried layer away from the substrate is denoted as the upper surface of the i-th buried layer, and the distance between the upper surface of the i-th buried layer and the upper surface of the (i+1)-th buried layer is 0.9um-1.1um, where i is a positive integer less than M.

[0024] Optionally, the semiconductor device further includes:

[0025] A dielectric layer is located on the side of the injection region away from the body region and fills the trench;

[0026] A drain metal layer is formed on the back side of the substrate;

[0027] A source metal layer is formed on the side of the dielectric layer away from the substrate and contacts the body region and the implantation region. The source metal layer is spaced apart from the gate through the dielectric layer.

[0028] On the other hand, this application also provides a method for fabricating a semiconductor device, used to fabricate any of the semiconductor devices described in the foregoing embodiments, comprising the following steps:

[0029] Provide a substrate;

[0030] A first epitaxial material layer is formed on the front side of the substrate, and a buried layer is formed in the first epitaxial material layer;

[0031] A second epitaxial material layer is formed on the first epitaxial material layer, and the first epitaxial material layer and the second epitaxial material layer constitute an epitaxial layer, wherein the doping concentration of the first epitaxial material layer is greater than that of the second epitaxial material layer;

[0032] A trench is formed that penetrates the second epitaxial material layer but does not penetrate the first epitaxial material layer;

[0033] A first to third insulating material layer, a shielding gate, and a gate are formed in the trench. The first insulating material layer is located between the shielding gate and the epitaxial layer, the second insulating layer is located between the shielding gate and the gate, and the third insulating layer is located between the gate and the epitaxial layer.

[0034] A body region and an injection region are sequentially formed on the surface of the second epitaxial material layer, wherein the injection region covers a portion of the surface of the body region;

[0035] A fourth insulating material layer is formed covering the injection region and the gate.

[0036] As described above, compared with the prior art, the semiconductor device and its fabrication method provided in this application have at least the following beneficial effects:

[0037] In the semiconductor device of this application, a buried layer is provided in the epitaxial layer. The buried layer is located on both sides of the trench along the first direction. By introducing the buried layer, a depleted electric field shielding layer can be formed on both sides below the trench, which can play the role of modulating and flattening the electric field. This avoids the electric field from concentrating in weak areas such as the bottom of the trench, reduces the peak electric field around the shielding gate, makes the electric field distribution inside the device more uniform, and improves the breakdown voltage of the device. Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 and Figure 2 The diagrams shown are schematic diagrams of two different semiconductor devices provided in Embodiment 1 of this application.

[0040] Figure 3 The diagram shown is a flowchart illustrating a method for fabricating a semiconductor device according to Embodiment 2 of this application.

[0041] Figure 4 and Figure 5 The diagrams show the structures of the first epitaxial material layer and the deep buried layer formed when M is 1 and 3 respectively in the preparation method provided in Embodiment 2 of this application.

[0042] Figure 6 and Figure 7 The images show schematic diagrams of the formation of the second epitaxial material layer when M is 1 and 3 respectively in the preparation method provided in Embodiment 2 of this application.

[0043] Figure 8 and Figure 9 The images show schematic diagrams of the grooves formed when M is 1 and 3 respectively in the preparation method provided in Embodiment 2 of this application.

[0044] Figure 10 and Figure 11 The diagrams shown are schematic diagrams of the shielding gate and the gate formed when M is 1 and 3 respectively in the preparation method provided in Embodiment 2 of this application.

[0045] Figure 12 and Figure 13 The diagrams show the structural schematics of the formed body region and the injected region when M is 1 and 3 respectively in the preparation method provided in Embodiment 2 of this application.

[0046] Figure 14 and Figure 15 The diagrams shown are schematic diagrams of the formation of the fourth insulating material layer when M is 1 and 3 respectively in the preparation method provided in Embodiment 2 of this application.

[0047] Illustration of reference numerals in the attached diagram:

[0048] 11. Substrate; 12. Epitaxial layer; 121. First epitaxial layer; 122. Second epitaxial layer; 123. Trench; 13. Shielding gate; 141. Gate; 142. Source metal layer; 143. Drain metal layer; 15. Dielectric layer; 16. Body region; 17. Implantation region; 18. Buried layer; 181. First buried layer; 182. Second buried layer; 183. Third buried layer; 221. First epitaxial material layer; 222. Second epitaxial material layer; 251. First insulating material layer; 252. Second insulating material layer; 253. Third insulating material layer; 254. Fourth insulating material layer. Detailed Implementation

[0049] To make the technical objectives, technical solutions, and technical effects of this application clearer, the technical solutions in this application will be clearly and completely described below in conjunction with embodiments. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0050] Therefore, the following detailed description of embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0051] In the description of this application, it should be noted that the terms "center", "longitudinal", "lateral", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0052] In the description of this application, the terms "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0053] Example 1

[0054] To further optimize the internal electric field distribution of traditional SGT MOSFET devices, this embodiment provides a semiconductor device, referring to... Figure 1 and Figure 2 The semiconductor device includes at least a substrate 11, an epitaxial layer 12, a shielding gate 13, a gate 141, a body region 16, an implantation region 17, and a buried layer 18.

[0055] The substrate 11 has a front side and a back side disposed opposite to each other. In this embodiment, the direction perpendicular to the front side of the substrate 11 is defined as the second direction, and the direction parallel to the front side of the substrate 11 and perpendicular to the second direction is defined as the first direction. The epitaxial layer 12 is of the first conductivity type and is formed on the front side of the substrate 11. A plurality of trenches 123 are formed in the epitaxial layer 12. The shielding gate 13 and the gate 141 are located in the trenches 123, wherein the gate 141 is spaced apart on the side of the shielding gate 13 away from the substrate 11. The body region 16 is of the second conductivity type and is formed on the side of the epitaxial layer 12 away from the substrate 11. The implantation region 17 is of the first conductivity type and is formed on the side of the body region 16 away from the epitaxial layer 12, and covers part of the surface of the body region 16. The buried layer 18 is of the second conductivity type, located in the epitaxial layer 12, and is located on both sides opposite to the trenches 123 along the first direction.

[0056] In this embodiment, the first conductivity type and the second conductivity type are opposite conductivity types. For example, the first conductivity type is N-type and the second conductivity type is P-type, or the second conductivity type is N-type and the first conductivity type is P-type. In this embodiment, N-type first conductivity type and P-type second conductivity type are used as examples.

[0057] The semiconductor device of this embodiment forms a depleted electric field shielding layer on both sides below the trench 123 by providing a buried layer 18 on both sides of the bottom of the epitaxial layer 12. This has the function of modulating and flattening the electric field, thereby avoiding the electric field from concentrating in weak areas such as the bottom of the trench 123, reducing the peak electric field around the shielding gate 13, improving the electric field distribution inside the device, and improving the withstand voltage performance of the device.

[0058] In this embodiment, the buried layer 18 is located between the shielding gate 13 and the substrate 11 along the second direction. That is, the distance between the surface of the buried layer 18 away from the substrate 11 and the substrate 11 is less than the distance between the shielding gate 13 and the substrate 11. Optionally, the distance between the buried layer 18 and the adjacent shielding gate 13 along the second direction is not less than a preset interval distance, which is used to reduce the obstruction to the flow of electrons when the device is turned on, while ensuring the electric field modulation effect of the buried layer 18 on the area around the shielding gate 13. The value of the preset interval distance can be set according to the overall size of the device.

[0059] In this embodiment, the distance between the buried layer 18 and the substrate 11 is not less than 1 μm, which is used to prevent the buried layer 18 from getting too close to the substrate 11, which would cause the electric field shielding area formed when the device is biased to easily penetrate the substrate 11, resulting in a decrease in withstand voltage performance.

[0060] In this embodiment, the deep buried layer 18 includes M buried layers, which are respectively denoted as the 1st to the Mth buried layers. The 1st to the Mth buried layers are distributed sequentially at intervals along the second direction and gradually move away from the substrate 11, where M is a positive integer.

[0061] The first to Mth buried layers can be formed by ion implantation or other suitable processes, where M can be, for example, 1. Figure 1 As shown, the deep buried layer 18 includes the first buried layer 181; or the value of M can also be 2 (not shown); or the value of M can also be 3, see reference. Figure 2 As shown, the buried layer 18 includes a first buried layer 181, a second buried layer 182, and a third buried layer 183; or the value of M can be other suitable values. By setting multiple buried layers, the device manufacturing process can be made compatible with existing processes without the need for additional special equipment. Furthermore, the multi-layered buried layer 18 can increase the area of ​​the electric field shielding region formed by the buried layer 18, thereby improving the optimization effect on the internal electric field of the device.

[0062] In an optional embodiment, the first to M buried layers are formed by ion implantation. When M is 1, the implantation energy and dose of the first buried layer 181 are greater than or equal to the implantation energy and dose of the first buried layer 181 when M is greater than 1. When M is 1, a larger ion implantation energy and dose help enhance the optimization effect of the buried layer 18 on the internal electric field of the device. When M is greater than 1, a smaller ion implantation energy and dose can be used to ensure the optimization effect of the buried layer 18 on the electric field while taking into account existing process equipment and saving device production costs.

[0063] In an optional embodiment, the first to M buried layers are formed by ion implantation, where M is greater than 1. The implantation energy and dose of the first buried layer 181 are greater than or equal to the implantation energy and dose of the second to M buried layers. Furthermore, the implantation energy and dose of the second to M buried layers can be gradually reduced, i.e., the implantation dose and energy of the first to M buried layers gradually decrease. By setting the implantation energy and dose to decrease sequentially, with shallower junction depth and lower concentration, and larger junction depth and higher dose, the electric field can be modulated more smoothly, thereby better modulating the bottom electric field region, suppressing the electric field spikes at the bottom of the trench 123, and further reducing the obstruction to electron flow during conduction. Therefore, compared to a single-layer deep buried layer 18, the multi-layer deep buried layer 18 can better suppress the electric field concentration at the bottom of the trench 123, making the electric field distribution in the device drift region more uniform, and further improving the breakdown voltage.

[0064] In some embodiments, the deep buried layer 18 is a P buried layer, where M is 1. The first buried layer 181 is formed by B ion implantation, with an implantation energy of 40 keV to 60 keV, specifically 40 keV, 45 keV, 50 keV, 55 keV, 60 keV, or other suitable values. The implantation dose is 1E13cm. -2 ~5E13cm -2 For example, it could be 1E13cm -22E13cm -2 3E13cm -2 4E13cm -2 5E13cm -2 Or other appropriate dosage.

[0065] In some embodiments, the deep buried layer 18 is a P buried layer, M is 3, and the first to M buried layers are all formed by B ion implantation. The implantation energy of the first buried layer 181 is 30 keV to 45 keV, specifically, it can be 30 keV, 35 keV, 40 keV, 45 keV or other suitable values, and the implantation dose is 7E12cm. -2 ~2E13cm -2 For example, it could be 7E12cm -2 8E12cm -2 1E13cm -2 2E13cm -2 Other suitable doses. The injection energy for layers 2 to M is 20 keV to 35 keV, specifically 20 keV, 25 keV, 30 keV, 32 keV, 35 keV, or other suitable values, with an injection dose of 5E12cm. -2 ~1E13cm -2 For example, it could be 5E12cm -2 6E12cm -2 7E12cm -2 8E12cm -2 9E12cm -2 1E13cm -2 Or other suitable doses. Furthermore, the injection energy and injection dose of the third buried layer 183 can be set to be less than the injection energy and injection dose of the second buried layer 182.

[0066] In this embodiment, the epitaxial layer 12 includes a first epitaxial layer 121 and a second epitaxial layer 122 stacked together. The first epitaxial layer 121 is located between the second epitaxial layer 122 and the substrate 11, and the buried layer 18 is located within the first epitaxial layer 121. The thickness of the first epitaxial layer 121 is greater than the distance between the shielding gate 13 and the substrate 11, so that the bottom of the shielding gate 13 and the area below it are all part of the first epitaxial layer 121, and the doping concentration of the first epitaxial layer 121 is greater than the doping concentration of the second epitaxial layer 122.

[0067] In an optional embodiment, the doping concentration of the first epitaxial layer 121 is 1E16cm. -3 ~8E16cm -3 For example, it could be 1E16cm -3 2E16cm -3 4E16cm-3 6E16cm -3 8E16cm -3 Or at other suitable concentrations, the doping concentration of the second epitaxial layer 122 is 7E15cm⁻¹. -3 ~2.5E16cm -3 For example, it could be 7E15cm -3 8E15cm -3 1E16cm -3 2E16cm -3 2.5E16cm -3 Or other suitable concentrations.

[0068] By setting a double-layer epitaxial layer 12 and simultaneously controlling the doping concentration of the first epitaxial layer 121 and the second epitaxial layer 122, the device can form a reasonable drift region to ensure the device's breakdown voltage capability. The high doping concentration of the first epitaxial layer 121 helps to reduce the drift region resistance, and the double-layer epitaxial layer 12 causes the electric field to form a stepped distribution. Combined with the deep buried layer 18, a lower on-resistance can be achieved without significantly sacrificing the device's breakdown voltage performance, thereby reducing the device's conduction loss.

[0069] In some embodiments, refer to Figure 1 M is set to 1. The thickness of the first epitaxial layer 121 is 5um to 8.5um, specifically, it can be 5um, 6um, 7um, 8um, 8.5um or other suitable dimensions. The thickness of the second epitaxial layer 122 is 4um to 7.5um, specifically, it can be 4um, 5um, 6um, 7um, 7.5um or other suitable dimensions. The depth of the trench 123 is 7um to 12um, specifically, it can be 7um, 8um, 10um, 12um or other suitable dimensions. The width of the first buried layer 181 along the first direction is 0.4um to 0.7um, specifically, it can be 0.4um, 0.5um, 0.6um, 0.7um or other suitable dimensions. The thickness of the first buried layer 181 is 0.5um to 0.8um, specifically, it can be 0.5um, 0.6um, 0.7um, 0.8um or other suitable dimensions.

[0070] In some embodiments, refer to Figure 2M is 3. The thickness of the first epitaxial layer 121 is 5um to 8.5um, specifically, it can be 5um, 6um, 7um, 8um, 8.5um or other suitable dimensions. The thickness of the second epitaxial layer 122 is 4um to 7.5um, specifically, it can be 4um, 5um, 6um, 7um, 7.5um or other suitable dimensions. The depth of the trench 123 is 7um to 12um, specifically, it can be 7um, 8um, 10um, 12um or other suitable dimensions. The width of the first to M buried layers along the first direction is 0.4um to 0.7um, specifically, it can be 0.4um, 0.5um, 0.6um, 0.7um or other suitable dimensions. The thickness of the first to M buried layers is 0.3um to 0.5um, specifically, it can be 0.3um, 0.35um, 0.4um, 0.45um, 0.5um or other suitable dimensions. The surface of the i-th buried layer away from the substrate 11 is denoted as the upper surface of the i-th buried layer. The distance between the upper surface of the i-th buried layer and the upper surface of the (i+1)-th buried layer is 0.9um to 1.1um, specifically, it can be 0.9um, 1um, 1.1um or other suitable dimensions, where i is a positive integer less than M.

[0071] By controlling the size of the buried layer 18, it is possible to ensure the optimization of the internal electric field of the device while preventing excessive obstruction of electron flow. It is understood that when the overall size of the device changes, the size of the buried layer 18 should also be adjusted accordingly. The scope of protection of this application is not limited to the above parameters.

[0072] In this embodiment, the semiconductor device further includes a dielectric layer 15, a drain metal layer 143, and a source metal layer 142. The dielectric layer 15 is located on the side of the implantation region 17 away from the body region 16 and fills the trench 123. The dielectric layer 15 covers the shielding gate 13. The gate 141 and the shielding gate 13 are spaced apart through the dielectric layer 15 so that the gate 141 and the shielding gate 13 are electrically insulated. The drain metal layer 143 is formed on the back side of the substrate 11. The source metal layer 142 is formed on the side of the dielectric layer 15 away from the substrate 11 and is in contact with the body region 16 and the implantation region 17. The source metal layer 142 is spaced apart from the gate 141 through the dielectric layer 15.

[0073] In the semiconductor device provided in this embodiment, the voltage of the gate 141 in the on state forms an inversion layer on the surface of the body region 16 and constitutes a conductive channel connecting the source and drain. The buried layer 18 is disposed below the shielding gate 13 and located on both sides below the trench 123. It is not directly located on the main current channel, so it will not significantly hinder the flow of electrons and thus significantly increase the on-resistance. At the same time, the buried layer 18 can form a depleted electric field shielding layer on both sides below the trench 123, avoiding the electric field from concentrating in weak areas such as the bottom of the trench 123, reducing the peak electric field around the shielding gate 13, improving the electric field distribution inside the device, and improving the breakdown voltage performance of the device. Furthermore, by setting a double-layer epitaxial layer 12 and making the first epitaxial layer 121 have a high doping concentration, the drift region resistance can be reduced, and the electric field can form a stepped distribution. In conjunction with the buried layer 18, a lower on-resistance can be achieved without significantly sacrificing the breakdown voltage performance of the device, and the conduction loss of the device can be reduced.

[0074] Therefore, compared to the problem that the breakdown voltage and on-resistance are usually mutually restrictive in traditional SGT MOSFET devices, the semiconductor device provided in this embodiment, by setting a deep buried layer + double-layer epitaxial structure, can simultaneously achieve higher breakdown voltage and lower on-resistance on the same device, which significantly improves the device's operating performance, reduces the risk of device failure under high voltage conditions, and improves the device's operating reliability.

[0075] Example 2

[0076] This embodiment provides a method for fabricating a semiconductor device, used to prepare any of the semiconductor devices described in this application, referring to... Figure 3 The preparation method includes steps S1 to S7, as detailed below.

[0077] First, step S1 is performed to provide a substrate.

[0078] In some embodiments, the substrate 11 may be, for example, a silicon substrate with a crystal orientation of 100, or the substrate 11 may be made of other suitable materials.

[0079] Next, step S2 is performed to form a first epitaxial material layer on the front side of the substrate and to form a buried layer in the first epitaxial material layer.

[0080] The buried layer 18 may include M buried layers, referred to as the 1st to the Mth buried layers, which are distributed sequentially along the second direction and gradually move away from the substrate 11. The steps of forming the first epitaxial material layer 221 and the buried layer 18 may include: growing a first epitaxial material layer 221 of a first thickness on the front side of the substrate 11; forming a first buried layer 181 on the surface of the current first epitaxial material layer 221 by ion implantation; continuing to grow a first epitaxial material layer 221 of a second thickness; forming a second buried layer 182 on the surface of the current first epitaxial material layer 221 by ion implantation, and so on, until the Mth buried layer is formed; continuing to grow a first epitaxial material layer 221 of the (M+1)th thickness, so that the first epitaxial material layer 221 constitutes the first epitaxial layer 121.

[0081] In some embodiments, refer to Figure 4 M is set to 1. The first epitaxial material layer 221 is an N-type doped semiconductor material layer. The buried layer 18 is formed by boron ion implantation. The steps for forming the first epitaxial material layer 221 and the buried layer 18 include: growing a first epitaxial material layer 221 with a thickness of 1.5 μm to 3 μm on the front side of the substrate 11; and growing the first buried layer 181 on the surface of the first epitaxial material layer 221 by boron ion implantation process, with an implantation energy of 40 keV to 60 keV and an implantation dose of 1E13cm. -2 ~5E13cm -2 The width of the first buried layer 181 is 0.4µm to 0.7µm, and the thickness is 0.5µm to 0.8µm. A first epitaxial material layer 221 of 3µm to 5.5µm is then grown, bringing the total thickness of the first epitaxial material layer 221 to 5µm to 8.5µm. The doping concentration of the first epitaxial material layer 221 is 1E16cm. -3 ~8E16cm -3 .

[0082] In some embodiments, refer to Figure 5 M is set to 3. The first epitaxial material layer 221 is an N-type doped semiconductor material layer. The buried layer 18 is formed by boron ion implantation. The steps for forming the first epitaxial material layer 221 and the buried layer 18 include: growing a first epitaxial material layer 221 with a thickness of 1.2 μm to 2.5 μm on the front side of the substrate 11; forming the first buried layer 181 by boron ion implantation, wherein the implantation energy of the first buried layer 181 is 30 keV to 45 keV and the implantation dose is 7E12cm. -2 ~2E13cm -2The width of the first buried layer 181 is 0.4 μm to 0.7 μm, and the thickness is 0.3 μm to 0.5 μm. A first epitaxial material layer 221 of 0.9 μm to 1.1 μm is then grown. A second buried layer 182 is formed using a boron ion implantation process, with an implantation energy of 20 keV to 35 keV and an implantation dose of 5E12cm. -2 ~1E13cm -2 The second buried layer 182 has a width of 0.4 μm to 0.7 μm and a thickness of 0.3 μm to 0.5 μm; a first epitaxial material layer 221 of 0.9 μm to 1.1 μm is then grown; a third buried layer 183 is formed by boron ion implantation, with an implantation energy of 20 keV to 35 keV and an implantation dose of 5E12cm. -2 ~1E13cm -2 The third buried layer 183 has a width of 0.4µm to 0.7µm and a thickness of 0.3µm to 0.5µm; a first epitaxial material layer 221 of 2µm to 3.5µm is then grown, so that the total thickness of the first epitaxial material layer 221 is 5µm to 8.5µm; wherein, the doping concentration of the first epitaxial material layer 221 is 1E16cm. -3 ~8E16cm -3 .

[0083] Next, step S3 is performed to form a second epitaxial material layer on the first epitaxial material layer.

[0084] Among them, reference Figure 6 and Figure 7 The second epitaxial material layer 222 constitutes the second epitaxial layer 122. The first epitaxial material layer 221 and the second epitaxial material layer 222 together constitute the epitaxial layer 12. The doping concentration of the first epitaxial material layer 221 is greater than that of the second epitaxial material layer 222. The second epitaxial material layer 222 can be made of the same material as the first epitaxial material layer 221.

[0085] In some embodiments, during the step of forming the second epitaxial material layer 222, the doping concentration of the second epitaxial material layer 222 is 7E15cm⁻¹. -3 ~2.5E16cm -3 The thickness is 4um to 7.5um, so that the thickness of the entire epitaxial layer 12 is 9um to 15um.

[0086] In steps S2 and S3, the materials of the first epitaxial material layer and the second epitaxial material layer can be silicon, silicon carbide, gallium nitride or other suitable materials. The specific materials can be set according to actual needs, and will not be described in detail in this embodiment.

[0087] Next, step S4 is performed to form a trench that penetrates the second epitaxial material layer but does not penetrate the first epitaxial material.

[0088] Specifically, refer to Figure 8 and Figure 9 The epitaxial layer 12 is patterned and etched to form a plurality of spaced trenches 123. In some embodiments, the thickness of the epitaxial layer 12 is 9 μm to 15 μm, the depth of the trenches 123 is 7 μm to 12 μm, and the width is 0.8 μm to 1 μm.

[0089] Next, step S5 is performed to form the first to third insulating material layers, the shielding gate, and the gate in the trench.

[0090] Reference Figure 10 and Figure 11 The first insulating material layer 251 is located between the shielding gate 13 and the epitaxial layer 12, forming the shielding gate insulating layer; the second insulating material layer 252 is located between the shielding gate 13 and the gate 141, forming the insulating layer between the shielding gate 13 and the gate 141; and the third insulating material layer 253 is located between the gate 141 and the epitaxial layer 12.

[0091] Next, step S6 is performed to sequentially form a volume region and an injection region on the surface of the second epitaxial material layer.

[0092] Reference Figure 12 and Figure 13 The implantation region 17 covers part of the surface of the body region 16. The body region 16 and the implantation region 17 can be formed by ion implantation or other suitable processes, and are combined with etching processes to expose part of the surface of the body region 16 by the implantation region 17. In this embodiment, a P-type body region and an N+ region are used as examples. The specific formation methods of the body region 16 and the implantation region 17 can be referred to the prior art, and will not be described in detail in this embodiment.

[0093] Next, step S7 is performed to form a fourth insulating material layer covering the injection region and the gate.

[0094] Reference Figure 14 and Figure 15 The first to fourth insulating material layers 254 can be made of the same material and using the same process, or they can be made of different materials and using different processes. For example, they can be formed by thermal oxidation and / or other growth processes, combined with other suitable processes. The first to fourth insulating layers constitute the dielectric layer 15 in this application. The thickness of the fourth insulating material layer 254 can be 0.4 μm to 0.7 μm.

[0095] In this embodiment, after forming the fourth insulating material layer 254 covering the implantation region 17 and the gate 141, the step may further include forming a source metal layer 142 and a drain metal layer 143. Specifically, this includes: forming the source metal layer 142 on the dielectric layer 15 and making the source metal layer 142 contact the implantation region 17 and the body region 16; and forming the drain metal layer 143 on the back side of the substrate 11, as follows. Figure 1 and Figure 2 As shown.

[0096] The preparation method of this embodiment is used to prepare any of the semiconductor devices in this application, and therefore this preparation method also has the beneficial effects of Embodiment 1.

[0097] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify, alter, or combine the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A semiconductor device, characterized in that, include: A substrate has a front side and a back side disposed opposite to each other, and a first direction and a second direction are defined, wherein the first direction is parallel to the front side of the substrate and perpendicular to the second direction, and the second direction is perpendicular to the front side of the substrate. An epitaxial layer of a first conductivity type is formed on the front side of the substrate, and a plurality of trenches are provided in the epitaxial layer; A shielding gate and a gate are located within the trench, with the gate spaced apart on the side of the shielding gate away from the substrate; A body region of the second conductivity type is formed on the side of the epitaxial layer away from the substrate; An implantation region of the first conductivity type is formed on the side of the body region away from the epitaxial layer and covers a portion of the surface of the body region; The second type of conductive buried layer is located within the epitaxial layer and is located on both sides opposite to the trench along the first direction. The buried layer includes M buried layers, which are respectively denoted as the 1st to the Mth buried layers. The 1st to the Mth buried layers are distributed sequentially at intervals along the second direction and gradually move away from the substrate. Where M is a positive integer, the first to the Mth buried layers are formed by ion implantation process, when M is 1, the implantation energy and implantation dose of the first buried layer are greater than or equal to the implantation energy and implantation dose of the first buried layer when M is greater than 1, and when M is greater than 1, the implantation energy and implantation dose of the first buried layer are greater than or equal to the implantation energy and implantation dose of the second to the Mth buried layers. The epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked together. The first epitaxial layer is located between the second epitaxial layer and the substrate, and the buried layer is located within the first epitaxial layer. The thickness of the first epitaxial layer is greater than the distance between the shielding gate and the substrate, and the doping concentration of the first epitaxial layer is greater than the doping concentration of the second epitaxial layer.

2. The semiconductor device according to claim 1, characterized in that, The distance between the surface of the buried layer away from the substrate and the substrate is less than the distance between the shielding gate and the substrate, and the distance between the buried layer and the substrate is not less than 1µm.

3. The semiconductor device according to claim 1, characterized in that, When M is 1, the first buried layer is formed by B ion implantation, the implantation energy is 40KeV~60KeV, and the implantation dose is 1E13cm -2 ~5E13cm -2 ; When M is 3, the first to M buried layers are all formed by B ion implantation. The implantation energy of the first buried layer is 30 keV to 45 keV, and the implantation dose is 7E12cm. -2 ~2E13cm -2 The injection energy for the second to M buried layers was 20 keV to 35 keV, and the injection dose was 5E12cm. -2 ~1E13cm -2 .

4. The semiconductor device according to claim 1, characterized in that, The doping concentration of the first epitaxial layer is 1E16cm. -3 ~8E16cm -3 The doping concentration of the second epitaxial layer is 7E15cm. -3 ~2.5E16cm -3 .

5. The semiconductor device according to claim 1, characterized in that, The buried layer includes M buried layers, denoted as the 1st to the Mth buried layers, which are distributed sequentially at intervals along the second direction and gradually move away from the substrate, where M is a positive integer; When M is 1, the thickness of the first epitaxial layer is 5um to 8.5um, the thickness of the second epitaxial layer is 4um to 7.5um, the depth of the trench is 7um to 12um, the width of the first buried layer along the first direction is 0.4um to 0.7um, and the thickness of the first buried layer is 0.5um to 0.8um. When M is 3, the thickness of the first epitaxial layer is 5um-8.5um, the thickness of the second epitaxial layer is 4um-7.5um, the depth of the trench is 7um-12um, the width of the first to M buried layers along the first direction is 0.4um-0.7um, the thickness of the first to M buried layers is 0.3um-0.5um, the surface of the i-th buried layer away from the substrate is denoted as the upper surface of the i-th buried layer, and the distance between the upper surface of the i-th buried layer and the upper surface of the (i+1)-th buried layer is 0.9um-1.1um, where i is a positive integer less than M.

6. The semiconductor device according to claim 1, characterized in that, Also includes: A dielectric layer is located on the side of the injection region away from the body region and fills the trench; A drain metal layer is formed on the back side of the substrate; A source metal layer is formed on the side of the dielectric layer away from the substrate and contacts the body region and the implantation region. The source metal layer is spaced apart from the gate through the dielectric layer.

7. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1 to 6, characterized in that, Includes the following steps: Provide a substrate; A first epitaxial material layer of a first conductivity type is formed on the front side of the substrate, and a buried layer is formed in the first epitaxial material layer; A second epitaxial material layer of a first conductivity type is formed on the first epitaxial material layer, the first epitaxial material layer and the second epitaxial material layer constitute the epitaxial layer, and the doping concentration of the first epitaxial material layer is greater than that of the second epitaxial material layer; A trench is formed that penetrates the second epitaxial material layer but does not penetrate the first epitaxial material layer; A first to third insulating material layer, a shielding gate, and a gate are formed in the trench. The first insulating material layer is located between the shielding gate and the epitaxial layer, the second insulating layer is located between the shielding gate and the gate, and the third insulating layer is located between the gate and the epitaxial layer. A body region and an injection region are sequentially formed on the surface of the second epitaxial material layer, wherein the injection region covers a portion of the surface of the body region; A fourth insulating material layer is formed covering the injection region and the gate.

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