Super junction mos device with strong terminal robustness, method for manufacturing the same, and chip

Abstract

The application belongs to the technical field of power devices, and provides a super-junction MOS device with strong terminal robustness, a preparation method thereof and a chip. The surface of a terminal withstand voltage region is higher than the surface of a cell region, so that a first P-type base region in a terminal transition region and a first P-type ring region in the terminal withstand voltage region form a first included angle, and the first P-type base region is in contact with a plurality of second P-type columns. The surface of the terminal withstand voltage region is higher than the surface of the cell region, and the first P-type base region and the first P-type ring region form a first included angle, so that the terminal transition region forms a slope along the terminal withstand voltage region to the cell region, thereby increasing the contact area of the terminal transition region and the source metal layer, improving the reverse extraction speed of the terminal holes, converting the one-dimensional hole channel of the terminal transition region structure into a two-dimensional channel, improving the extraction speed of the holes, and weakening the aggregation phenomenon of the electrons, thereby reducing the peak electric field and improving the terminal robustness of the device.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a superjunction MOS device with strong termination robustness, its fabrication method, and chip. Background Technology

[0002] Because superjunction metal-oxide field-effect transistors (SJ MOSFETs) can modulate their internal electric field through N-pillars and P-pillars, they break through the "silicon limit" between specific on-resistance (Ron,sp) and breakdown voltage (VB) of traditional power devices. In power semiconductors, SJ MOSFETs are widely used in high-voltage switching scenarios. High-voltage devices often require terminal protection, and the terminal protection technology of superjunction structures is constantly being optimized.

[0003] For SJ MOSFETs, robust termination is crucial for reliable operation in practical applications, and the reverse recovery performance of the body diode is an important indicator for evaluating termination robustness. During reverse recovery, because the termination area is much larger than the area of ​​a single cell, the extraction rate of non-equilibrium holes in the termination is much slower than in the cell region. This forces the termination region to withstand both high voltage and high current, leading to localized dynamic avalanche. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a superjunction MOS device with strong termination robustness, its fabrication method, and a chip, aiming to improve the termination robustness of the superjunction MOS device.

[0005] A first aspect of this application provides a superjunction MOS device with strong termination robustness, the superjunction MOS device comprising:

[0006] A substrate layer and an N-type epitaxial layer formed on the front side of the substrate layer; wherein the N-type epitaxial layer is divided into a terminal withstand voltage region, a terminal transition region and a cell region from a first side to a second side;

[0007] Multiple first P-pillars formed in the terminal withstand voltage region, multiple second P-pillars formed in the terminal transition region, and multiple third P-pillars formed in the cell region;

[0008] A first P-type ring region is formed in the terminal withstand voltage region and in contact with the plurality of first P pillars; wherein, the first P-type ring region is located on the N-type epitaxial layer;

[0009] A first P-type base region is formed within the terminal transition region; wherein the surface of the terminal pressure-resistant region is higher than the surface of the cell region, the first P-type base region and the first P-type ring region form a first angle, and the first P-type base region is in contact with a plurality of second P-pillars;

[0010] A first P-type heavily doped region and a first N-type heavily doped region are formed on the first P-type base region, and the first P-type heavily doped region is in contact with the insulating dielectric layer.

[0011] Multiple second P-type base regions are formed within the cell region; wherein, the second P-type base regions are formed on the corresponding third P pillars, and each second P-type base region is formed with a second P-type heavily doped region and a second N-type heavily doped region located on both sides of the second P-type heavily doped region;

[0012] An insulating dielectric layer, a first gate dielectric layer, and a first polysilicon layer are formed on the terminal withstand voltage region, wherein the first gate dielectric layer encapsulates the first polysilicon layer and is located on the insulating dielectric layer;

[0013] Multiple second gate dielectric layers and second polysilicon layers are formed on the cell region, each second gate dielectric layer encapsulating the corresponding second polysilicon layer, and the second gate dielectric layer is located on the N-type epitaxial layer between adjacent third P pillars;

[0014] A metal layer covering the terminal transition region and the cell region.

[0015] In some embodiments, the first P-ring region is disposed on an N-type epitaxial layer between adjacent first P pillars, and the first P-ring is in contact with the insulating dielectric layer.

[0016] In some embodiments, the width of the first P-type ring region gradually increases from the first side to the second side of the N-type epitaxial layer.

[0017] In some embodiments, the first P-type heavily doped region extends below the insulating dielectric layer, and the first P-type heavily doped region contacts at least one of the first P-pillars on the second side of the terminal withstand voltage region.

[0018] In some embodiments, the width of the first P-pillar is smaller than the width of the second P-pillar.

[0019] In some embodiments, the width of the second P-pillar is smaller than the width of the third P-pillar.

[0020] In some embodiments, a stop ring is provided on the first side of the terminal withstand voltage region, and the insulating dielectric layer is not provided on the stop ring. A plurality of the first P-posts on the first side of the terminal withstand voltage region are in contact with the insulating dielectric layer, and a first P-type ring region is provided between the first P-posts on the second side of the terminal withstand voltage region and the insulating dielectric layer.

[0021] In some embodiments, the depth of the plurality of first P pillars gradually increases from the first side to the second side of the N-type epitaxial layer.

[0022] A second aspect of this application also provides a method for fabricating a superjunction MOS device as described in any of the preceding claims, the method comprising:

[0023] An N-type epitaxial layer is grown on the front side of the substrate; wherein the N-type epitaxial layer is divided from the first side to the second side into a terminal withstand voltage region, a terminal transition region, and a cell region;

[0024] P-pillars are formed at intervals in the N-type epitaxial layer; wherein, the terminal withstand voltage region includes a plurality of first P-pillars, the terminal transition region includes a plurality of second P-pillars, and the cell region includes a plurality of third P-pillars;

[0025] A first P-type ring region and an insulating dielectric layer are sequentially formed on the terminal withstand voltage region, and the surface of the cell region is etched so that the surface of the cell region is lower than the surface of the terminal withstand voltage region, and the first P-type base region and the first P-type ring region form a first included angle.

[0026] A first gate dielectric layer and a first polysilicon layer are formed on the insulating dielectric layer, and a plurality of second gate dielectric layers and a plurality of second polysilicon layers are formed on the cell region; wherein, the first P-type ring region is located between the N-type epitaxial layer and the first gate dielectric layer, the first gate dielectric layer encapsulates the first polysilicon layer, the first gate dielectric layer is located on the insulating dielectric layer, each second gate dielectric layer encapsulates the corresponding second polysilicon layer, and the second gate dielectric layer is located on the N-type epitaxial layer between adjacent third P pillars;

[0027] A first P-type base region is formed in the terminal transition region, and a second P-type base region is formed in the cell region; wherein, the second P-type base region is formed on the corresponding third P pillar, and a second P-type heavily doped region and a second N-type heavily doped region located on both sides of the second P-type heavily doped region are formed on each second P-type base region, and a first P-type heavily doped region and a first N-type heavily doped region are formed on the first P-type base region;

[0028] A metal layer is formed covering the terminal transition region and the cell region.

[0029] A third aspect of this application also provides a chip including a superjunction MOS device as described in any of the above embodiments.

[0030] The beneficial effects of this application embodiment are as follows: By setting the surface of the terminal withstand voltage region higher than the surface of the cell region, the first P-type base region in the terminal transition region and the first P-type ring region in the terminal withstand voltage region form a first angle, and the first P-type base region contacts multiple second P pillars. By setting the surface of the terminal withstand voltage region higher than the surface of the cell region, and the first P-type base region and the first P-type ring region forming a first angle, the terminal transition region forms a slope along the terminal withstand voltage region to the cell region, thereby increasing the contact area between the terminal transition region and the source metal layer, improving the reverse extraction speed of terminal holes, and transforming the one-dimensional hole channel of the terminal transition region structure into a two-dimensional channel, thereby improving the hole extraction speed and weakening the minority carrier aggregation phenomenon, thereby reducing the peak electric field and improving the terminal robustness of the device. Attached Figure Description

[0031] Figure 1a This is a top view schematic diagram of the superjunction MOS device provided in the embodiments of this application;

[0032] Figure 1b This is a schematic diagram of the structure of the superjunction MOS device provided in the embodiments of this application;

[0033] Figure 2 This is a schematic diagram of the structure of the superjunction MOS device provided in the embodiments of this application. Figure 2 ;

[0034] Figure 3a This is a schematic diagram of the structure of the superjunction MOS device provided in the embodiments of this application;

[0035] Figure 3b This is a schematic diagram of the structure of the superjunction MOS device provided in the embodiments of this application. Figure 4 ;

[0036] Figure 4 This is a simulation diagram of the superjunction MOS device provided in the embodiments of this application;

[0037] Figure 5 This is a schematic diagram of the REC curve of the superjunction MOS device provided in the embodiments of this application;

[0038] Figure 6 This is a schematic diagram of the BV curve of the superjunction MOS device provided in the embodiments of this application;

[0039] Figure 7 This is a simulation diagram of the hole density of the superjunction MOS device provided in the embodiments of this application;

[0040] Figure 8 This is a schematic diagram of the hole density distribution of the superjunction MOS device provided in the embodiments of this application;

[0041] Figure 9This is a simulation diagram of the superjunction MOS device provided in the embodiments of this application during reverse recovery;

[0042] Figure 10 This is a schematic diagram of the electric field distribution of the superjunction MOS device provided in the embodiments of this application;

[0043] Figure 11 This is a schematic diagram of the fabrication method of the superjunction MOS device provided in the embodiments of this application;

[0044] Figure 12 This is a partial schematic diagram of the formation of an N-type epitaxial layer provided in an embodiment of this application;

[0045] Figure 13 This is a partial schematic diagram of the P-pillars with spaced intervals provided in the embodiments of this application;

[0046] Figure 14 This is a partial schematic diagram of the formation of an insulating dielectric layer provided in an embodiment of this application;

[0047] Figure 15 This is a partial schematic diagram of the formation of the first gate dielectric layer, the first polysilicon layer, the second gate dielectric layer, and the second polysilicon layer provided in the embodiments of this application;

[0048] Figure 16 This is a partial schematic diagram provided in the embodiments of this application after implantation of P-type doped ions and N-type doped ions. Detailed Implementation

[0049] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0050] Superjunction metal-oxide-semiconductor field-effect transistors (SJ MOSFETs) modulate their internal electric field through charge balance between N-pillars and P-pillars, breaking the "silicon limit" between specific on-resistance and breakdown voltage in traditional power devices. Therefore, they are widely used in high-voltage power conversion. For high-voltage devices, the termination structure at their edges is crucial for achieving reliable high-voltage blocking.

[0051] In practical applications, especially under hard-switching conditions, the reverse recovery characteristics of the SJ MOSFET body diode are a key indicator of its termination robustness. During reverse recovery, because the area of ​​the termination region is much larger than that of a single cell, the extraction rate of non-equilibrium minority carriers (holes) in the termination region is much slower than in the cell region. This results in a large accumulation of minority carriers near the main junction in the termination transition region even after the minority carriers in the cell region have been completely extracted. This forms a localized region that simultaneously withstands high voltage and high current, making it highly susceptible to dynamic avalanche, generating high-heat carrier injection, forming "hot spots," and ultimately leading to device failure. This problem is particularly prominent in applications with high dI / dt (current change rate).

[0052] Therefore, how to improve the minority carrier extraction speed of the SJ MOSFET terminal region during reverse recovery, suppress minority carrier aggregation, reduce the peak electric field, and thus enhance the robustness of the terminal has become a technical problem that urgently needs to be solved in this field.

[0053] To address the aforementioned technical problems, embodiments of this application provide a superjunction MOS device with strong termination robustness, see [link to relevant documentation]. Figure 1a As shown, the superjunction MOS device includes a termination region 100 and a cell region 200 in a horizontal cross-section. The termination region 100 is annular, and the cell region 200 is located within the enclosure of the termination region 100. Figure 1b As shown, Figure 1b for Figure 1a The schematic structure of section AA' in the diagram shows that the terminal region 100 includes a terminal withstand region 110 and a terminal transition region 120, with the terminal transition region 120 located between the terminal withstand region 110 and the cell region 200. (Combined with...) Figure 1b As shown in the vertical cross-sectional schematic diagram, the superjunction MOS device includes a substrate layer 300, an N-type epitaxial layer 310, a first P-pillar 410, a second P-pillar 420, a third P-pillar 430, a first P-type ring region 411, a first P-type base region 421, an insulating dielectric layer 600, a first gate dielectric layer 511, a first polysilicon layer 512, a second gate dielectric layer 521, a second polysilicon layer 522, and a metal layer 700.

[0054] In this embodiment, an N-type epitaxial layer 310 is formed on the front side of a substrate 300, which is an N-type substrate. The doping concentration of the substrate 300 is greater than that of the N-type epitaxial layer 310. The back side of the substrate 300 is used to form a drain metal layer. The N-type epitaxial layer 310 is divided into a terminal withstand voltage region 110, a terminal transition region 120, and a cell region 200 from the first side to the second side. At least one P-pillar is provided in each of the terminal withstand voltage region 110, the terminal transition region 120, and the cell region 200. The longitudinal axes of the multiple P-pillars are arranged in parallel, and adjacent P-pillars can serve as N-pillars. Specifically, multiple first P-pillars 410 are formed in the terminal withstand voltage region 110, multiple second P-pillars 420 are formed in the terminal transition region 120, and multiple third P-pillars 430 are formed in the cell region 200, so that the N-type epitaxial layer 310 forms a structure in which P-pillars and N-pillars are arranged alternately.

[0055] In some embodiments, a first P-type ring region 411 is formed on the terminal withstand voltage region 110 and contacts a plurality of first P-pillars 410. The first P-type ring region 411 is located on the N-type epitaxial layer 310 and is used to optimize the electric field on the surface of the terminal withstand voltage region 110.

[0056] In some embodiments, a first P-type base region 421 is formed within a terminal transition region 120, the surface of a terminal withstand voltage region 110 is higher than the surface of a cell region 200, the first P-type base region 421 and the first P-type ring region 411 form a first angle, and the first P-type base region 421 contacts a plurality of second P-pillars 420. A first P-type heavily doped region 422 and a first N-type heavily doped region 423 are formed on the first P-type base region 421, one side of the first P-type heavily doped region 422 contacts an insulating dielectric layer 600, and the other side of the first P-type heavily doped region 422 contacts a first N-type heavily doped region 423. The area of ​​the first P-type heavily doped region 422 is larger than the area of ​​the first N-type heavily doped region 423, and the doping concentration of the first P-type heavily doped region 422 is greater than the doping concentration of the first P-type base region 421.

[0057] In this embodiment, the metal layer 700 is the source metal layer, and the back side of the substrate layer 300 is provided with a drain metal layer. During reverse recovery, the first P-type heavily doped region 422, the first P-type base region 421, the N-type epitaxial layer 310, and the substrate layer 300 form a reverse diode. Since the surface of the terminal breakdown region 110 is higher than the surface of the cell region 200, the first P-type base region 421 and the first P-type ring region 411 form a first angle, making the surface of the terminal transition region 120 a slope along the terminal breakdown region 110 to the cell region 200. This increases the contact area between the terminal transition region 120 and the source metal layer, improves the reverse extraction speed of the terminal hole, and transforms the one-dimensional hole channel of the terminal transition region 120 structure into a two-dimensional channel, thereby improving the hole extraction speed and reducing the minority carrier aggregation phenomenon, thus reducing the peak electric field and improving the terminal robustness of the device.

[0058] In some embodiments, a plurality of second P-type base regions 431 are formed within the cell region 200, each second P-type base region 431 is formed on a corresponding third P-pillar 430, and each second P-type base region 431 has a second P-type heavily doped region 432 and a second N-type heavily doped region 433 located on both sides of the second P-type heavily doped region 432. An insulating dielectric layer 600 is formed on the terminal withstand voltage region 110, and a first gate dielectric layer 511 is formed on the insulating dielectric layer 600, the first gate dielectric layer 511 encapsulating a first polysilicon layer 512. Each second gate dielectric layer 521 encapsulates a corresponding second polysilicon layer 522, and the second gate dielectric layer 521 is located on the N-type epitaxial layer 310 between adjacent third P-pillars 430. A metal layer 700 covers the terminal transition region 120 and the cell region 200, and this metal layer 700 can serve as a source metal layer.

[0059] In this embodiment, the second P-type heavily doped region 432, the second P-type base region 431, the N-type epitaxial layer 310, and the substrate layer 300 form a reverse diode. The area of ​​the second P-type heavily doped region 432 in the cell region 200 determines the size of the equivalent diode in the cell region 200. By etching the terminal transition region 120, the height of the surface of the terminal breakdown region 110 is made higher than the height of the surface of the cell region 200. The terminal transition region 120 forms a slope that gradually descends along the direction from the terminal breakdown region 110 to the cell region 200, increasing the contact area between the terminal transition region 120 and the source metal layer, thereby improving the reverse extraction speed of terminal holes. It can also transform the one-dimensional hole channel of the traditional terminal transition region 120 structure into a two-dimensional channel, improving the hole extraction speed and weakening the minority carrier aggregation phenomenon, thereby reducing the peak electric field.

[0060] In some embodiments, the area of ​​the second P-type heavily doped region 432 is smaller than the area of ​​the first P-type heavily doped region 422. Therefore, the equivalent diode of the terminal region 100 is much larger than the diode of the cell region 200. By increasing the minority carrier extraction speed of the terminal region 100, the minority carriers at the terminal are prevented from accumulating near the main junction of the terminal transition region 120 to form a high electric field region.

[0061] In some embodiments, the second P-type heavily doped region 432 forms a PN junction with the second N-type heavily doped regions 433 on both sides, and the first P-type heavily doped region 422 forms a PN junction with the first N-type heavily doped region 423. The area of ​​the first P-type heavily doped region 422 is at least 5 times the area of ​​the second P-type heavily doped region 432.

[0062] In some embodiments, see Figure 2 As shown, the first P-type ring region 411 is disposed on the N-type epitaxial layer 310 between adjacent first P-pillars 410, and the first P-type ring region 411 is in contact with the insulating dielectric layer 600.

[0063] In this embodiment, each first P-pillar 410 is in contact with the insulating dielectric layer 600. In the region near the terminal transition region 120, a first P-type ring region 411 is formed between adjacent first P-pillars 410. The first P-type ring region 411 is in contact with the insulating dielectric layer 600. When the device is in the reverse recovery process, the holes in the terminal region 100 can not only be extracted by the second P-type base region 431 (i.e., P-type body region) of the cell region 200 through the lateral path, but also be extracted quickly in two dimensions through the large-area contact between the ramp surface and the source metal layer, thereby avoiding accumulation and improving robustness.

[0064] In some embodiments, the first P-type ring region 411 can be an integral whole, and the first P-type ring region 411 is formed between a plurality of first P pillars 410 and the insulating dielectric layer 600.

[0065] In some embodiments, there may be multiple first P-type ring regions 411, each first P-type ring region 411 is formed between adjacent first P-pillars 410, and the multiple first P-type ring regions 411 are in contact with the insulating dielectric layer 600.

[0066] In some embodiments, a portion of the first P-pillar 410 near the first side of the N-type epitaxial layer 310 is in direct contact with the insulating dielectric layer 600.

[0067] In some embodiments, the width of the first P-type ring region 411 gradually increases from the first side of the N-type epitaxial layer 310 to the second side of the N-type epitaxial layer 310.

[0068] In this embodiment, the surface electric field of the terminal withstand voltage region 110 is optimized by multiple spaced first P-type ring regions 411. The multiple first P-type ring regions 411 are separated by first P-pillars 410, thereby forming multiple floating P-type ring pillars whose size and spacing can be independently adjusted. By carefully designing the size and spacing of these floating P-type ring pillars, the surface electric field distribution of the terminal region 100 can be adjusted more precisely, making the electric field gradient change more gradual during reverse recovery, thereby further improving the withstand voltage and robustness of the device.

[0069] In some embodiments, the widths of the plurality of first P-type ring regions 411 are arranged in an arithmetic sequence. By setting their widths in an arithmetic sequence, the surface electric field distribution of the terminal region 100 can be balanced, making the electric field gradient change more gradual during the reverse recovery process, thereby further improving the withstand voltage and robustness of the device.

[0070] In some embodiments, combined with Figure 3a As shown, the first P-type heavily doped region 422 extends below the insulating dielectric layer 600, and the first P-type heavily doped region 422 is in contact with at least one first P-pillar 410 on the second side of the terminal withstand voltage region 110.

[0071] In this embodiment, the first P-type heavily doped region 422 extends below the first gate dielectric layer 511, which can increase the area of ​​the first P-type heavily doped region 422. During the reverse recovery process, thanks to the increased contact area and two-dimensional extraction channel, the non-equilibrium minority carriers (holes) in the terminal region 100 can be extracted more quickly, thereby effectively alleviating the minority carrier aggregation phenomenon near the main junction in the terminal transition region 120 and avoiding the local high electric field caused by high concentration of minority carriers.

[0072] In some embodiments, the angle between the ramp surface and the horizontal plane of the cell region 200 within the terminal transition region 120 is between 120° and 150°. The height of the ramp structure within the terminal transition region 120 gradually changes. Thanks to the increased contact area and two-dimensional extraction channel, the non-equilibrium minority carriers (holes) of the terminal region 100 can be extracted more quickly during the reverse recovery process, thereby effectively alleviating the minority carrier aggregation phenomenon near the main junction of the terminal transition region 120 and avoiding the local high electric field caused by high concentration of minority carriers.

[0073] In some embodiments, combined with Figure 2 As shown, multiple first P-pillars 410 on the second side inside the terminal withstand voltage zone 110 are in contact with the insulating dielectric layer 600. A stop ring 320 is provided on the first side inside the terminal withstand voltage zone 110. The insulating dielectric layer 600 is not provided on the stop ring 320. Multiple first P-pillars 410 on the first side of the terminal withstand voltage zone 110 are in contact with the insulating dielectric layer 600. A first P-type ring area 411 is provided between the first P-pillars 410 on the second side of the terminal withstand voltage zone 110 and the insulating dielectric layer 600.

[0074] In this embodiment, the cutoff ring 320 is disposed at the outermost periphery of the terminal region 100, and the cutoff ring 320 is used to cut off the transverse electric field.

[0075] In some embodiments, the thickness of the stop ring 320 is less than the thickness of the first P-type ring region 411.

[0076] In some embodiments, the cutoff ring 320 is N-type doped, and the doping concentration of the cutoff ring 320 is greater than the doping concentration of the N-type epitaxial layer 310.

[0077] In some embodiments, combined with Figure 3b As shown, the depth of the multiple first P pillars 410 gradually increases from the first side to the second side of the N-type epitaxial layer 310.

[0078] In this embodiment, the depth of the first P-pillar 410 gradually increases from the terminal withstand voltage region 110 toward the cell region 200, which helps to optimize the electric field of the terminal region 100. The electric field curvature within the terminal region 100 is lower, resulting in a taller terminal structure. Within the terminal withstand voltage region 110, due to the bending of the junction, the electric field concentrates (electric field curvature effect), causing the device to break down prematurely below the ideal planar junction breakdown voltage (BV). By gradually increasing the depth of the first P-pillar 410 from the terminal withstand voltage region 110 toward the cell region 200, the lateral electric field of the terminal region 100 can be modulated more effectively, making its distribution more uniform and mitigating electric field spikes, thereby raising the actual breakdown voltage of the device to a level closer to the theoretical limit of the material.

[0079] Furthermore, in the terminal region 100, especially in the first side edge region of the terminal withstand voltage region 110, maintaining a precise charge balance is more difficult. The gradually increasing depth of the first P pillar 410 helps to achieve better charge compensation throughout the entire terminal region 100, ensuring that the depletion region can expand smoothly and controllably when subjected to high reverse voltage, avoiding early breakdown or voltage instability caused by local charge imbalance.

[0080] In some embodiments, the width of the first P-pillar 410 is smaller than the width of the second P-pillar 420.

[0081] In this embodiment, an insulating dielectric layer 600 is disposed on the surface of the terminal region 100, and a first gate dielectric layer 511 and a first polysilicon layer 512 are disposed above it. The first polysilicon layer 512 and the structure below form a MOS structure. By setting the width of the first P-pillar 410 to be smaller than the width of the second P-pillar 420, the width of the first P-pillar 410 can also gradually increase from the terminal withstand voltage region 110 towards the cell region 200. In this way, the potential of the surface of the terminal region 100 is affected. Combined with the raised terminal withstand voltage region 110 and the insulating layer / polysilicon above, this region actually forms a junction termination extension (JTE) or field plate structure. Adjusting the width of the P-pillar can optimize the modulation effect of this integrated "field plate" on the surface electric field, making the electric field more uniform in both the longitudinal and lateral directions.

[0082] In some embodiments, the width of the second P-pillar 420 is smaller than the width of the third P-pillar 430.

[0083] In this embodiment, the second P-pillar 420 of the termination voltage withstand region 110 is narrower, potentially reducing the initial total number of holes stored in the termination voltage withstand region 110. When the device transitions from conduction to turn-off, the total number of holes that need to be removed is also reduced accordingly. This alleviates the burden of reverse recovery from the outset. Furthermore, combined with the two-dimensional extraction channel provided by the ramp structure of the termination voltage withstand region 110, the narrower P-pillar may allow holes to be extracted more quickly by the source metal contacts on the ramp surface, as the average distance the hole travels laterally to the extraction point may be shortened, further reducing the reverse recovery time (Irr) and lowering the peak electric field.

[0084] In some embodiments, Figure 4 The horizontal axis in the diagram is the Y-axis, representing the horizontal dimension of the device, with the unit of measurement being μm. Figure 4 The vertical axis in the diagram is the X-axis, representing the vertical dimension of the device, with the unit of measurement being μm. Figure 4 As shown, in the vertical direction, the surface of the terminal withstand voltage region 110 is higher than the surface of the cell region 200. At the same time, the terminal transition region 120 forms a slope that gradually decreases in the direction pointing to the cell region 200. The doping concentration of the first P-type base region 421 is greater than the doping concentration of the second P-pillar 420. This slope structure is beneficial to increasing the contact area between the terminal transition region 120 and the source metal layer, thereby increasing the reverse extraction speed of terminal holes. In addition, it can also transform the one-dimensional hole channel of the traditional terminal transition region 120 structure into a two-dimensional channel, increasing the hole extraction speed and weakening the minority carrier aggregation phenomenon, thereby reducing the peak electric field. Figure 5This is a schematic diagram of the reverse recovery characteristic curves (REC curves) of the superjunction MOS device (S1) and the comparative structure (S2) in this application embodiment. In the comparative structure (S2), the terminal withstand voltage region 110 is flush with the surface of the cell region 200. The REC curve is used to characterize the reverse recovery test waveform of the device. This curve is the core test graph for evaluating the key dynamic characteristics of the body diode inside the device during the switching process. Its horizontal axis represents time, and the vertical axis represents the reverse recovery current flowing through the body diode of the device. Figure 5 As can be seen, the comparative structure, due to slow hole extraction during reverse recovery, leads to local current and electric field spikes, which may manifest as more severe current oscillations or higher effective recovery charge on the REC curve. Through the device structure optimization in this embodiment, the ramp structure accelerates hole extraction, aiming to obtain a better (i.e., softer, lower-loss) REC curve. In actual test comparisons, the reverse recovery peak current (Ipeak) of the superjunction MOS device in this embodiment increased from 11.3A to 13.5A, and the reverse recovery time (Trr) decreased from 194µs to 158µs. This demonstrates that the superjunction device in this embodiment can effectively improve the minority carrier extraction speed at the terminal, enhancing the device's reliability in hard-switching applications. Furthermore, the reduction in minority carrier aggregation directly leads to a significant decrease in the peak electric field in the terminal region 100 during reverse recovery, greatly reducing the risk of dynamic avalanche breakdown, thereby improving the device's reliability and robustness under harsh operating conditions such as high dI / dt.

[0085] Figure 6 This is a schematic diagram of the breakdown voltage (BV) curves of the superjunction MOS device (S1) and the comparative structure (S2) in this embodiment. The horizontal axis represents the reverse bias voltage (Vds) applied across the device, and the vertical axis represents the reverse leakage current (Ids) flowing through the device. Through the optimization of the superjunction device by the ramp structure in this embodiment, in actual testing, the breakdown voltage of the superjunction device is increased from 516V to 530V, and the reverse leakage current is increased from 9uA to 12uA. The design of raising the terminal withstand voltage region 110, combined with the ramp transition in the terminal transition region 120, can better optimize the electric field distribution on the terminal surface, alleviate the electric field curvature effect, and help to obtain a higher device breakdown voltage. As can be seen, the termination structure can still maintain the device's withstand voltage capability and will not cause premature breakdown. While maintaining static breakdown voltage and leakage current characteristics similar to the comparative structure, its peak current during the reverse recovery process can be increased by about 20%, the reverse recovery time can be reduced by about 19%, and the peak electric field near the termination transition region 120 is significantly reduced. This fully demonstrates the significant enhancement effect of the superjunction MOS device in this embodiment on the robustness of the termination.

[0086] Figure 7 This is a simulation diagram of the hole current density of the superjunction MOS device in this embodiment. Figure 7 The horizontal axis in the diagram is the Y-axis, representing the horizontal dimension of the device, with the unit of measurement being μm. Figure 7 The vertical axis in the diagram is the X-axis, representing the vertical dimension of the device, with the unit of measurement being μm. Figure 8 for Figure 7 A schematic diagram of the hole current density curves at position C11 in the terminal transition region 120 of the superjunction MOS device (S1) and the comparative structure (S2). Figure 9 This is a simulation diagram of the electric field distribution of the superjunction MOS device in this embodiment. Figure 9 The horizontal axis in the diagram represents the dimension of the device in the Y-direction (horizontal direction). Figure 9 The vertical axis in the figure represents the dimension of the device in the X direction (vertical direction). Figure 10 This is a schematic diagram showing the hole current density curves at position C12 within the terminal region 100 in the superjunction MOS device (S1) of the embodiment and the comparative structure (S2). Figure 10 The horizontal axis in the diagram represents the dimension of the device in the Y direction. Figure 10 The vertical axis in the diagram represents the electric field distribution of the device. Combined with... Figure 7 , Figure 8 , Figure 9 , Figure 10 It is known that by etching a gradient height difference between the terminal withstand voltage region 110 and the cell region 200, a height gradient region is formed within the withstand voltage transition region. This height gradient region is then used to form the diode main junction of the MOS transition region. This not only increases the main junction area of ​​the transition region but also transforms the one-dimensional hole channel into a two-dimensional channel, significantly improving the reverse extraction speed of terminal holes. Figure 8 As shown, the hole current density near the main junction in the terminal transition region 120 is much greater than that in the comparative structure, and, as Figure 10 As shown, the peak electric field near the terminal transition region 120 and the terminal withstand voltage region 110 is significantly lower than that of the comparative structure, proving that the superjunction MOS device in this embodiment can effectively reduce the peak electric field at the terminal during reverse recovery and can effectively improve the terminal robustness of the superjunction MOS device.

[0087] This application also provides a method for fabricating a superjunction MOS device as described in any of the above embodiments, see [link to relevant documentation]. Figure 11 As shown, the preparation method in this embodiment includes steps S100 to S700.

[0088] In step S100, an N-type epitaxial layer 310 is epitaxially grown on the front side of the substrate layer 300.

[0089] In this embodiment, as Figure 12 As shown, the N-type epitaxial layer 310 is divided into a terminal withstand region 110, a terminal transition region 120, and a cell region 200 from the first side to the second side.

[0090] In some embodiments, the substrate 300 is N-type doped, and the doping concentration of the substrate 300 is greater than that of the N-type epitaxial layer 310. An epitaxial process is used to epitaxially grow the N-type epitaxial layer 310 on the front side of the substrate 300.

[0091] In step S200, spaced P-pillars are formed in the N-type epitaxial layer 310.

[0092] In this embodiment, as Figure 13 As shown, the terminal withstand voltage region 110 includes a plurality of first P pillars 410, the terminal transition region 120 includes a plurality of second P pillars 420, and the cell region 200 includes a plurality of third P pillars 430.

[0093] In step S300, a first P-type ring region 411 and an insulating dielectric layer 600 are sequentially formed on the terminal withstand voltage region 110, and the surface of the cell region 200 is etched so that the surface of the cell region 200 is lower than the surface of the terminal withstand voltage region 110, and the first P-type base region 421 and the first P-type ring region 411 form a first included angle.

[0094] In this embodiment, combined with Figure 13 As shown, a superjunction composed of alternating N-pillars and P-pillars is formed through multiple epitaxial, implantation, or etching filling processes, and a first P-type ring region 411 is implanted at a predetermined position in the terminal withstand voltage region 110. The upper surface of the first P-type ring region 411 is flush with the surface of the N-type epitaxial layer 310 of the terminal withstand voltage region 110.

[0095] Combination Figure 14 As shown, an insulating dielectric layer 600 can also be formed on the surface of the N-type epitaxial layer 310 of the terminal withstand voltage region 110 by an insulating dielectric material deposition process. With silicon oxide hard mask and photoresist as a mask, anisotropic etching is performed on silicon to form a three-dimensional structure in which the terminal withstand voltage region 110 is raised and the terminal transition region 120 is a slope. This makes the surface of the cell region 200 lower than the surface of the terminal withstand voltage region 110, and the first P-type base region 421 and the first P-type ring region 411 form a first angle, so that the surface of the terminal withstand voltage region 110 transitions to the surface of the cell region 200 on the slope in the terminal transition region 120.

[0096] In step S400, a first gate dielectric layer 511 and a first polysilicon layer 512 are formed on the insulating dielectric layer 600, and a plurality of second gate dielectric layers 521 and a plurality of second polysilicon layers 522 are formed on the cell region 200.

[0097] In this embodiment, combined with Figure 15As shown, gate oxide is grown in the terminal withstand voltage region 110 and the cell region 200, and polysilicon is deposited and patterned to form the gate. The first P-type ring region 411 is located between the N-type epitaxial layer 310 and the first gate dielectric layer 511. The first gate dielectric layer 511 wraps the first polysilicon layer 512. The first gate dielectric layer 511 is located on the insulating dielectric layer 600. Each second gate dielectric layer 521 wraps the corresponding second polysilicon layer 522, and the second gate dielectric layer 521 is located on the N-type epitaxial layer 310 between adjacent third P pillars 430.

[0098] In step S500, a first P-type base region 421 is formed in the terminal transition region 120, and a second P-type base region 431 is formed in the cell region 200.

[0099] In this embodiment, combined with Figure 16 As shown, P-type doped ions and N-type doped ions are implanted sequentially, and P-body region and N+ source region are implanted. The second P-type base region 431 is formed on the corresponding third P pillar 430. A second P-type heavily doped region 432 and a second N-type heavily doped region 433 located on both sides of the second P-type heavily doped region 432 are formed on each second P-type base region 431. A first P-type heavily doped region 422 and a first N-type heavily doped region 423 are formed on the first P-type base region 421.

[0100] In step S600, a metal layer 700 is formed covering the terminal transition region 120 and the cell region 200.

[0101] In some embodiments, a chip is also provided, the chip including a chip substrate, on which one or more superjunction MOS devices are disposed.

[0102] Other related semiconductor devices, as well as integrated circuits composed of MOSFETs, can also be integrated on the chip substrate.

[0103] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0104] The beneficial effects of this application embodiment are as follows: By setting the surface of the terminal withstand voltage region 110 to be higher than the surface of the cell region 200, the first P-type base region 421 in the terminal transition region 120 and the first P-type ring region 411 in the terminal withstand voltage region 110 form a first included angle, and the first P-type base region 421 contacts the multiple second P-pillars 420. By setting the surface of the terminal withstand voltage region 110 to be higher than the surface of the cell region 200, the terminal transition region 120 forms a slope along the terminal withstand voltage region 110 to the cell region 200, thereby increasing the contact area between the terminal transition region 120 and the source metal layer, improving the reverse extraction speed of terminal holes, and transforming the one-dimensional hole channel of the terminal transition region 120 structure into a two-dimensional channel, thereby improving the hole extraction speed and weakening the minority carrier aggregation phenomenon, thereby reducing the peak electric field and improving the terminal robustness of the device.

[0105] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0106] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0107] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0108] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0109] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A superjunction MOS device with strong termination robustness, characterized in that, The superjunction MOS device includes: A substrate layer and an N-type epitaxial layer formed on the front side of the substrate layer; wherein the N-type epitaxial layer is divided into a terminal withstand voltage region, a terminal transition region and a cell region from a first side to a second side; Multiple first P-pillars formed in the terminal withstand voltage region, multiple second P-pillars formed in the terminal transition region, and multiple third P-pillars formed in the cell region; A first P-type ring region is formed in the terminal withstand voltage region and in contact with the plurality of first P pillars; wherein, the first P-type ring region is located on the N-type epitaxial layer; A first P-type base region is formed within the terminal transition region; wherein the surface of the terminal pressure-resistant region is higher than the surface of the cell region, the first P-type base region and the first P-type ring region form a first angle, and the first P-type base region is in contact with a plurality of second P-pillars; The first P-type heavily doped region and the first N-type heavily doped region are formed on the first P-type base region; Multiple second P-type base regions are formed within the cell region; wherein, the second P-type base regions are formed on the corresponding third P pillars, and each second P-type base region is formed with a second P-type heavily doped region and a second N-type heavily doped region located on both sides of the second P-type heavily doped region; An insulating dielectric layer, a first gate dielectric layer, and a first polysilicon layer are formed on the terminal withstand voltage region. The first gate dielectric layer encapsulates the first polysilicon layer and is located on the insulating dielectric layer. The first P-type heavily doped region is in contact with the insulating dielectric layer. Multiple second gate dielectric layers and second polysilicon layers are formed on the cell region, each second gate dielectric layer encapsulating the corresponding second polysilicon layer, and the second gate dielectric layer is located on the N-type epitaxial layer between adjacent third P pillars; A metal layer covering the terminal transition region and the cell region.

2. The superjunction MOS device as described in claim 1, characterized in that, The first P-type ring region is disposed on the N-type epitaxial layer between adjacent first P-pillars, and the first P-type ring is in contact with the insulating dielectric layer.

3. The superjunction MOS device as described in claim 2, characterized in that, The width of the first P-type ring region gradually increases from the first side to the second side of the N-type epitaxial layer.

4. The superjunction MOS device as described in claim 1, characterized in that, The first P-type heavily doped region extends below the insulating dielectric layer, and the first P-type heavily doped region contacts at least one of the first P-pillars on the second side of the terminal withstand voltage region.

5. The superjunction MOS device as described in claim 1, characterized in that, The width of the first P-pillar is smaller than the width of the second P-pillar.

6. The superjunction MOS device as described in claim 5, characterized in that, The width of the second P-pillar is smaller than the width of the third P-pillar.

7. The superjunction MOS device according to any one of claims 1-6, characterized in that, A stop ring is provided on the first side of the terminal withstand voltage zone, and the insulating dielectric layer is not provided on the stop ring. The plurality of first P pillars on the first side of the terminal withstand voltage zone are in contact with the insulating dielectric layer. A first P-type ring zone is provided between the first P pillars on the second side of the terminal withstand voltage zone and the insulating dielectric layer.

8. The superjunction MOS device according to any one of claims 1-6, characterized in that, The depth of the plurality of first P pillars gradually increases from the first side to the second side of the N-type epitaxial layer.

9. A method for fabricating a superjunction MOS device as described in any one of claims 1-8, characterized in that, The preparation method includes: An N-type epitaxial layer is grown on the front side of the substrate; wherein the N-type epitaxial layer is divided from the first side to the second side into a terminal withstand voltage region, a terminal transition region, and a cell region; P-pillars are formed at intervals in the N-type epitaxial layer; wherein, the terminal withstand voltage region includes a plurality of first P-pillars, the terminal transition region includes a plurality of second P-pillars, and the cell region includes a plurality of third P-pillars; A first P-type ring region and an insulating dielectric layer are sequentially formed on the terminal withstand voltage region, and the surface of the cell region is etched so that the surface of the cell region is lower than the surface of the terminal withstand voltage region, and the first P-type base region and the first P-type ring region form a first included angle. A first gate dielectric layer and a first polysilicon layer are formed on the insulating dielectric layer, and a plurality of second gate dielectric layers and a plurality of second polysilicon layers are formed on the cell region; wherein, the first P-type ring region is located between the N-type epitaxial layer and the first gate dielectric layer, the first gate dielectric layer encapsulates the first polysilicon layer, the first gate dielectric layer is located on the insulating dielectric layer, each second gate dielectric layer encapsulates the corresponding second polysilicon layer, and the second gate dielectric layer is located on the N-type epitaxial layer between adjacent third P pillars; A first P-type base region is formed in the terminal transition region, and a second P-type base region is formed in the cell region; wherein, the second P-type base region is formed on the corresponding third P pillar, and a second P-type heavily doped region and a second N-type heavily doped region located on both sides of the second P-type heavily doped region are formed on each second P-type base region, and a first P-type heavily doped region and a first N-type heavily doped region are formed on the first P-type base region; A metal layer is formed covering the terminal transition region and the cell region.

10. A chip, characterized in that, Including the superjunction MOS device as described in any one of claims 1-8.

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