Epitaxial method for improving performance of SJ device
By employing epitaxial methods involving temperature field calibration and optimized doping levels, the consistency problem of BV and Ron in SJ devices was solved, thereby improving the reliability and yield of SJ MOS.
Patent Information
- Application Number
- CN202610189129.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-02-10
- Publication Date
- 2026-05-29
AI Technical Summary
In traditional SJ stacked epitaxial processes, edge self-doping, lack of epitaxial temperature control compensation, and inaccurate thermal budget control lead to variations in P/N column concentration and width in different regions within the wafer. This results in poor consistency between BV and Ron, and a high slip line occurrence rate, affecting the reliability of SJ Mos.
By adjusting the temperature field distribution of the wafer through temperature field calibration, and combining the ion implantation amount and heat treatment time, the doping amount is optimized, the thermal budget and epitaxial growth process are controlled, and the temperature field distribution gradient control is achieved. This reduces the difference in doping amount between the center and the edge regions, and ensures the width of P/N pillars and the uniformity of doping in the wafer after heat treatment.
This improved the consistency of the breakdown voltage and on-resistance of SJ MOSFETs, reduced the probability of slip lines, and improved the overall yield of the devices.
Smart Images
Figure CN122121241A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology, specifically relating to an epitaxial method for improving the performance of SJ (Super Junction) devices. Background Technology
[0002] Traditional SJ stacked epitaxial processes generally suffer from varying P / N pillar concentrations and widths in different regions of the wafer due to edge self-doping, lack of epitaxial temperature control compensation, and inaccurate thermal budget control. This leads to poor consistency in BV (Breakdown Voltage) and Ron (Resistance On). Furthermore, with the increase in epitaxial cycles, the occurrence rate of slip lines increases significantly, which in turn affects the overall reliability of the SJ MOSFET (Superjunction Transistor). Summary of the Invention
[0003] To address the aforementioned problems in the prior art, this invention provides an epitaxial method for improving the performance of SJ devices.
[0004] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides an epitaxial method for improving the performance of an SJ device, the method comprising: Perform temperature field calibration to obtain the temperature field distribution of the wafer after temperature field calibration; The estimated P / N pillar width is obtained based on the ion implantation amount and implantation window of the wafer to be processed, and the thermal budget is obtained based on the estimated P / N pillar width. The heat treatment time and epitaxial deposition time are determined based on the aforementioned thermal budget; The wafer to be processed is subjected to heat treatment under the wafer temperature field distribution according to the heat treatment time, so as to obtain the heat-treated wafer; Epitaxial growth is performed on the heat-treated wafer based on the auxiliary doping pipeline, the wafer temperature field distribution, and the epitaxial deposition time to obtain the epitaxial wafer.
[0005] Optionally, the temperature field distribution of the wafer after temperature field calibration shows a gradual decreasing trend from the center region to the edge region, with the temperature field temperature in the center region being higher and the temperature field temperature in the edge region being lower. The temperature difference between the temperature field in the center region and the temperature field in the edge region ranges from 5℃ to 10℃.
[0006] Optionally, the step of performing temperature field calibration to obtain the calibrated wafer temperature field distribution includes: Temperature field calibration was performed using an ion implantation sheet to obtain an ion implantation sheet with the target resistance distribution, confirming that the temperature field calibration was completed. The temperature field distribution of the wafer after temperature field calibration is obtained.
[0007] Optionally, the temperature field distribution of the wafer after temperature field calibration can be adjusted by adjusting the power ratio of the temperature zone inside the reaction chamber of the ion implantation wafer.
[0008] Optionally, after performing temperature field calibration to obtain the calibrated wafer temperature field distribution, the method further includes: The substrate of the wafer to be processed is etched using HCl to obtain the etched substrate; The etched substrate is heat-treated with H2 and then silicon-coated to obtain the finished substrate.
[0009] Optionally, the process temperature for temperature field calibration is 1100℃-1180℃; the process temperature for heat treatment of the wafer to be processed under the wafer temperature field distribution is 1100℃-1200℃.
[0010] Optionally, when performing epitaxial deposition on the heat-treated wafer, the main reactive gas introduced is trichlorosilane with a flow rate of 3 slm-10 slm; the doping gas is phosphine with a flow rate of 30 sccm-300 sccm.
[0011] Optionally, the auxiliary doping pipeline is used to optimize the doping amount in the central region of the heat-treated wafer to reduce the difference in doping amount between the central region and the edge region.
[0012] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, the present invention controls the temperature field distribution of the wafer and establishes a strict temperature distribution gradient. At the same time, by adjusting the doping amount and heat treatment time in the wafer to be processed, the difference between SJ, Mos, BV and Ron in the same wafer can be reduced and the BV can be improved to a certain extent. Moreover, due to the strict temperature field control, the probability of slip lines occurring is extremely low, thereby improving the overall yield of the device.
[0013] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0014] Figure 1 This is a flowchart of an epitaxial method for improving the performance of an SJ device provided in an embodiment of the present invention. Detailed Implementation
[0015] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0016] Figure 1 This is a flowchart of an epitaxial method for improving the performance of an SJ device provided in an embodiment of the present invention, such as... Figure 1 As shown, the method may include the following steps: S101. Perform temperature field calibration to obtain the temperature field distribution of the wafer after temperature field calibration.
[0017] Optionally, S101 may include: Temperature field calibration was performed using an ion implantation sheet to obtain an ion implantation sheet with the target resistance distribution, confirming that the temperature field calibration was completed. The temperature field distribution of the wafer after temperature field calibration is obtained.
[0018] Optionally, the temperature field distribution of the wafer after temperature field calibration shows a gradual decreasing trend from the center region to the edge region, with the temperature field temperature in the center region being higher and the temperature field temperature in the edge region being lower. The temperature difference between the temperature field in the center region and the temperature field in the edge region ranges from 5℃ to 10℃.
[0019] Optionally, the temperature field distribution of the wafer after temperature field calibration can be adjusted by adjusting the power ratio of the temperature zone inside the reaction chamber of the ion implantation wafer.
[0020] For example, during temperature field calibration, an ion implantation wafer is used. When the ion implantation wafer achieves the target resistance distribution, the temperature field calibration is considered complete, yielding the calibrated wafer temperature field distribution. This calibrated wafer temperature field distribution corresponds to the process temperature (1100-1180℃) required for epitaxial growth. It is worth noting that the required process temperature for temperature field calibration is determined based on the resistance of the ion implantation wafer. For example, the ion implantation wafer used for temperature control in this invention is 420 ohms. cm -2 The corresponding temperature is 1150℃; within the range of 1150℃±20℃, it satisfies approximately 1.5 ohms. cm -2 Corresponding to a linear relationship of 1℃, temperature and resistance are negatively correlated; that is, the higher the resistance, the lower the temperature. The trend of the wafer temperature field distribution after temperature field calibration is confirmed to be a gradual decrease from the central region, 1 / 3 radius, 2 / 3 radius, to the edge region. The temperature difference between the central and edge regions ranges from 5℃ to 10℃, meaning the corresponding resistance difference between the central and edge regions is approximately 7.5 ohms. cm -2 -15ohm cm -2 The temperature distribution adjustment method involves adjusting the temperature-power ratio within the ion implantation wafer. Specifically, the adjustment range for the total power and inner ring power ratio is: total power 50±10 / upper inner ring power 50±10 / lower inner ring power 50±10, with the total power being 100%. Lowering the inner ring power will increase the outer ring power, resulting in a corresponding increase in the outer ring temperature. For example, if the current ratio of total power to inner ring power is 50 / 50 / 50, when it is necessary to increase the outer ring temperature, the power of the upper / lower inner rings can be simultaneously reduced to 50 / 45 / 45.
[0021] Optionally, after S101, the method of the present invention may further include: The substrate of the wafer to be processed is etched using HCl to obtain the etched substrate; The etched substrate is heat-treated with H2 and then silicon-coated to obtain the finished substrate.
[0022] For example, the substrate of the wafer to be processed can first be etched with HCl at 1190℃-1200℃ to remove residual impurities. Then, the etched substrate is heat-treated with H2 and followed by silicon encapsulation to obtain a processed substrate, which provides a good environment for subsequent processes. After the above pretreatment, the metal contamination content on the substrate surface is reduced to below 5E10 atoms / cm² and the oxygen content is reduced to below 1E13 atoms / cm², which can be verified by SIMS (Secondary Ion Mass Spectrometry). The surface Ra (Roughness Average) value of the processed substrate is less than 0.5nm, and the surface exhibits stable hydrophobic properties. Using this pretreated substrate for subsequent epitaxial growth can reduce the defect density in the epitaxial layer by at least one order of magnitude and significantly improve the uniformity of inter-wafer resistance within the wafer. It is worth mentioning that, as a substitute or supplement to HCl, gases with cleaning capabilities such as Cl2 and SF6 can be used for etching; after H2 heat treatment, the base temperature can be monitored by an in-situ optical thermometer to ensure that it is stable within ±5℃ of the target value; and / or, throughout the process, the partial pressure of H2O and O2 in the chamber can be monitored by a mass spectrometer to ensure that it drops below 1E-6 Torr to confirm the heat treatment effect.
[0023] S102. Based on the ion implantation amount and implantation window of the wafer to be processed, the estimated P / N pillar width is obtained, and the thermal budget is obtained based on the estimated P / N pillar width.
[0024] S103. Determine the heat treatment time and epitaxial deposition time based on the thermal budget.
[0025] Understandably, the heat treatment time and epitaxial deposition are precisely matched to the P / N pillar width, ion implantation amount, and implantation window. For example, after photolithography, the ion implantation window size of the P-shaped pillar is 4 μm, that is, the distance between adjacent P-shaped pillars is 3.8 μm (N pillar width is 3.8 μm), and the ion (boron ion) implantation amount is 3.5E16-4E16. When the heat treatment time is 30s, the implanted ions cannot push the junction depth to produce a completely depleted layer in the N epitaxial layer, and some majority carriers are still eigenvalued in the N epitaxial layer. Therefore, with the same ion implantation window size of the P-shaped pillar, slightly increasing the heat treatment time to 40s and adjusting the ion implantation amount (3.5E16-4E16, this operation depends on the situation and is not necessary) will increase the junction depth, which can completely deplete the majority carriers in the N epitaxial layer, thereby improving the breakdown voltage.
[0026] For example, if the width of the P-pillar implantation window is 2.8 μm and the distance between the lithographic windows of adjacent P-pillars is 3.5 μm, this means that the distance between adjacent P-pillars is 3.5 μm when they are not activated for push-in. As the number of epitaxial cycles increases, the overall heat treatment time increases. As a result, the P-pillars become wider after push-in, and the distance between adjacent P-pillars gradually decreases. The decrease in distance leads to a reduction in the width of the N-pillars in the middle of the adjacent P-pillars. When the device is off, the depletion layer is more likely to extend to the center of the N-pillars, thereby increasing the BV. If the distance between P-pillars is 3.5 μm, the corresponding EPI (Epitaxy) single-layer heat treatment time needs to be <45s and the deposition time <120s. If the distance between P-pillars is wider, the corresponding time can be extended, and if it is narrower, it can be shortened. The specific time can be flexibly adjusted according to different products.
[0027] S104. The wafer to be processed is subjected to heat treatment under the wafer temperature field distribution according to the heat treatment time to obtain the heat-treated wafer.
[0028] For example, the process temperature for heat treatment of the wafer under the wafer temperature field distribution is 1100℃-1200℃.
[0029] S105. Based on the auxiliary doping pipeline, wafer temperature field distribution and epitaxial deposition time, the heat-treated wafer is epitaxially grown to obtain the epitaxial wafer.
[0030] Among them, the auxiliary doping pipeline is used to optimize the doping amount in the central region of the wafer after heat treatment, so as to reduce the difference in doping amount between the central region and the edge region.
[0031] Understandably, after heat treatment, the wafer undergoes epitaxial growth within the range of 1100℃-1180℃±0.5℃. Due to the influence of self-doping in the edge region, the doping amount in the edge region will be greater than that in the center region, resulting in a lower risk of breakdown voltage and on-resistance in the edge region compared to the overall region. Therefore, the breakdown voltage and on-resistance in the edge region can be adjusted by adjusting the temperature field distribution. Furthermore, the doping amount in the center region of the wafer after heat treatment can be optimized using doping pipelines to reduce the difference in doping amount between the center region and the edge region.
[0032] For example, when performing epitaxial deposition on a heat-treated wafer, the main reactive gas is trichlorosilane with a flow rate of 3 slm-10 slm; the doping gas is phosphine with a flow rate of 30 sccm-300 sccm.
[0033] In one embodiment, the heat treatment temperature is set to 1180°C, the heat treatment time to 25 seconds, the first layer epitaxial deposition time to 120 seconds, the trichlorosilane flow rate to 7.8 slm, the 50 ppm phosphine dopant gas flow rate to 120 sccm, the auxiliary doping pipeline flow rate to 30 sccm, and the total power to inner ring power ratio to 52:55:55. The second to seventh layers epitaxial deposition time is 180 seconds, the trichlorosilane flow rate to 5.6 slm, the 100 ppm phosphine dopant gas flow rate to 30 sccm, the auxiliary doping flow rate to 15 sccm, and the total power to inner ring power ratio to 52:55:55. Based on mass production data, under conditions of ion implantation concentration of 3.9E16 and P-type column width, the breakdown voltage can be increased by 3%, the slip line occurrence rate reduced by 30%, and the uniformity of breakdown voltage and on-resistance improved by approximately 25%.
[0034] In another embodiment, the heat treatment temperature was determined to be 1190°C, the heat treatment time to be 15 seconds, the first layer epitaxial deposition time to be 100 seconds, the trichlorosilane flow rate to be 7.3 slm, the 50 ppm phosphine dopant gas flow rate to be 105 sccm, the auxiliary doping flow rate to be 27 sccm, and the total power to inner ring power ratio to be 49:53:53; the second to seventh layer epitaxial deposition time to be 180 seconds, the trichlorosilane flow rate to be 5.45 slm, the 100 ppm phosphine dopant gas flow rate to be 30 sccm, the auxiliary doping flow rate to be 15 sccm, and the power ratio to be 50:51:51. Based on mass production data, under the conditions of ion implantation concentration of 3.8E16 and P-type column width, the breakdown voltage can be increased by 5.5%, the slip line occurrence rate reduced by 40%, and the uniformity of breakdown voltage and on-resistance improved by approximately 20%.
[0035] In another embodiment, the heat treatment temperature was set at 1150°C, the heat treatment time at 55 seconds, the first layer epitaxial deposition time at 105 seconds, the trichlorosilane flow rate at 7.65 slm, the 50 ppm phosphine dopant flow rate at 98 sccm, the auxiliary doping pipeline flow rate at 35 sccm, and the power ratio at 57:53:53; the second to ninth layers epitaxial deposition time was 180 seconds, the trichlorosilane flow rate at 5.77 slm, the 50 ppm phosphine dopant flow rate at 15 sccm, the auxiliary doping flow rate at 15 sccm, and the power ratio at 50:51:51. Based on the data, under the conditions of ion implantation concentration of 3.6E16 and P-type column width, the breakdown voltage could be increased by 2.8%, the slip line occurrence rate reduced by 38%, and the uniformity of breakdown voltage and on-resistance improved by approximately 27%.
[0036] This invention employs a temperature distribution trend with a higher temperature in the central region and a lower temperature in the peripheral region, along with a quantitative method for the distribution gradient, to ensure optimal wafer temperature field distribution. This significantly reduces the probability of slip lines caused by thermal stress concentration, thereby improving product yield. Using a temperature field calibrated in conjunction with an auxiliary doping pipeline for epitaxial processing can greatly improve the consistency of parameters such as BV and Ron of each SJMo within the wafer. Based on the P / N pillar width and ion implantation distribution, the heat treatment time can be precisely controlled. By controlling the heat budget and boron implantation amount, complete depletion of the N pillars between P / N / P pillars can be achieved, greatly improving the BV parameter performance of SJMo.
[0037] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0038] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure of the specification in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0039] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. An epitaxial method for improving the performance of SJ devices, characterized in that, The method includes: Perform temperature field calibration to obtain the temperature field distribution of the wafer after temperature field calibration; The estimated P / N pillar width is obtained based on the ion implantation amount and implantation window of the wafer to be processed, and the thermal budget is obtained based on the estimated P / N pillar width. The heat treatment time and epitaxial deposition time are determined based on the aforementioned thermal budget; The wafer to be processed is subjected to heat treatment under the wafer temperature field distribution according to the heat treatment time, so as to obtain the heat-treated wafer; Epitaxial growth is performed on the heat-treated wafer based on the auxiliary doping pipeline, the wafer temperature field distribution, and the epitaxial deposition time to obtain the epitaxial wafer.
2. The epitaxial method for improving the performance of SJ devices according to claim 1, characterized in that, The temperature field distribution of the wafer after temperature field calibration shows a gradual decreasing trend from the center region to the edge region, with the temperature field temperature being higher in the center region and lower in the edge region. The temperature difference between the temperature field in the center region and the temperature field in the edge region ranges from 5℃ to 10℃.
3. The epitaxial method for improving the performance of SJ devices according to claim 1, characterized in that, The process of performing temperature field calibration to obtain the calibrated wafer temperature field distribution includes: Temperature field calibration was performed using an ion implantation sheet to obtain an ion implantation sheet with the target resistance distribution, confirming that the temperature field calibration was completed. The temperature field distribution of the wafer after temperature field calibration is obtained.
4. The epitaxial method for improving the performance of SJ devices according to claim 2, characterized in that, The temperature field distribution of the wafer after temperature field calibration is adjusted by adjusting the power ratio of the temperature zone inside the reaction chamber of the ion implantation wafer.
5. The epitaxial method for improving the performance of SJ devices according to claim 1, characterized in that, After performing temperature field calibration to obtain the calibrated wafer temperature field distribution, the method further includes: The substrate of the wafer to be processed is etched using HCl to obtain the etched substrate; The etched substrate is heat-treated with H2 and then silicon-coated to obtain the finished substrate.
6. The epitaxial method for improving the performance of SJ devices according to claim 1, characterized in that, The process temperature for temperature field calibration is 1100℃-1180℃; the process temperature for heat treatment of the wafer to be processed under the wafer temperature field distribution is 1100℃-1200℃.
7. The epitaxial method for improving the performance of SJ devices according to claim 1, characterized in that, When performing epitaxial deposition on the heat-treated wafer, the main reactive gas introduced is trichlorosilane, with a flow rate of 3 slm-10 slm; the doping gas is phosphine, with a flow rate of 30 sccm-300 sccm.
8. The epitaxial method for improving the performance of SJ devices according to claim 1, characterized in that, The auxiliary doping pipeline is used to optimize the doping amount in the central region of the heat-treated wafer, so as to reduce the difference in doping amount between the central region and the edge region.