Display substrate, spliced display panel and display device

Abstract

A display substrate, comprising: a substrate substrate comprising at least one side edge and a display area; a plurality of pixel units arranged in the display area, the plurality of pixel units comprising first pixel units, second pixel units and third pixel units in the display area, wherein the plurality of second pixel units are located on one side of the plurality of first pixel units close to the side edge, an edge of the plurality of second pixel units comprises the side edge, the third pixel units are located between the first pixel units and the second pixel units, and the third pixel units are adjacent to the second pixel units; and a plurality of light-emitting diode chips arranged on the substrate substrate, the plurality of light-emitting diode chips comprising first light-emitting diode chips and second light-emitting diode chips, wherein the first light-emitting diode chips are located in the first pixel units, a part of the second light-emitting diode chips is located in the second pixel units, and other parts of the second light-emitting diode chips are located in the third pixel units.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 202180001624.3 (filed on June 25, 2021; invention title: display substrate, splicing display panel and display device). Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display substrate, a splicing display panel, and a display device. Background Technology

[0003] Light-emitting diode (LED) technology has been developing for nearly thirty years, and its applications have continued to expand. For example, it can be used in the display field as a backlight for display devices or as an LED display screen. With technological advancements, Mini LED (Mini Light Emitting Diode) and Micro LED (Micro Light Emitting Diode) display technologies have gradually become a hot topic in display devices. LEDs have advantages such as self-illumination, wide viewing angle, fast response, simple structure, and long lifespan. Moreover, Mini LED / Micro LED displays can achieve large-size displays through splicing, so they have good market prospects. Currently, the structure and manufacturing process of Mini LED / Micro LED display devices are one of the important topics of research and development.

[0004] The information disclosed in this section is only for understanding the background of the inventive concept of this disclosure, and therefore may include information that does not constitute prior art. Summary of the Invention

[0005] In one aspect, a display substrate is provided, comprising: a substrate including at least one side edge and a display area; a plurality of pixel units disposed in the display area, the plurality of pixel units including a first pixel unit, a second pixel unit, and a third pixel unit located in the display area, wherein the plurality of second pixel units are located on the side of the plurality of first pixel units near the side edge, the edges of the plurality of second pixel units include the side edge, the third pixel unit is located between the first pixel unit and the second pixel unit, and the third pixel unit is adjacent to the second pixel unit; and a plurality of light-emitting diode (LED) chips disposed on the substrate, the plurality of LED chips including a first LED chip and a second LED chip, wherein the first LED chip is located within the first pixel unit, a portion of the second LED chip is located within the second pixel unit, and other portions of the second LED chip are located within the third pixel unit.

[0006] According to some exemplary embodiments, the shortest distance between the second light-emitting diode chip and the boundary of the second pixel unit where a portion of the second light-emitting diode chip is located is greater than the shortest distance between the first light-emitting diode chip and the edge of the first pixel unit where the first light-emitting diode chip is located.

[0007] According to some exemplary embodiments, the area of ​​the portion of the second light-emitting diode chip located within the second pixel unit projected onto the substrate is smaller than the area of ​​the first light-emitting diode chip projected onto the substrate.

[0008] According to some exemplary embodiments, the area of ​​the orthographic projection of the second light-emitting diode chip on the substrate is greater than the area of ​​the orthographic projection of the first light-emitting diode chip on the substrate, and the area of ​​the orthographic projection of the second light-emitting diode chip on the substrate is less than twice the area of ​​the orthographic projection of the first light-emitting diode chip on the substrate.

[0009] According to some exemplary embodiments, the plurality of pixel units further includes a fourth pixel unit, a fifth pixel unit, a sixth pixel unit, and a seventh pixel unit located in the display area. The edge of the fourth pixel unit includes a first side edge and a second side edge that intersect each other. The fifth pixel unit, the sixth pixel unit, and the seventh pixel unit are respectively adjacent to the fourth pixel unit. The plurality of light-emitting diode chips further includes a third light-emitting diode chip. A portion of the third light-emitting diode chip is located within the fourth pixel unit, and other portions of the third light-emitting diode chip are respectively located within the fifth pixel unit, the sixth pixel unit, and the seventh pixel unit.

[0010] According to some exemplary embodiments, the shortest distance between the third light-emitting diode chip and the boundary of the third pixel unit where a portion of the third light-emitting diode chip is located is greater than the shortest distance between the first light-emitting diode chip and the edge of the first pixel unit where the first light-emitting diode chip is located.

[0011] According to some exemplary embodiments, the area of ​​the portion of the third light-emitting diode chip located within the fourth pixel unit projected onto the substrate is smaller than the area of ​​the first light-emitting diode chip projected onto the substrate.

[0012] According to some exemplary embodiments, the area of ​​the orthogonal projection of the third light-emitting diode chip on the substrate is greater than the area of ​​the orthogonal projection of the first light-emitting diode chip on the substrate, and the area of ​​the orthogonal projection of the third light-emitting diode chip on the substrate is less than four times the area of ​​the orthogonal projection of the first light-emitting diode chip on the substrate.

[0013] According to some exemplary embodiments, the light-emitting diode chip includes a substrate and a plurality of light-emitting regions, a plurality of anodes and a cathode disposed on the substrate, wherein the plurality of light-emitting regions and the plurality of anodes correspond one-to-one and the plurality of light-emitting regions are spaced apart from each other.

[0014] According to some exemplary embodiments, the light-emitting diode chip further includes a cathode pad electrically connected to the cathode, and the cathode pad and the plurality of light-emitting areas are spaced apart from each other.

[0015] According to some exemplary embodiments, some of the plurality of light-emitting regions of the second light-emitting diode chip are located within the second pixel unit, and others of the plurality of light-emitting regions are located within the third pixel unit, wherein the number of light-emitting regions of the second light-emitting diode chip is greater than the number of light-emitting regions of the first light-emitting diode chip.

[0016] According to some exemplary embodiments, some of the multiple light-emitting areas of the third light-emitting diode chip are located within the fourth pixel unit, and other multiple light-emitting areas are located within the fifth pixel unit, the sixth pixel unit, and the seventh pixel unit, respectively. The number of light-emitting areas of the third light-emitting diode chip is greater than the number of light-emitting areas of the second light-emitting diode chip.

[0017] According to some exemplary embodiments, the orthographic projection of the cathode pad of the second light-emitting diode chip onto the substrate is located at the junction of the second pixel unit and the third pixel unit.

[0018] According to some exemplary embodiments, the orthogonal projection of the cathode pad of the third light-emitting diode chip onto the substrate is located at the intersection of the fourth pixel unit, the fifth pixel unit, the sixth pixel unit, and the seventh pixel unit.

[0019] According to some exemplary embodiments, the distance between the multiple light-emitting areas of the light-emitting diode chip is more than 8 micrometers.

[0020] According to some exemplary embodiments, the display substrate further includes a wiring area located at at least one of the side edges; the display substrate further includes a plurality of traces located in the wiring area, the plurality of traces being used to provide electrical signals to the plurality of light-emitting diode chips respectively.

[0021] According to some exemplary embodiments, the display substrate further includes a plurality of light conversion units, the orthographic projections of the plurality of light conversion units on the substrate and the orthographic projections of the plurality of light-emitting areas on the substrate respectively at least partially overlap.

[0022] In another aspect, a splicing display device is provided, comprising: a plurality of first display substrates and a plurality of second display substrates, wherein the plurality of first display substrates and the plurality of second display substrates are respectively display substrates as described above, wherein the side edge of the first display substrate is spliced ​​with the side edge of the second display substrate along a first direction, and / or the side edge of the first display substrate is spliced ​​with the side edge of the second display substrate along a second direction, wherein the first direction and the second direction intersect.

[0023] According to some exemplary embodiments, the first display substrate and the second display substrate are symmetrically distributed along the splicing point, which includes the side edge of the first display substrate near the second substrate and the side edge of the second display substrate near the first display substrate.

[0024] In another aspect, a display device is provided, comprising: a splicing display panel as described above; and a driving circuit for driving the splicing display panel. Attached Figure Description

[0025] Other objects and advantages of this disclosure will become apparent from the following description of the disclosure with reference to the accompanying drawings, and will help to provide a comprehensive understanding of the disclosure.

[0026] Figure 1 This is a plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0027] Figure 2 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0028] Figure 3 This is a partial enlarged view of a first light-emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure;

[0029] Figure 4 This is a partial enlarged view of a second or fourth light-emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure;

[0030] Figure 5 This is a partial enlarged view of a third light-emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure;

[0031] Figure 6 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 3 , Figure 4 or Figure 5 A cross-sectional view taken from line AA' in the middle;

[0032] Figure 7 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 2 A cross-sectional view taken from line BB' in the middle;

[0033] Figures 8A to 8G This is a schematic cross-sectional view illustrating the structure formed after some steps of the manufacturing method of the display substrate are performed;

[0034] Figure 9 This is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure;

[0035] Figure 10 The display panel is based on some exemplary embodiments of this disclosure. Figure 5 A cross-sectional view taken from line CC' in the diagram;

[0036] Figure 11A and Figure 11B These are partial plan views of a display panel according to other exemplary embodiments of the present disclosure;

[0037] Figure 12 The display substrate according to some exemplary embodiments of the present disclosure is in Figure 2 A magnified view of part I in the image; and

[0038] Figure 13 A schematic plan view of a third light-emitting diode chip according to some exemplary embodiments of the present disclosure is shown.

[0039] It should be noted that, for clarity, the dimensions of layers, structures, or regions in the accompanying drawings used to describe embodiments of this disclosure may be enlarged or reduced; that is, these drawings are not drawn to actual scale. Detailed Implementation

[0040] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and apparatuses are shown in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0041] In the accompanying drawings, the dimensions and relative dimensions of the elements may be enlarged for clarity and / or descriptive purposes. Thus, the dimensions and relative dimensions of the individual elements are not necessarily limited to those shown in the drawings. When exemplary embodiments can be implemented differently, the specific process sequence may be performed differently than the order described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of description. Furthermore, the same reference numerals denote the same elements.

[0042] When an element is described as being "on" another element, "connected to" another element, or "attached to" another element, the element may be directly on, directly connected to, or directly attached to the other element, or there may be intermediate elements. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly attached to" another element, there are no intermediate elements. Other terms and / or expressions used to describe relationships between elements should be interpreted in a similar manner, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connection" can refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. Moreover, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the listed related items.

[0043] It should be understood that although the terms first, second, etc., may be used herein to describe different elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, a first element may be named a second element, and similarly, a second element may be named a first element.

[0044] In this paper, inorganic light-emitting diodes refer to light-emitting elements made of inorganic materials, where LED represents an inorganic light-emitting element distinct from OLED. Specifically, inorganic light-emitting elements can include miniature light-emitting diodes (Mini LEDs) and micro light-emitting diodes (Micro LEDs). Micro LEDs are ultra-small light-emitting diodes with a die size of less than 100 micrometers, while miniature LEDs are small light-emitting diodes with a die size between Micro LEDs and traditional LEDs. For example, the die size of a Mini LED can be between 100 and 300 micrometers, while the die size of a Micro LED can be between 10 and 100 micrometers.

[0045] Some exemplary embodiments of this disclosure provide a display substrate and a display panel and display device including the display substrate. For example, a display substrate includes: a substrate having at least one side edge and a display area; a plurality of pixel units disposed in the display area, the plurality of pixel units including a first pixel unit, a second pixel unit, and a third pixel unit located in the display area, wherein the plurality of second pixel units are located on the side of the plurality of first pixel units near the side edge, the edges of the plurality of second pixel units include the side edge, the third pixel unit is located between the first pixel unit and the second pixel unit, and the third pixel unit is adjacent to the second pixel unit; and a plurality of light-emitting diode (LED) chips disposed on the substrate, the plurality of LED chips including a first LED chip and a second LED chip, wherein the first LED chip is located within the first pixel unit, a portion of the second LED chip is located within the second pixel unit, and other portions of the second LED chip are located within the third pixel unit.

[0046] For example, some embodiments of this disclosure provide a display substrate, including: a substrate including a first side edge and a first region away from the first side edge; a plurality of pixel units disposed on the substrate, the plurality of pixel units including a first pixel unit located in the first region and a second pixel unit near the first side edge, the first pixel unit being located on the side of the second pixel unit away from the first side edge; and a plurality of light-emitting diode (LED) chips disposed on the substrate, the plurality of LED chips including a first LED chip and a second LED chip, wherein the first LED chip is located within the first pixel unit, and at least a portion of the second LED chip is located within the second pixel unit, wherein the second pixel unit includes a first LED chip and a second LED chip. The second pixel unit boundary is near the first side edge, the second light-emitting diode chip includes a second chip side near the first side edge, the vertical distance between the orthographic projection of the second chip side on the substrate and the orthographic projection of the second pixel unit boundary on the substrate is greater than or equal to a predetermined distance; and the first pixel unit includes a first pixel unit boundary parallel to the first side edge, the first light-emitting diode chip has a first chip side near the first pixel unit boundary, the vertical distance between the orthographic projection of the first chip side on the substrate and the orthographic projection of the first pixel unit boundary on the substrate is less than the vertical distance between the orthographic projection of the second chip side on the substrate and the orthographic projection of the second pixel unit boundary on the substrate.

[0047] Thus, in the embodiments disclosed herein, a larger splicing distance can be reserved at the side edge of the display substrate, which is beneficial for splicing multiple display substrates.

[0048] Wire bonding is a process that uses heat, pressure, or ultrasonic energy to tightly bond metal bonding wires to substrate pads. For example, in IC packaging, wire bonding can be used to connect semiconductor chip bonding pads to I / O bonding wires in microelectronic packages or metal wiring bonding pads on the substrate using thin metal wires. The principle of wire bonding is to use heating, pressure, or ultrasound to break down the oxide layer and contaminants on the surface to be bonded, causing plastic deformation, which allows the metal bonding wires to come into close contact with the surface to be bonded, reaching the range of interatomic attraction and causing interfacial atomic diffusion to form a bonding point.

[0049] Figure 1 This is a plan view of a display substrate according to some exemplary embodiments of the present disclosure. (See reference 1) Figure 1The display substrate may include: a substrate 1; a plurality of pixel units PX disposed on the substrate 1; and a plurality of light-emitting diode (LED) chips 5 disposed on the substrate 1. In embodiments of this disclosure, the plurality of LED chips 5 includes a first LED chip 51 and a second LED chip 52. For example, the second LED chip 52 is disposed in a pixel unit near the side edge of the display substrate, and the first LED chip 51 is disposed in a pixel unit away from the side edge of the display substrate. In embodiments of this disclosure, the display substrate can be used as a single display substrate for a spliced ​​display panel. For example, in… Figure 1 In this embodiment, the splicing area PJ is schematically shown on the upper, right, and lower sides of the display substrate. The second light-emitting diode chip 52 may be disposed in the pixel unit PX near the splicing area PJ.

[0050] Continue to refer to Figure 1 The plurality of light-emitting diode (LED) chips 5 includes a second LED chip 52 and a fourth LED chip 53. For example, the second LED chip 52 can be disposed in a pixel unit in the splicing area near the right edge, and the fourth LED chip 53 can be disposed in a pixel unit in the splicing area near the upper and lower edges. Optionally, the specifications and dimensions of the second LED chip 52 and the fourth LED chip 53 can be substantially the same; however, when disposed on the substrate 1, the second LED chip 52 can be rotated relative to the fourth LED chip 53 by a certain angle, for example, 90°.

[0051] It should be noted that, in this article, the specifications and dimensions of the second light-emitting diode chip 52 and the fourth light-emitting diode chip 53 can be basically the same. Therefore, in other parts, for the sake of convenience, the second light-emitting diode chip 52 and the fourth light-emitting diode chip 53 can be collectively referred to as the second light-emitting diode chip.

[0052] Continue to refer to Figure 1 The plurality of light-emitting diode chips 5 includes a third light-emitting diode chip 54. For example, the third light-emitting diode chip 54 can be disposed in pixel units near the splicing area and near the corners of the display substrate. Figure 1 In the illustrated embodiment, the third light-emitting diode chip 54 can be disposed at the upper right corner and the lower right corner of the display substrate, respectively.

[0053] Figure 2 This is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure. Figure 3 This is a partial enlarged view of a first light-emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure. Figure 4This is a partially enlarged view of a second or fourth light-emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure. Figure 5 This is a partial enlarged view of a third light-emitting diode chip included in a display substrate according to some exemplary embodiments of the present disclosure. Figure 6 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 3 , Figure 4 or Figure 5 The cross-sectional view taken from line AA' in the diagram.

[0054] Combined with reference Figures 1 to 6 The display substrate may include: a substrate 1, the substrate 1 including a first side edge 11 and a first region AA away from the first side edge 11; a plurality of pixel units PX disposed on the substrate 1, the plurality of pixel units PX including a first pixel unit PX1 located in the first region AA and a second pixel unit PX2 near the first side edge 11, the first pixel unit PX1 being located on the side of the second pixel unit PX2 away from the first side edge 11; and a plurality of light-emitting diode chips 5 disposed on the substrate 1, the plurality of light-emitting diode chips 5 including a first light-emitting diode chip 51 and a second light-emitting diode chip 52, wherein the first light-emitting diode chip 51 is located within the first pixel unit PX1, and at least a portion of the second light-emitting diode chip 52 is located within the second pixel unit PX2.

[0055] It should be noted that, unless otherwise stated, in this document, the term "side edge" refers to the side surface of a substrate, component, or element, for example... Figure 1 or Figure 2 In the plan view, the "side edge" is shown as a line, for example, the first side edge 11 is the leftmost line.

[0056] like Figure 2 As shown, the second pixel unit PX2 includes a second pixel unit boundary PX21 near the first side edge 11, and the second light-emitting diode chip 52 includes a second chip side portion 521 near the first side edge 11. The vertical distance between the orthographic projection of the second chip side portion 521 on the substrate 1 and the orthographic projection of the second pixel unit boundary PX21 on the substrate 1 is (e.g., ...). Figure 2 The distance L2 in the figure is greater than or equal to the specified distance. It should be noted that the "specified distance" here can be the splicing distance that enables the splicing of display panels. The "specified distance" and "sponging distance" will be described in more detail below.

[0057] For example, the first pixel unit PX1 includes a first pixel unit boundary PX11 parallel to the first side edge 11, and the first light-emitting diode chip 51 has a first chip side portion 511 near the first pixel unit boundary PX11. The vertical distance between the orthographic projection of the first chip side portion 511 on the substrate 1 and the orthographic projection of the first pixel unit boundary PX11 on the substrate 1 is (e.g.) Figure 2 L1) is less than the vertical distance between the orthographic projection of the second chip side portion 521 on the substrate 1 and the orthographic projection of the second pixel unit boundary PX21 on the substrate 1 (e.g., Figure 2 (L2 in the text). That is, the shortest distance between the second light-emitting diode chip 52 and the boundary of the corresponding second pixel unit PX2 near the side edge is greater than the shortest distance between the first light-emitting diode chip 51 and the edge of the corresponding pixel unit PX1.

[0058] For example, the shortest distance M1 between the orthographic projection of the side portion 511 of the first LED chip 51 near the first side edge 11 on the substrate and the first side edge 11, and the shortest distance M2 between the orthographic projection of the side portion 521 of the second LED chip 52 near the first side edge 11 on the substrate and the first side edge 11, satisfy: M2 > M1 - 2P, where P is the pixel period of the display substrate. For example, the shortest distance M2 between the orthographic projection of the side portion 521 of the second LED chip 52 near the first side edge 11 on the substrate and the first side edge 11 can be equal to the vertical distance L2 between the orthographic projection of the second chip side portion 521 on the substrate 1 and the orthographic projection of the second pixel unit boundary PX21 on the substrate 1.

[0059] For example, the pixel period P of the display substrate can be equal to the distance between the pixel boundaries of two adjacent pixel units in the same pixel row that are closest to the first side edge 11 in the second direction Y.

[0060] exist Figure 2 In an exemplary embodiment, a first direction X and a second direction Y are schematically illustrated. For example, multiple pixel units PX can be arranged in an array along the first direction X and the second direction Y. The first direction X can correspond to the row direction of the pixel unit arrangement, and the second direction Y can correspond to the column direction of the pixel unit arrangement. It should be noted that the embodiments of this disclosure are not limited thereto.

[0061] For example, the substrate 1 can have a rectangular, rounded rectangular, or quadrilateral shape, and the first side edge 11 can be one of the four side edges of the substrate 1 that extends along the second direction Y. Figure 2As shown, the first side edge 11 can be the right side edge of the substrate 1. The second pixel unit PX2 can be one of the pixel units in the column of pixel units closest to the first side edge 11.

[0062] In the embodiments of this disclosure, the light-emitting diode chips in the column of pixel units closest to the first side edge 11 are disposed away from the first side edge 11. This allows for a larger splicing distance at the side edge of the display substrate, which is beneficial for splicing multiple display substrates. The term "splicing" will be described in more detail below.

[0063] For example, the area of ​​the orthogonal projection of the second light-emitting diode chip 52 on the substrate 1 is greater than the area of ​​the orthogonal projection of the first light-emitting diode chip 51 on the substrate 1, and the area of ​​the orthogonal projection of the second light-emitting diode chip 52 on the substrate 1 is less than twice the area of ​​the orthogonal projection of the first light-emitting diode chip 51 on the substrate 1.

[0064] For example, the area of ​​the portion of the second light-emitting diode chip 52 located within the second pixel unit PX2, projected onto the substrate 1, is smaller than the area of ​​the first light-emitting diode chip 51 projected onto the substrate 1. This arrangement allows the light-emitting diode chips in the column of pixel units closest to the first side edge 11 to be positioned further away from the first side edge 11, thereby facilitating the splicing of the display substrates.

[0065] Continue to refer to Figure 2 The substrate 1 may further include a second side edge 12, which is connected to the first side edge 11. Exemplarily, the second side edge 12 may be one of the four side edges of the substrate 1 extending along a first direction X. For example, the second side edge 12 may be the lower side edge of the substrate 1.

[0066] The plurality of pixel units PX may further include an eighth pixel unit PX3 near the second side edge 12, and the plurality of light-emitting diode chips 5 may further include a fourth light-emitting diode chip 53, at least a portion of which is located within the eighth pixel unit PX3.

[0067] The eighth pixel unit PX3 includes an eighth pixel unit boundary PX31 near the second side edge 12, and the fourth light-emitting diode chip 53 includes a third chip side portion 531 near the second side edge 12. The vertical distance between the orthographic projection of the third chip side portion 531 on the substrate 1 and the orthographic projection of the eighth pixel unit boundary PX31 on the substrate 1 is (e.g.) Figure 2 L3 in the distance is greater than or equal to the specified distance.

[0068] For example, the area of ​​the orthogonal projection of the fourth light-emitting diode chip 53 on the substrate 1 is greater than the area of ​​the orthogonal projection of the first light-emitting diode chip 51 on the substrate 1, and the area of ​​the orthogonal projection of the fourth light-emitting diode chip 53 on the substrate 1 is less than twice the area of ​​the orthogonal projection of the first light-emitting diode chip 51 on the substrate 1.

[0069] For example, the area of ​​the orthogonal projection of the fourth light-emitting diode chip 53 on the substrate 1 can be substantially equal to the area of ​​the orthogonal projection of the second light-emitting diode chip 52 on the substrate 1.

[0070] For example, the area of ​​the portion of the fourth light-emitting diode chip 53 located within the eighth pixel unit PX3 that is projected onto the substrate 1 is smaller than the area of ​​the first light-emitting diode chip 51 that is projected onto the substrate 1.

[0071] Continue to refer to Figure 2 The plurality of pixel units PX further includes a third pixel unit PX4, which is adjacent to the second pixel unit PX2. The third pixel unit PX4 is located between the first pixel unit PX1 and the second pixel unit PX2 in a direction perpendicular to the first side edge 11 (e.g., the first direction X). The third pixel unit PX4 and the second pixel unit PX2 are located in the same row in a direction perpendicular to the first side edge.

[0072] In embodiments of this disclosure, the second pixel unit PX2 and the third pixel unit PX4 may share the second light-emitting diode chip 52. (Refer to...) Figure 2 A portion of the second light-emitting diode chip 52 is located in the second pixel unit PX2, and another portion of the second light-emitting diode chip 52 is located in the third pixel unit PX4.

[0073] For ease of description, the portion of the second LED chip 52 located in the second pixel unit PX2 can be referred to as the first portion, and the portion of the second LED chip 52 located in the third pixel unit PX4 can be referred to as the second portion. For example, the area of ​​the orthographic projection of the first portion of the second LED chip 52 onto the substrate 1 can be substantially equal to the area of ​​the orthographic projection of the second portion of the second LED chip 52 onto the substrate 1. However, the embodiments of this disclosure are not limited thereto.

[0074] Reference Figure 2The plurality of pixel units PX further includes a ninth pixel unit PX5, which is adjacent to the eighth pixel unit PX3. The ninth pixel unit PX5 is located between the first pixel unit PX1 and the eighth pixel unit PX3 in a direction perpendicular to the second side edge 12 (i.e., the second direction Y). The ninth pixel unit PX5 and the eighth pixel unit PX3 are located in the same column in a direction perpendicular to the second side edge 12.

[0075] In embodiments of this disclosure, the eighth pixel unit PX3 and the ninth pixel unit PX5 may share the fourth light-emitting diode chip 53. (See also...) Figure 2 A portion of the fourth light-emitting diode chip 53 is located in the eighth pixel unit PX3, and another portion of the fourth light-emitting diode chip 53 is located in the ninth pixel unit PX5.

[0076] Similarly, for ease of description, the portion of the fourth LED chip 53 located in the eighth pixel unit PX3 can be referred to as the first portion, and the portion of the fourth LED chip 53 located in the ninth pixel unit PX5 can be referred to as the second portion. For example, the area of ​​the orthographic projection of the first portion of the fourth LED chip 53 onto the substrate 1 can be substantially equal to the area of ​​the orthographic projection of the second portion of the fourth LED chip 53 onto the substrate 1. However, the embodiments of this disclosure are not limited thereto.

[0077] For example, the fourth light-emitting diode chip 53 is closer to the second side edge 12 than the first light-emitting diode chip 51. The shortest distance M4 between the orthographic projection of the side portion 512 of the first light-emitting diode chip 51 near the second side edge 12 on the substrate and the shortest distance M5 between the orthographic projection of the side portion 531 of the fourth light-emitting diode chip 53 near the second side edge 12 on the substrate and the second side edge 12 satisfies: M5 > M4 - 2P, where P is the pixel period of the display substrate.

[0078] For example, the shortest distance M5 between the orthographic projection of the side portion 531 of the fourth LED chip 53 near the second side edge 12 on the substrate and the second side edge 12 can be equal to the vertical distance L3 between the orthographic projection of the third chip side portion 531 on the substrate 1 and the orthographic projection of the eighth pixel unit boundary PX31 on the substrate 1.

[0079] For example, the pixel period P of the display substrate can be equal to the distance between the pixel boundaries of the two adjacent pixel units located in the same pixel column that are closest to the second side edge 12 in the first direction X.

[0080] Continue to refer to Figure 2The plurality of pixel units PX may further include a fourth pixel unit PX6, a fifth pixel unit PX7, a sixth pixel unit PX8, and a seventh pixel unit PX9. The fourth pixel unit PX6 is adjacent to the connection position of the first side edge 11 and the second side edge 12; for example, the connection position of the first side edge 11 and the second side edge 12 may correspond to a corner of the substrate 1. The fifth pixel unit PX7 is adjacent to the fourth pixel unit PX6 in a direction parallel to the first side edge 11, the sixth pixel unit PX8 is adjacent to the fourth pixel unit PX6 in a direction parallel to the second side edge 12, and the seventh pixel unit PX9 is adjacent to the fifth pixel unit PX7 and the sixth pixel unit PX8.

[0081] In embodiments of this disclosure, the plurality of light-emitting diode chips 5 further includes a third light-emitting diode chip 54, and the fourth pixel unit PX6, the fifth pixel unit PX7, the sixth pixel unit PX8, and the seventh pixel unit PX9 can share the third light-emitting diode chip 54. (Refer to...) Figure 2 The third light-emitting diode chip 54 comprises four parts (e.g., a first part, a second part, a third part, and a fourth part), wherein the first part of the third light-emitting diode chip 54 is located in the fourth pixel unit PX6, the second part of the third light-emitting diode chip 54 is located in the fifth pixel unit PX7, the third part of the third light-emitting diode chip 54 is located in the sixth pixel unit PX8, and the fourth part of the third light-emitting diode chip 54 is located in the seventh pixel unit PX9. For example, the areas of the orthographic projections of the first, second, third, and fourth parts of the third light-emitting diode chip 54 onto the substrate 1 can be substantially equal to each other. However, the embodiments of this disclosure are not limited thereto.

[0082] In other words, the edge of the fourth pixel unit PX6 includes a first side edge and a second side edge that intersect each other. A portion of the third light-emitting diode chip 54 is located within the fourth pixel unit PX6, and other portions of the third light-emitting diode chip 54 are located within pixel units adjacent to the fourth pixel unit PX6 (e.g., the fifth pixel unit PX7, the sixth pixel unit PX8, and the seventh pixel unit PX9). The third light-emitting diode chip 54 is located within four adjacent pixel units.

[0083] For example, the vertical distance between the orthographic projection of the side edge of the third LED chip 54 near the first side edge 11 on the substrate 1 and the orthographic projection of the first side edge 11 on the substrate 1 is greater than or equal to a predetermined distance, and the vertical distance between the orthographic projection of the side edge of the third LED chip 54 near the second side edge 12 on the substrate 1 and the orthographic projection of the second side edge 12 on the substrate 1 is greater than or equal to a predetermined distance. That is, the shortest distance between the boundary of the third LED chip 54 and the corresponding fourth pixel unit PX6 near its side edge is greater than the shortest distance between the edge of the first LED chip 51 and the corresponding first pixel unit PX1.

[0084] For example, the shortest distance M1 between the orthographic projection of the side portion 511 of the first light-emitting diode chip 51 near the first side edge 11 on the substrate and the shortest distance M3 between the orthographic projection of the side portion 541 of the third light-emitting diode chip 54 near the first side edge 11 on the substrate and the first side edge 11 satisfies: M3 > M1 - 2P, where P is the pixel period of the display substrate.

[0085] For example, the shortest distance M4 between the orthographic projection of the side portion 512 of the first LED chip 51 near the second side edge 12 and the second side edge 12 and the shortest distance M6 between the orthographic projection of the side portion 542 of the third LED chip 54 near the second side edge 12 and the second side edge 12 and the second side edge 12 and the third LED chip 54 near the second side edge 12 and the second side edge 12 and the third LED chip 54 is satisfied that: M6 > M4 - 2P, where P is the pixel period of the display substrate. For example, the area of ​​the orthographic projection of the second LED chip 52 or the fourth LED chip 53 on the substrate 1 is smaller than the area of ​​the orthographic projection of the third LED chip 54 on the substrate 1.

[0086] The area of ​​the portion of the third light-emitting diode chip 54 located within the fourth pixel unit PX6 on the substrate is smaller than the area of ​​the first light-emitting diode chip 51 on the substrate.

[0087] The area of ​​the orthogonal projection of the third light-emitting diode chip 54 on the substrate is greater than the area of ​​the orthogonal projection of the first light-emitting diode chip 51 on the substrate, and the area of ​​the orthogonal projection of the third light-emitting diode chip 54 on the substrate is less than 4 times the area of ​​the orthogonal projection of the first light-emitting diode chip 51 on the substrate.

[0088] In the embodiments of this disclosure, by the above-described arrangement, the light-emitting diode chips in the column of pixel units and the row of pixel units closest to the side edge of the display substrate can be arranged away from the side edge in either the first or second direction. The pixel units closest to the corner of the display substrate can also be arranged away from the corner in both the first and second directions. This helps to ensure that the display substrate has sufficient splicing distance and facilitates the realization of splicing display panels and splicing display devices.

[0089] It should be noted that in this paper, the eighth pixel unit PX3 and the second pixel unit PX2 can have essentially the same structure, differing only in their orientation. Therefore, for ease of description, in other parts, the eighth pixel unit PX3 and the second pixel unit PX2 can be collectively referred to as the second pixel unit. Similarly, the ninth pixel unit PX5 and the third pixel unit PX3 can have essentially the same structure, differing only in their orientation. Therefore, for ease of description, in other parts, the ninth pixel unit PX5 and the third pixel unit PX3 can be collectively referred to as the third pixel unit.

[0090] Figure 12 The display substrate according to some exemplary embodiments of the present disclosure is in Figure 2 A magnified view of part I in the image. (Refer to reference.) Figure 2 , Figure 4 and Figure 12 Multiple rectangular boxes schematically illustrate several boundaries. For example, rectangular box R1 represents the boundary of a pixel unit, rectangular box R2 represents the boundary of a light-emitting diode (LED) chip, rectangular box R3 represents the boundary of a protective layer, and rectangular box R4 represents the boundary of multiple light-emitting areas or PADs of the LED chip. For instance, during the transfer of multiple LED chips onto a substrate, certain positional deviations may occur due to limitations in the transfer process precision. Considering this positional deviation, a certain spacing distance exists between rectangular boxes R1 and R2 along both the first direction X and the second direction Y. This spacing distance is designed to avoid interference between two adjacent LED chips. Similarly, a certain spacing distance exists between rectangular boxes R2 and R3 along both the first direction X and the second direction Y, taking into account process errors generated during laser chip cutting. Again, a certain spacing distance exists between rectangular boxes R2 and R3 along both the first direction X and the second direction Y, taking into account process errors generated during the formation of the protective layer.

[0091] In embodiments of this disclosure, reference is made to Figures 2 to 6The light-emitting diode (LED) chip 5 (which may be a first LED chip 51, a second LED chip 52, a fourth LED chip 53, or a third LED chip 54) may include a substrate 5S, a light-emitting region 5A, a cathode 5C, and an anode 5B. For example, the substrate 5S may be a sapphire substrate. The LED chip 5 may have a flip-chip structure. The light-emitting region 5A is sandwiched between the cathode 5C and the anode 5B. One LED chip 5 may include multiple light-emitting regions 5A, each corresponding to an anode 5B. Each anode 5B is electrically connected to a corresponding anode pad 5P1. One LED chip 5 may have a common cathode 5C, which is electrically connected to a cathode pad 5P2. Specified electrical signals can be supplied to the anode 5B and the cathode 5C respectively through the anode pad 5P1 and the cathode pad 5P2. For example, in a light-emitting diode chip 5, the plurality of light-emitting areas 5A and the plurality of anodes 5B correspond one-to-one, the plurality of light-emitting areas 5C are spaced apart from each other, and the cathode pad 5P2 and the plurality of light-emitting areas 5C are spaced apart from each other.

[0092] Combined with reference Figure 3 and Figure 6 The first light-emitting diode chip 51 may include three light-emitting areas 5A. Correspondingly, the first light-emitting diode chip 51 may include three anodes 5B and one common cathode 5C. Each of the three light-emitting areas 5A corresponds one-to-one with one of the three anodes 5B. Each of the three anodes 5B is electrically connected to one of the three anode pads 5P1, and the common cathode 5C is electrically connected to one of the cathode pads 5P2. For example, the three light-emitting areas 5A may be configured to emit red, green, and blue light, respectively. For ease of description, the light-emitting area emitting red light is referred to as the first light-emitting area 5A1, the light-emitting area emitting green light is referred to as the second light-emitting area 5A2, and the light-emitting area emitting blue light is referred to as the third light-emitting area 5A3.

[0093] For example, the area of ​​the first light-emitting region 5A1 projected onto the substrate 5S is larger than the area of ​​the second light-emitting region 5A2 projected onto the substrate 5S, and the area of ​​the second light-emitting region 5A2 projected onto the substrate 5S is larger than the area of ​​the third light-emitting region 5A3 projected onto the substrate 5S.

[0094] Reference Figure 3 The first light-emitting area 5A1, the second light-emitting area 5A2, the third light-emitting area 5A3, and the cathode pad 5P2 of the first light-emitting diode chip 51 are arranged at intervals on the orthogonal projection of the first light-emitting diode chip 51 onto the substrate 5S. For example, they are located at the four corners of the substrate 5S respectively.

[0095] For example, the orthogonal projections of the first light-emitting region 5A1, the second light-emitting region 5A2, and the third light-emitting region 5A3 of the first light-emitting diode chip 51 onto the substrate 5S of the first light-emitting diode chip 51 can respectively cover the orthogonal projection of their respective anode pads 5P1 onto the substrate 5S of the first light-emitting diode chip 51.

[0096] Combined with reference Figure 2 , Figure 4 and Figure 6 The second LED chip 52 or the fourth LED chip 53 may include six light-emitting areas 5A. Correspondingly, the second LED chip 52 or the fourth LED chip 53 may include six anodes 5B and one common cathode 5C. Three light-emitting areas 5A correspond one-to-one with the six anodes 5B. The six anodes 5B are electrically connected to six anode pads 5P1, and the common cathode 5C is electrically connected to a cathode pad 5P2. For example, in the six light-emitting areas, three light-emitting areas 5A form a group and can be configured to emit red, green, and blue light, respectively. For ease of description, the light-emitting area emitting red light is referred to as the first light-emitting area 5A1, the light-emitting area emitting green light is referred to as the second light-emitting area 5A2, and the light-emitting area emitting blue light is referred to as the third light-emitting area 5A3.

[0097] For example, some of the multiple light-emitting areas 5A of the second light-emitting diode chip 52 or the fourth light-emitting diode chip 53 are located within the second pixel unit, and other multiple light-emitting areas 5A are located within the first pixel unit. The number of light-emitting areas 5A of the second light-emitting diode chip 52 or the fourth light-emitting diode chip 53 is greater than the number of light-emitting areas of the first light-emitting diode chip 51.

[0098] For example, the area of ​​the first light-emitting region 5A1 projected onto the substrate 5S is larger than the area of ​​the second light-emitting region 5A2 projected onto the substrate 5S, and the area of ​​the second light-emitting region 5A2 projected onto the substrate 5S is larger than the area of ​​the third light-emitting region 5A3 projected onto the substrate 5S.

[0099] Reference Figure 2 One set of light-emitting areas 5A1, 5A2, and 5A3 is located in one pixel unit of the shared second light-emitting diode chip 52 or the fourth light-emitting diode chip 53, and another set of light-emitting areas 5A1, 5A2, and 5A3 is located in another pixel unit of the shared second light-emitting diode chip 52 or the fourth light-emitting diode chip 53.

[0100] The six light-emitting regions of the second LED chip 52 and the cathode pad 5P2 are arranged at intervals on the orthographic projections of the second LED chip 52 onto the substrate 5S. For example, the orthographic projections of the two first light-emitting regions 5A1 of the second LED chip 52 onto the substrate 5S are located at two opposite corners of the substrate 5S. The orthographic projections of the two second light-emitting regions 5A2 of the second LED chip 52 onto the substrate 5S are located at two opposite corners of the substrate 5S. The orthographic projections of the two third light-emitting regions 5A3 of the second LED chip 52 onto the substrate 5S are located at two opposite sides of the substrate 5S. For example, the orthographic projection of one third light-emitting region 5A3 of the second LED chip 52 onto the substrate 5S is located at the midpoint between the orthographic projections of one first light-emitting region 5A1 and one second light-emitting region 5A2 onto the substrate 5S.

[0101] For example, the orthographic projection of the cathode pad 5P2 of the second LED chip 52 onto its substrate 5S can be approximately located at the geometric center of the substrate 5S. Alternatively, the orthographic projection of the cathode pad 5P2 of the second LED chip 52 onto its substrate 5S can be approximately located at the intersection of the two diagonals of the substrate 5S. Or, the orthographic projection of the cathode pad 5P2 of the second LED chip 52 onto its substrate 5S can be located at the boundary between the first pixel unit and the second pixel unit.

[0102] For example, the distance G4 from the orthogonal projection of the cathode pad 5P2 of the second light-emitting diode chip 52 onto the first side edge 11 can be equal to the pixel period P of the display substrate.

[0103] For example, the orthogonal projections of the first light-emitting region 5A1, the second light-emitting region 5A2, and the third light-emitting region 5A3 of the second light-emitting diode chip 52 onto the substrate 5S of the second light-emitting diode chip 52 can respectively cover the orthogonal projection of their respective anode pads 5P1 onto the substrate 5S of the second light-emitting diode chip 52.

[0104] Combined with reference Figure 2 , Figure 5 and Figure 6 The third light-emitting diode chip 54 may include 12 light-emitting areas 5A, and correspondingly, the third light-emitting diode chip 54 may include 12 anodes 5B and one common cathode 5C. Each of the 12 light-emitting areas 5A corresponds one-to-one with one of the 12 anodes 5B. Each of the 12 anodes 5B is electrically connected to one of the 12 anode pads 5P1, and the common cathode 5C is electrically connected to one of the cathode pads 5P2. For example, in the 12 light-emitting areas, three light-emitting areas 5A form a group and can be configured to emit red, green, and blue light, respectively. For ease of description, the light-emitting area emitting red light is referred to as the first light-emitting area 5A1, the light-emitting area emitting green light is referred to as the second light-emitting area 5A2, and the light-emitting area emitting blue light is referred to as the third light-emitting area 5A3.

[0105] For example, some of the multiple light-emitting areas 5A of the third light-emitting diode chip 54 are located within the third pixel unit, while others of the multiple light-emitting areas 5A are located within the first pixel unit and the second pixel unit. The number of light-emitting areas 5A of the third light-emitting diode chip 54 is greater than the number of light-emitting areas 5A of the second light-emitting diode chip 52.

[0106] For example, the area of ​​the first light-emitting region 5A1 projected onto the substrate 5S is larger than the area of ​​the second light-emitting region 5A2 projected onto the substrate 5S, and the area of ​​the second light-emitting region 5A2 projected onto the substrate 5S is larger than the area of ​​the third light-emitting region 5A3 projected onto the substrate 5S.

[0107] Reference Figure 2 Each group of light-emitting areas 5A1, 5A2, and 5A3 is located in one of the four pixel units of the shared third light-emitting diode chip 54.

[0108] The 12 light-emitting areas of the third light-emitting diode chip 54 and the cathode pad 5P2 are arranged at intervals on the orthogonal projection of the third light-emitting diode chip 54 onto the substrate 5S of the third light-emitting diode chip 54.

[0109] For example, the orthographic projection of the cathode pad 5P2 of the third LED chip 54 onto its substrate 5S can be approximately located at the geometric center of the substrate 5S. Alternatively, the orthographic projection of the cathode pad 5P2 of the third LED chip 54 onto its substrate 5S can be approximately located at the intersection of the two diagonals of the substrate 5S. Or, the orthographic projection of the cathode pad 5P2 of the third LED chip 54 onto its substrate 5S can be located at the boundary between the first pixel unit, the second pixel unit, and the third pixel unit.

[0110] For example, the distance G5 from the cathode pad 5P2 of the third light-emitting diode chip 54 to the first side edge 11 can be equal to the pixel period P of the display substrate.

[0111] For example, the distance G6 from the cathode pad 5P2 of the third light-emitting diode chip 54 to the second side edge 12 can be equal to the pixel period P of the display substrate.

[0112] For example, the orthographic projections of the first light-emitting region 5A1, the second light-emitting region 5A2, and the third light-emitting region 5A3 of the third light-emitting diode chip 54 onto the substrate 5S of the third light-emitting diode chip 54 can respectively cover the orthographic projection of their respective anode pads 5P1 onto the substrate 5S of the third light-emitting diode chip 54.

[0113] Continue to refer to Figure 2The second light-emitting diode chip 52 may include multiple light-emitting areas 5A, multiple anodes 5B, and a cathode 5C. The multiple light-emitting areas 5A and the multiple anodes 5B correspond one-to-one. The multiple light-emitting areas 5A are spaced apart from each other. Some of the multiple light-emitting areas 5A are located within the second pixel unit PX2, and others are located within the third pixel unit PX4. For example, in... Figure 2 In the embodiment shown, the second light-emitting diode chip 52 may include six light-emitting areas 5A, six anodes 5B and one cathode 5C, wherein three light-emitting areas 5A are located within the second pixel unit PX2 and the other three light-emitting areas 5A are located within the third pixel unit PX4.

[0114] Similarly, the fourth light-emitting diode chip 53 includes multiple light-emitting areas 5A, multiple anodes 5B, and a cathode 5C. The multiple light-emitting areas 5A and the multiple anodes 5B of the fourth light-emitting diode chip 53 correspond one-to-one. The multiple light-emitting areas 5A of the fourth light-emitting diode chip 53 are spaced apart from each other. Some of the multiple light-emitting areas 5A of the fourth light-emitting diode chip 53 are located within the eighth pixel unit PX3, and others are located within the ninth pixel unit PX5. For example, in... Figure 2 In the embodiment shown, the fourth light-emitting diode chip 53 may include six light-emitting areas 5A, six anodes 5B and one cathode 5C, wherein three light-emitting areas 5A are located in the eighth pixel unit PX3 and the other three light-emitting areas 5A are located in the ninth pixel unit PX5.

[0115] The third light-emitting diode (LED) chip 54 may include multiple light-emitting areas 5A, multiple anodes 5B, and one cathode 5C. The multiple light-emitting areas 5A and the multiple anodes 5B of the third LED chip 54 correspond one-to-one. The multiple light-emitting areas 5A of the third LED chip 54 are spaced apart from each other. A first portion of the multiple light-emitting areas 5A of the third LED chip 54 is located within the fourth pixel unit PX6, a second portion is located within the fifth pixel unit PX7, a third portion is located within the sixth pixel unit PX8, and a fourth portion is located within the seventh pixel unit PX9. For example, three light-emitting areas 5A may be disposed within the fourth pixel unit PX6, the fifth pixel unit PX7, the sixth pixel unit PX8, and the seventh pixel unit PX9, respectively.

[0116] Combined with reference Figures 2 to 6In the embodiments disclosed herein, the display substrate employs a light-emitting diode chip 5 and a light conversion unit 600 to achieve color display. For example, the light conversion unit may include light conversion materials such as quantum dots for converting light of a first wavelength into light of a second wavelength. Exemplarily, the light-emitting diode chip is an LED chip that emits blue light, and the light conversion unit includes a first light conversion unit for converting blue light into red light; and a second light conversion unit for converting blue light into filtered light.

[0117] like Figure 6 The diagram schematically illustrates a portion of the structure of a light-emitting diode chip and a light conversion unit. Figure 6 In the illustrated embodiment, the light conversion unit 600 is disposed on the side of the substrate 5S away from the light-emitting region 5A, that is, the light conversion unit 600 and the light-emitting region 5A are respectively disposed on both sides of the substrate 5S. Each of the plurality of light conversion units 600 corresponds one-to-one with a plurality of light-emitting regions 5A. For example, the orthographic projections of the plurality of light conversion units 600 on the substrate 1 and the orthographic projections of the plurality of light-emitting regions 5A on the substrate 1 respectively at least partially overlap.

[0118] To prevent color mixing between adjacent sub-pixels, a light-shielding section 400 is provided between adjacent light conversion sections 600. For example... Figure 6 As shown, the width of the light-shielding portion 400 can be calculated based on the light path emitted from the light-emitting region 5A, that is, the spacing distance between adjacent light-converting portions 600 can be calculated. For example, the inventors have found that the spacing distance between adjacent light-converting portions 600 is 8 micrometers or more. Specifically, in the embodiments of this disclosure, the spacing distance between the plurality of light-emitting regions of the second light-emitting diode chip 52 is 8 micrometers or more. The spacing distance between the plurality of light-emitting regions of the fourth light-emitting diode chip 53 is 8 micrometers or more. The spacing distance between the plurality of light-emitting regions of the third light-emitting diode chip 54 is 8 micrometers or more. In this way, while reducing the area of ​​the light-emitting diode chip, cross-coloring between adjacent sub-pixels can be avoided.

[0119] Figure 7 The display substrate according to some exemplary embodiments of the present disclosure is along Figure 2 The image shows a cross-sectional view taken from line BB'. In the process of manufacturing a display substrate according to an embodiment of the present disclosure, it is usually necessary to fold or flip a substrate carrying a circuit board or integrated circuit (hereinafter referred to as the second substrate) to the back side of the substrate, and electrically connect the terminals (i.e., PADs) of the light-emitting diode chip located on the front side of the substrate and the circuit located on the back side of the substrate by bonding leads. Figures 8A to 8G This is a schematic cross-sectional view illustrating the structure formed after some steps of the manufacturing method of the display substrate are performed. (Refer to reference...) Figure 7 as well as Figures 8A to 8GThe manufacturing method of the display substrate can be performed according to the following steps.

[0120] Exemplary, in some embodiments of this disclosure, reference is made to Figure 7 The display substrate may include a first substrate 100, which may include a substrate 1 and a plurality of first electrodes 2 and a plurality of first terminals 3 disposed on the same side (e.g., the upper side) of the substrate 1. The plurality of first terminals 3 may be located at the first edge of the first substrate 100 and are used to electrically connect signal lines located on the first substrate 100 to an external driving circuit 61. The signal lines may be electrically connected to a plurality of light-emitting diode chips.

[0121] For example, the external driving circuit 61 may be located on the side of the substrate 1 away from the first terminal 3.

[0122] For example, the display substrate may also include a second substrate 200, which may include a second substrate 6, an external driving circuit 61 disposed on the second substrate 6, and a plurality of second terminals 7.

[0123] For example, the first substrate 100 and the second substrate 200 can be stacked, with a plurality of first terminals 3 located on the side of the substrate 1 away from the second substrate 200, and a plurality of second terminals 7 located on the side of the second substrate 6 away from the first substrate 100.

[0124] For example, the display substrate may also include bonding leads 9 that electrically connect the first terminal 3 and the second terminal 7.

[0125] For example, the bonding wire 9 can cover the sides of both the first substrate 100 and the second substrate 200.

[0126] For example, the external drive circuit 61 is an integrated circuit chip.

[0127] In step S101, a first substrate 100 is provided.

[0128] Reference Figure 2 and Figure 8A The first substrate 100 may include a substrate 1 and a plurality of first electrodes 2 and a plurality of first terminals 3 disposed on the substrate 1. The plurality of first terminals 3 are located at the edge of the first substrate 100. For example, the plurality of first terminals 3 are located in the fan-out region of the first substrate 100, and are used to electrically connect signal lines located on the first substrate 100 (e.g., the signal lines are electrically connected to the terminals of each light-emitting diode) to an external driving circuit.

[0129] For example, the material of the substrate 1 may include, but is not limited to, glass, quartz, plastic, silicon, polyimide, etc. The first electrode 2 and the first terminal 3 may be columnar structures. The materials of the first electrode 2 and the first terminal 3 may include conductive materials, such as metallic materials, etc. Specifically, they may be at least one or a combination of at least two of the following: gold, silver, copper, aluminum, molybdenum, gold alloys, silver alloys, copper alloys, aluminum alloys, molybdenum alloys, etc. The embodiments disclosed herein are not limited in this regard.

[0130] For example, the first substrate 100 may further include a driving circuit 4 electrically connected to a plurality of first electrodes 2, the driving circuit 4 being disposed on the substrate 1. The driving circuit 4 can be used to provide electrical signals to light-emitting diode chips subsequently formed on the plurality of first electrodes 2, controlling their light emission brightness. For example, in some examples, the driving circuit 4 may be a plurality of pixel driving circuits connected one-to-one with each light-emitting diode chip, or a plurality of micro-integrated circuit chips connected one-to-one with each light-emitting diode chip, etc., which can control each light-emitting diode chip to emit different brightness grayscale levels. It should be noted that the specific circuit structure of the driving circuit 4 on the first substrate 100 can be set according to actual needs, and the embodiments disclosed herein do not limit this. In the following, the driving circuit 4 will be described by way of example with reference to the accompanying drawings.

[0131] In step S102, multiple light-emitting diode chips 5 are transferred and bonded to the first substrate 100.

[0132] Reference Figure 2 and Figure 8B Each of the plurality of light-emitting diode chips 5 includes an N electrode and a P electrode. The N electrode and the P electrode of the light-emitting diode chip 5 are respectively connected to the corresponding first electrode 2, while the surfaces of the plurality of first terminals 3 are exposed.

[0133] Reference Figure 2 Multiple light-emitting diode (LED) chips are arranged in an array along a first direction X and a second direction Y. For example, the first direction X is a row direction and the second direction Y is a column direction. Of course, the embodiments of this disclosure are not limited to this; the first and second directions can be any directions, as long as they intersect. Furthermore, the multiple LED chips are not limited to being arranged in a straight line; they can also be arranged along a curve, in a ring, or in any other manner, depending on actual needs. The embodiments of this disclosure do not impose any limitations on this.

[0134] For example, the light-emitting diode chip may include a micro LED or a sub-millimeter light-emitting diode.

[0135] In step S103, a second substrate 200 is provided, and the first substrate 100 and the second substrate 200 are placed on a carrier 300.

[0136] For example, the second substrate 200 can be a circuit board, such as a PCB (Printed Circuit Board), FPC (Flexible Printed Circuit), or COF (Chip On Film).

[0137] Reference Figure 8C The second substrate 200 may include a second substrate 6 and a plurality of second terminals 7 disposed on the second substrate 6. For example, the plurality of second terminals 7 may be disposed along a first direction X (in Figure 8C The second terminals 7 are arranged in a direction perpendicular to the paper, meaning that multiple second terminals 7 form a second terminal row. For example, multiple second terminals 7 can correspond one-to-one with multiple first terminals 3. That is, the arrangement period of the second terminals 7 is the same as the arrangement period of the first terminals 3.

[0138] Of course, the second substrate 200 may also include an external driving circuit, such as an integrated circuit chip, disposed on the second substrate 6, but the embodiments disclosed herein are not limited thereto.

[0139] The carrier 300 is used to space and fix the first substrate 100 and the second substrate 200 to maintain their relative positional relationship. (Refer to...) Figure 8C The first terminal 3 disposed on the first substrate 100 has a first surface 31 (shown as the upper surface in the figure) away from the substrate 1, and the second terminal 7 disposed on the second substrate 200 has a second surface 71 (shown as the upper surface in the figure) away from the second substrate 6.

[0140] In step S104, in conjunction with reference Figure 8C and Figure 8D A first protective adhesive layer 8 is formed in the gap 400 between the first terminal row where the first terminal 3 is located and the second terminal row where the second terminal 7 is located.

[0141] For example, a protective adhesive of a certain thickness can be applied within the gap 400, ensuring that the gap 400 is completely filled. Due to limitations in coating precision, the protective adhesive may also cover at least a portion of the surfaces of the first terminal 3 and the second terminal 7 located on both sides of the gap 400. However, this portion of the protective adhesive covering the first terminal 3 and the second terminal 7 can be removed later by laser ablation or film removal to avoid affecting subsequent processes, thereby obtaining a first protective adhesive layer 8 that only fills the gap 400. It can be understood that the orthographic projection of the first protective adhesive layer 8 on the carrier 300 covers the orthographic projection of the gap 400 on the carrier 300.

[0142] Reference Figure 8D The first protective adhesive layer 8 contacts the first terminal 3 near the side wall of the first substrate 100, and the first protective adhesive layer 8 contacts the second terminal 7 near the side wall of the second substrate 100.

[0143] For example, the first protective adhesive layer 8 includes a third surface 81 located away from the carrier 300. The third surface 81, the first surface 31, and the second surface 71 are substantially at the same level to ensure that subsequent bonding wires are formed on a relatively flat surface.

[0144] For example, the thickness of the first protective adhesive layer 8 is in the range of 5 to 500 micrometers, and the specific value is the same as the thickness of the first terminal 3 and / or the second terminal 7. The Young's modulus of the material used in the first protective adhesive layer 8 can be between 0.1 MPa and 80 GPa. For example, the material can be silicone or polydimethylsiloxane (i.e., PDMS).

[0145] In step S105, a bonding wire 9 is formed, such that the bonding wire 9 electrically connects the first terminal 3 and the second terminal 7.

[0146] Reference Figure 8E A bonding wire 9 is formed, such that one end 91 of the bonding wire 9 is connected to the first terminal 3, and the other end 92 is connected to the second terminal 7. That is, one end 91 of the bonding wire 9 is soldered to the first terminal 3, and the other end 92 is soldered to the second terminal 7. The solder joint where end 91 is soldered to the first terminal 3 is called the first solder joint 911, and the solder joint where end 92 is soldered to the second terminal 7 is called the second solder joint 921. (Refer to...) Figure 7 .

[0147] exist Figure 8E In the embodiment shown, the bonding wire 9 extends substantially within the plane containing the first terminal 3 and the second terminal 7, which facilitates the subsequent bending process.

[0148] For example, the first solder joint 911 can be a wedge-shaped solder joint, that is, the shape of the orthographic projection of the first solder joint 911 on the substrate 1 is wedge-shaped. In this case, the height of the first solder joint 911 on the first terminal 3 can be controlled between 1 and 10 micrometers. The diameter of the bonding wire 9 can be between 10 and 500 micrometers. The height of the first solder joint 911 on the first terminal 3 is smaller than the diameter of the bonding wire 9, so that the bonding wire 9 can extend substantially within the plane containing the first terminal 3 and the second terminal 7.

[0149] For example, the bonding wire 9 can be made of metals such as Cu, Al, Au, Ag, or their alloys.

[0150] Combined with reference Figure 8EEach bonding wire 9 is electrically connected to a first terminal 3 and its corresponding second terminal 7. Since the multiple first terminals 3 are arranged at equal intervals along the first direction X, the multiple bonding wires 9 are also arranged at equal intervals along the first direction X.

[0151] In step S106, a second protective adhesive layer 110 is formed on the surface of each of the first terminal 3, the second terminal 7, and the bonding lead 9 away from the substrate 1 and the second substrate 6.

[0152] Reference Figure 8F The orthographic projection of the second protective adhesive layer 110 in a direction perpendicular to the first surface 31 covers the orthographic projection of each of the first terminal 3, the second terminal 7, and the bonding wire 9 in a direction perpendicular to the first surface 31. This protects the bonding wire 9 and the solder joints of each of the first terminal 3 and the second terminal 7 with the bonding wire 9.

[0153] For example, the thickness of the second protective adhesive layer 110 is in the range of 5 to 500 micrometers, and the Young's modulus of the material used in the second protective adhesive layer 110 can be between 0.1 MPa and 80 GPa. For example, the material can be silicone or polydimethylsiloxane (i.e., PDMS).

[0154] In some examples, the thickness of the second protective adhesive layer 110 can be substantially equal to the thickness of the first protective adhesive layer 8. This ensures that the bonding wire 9 is positioned at the neutral layer between the upper and lower protective adhesive layers.

[0155] In step S107, adhesive 120 is applied to either the surface of substrate 1 away from the first terminal 3 or the surface of the second substrate 6 away from the second terminal 7. For example, refer to... Figure 8G Adhesive 120 is attached to the surface of the substrate 1 away from the first terminal 3.

[0156] In step S108, in conjunction with reference Figure 8G and Figure 7 The second substrate 200 is flipped toward the first substrate 100, so that the surface of the second substrate 6 away from the second terminal 7 is attached to the adhesive 120.

[0157] In this way, the second substrate 200 can be bent to the back of the first substrate 100, and the two substrates 100 and 200 can be attached together with adhesive 120.

[0158] For example, during the flipping of the second substrate 200, the second substrate 200 can be rotated to the lower surface of the first substrate 100 by a carrier 300 with a fixed rotation trajectory, so as to ensure the stability of the flipping process and reduce the risk of breakage of the bonding wire 9.

[0159] Reference Figure 7 In step S108, the second substrate 200 is flipped, and the surface of the first protective adhesive layer 8 away from the bonding wire 9 contacts the first substrate 100, the backing adhesive 120, and the second substrate 200. Specifically, the surface of the first protective adhesive layer 8 away from the bonding wire 9 contacts the sidewalls of the first substrate 100, the sidewalls of the backing adhesive 120, and the sidewalls of the second substrate 200. In this way, the sidewalls of the first substrate 100, the sidewalls of the backing adhesive 120, and the sidewalls of the second substrate 200 completely support the first protective adhesive layer 8, thereby completely supporting the bonding wire 9 and improving reliability. In the method for manufacturing a display substrate according to the embodiments of this disclosure, the bonding wires are fabricated using a wire bonding process, and the substrates are flipped to achieve a stacked structure of upper and lower substrates, which can reduce process complexity and manufacturing costs.

[0160] Combined with reference Figures 1 to 7 At the side edge of the display substrate, a specified distance D needs to be reserved to accommodate the bonding wires 9 and the protective adhesive layer, ensuring that the bonding wires 9 have a sufficient bending radius to bend to the back side of the display substrate. Specifically, the specified distance D may include a first distance D1, a second distance D2, and a third distance D3. For example, the first distance D1 may correspond to the length of the bonding wire 9 at the side edge, the second distance D2 may correspond to the minimum bending distance that the bonding wire 9 needs to bend to the back side, and the third distance D3 may correspond to the thickness of the protective adhesive layer. The inventors have found that, under current process conditions, the specified distance D is greater than 150 micrometers.

[0161] Figure 9 This is a partial plan view of a display panel according to some exemplary embodiments of the present disclosure. Figure 10 The display panel is based on some exemplary embodiments of this disclosure. Figure 9 The cross-sectional view taken from line CC' in the diagram. (Refer to reference...) Figure 9 and Figure 10 The display panel can be a spliced ​​display substrate. For example, the display panel can be formed by splicing two of the above-mentioned display substrates. In order to set the bonding wires 9 and protective adhesive layers, and to ensure that the bonding wires 9 have a sufficient bending radius to bend to the back of the display substrate, a sufficient splicing distance needs to be reserved at the splicing position. For example, the splicing distance can be more than twice the specified distance D. In the embodiments of this disclosure, a sufficient distance can be reserved at the side edge of the display substrate, which is beneficial to forming a spliced ​​display panel. At the same time, with the spliced ​​display panel provided by the embodiments of this disclosure, the light effect at the splicing position is less affected, which is beneficial to improving the display effect of the display panel.

[0162] exist Figure 9In the embodiments described, four display substrates with identical structures and specifications are schematically shown spliced ​​together to form a display panel. However, the embodiments disclosed herein are not limited to this. Figure 11A and Figure 11B Plan view diagrams of display panels according to embodiments of the present disclosure are shown schematically. For example... Figure 11A As shown, two display substrates with identical structure and specifications are joined together to form a display panel; that is, the two display substrates can be distributed symmetrically along the boundary line. Figure 11B As shown, four display substrates are spliced ​​together to form a display panel, wherein the edges of the second or fourth light-emitting diode chips on two adjacent display substrates are close to each other.

[0163] In embodiments of this disclosure, the side edge of one display substrate can be joined to the side edge of another display substrate along a first direction. The side edge of one display substrate can also be joined to the side edge of another display substrate along a second direction.

[0164] For example, in conjunction with reference Figure 2 and Figure 9 The splicing display panel may include a first display substrate 501 and a second display substrate 502. The first display substrate 501 and the second display substrate 502 are symmetrically distributed along the splicing point, which includes the side edge of the first display substrate 501 near the second display substrate and the side edge of the second display substrate 502 near the first display substrate.

[0165] For example, for the second display substrate 502, at least one side edge includes a third side edge 113, and the first side edge 111 of the first display substrate 501 is spliced ​​with the third side edge 113 of the second display substrate 502 along the first direction X.

[0166] For example, in the second display substrate 502, the second light-emitting diode chip 52 is arranged between the first light-emitting diode chip 51 and the third side edge 113. The light-emitting diode chip includes a plurality of light-emitting regions spaced apart from each other, and the number of light-emitting regions of the second light-emitting diode chip 52 is greater than the number of light-emitting regions of the first light-emitting diode chip 51.

[0167] For example, for the second display substrate 502, the shortest distance M7 between the orthographic projection of the side portion 511 of the first light-emitting diode chip 51 near the third side edge 113 on the substrate and the shortest distance M8 between the orthographic projection of the side portion 521 of the second light-emitting diode chip 52 near the third side edge 113 on the substrate and the third side edge 113 satisfies: M8 > M7 - 2P, where P is the pixel period of the display substrate.

[0168] In the above embodiments, the orthographic projection of each LED chip on the substrate 1 is rectangular. However, the embodiments of this disclosure are not limited to this. For example, the orthographic projection of the LED chip on the substrate 1 can be circular, elliptical, or other shapes. Figure 13 A schematic plan view of a third light-emitting diode chip according to some exemplary embodiments of the present disclosure is shown. Figure 13 In the embodiment shown, the orthographic projection of the third light-emitting diode chip onto the substrate 1 is circular.

[0169] For example, the driving circuit 4 may include a thin-film transistor array layer. This thin-film transistor array layer may specifically include an active layer, a gate insulating layer, a gate, a source, a drain, and a planarization layer. The specific film layer structure of the driving circuit 4 can refer to the film layer structures used in existing array substrates, and will not be described in detail here.

[0170] Some exemplary embodiments of this disclosure also provide a display device. (See also...) Figure 10 , Figure 11A and Figure 11B The display device includes at least two display substrates as described above. The display device is formed by splicing together at least two display substrates as described above. Since the light-emitting diode chips in the pixel units closest to the side edge of the display substrate are disposed away from the side edge, a sufficient splicing distance can be reserved at the splicing position; for example, this splicing distance can be twice the specified distance D. This facilitates the formation of the spliced ​​display device.

[0171] It should be noted that some steps of the above manufacturing method can be performed individually or in combination, and can be performed in parallel or sequentially, and are not limited to the specific order of operations shown in the figure.

[0172] It should be understood that the display device according to some exemplary embodiments of this disclosure has all the features and advantages of the display substrate described above, which can be referred to in the above description of the display substrate and will not be repeated here.

[0173] As used herein, the terms “substantially,” “approximately,” “about,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “approximately” or “about” as used herein includes the stated value and indicates that the particular value is within an acceptable range of deviation for one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0174] While some embodiments based on the general inventive concept of this disclosure have been illustrated and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of this disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display substrate, comprising: A substrate, the substrate including at least one side edge and a display area; A plurality of light-emitting diode (LED) chips are disposed on the substrate, the plurality of LED chips including a first LED chip and a second LED chip, wherein at least one side edge includes a first side edge, and the second LED chip is arranged between the first LED chip and the first side edge; wherein each LED chip includes a plurality of light-emitting regions spaced apart from each other, and the number of light-emitting regions of the second LED chip is greater than the number of light-emitting regions of the first LED chip.

2. The display substrate according to claim 1, wherein, The shortest distance M1 between the orthographic projection of the side of the first LED chip near the first side edge on the substrate and the first side edge and the shortest distance M2 between the orthographic projection of the side of the second LED chip near the first side edge on the substrate and the first side edge satisfy: M2 > M1 - 2P, where P is the pixel period of the display substrate.

3. The display substrate according to claim 1 or 2, wherein, The area of ​​the orthogonal projection of the second light-emitting diode chip on the substrate is greater than the area of ​​the orthogonal projection of the first light-emitting diode chip on the substrate, and the area of ​​the orthogonal projection of the second light-emitting diode chip on the substrate is less than twice the area of ​​the orthogonal projection of the first light-emitting diode chip on the substrate.

4. The display substrate according to claim 1, wherein, The at least one side edge further includes a second side edge, which is adjacent to and intersects with the first side edge; The plurality of light-emitting diode chips also includes a third light-emitting diode chip, which is closer to the intersection of the first side edge and the second side edge than the first light-emitting diode chip. The number of light-emitting areas of the third LED chip is greater than the number of light-emitting areas of the first LED chip; the number of light-emitting areas of the third LED chip is greater than the number of light-emitting areas of the second LED chip.

5. The display substrate according to claim 4, wherein, The shortest distance M1 between the orthographic projection of the side of the first LED chip near the first side edge on the substrate and the first side edge and the shortest distance M3 between the orthographic projection of the side of the third LED chip near the first side edge on the substrate and the first side edge satisfy: M3 > M1 - 2P, where P is the pixel period of the display substrate.

6. The display substrate according to claim 5, wherein, The plurality of light-emitting diode chips also includes a fourth light-emitting diode chip, which is closer to the second side edge than the first light-emitting diode chip; the shortest distance M4 between the orthographic projection of the side of the first light-emitting diode chip near the second side edge on the substrate and the second side edge and the shortest distance M5 between the orthographic projection of the side of the fourth light-emitting diode chip near the second side edge on the substrate and the second side edge satisfy: M5 > M4 - 2P; The shortest distance M4 between the orthographic projection of the side of the first light-emitting diode chip near the second side edge on the substrate and the second side edge and the shortest distance M6 between the orthographic projection of the side of the third light-emitting diode chip near the second side edge on the substrate and the second side edge satisfies: M6 > M4 - 2P, where P is the pixel period of the display substrate.

7. The display substrate according to any one of claims 4-6, wherein, The area of ​​the orthogonal projection of the third light-emitting diode chip on the substrate is greater than the area of ​​the orthogonal projection of the first light-emitting diode chip on the substrate, and the area of ​​the orthogonal projection of the third light-emitting diode chip on the substrate is less than 4 times the area of ​​the orthogonal projection of the first light-emitting diode chip on the substrate.

8. The display substrate according to any one of claims 1, 2, 4-6, wherein, The light-emitting diode chip includes a substrate and multiple light-emitting regions, multiple anodes and a cathode disposed on the substrate, wherein the multiple light-emitting regions and the multiple anodes correspond one-to-one; The light-emitting diode chip also includes a cathode pad electrically connected to the cathode, and the cathode pad and the plurality of light-emitting areas are spaced apart from each other.

9. The display substrate according to claim 8, wherein, The distance from the orthogonal projection of the cathode pad of the second light-emitting diode chip onto the substrate to the first side edge is equal to the pixel period of the display substrate.

10. The display substrate according to any one of claims 4-6, wherein, The light-emitting diode chip includes a substrate and multiple light-emitting regions, multiple anodes and a cathode disposed on the substrate, wherein the multiple light-emitting regions and the multiple anodes correspond one-to-one; The light-emitting diode chip also includes a cathode pad electrically connected to the cathode, and the cathode pad and the plurality of light-emitting areas are spaced apart from each other; The distance from the cathode pad of the third light-emitting diode chip to the first side edge is equal to the pixel period of the display substrate; The distance from the cathode pad of the third light-emitting diode chip to the second side edge is equal to the pixel period of the display substrate.

11. The display substrate according to any one of claims 1, 2, 4-6, wherein, The display substrate further includes a wiring area located at at least one of the side edges; The display substrate also includes multiple traces located in the wiring area, which are used to provide electrical signals to the multiple light-emitting diode chips respectively.

12. The display substrate according to claim 8, wherein, The display substrate further includes a plurality of light conversion units, the orthographic projections of the plurality of light conversion units on the substrate and the orthographic projections of the plurality of light-emitting areas on the substrate respectively at least partially overlap; The light-emitting diode chip is a blue light-emitting LED chip, and the light conversion unit includes a first light conversion unit for converting blue light into red light.

13. The display substrate according to claim 12, wherein, The display substrate includes a light-shielding portion located between adjacent light conversion portions; the distance between the multiple light-emitting areas of the light-emitting diode chip is more than 8 micrometers.

14. The display substrate according to any one of claims 1, 2, 4-6, wherein, The light-emitting diode chip includes a micro LED or a sub-millimeter light-emitting diode.

15. The display substrate according to any one of claims 1, 2, 4-6, wherein, The substrate material includes one of glass, quartz, plastic, silicon, and polyimide.

16. The display substrate according to any one of claims 1, 2, 4-6, wherein, The display substrate includes a first substrate, which includes the substrate substrate and a plurality of first electrodes and a plurality of first terminals disposed on the same side of the substrate substrate; the plurality of first terminals are located at the first side edge of the first substrate and are used to electrically connect signal lines located on the first substrate to an external driving circuit; the signal lines are electrically connected to the plurality of light-emitting diode chips; The external driving circuit is located on the side of the substrate away from the first terminal.

17. The display substrate according to claim 16, wherein, The display substrate further includes a second substrate, the second substrate including a second substrate and the external driving circuit and a plurality of second terminals disposed on the second substrate; The first substrate and the second substrate are stacked together. The plurality of first terminals are located on the side of the substrate opposite to the second substrate, and the plurality of second terminals are located on the side of the second substrate opposite to the first substrate. The display substrate also includes bonding wires that electrically connect the first terminals and the second terminals, and the bonding wires cover the sides of both the first substrate and the second substrate.

18. The display substrate according to claim 16, wherein, The external driving circuit is an integrated circuit chip.

19. A video wall display panel, comprising: A plurality of first display substrates and a plurality of second display substrates, wherein the plurality of first display substrates and the plurality of second display substrates are respectively display substrates according to any one of claims 1-18. Wherein, the side edge of the first display substrate is spliced ​​with the side edge of the second display substrate along a first direction, and / or, the side edge of the first display substrate is spliced ​​with the side edge of the second display substrate along a second direction, wherein the first direction and the second direction intersect.

20. The splicing display panel according to claim 19, wherein, The first display substrate and the second display substrate are symmetrically distributed along the splicing point, which includes the side edge of the first display substrate near the second display substrate and the side edge of the second display substrate near the first display substrate.

21. The splicing display panel according to claim 19 or 20, wherein, For the second display substrate, the at least one side edge includes a third side edge, and the first side edge of the first display substrate is spliced ​​with the third side edge of the second display substrate along a first direction; For the second display substrate, the second light-emitting diode chip is arranged between the first light-emitting diode chip and the third side edge; the light-emitting diode chip includes a plurality of light-emitting areas spaced apart from each other, and the number of light-emitting areas of the second light-emitting diode chip is greater than the number of light-emitting areas of the first light-emitting diode chip.

22. The splicing display panel according to claim 21, wherein, For the second display substrate, the shortest distance M7 between the orthographic projection of the side of the first light-emitting diode chip near the third side edge on the substrate and the third side edge and the shortest distance M8 between the orthographic projection of the side of the second light-emitting diode chip near the third side edge on the substrate and the third side edge satisfy: M8 > M7 - 2P, where P is the pixel period of the display substrate.

23. A display device, comprising: The splicing display panel as described in any one of claims 19-22; And a driving circuit, which is used to drive the splicing display panel.

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