Display device

Abstract

A display apparatus includes a pixel array. The pixel array can include a plurality of light emitting diode (LED) units each including a first conductive type semiconductor layer, an active layer, a second conductive type semiconductor layer, and a transparent electrode including a first lower surface and a second lower surface offset from the first lower surface to form a step. The pixel array can also include a cover electrode on the first lower surface of the transparent electrode of the plurality of LED units, a cap layer covering a lower surface of the cover electrode and the second lower surface of the transparent electrode, a reflective electrode extending at least on side surfaces of the plurality of LED units, and a connection electrode connected to the cover electrode on the plurality of LED units through a contact hole of the cap layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0175151, filed on November 29, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments of this disclosure relate to display devices including miniature light-emitting diodes (LEDs). Background Technology

[0004] Semiconductor LEDs have been used not only as light sources for lighting systems, but also as light sources in various electronic devices. Specifically, LEDs have been widely used as light sources in various display devices, such as televisions, mobile phones, personal computers (PCs), laptops, personal digital assistants (PDAs), etc.

[0005] Display devices in related technologies may include display panels with liquid crystal displays (LCDs) and backlighting. However, recent advancements have led to the development of display devices that use LEDs as pixels and do not require separate backlighting. Compared to traditional LCDs, such display devices offer advantages such as miniaturization, high brightness, and excellent luminous efficiency. Summary of the Invention

[0006] One or more embodiments of this disclosure provide a display device with luminous efficiency.

[0007] According to one aspect of this disclosure, a display device may include a pixel array. The pixel array may include: a plurality of light-emitting diode (LED) units, each including a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, and a transparent electrode, the transparent electrode including a first lower surface and a second lower surface offset from the first lower surface to form a step; a cover electrode located on the first lower surface of the transparent electrode of the plurality of LED units; a capping layer covering the lower surface of the cover electrode and the second lower surface of the transparent electrode; a reflective electrode extending at least on the side surfaces of the plurality of LED units; and a connecting electrode connected to the cover electrode on the plurality of LED units through contact holes in the capping layer.

[0008] According to one aspect of this disclosure, a display device may include a pixel array. The pixel array may include: a plurality of light-emitting diode (LED) units, each including a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, and a contact electrode; a cover electrode contacting a first lower surface of the contact electrode of the plurality of LED units; a first capping layer covering the cover electrode; a second capping layer contacting a second lower surface of the contact electrode, a side surface of the first capping layer, and a side surface of the cover electrode; a reflective electrode extending at least on the side surfaces of the plurality of LED units; and a connection electrode passing through a contact hole in the first capping layer and connected to a connection region on the lower surface of the cover electrode, wherein the area of ​​the first lower surface of the contact electrode is larger than the area of ​​the second lower surface of the contact electrode and the area of ​​the connection region of the cover electrode.

[0009] According to one aspect of this disclosure, a display device may include a pixel array. The pixel array may include: a plurality of light-emitting diode (LED) units, each including a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, and a contact electrode; a cover electrode located on a lower surface of the contact electrode of the plurality of LED units; a cap layer covering at least a portion of each of the cover electrode and the contact electrode; a reflective electrode extending at least on a side surface of the plurality of LED units; and a connection electrode connected to the lower surface of the cover electrode through a contact hole in the cap layer. The contact electrode may include a central portion and a peripheral portion, the central portion overlapping the cover electrode in a vertical direction, and the peripheral portion defining a trench region around the central portion. The cap layer fills the trench region. Attached Figure Description

[0010] The above and other aspects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a schematic perspective view of a display device according to one or more exemplary embodiments of the present disclosure;

[0012] Figure 2 yes Figure 1 Enlarged plan view of part "A" of the display device in the image;

[0013] Figure 3 This is a schematic cross-sectional view of a display device according to one or more exemplary embodiments of the present disclosure;

[0014] Figure 4A yes Figure 3 An enlarged cross-sectional view of part "B" of the display device in the image, and Figure 4B This is a schematic bottom view of the contact electrodes according to one or more example embodiments;

[0015] Figure 5It is a driving circuit implemented in a display device according to one or more example embodiments of the present disclosure;

[0016] Figure 6 This is a schematic cross-sectional view of a display device according to one or more exemplary embodiments of the present disclosure;

[0017] Figure 7 yes Figure 6 A partially enlarged cross-sectional view of the display device "B1" in the image;

[0018] Figure 8 This is a schematic cross-sectional view of a display device according to one or more exemplary embodiments of the present disclosure;

[0019] Figure 9 yes Figure 8 A partially enlarged cross-sectional view of the display device in section "B2";

[0020] Figure 10 This is a schematic cross-sectional view of a display device according to one or more exemplary embodiments of the present disclosure;

[0021] Figure 11 yes Figure 10 A partially enlarged cross-sectional view of the display device in section "B3";

[0022] Figure 12 This is a schematic cross-sectional view of a display device according to one or more exemplary embodiments of the present disclosure;

[0023] Figure 13 yes Figure 12 A partially enlarged cross-sectional view of the display device in section "B4";

[0024] Figures 14A to 14I This is a cross-sectional view of the main process in a method of manufacturing a display device according to one or more exemplary embodiments of the present disclosure;

[0025] Figures 15A to 15L This is a cross-sectional view of the main process in a method of manufacturing a display device according to one or more exemplary embodiments of the present disclosure;

[0026] Figures 16A to 16C This is a cross-sectional view of the main process in a method of manufacturing a display device according to one or more example embodiments of the present disclosure; and

[0027] Figure 17 This is a schematic diagram of an electronic device including a display device according to one or more exemplary embodiments of the present disclosure. Detailed Implementation

[0028] Preferred exemplary embodiments will be described in detail below. Unless otherwise described, terms such as “upper,” “superior,” “upper surface,” “lower,” “lower part,” “lower surface,” and “side surface” are based on the drawings and may vary depending on the actual orientation of the components.

[0029] Furthermore, ordinal numbers such as "first," "second," and "third" can be used as markers for specific elements, operations, directions, etc., to distinguish various elements, steps, directions, etc. from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Moreover, a term referenced by a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere using a different ordinal number (e.g., "second" in the specification or another claim).

[0030] Figure 1 This is a schematic perspective view of a display device according to one or more exemplary embodiments of the present disclosure. Figure 2 yes Figure 1 Enlarged plan view of part "A" of the display device.

[0031] Reference Figure 1 and Figure 2 The display device 10 according to this example embodiment may include a circuit board 200 having driving circuitry and a pixel array 100 disposed on the circuit board 200, with a plurality of pixels PX arranged in the pixel array 100. Furthermore, the display device 10 may also include a frame 11 surrounding the circuit board 200 and the pixel array 100.

[0032] The circuit board 200 may include driving circuitry with thin-film transistor (TFT) cells. In some example embodiments, the circuit board 200 may also include other circuitry besides the driving circuitry for the display device. In some example embodiments, the circuit board 200 may include a flexible board, and the display device 10 may be implemented as a display device with a curved profile.

[0033] Pixel array 100 may include a display area DA and a peripheral area PA located on at least one side of the display area DA. The display area DA may include an LED module for display. Pixel array 100 may have a display area DA in which a plurality of pixels PX are arranged. The peripheral area PA may include a pad area PAD, a connection area CR connecting the plurality of pixels PX and the pad area PAD to each other, and an edge area ISO.

[0034] Each of the plurality of pixels PX may include first to third subpixels SP1, SP2, and SP3 configured to emit light of different colors to provide a color image. For example, the first to third subpixels SP1, SP2, and SP3 may be configured to emit red (R) light, green (G) light, and blue (B) light, respectively.

[0035] In some example embodiments, within each pixel PX (also referred to as a "pixel unit"), the first to third sub-pixels SP1, SP2, and SP3 can be arranged in a Bayer pattern. For example... Figure 2 As shown, each pixel PX may include a first sub-pixel SP1 and a third sub-pixel SP3 (e.g., red (R) and blue (B)) arranged in a first diagonal direction, and two second sub-pixels SP2 (e.g., green (G)) arranged in a second diagonal direction intersecting the first diagonal direction. An electrode contact portion 130C may be formed along the pixel PX to establish an electrical connection between the pixel and the semiconductor substrate layer.

[0036] In this example embodiment, each pixel PX is shown to include first to third sub-pixels SP1, SP2, and SP3 arranged in a 2×2 Bayer pattern. This disclosure is not limited thereto. In other example embodiments, each pixel PX may be constructed in another arrangement such as 3×3 or 4×4. Furthermore, in some example embodiments, each pixel PX may include sub-pixels configured to emit light having a different color than the illustrated colors (R), (G), and (B) (e.g., yellow light). Figure 1 In the pixel array 100, multiple pixels PX are shown arranged in a 15×15 configuration. However, rows and columns can be implemented in any suitable number (e.g., 1024×768 or 1800×1350). For example, the multiple pixels PX can be arranged differently depending on the desired resolution.

[0037] Frame 11 may be a guiding structure surrounding pixel array 100. Frame 11 may include at least one material such as polymer, ceramic, semiconductor, or metal. For example, frame 11 may include a black matrix, which refers to a light-absorbing structure located between pixels to enhance contrast by blocking ambient light and preventing optical crosstalk. However, frame 11 is not limited to a black matrix and may include a white matrix or a structure of another color, depending on the purpose of display device 10. For example, a white matrix may include reflective or scattering materials to improve overall brightness and light efficiency. Although Figure 1 The display device 10 is shown as having a rectangular planar structure, but according to the example embodiment, the display device 10 may have different shapes.

[0038] Figure 3This is a schematic cross-sectional view of a display device according to one or more exemplary embodiments of the present disclosure. Figure 3 Show Figure 1 A partial cross-section (I-I') of the peripheral area PA of the display device and Figure 2 A partial cross-section (II-II') of the display area DA of the display device.

[0039] Figure 4A yes Figure 3 An enlarged cross-sectional view of part "B" of the display device in the image, and Figure 4B This is a schematic bottom view of a contact electrode according to one or more example embodiments.

[0040] Reference Figure 3 , Figure 4A and Figure 4B The display device 10 may include a pixel array 100 and a circuit board 200. The pixel array 100 may include a semiconductor stack 110, which includes first to third LED units LC1, LC2, and LC3 configured to emit light with different wavelengths. The semiconductor stack 110 may have a first surface (or lower surface) opposite to the circuit board 200 and a second surface (or upper surface) opposite to the first surface. In this example embodiment, the semiconductor stack 110 may include a first conductivity type semiconductor substrate layer 112B providing the second surface of the semiconductor stack 110, and a plurality of LED units LC1, LC2, and LC3 disposed on the lower surface of the first conductivity type semiconductor substrate layer 112B. The upper surface of the first conductivity type semiconductor substrate layer 112B may be configured as the second surface (i.e., the light-emitting surface) of the semiconductor stack 110.

[0041] Each of the plurality of LED units LC1, LC2, and LC3 may include at least an active layer 114R, 114G, and 114B stacked on the lower surface of a first conductivity type semiconductor substrate layer 112B, and a second conductivity type semiconductor layer 116. The active layers 114R, 114G, and 114B may refer to regions within the LED unit that generate light by electroluminescence and have a quantum well structure in which electrons and holes recombine when a voltage is applied, resulting in light emission. The first conductivity type semiconductor substrate layer 112B may be a substrate layer shared by the first through third LED units LC1, LC2, and LC3, and may provide contact regions for driving the plurality of LED units LC1, LC2, and LC3. In this example embodiment, the first conductivity type semiconductor substrate layer 112B may be formed with a thickness for reducing light leakage effects while providing contact regions. In some example embodiments, the thickness of the first conductivity type semiconductor substrate layer 112B may be in the range of 0.1 μm to 2 μm.

[0042] Multiple LED units LC1, LC2, and LC3 can each have a micro-LED structure and can be arranged to correspond to the first to third sub-pixels SP1, SP2, and SP3, respectively. The LED unit LC can be arranged in a planar diagram (see...). Figure 2 The LEDs are arranged in multiple rows and columns. Multiple LED units LC1, LC2, and LC3 can be configured as light sources for sub-pixels SP1, SP2, and SP3. In this example embodiment, the multiple LED units LC1, LC2, and LC3 may include active layers 114R, 114G, and 114B that emit light with different wavelengths. Each of the first LED units LC1 may include a first active layer 114R configured to emit red light (e.g., light with wavelengths from 620 nm to 660 nm) and may be configured as a red sub-pixel SP1. Each of the second LED units LC2 may include a second active layer 114G configured to emit green light (e.g., light with wavelengths from 510 nm to 550 nm) and may be configured as a green sub-pixel SP2. Each of the third LED units LC3 may include a third active layer 114B configured to emit blue light (e.g., light with wavelengths from 430 nm to 480 nm) and may be configured as a blue sub-pixel SP3. The first to third active layers 114R, 114G, and 114B can have different emission efficiencies depending on the emission wavelength. In order to achieve smooth color reproduction of the display device 10, the area of ​​the LED unit or the structure of the active layer (the number of quantum wells) can be changed to reduce the variation between the amount of light emitted from the different sub-pixels SP1, SP2, and SP3.

[0043] Each of the plurality of LED units LC1, LC2, and LC3 according to this example embodiment may further include a first conductivity type semiconductor layer 112 located between a first conductivity type semiconductor substrate layer 112B and active layers 114R, 114G, and 114B. The first conductivity type semiconductor layer 112 may be a portion obtained by etching the first conductivity type semiconductor substrate layer 112B. The active layers 114R, 114G, and 114B of the first to third LED units LC1, LC2, and LC3 may be configured to emit light with different wavelengths (e.g., red, green, and blue). In this example embodiment, the first to third active layers 114R, 114G, and 114B of the first to third LED units may include quantum well layers with different indium contents.

[0044] The first conductivity type semiconductor substrate layer 112B and the first conductivity type semiconductor layer 112 can each have N-type In x Al y Ga1-x-y A nitride epitaxial layer composed of N (0≤x<1, 0≤y<1, 0≤x+y<1). For example, the first conductivity type semiconductor layer 112 may be an N-type gallium nitride (n-GaN) layer doped with silicon (Si), germanium (Ge), or carbon (C). Specifically, the first conductivity type semiconductor substrate layer 112B may include a high concentration of N-type nitride (n-GaN) doped in the contact region. + -GaN) layer. The second conductivity type semiconductor layer 116 can be a P-type In) layer. x Al y Ga 1-x-y A nitride semiconductor layer composed of N (0≤x<1, 0≤y<1, 0≤x+y<1). For example, the second conductivity type semiconductor layer 116 can be a p-type nitride (p-GaN) layer doped with magnesium (Mg) or zinc (Zn). The first conductivity type semiconductor layer 112 and the second conductivity type semiconductor layer 116 can each be formed as a single layer, but can also include multiple layers with different properties (such as doping concentration, composition, etc.).

[0045] The semiconductor stack 110 of the first to third LED units LC1, LC2, and LC3 according to this example embodiment may include a nitride epitaxial layer grown on the same substrate. The growth substrate may include a substrate for nitride single-crystal growth, such as at least one selected from sapphire, silicon (Si), silicon carbide (SiC), magnesium aluminate (MgAl2O4), magnesium oxide (MgO), lithium aluminate (LiAlO2), lithium gallium oxide (LiGaO2), and gallium nitride (GaN). In some example embodiments, to improve the crystallinity and light extraction efficiency of the nitride epitaxial layer, the growth substrate may have a non-planar structure on at least a portion of its upper surface.

[0046] Multiple LED units LC1, LC2, and LC3 may include contact electrodes 152 disposed on a second conductivity type semiconductor layer 116. Contact electrodes 152 may be transparent electrodes formed from a transparent conductive oxide and a nitride. For example, contact electrodes 152 may be selected from indium tin oxide (ITO), zinc-doped indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc oxide (ZnO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), gallium tin oxide (GTO), aluminum-doped zinc oxide (AZO), gallium-doped zinc oxide (GZO), and In4Sn3O. 12 and zinc oxide magnesium (Zn (1-x) Mg x O, where 0 ≤ x ≤ 1) at least one of them.

[0047] According to one or more example embodiments, the display device 10 may further include a cover electrode 162 and a capping layer 165. The cover electrode 162 may be disposed on the lower surface of the contact electrode 152. The cover electrode 162 may contact the upper portion of the lower surface of the contact electrode 152 (“first lower surface S1”). The cover electrode 162 may include a metallic material for ohmic contact with the contact electrode 152. The cover electrode 162 may include, for example, silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Pd), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). The cover electrode 162 may reflect light transmitted through the contact electrode 152 toward the reflective electrode 130 and the light-emitting surface of the first conductivity type semiconductor substrate layer 112B, thereby improving the light extraction efficiency (LEE) of the display device 10.

[0048] In one or more example embodiments, the cover electrode 162 may contact a first lower surface S1 of the contact electrode 152. The contact electrode 152 may include a central portion 152a providing the first lower surface S1 and a peripheral portion 152b providing a second lower surface S2. The central portion 152a may overlap the cover electrode 162 in the vertical direction Z. The peripheral portion 152b may surround the central portion 152a and may define a trench region GR. The trench region GR may extend along the outer periphery of the central portion 152a. The thickness t1 of the central portion 152a in the vertical direction Z may be greater than the thickness t2 of the peripheral portion 152b in the vertical direction Z. The first lower surface S1 and the second lower surface S2 may have stepped portions in the vertical direction. The area of ​​the first lower surface S1 of the contact electrode 152 may be greater than the area of ​​each of the second lower surface S2 of the contact electrode 152 and the contact area 155C of the connecting electrode 155.

[0049] The width d1 of the cover electrode 162 can be greater than the upper width d2 of each of the connecting electrodes 155 that contact the cover electrode 152, and can be less than the width d3 of the contact electrode 152. The width d1 of the cover electrode 162 can be substantially equal to the width of the central portion 152a of the contact electrode 152. The difference between the width d1 and the width d3 of the cover electrode 162 can be approximately 200 nm or less. That is, the width of the peripheral portion 152b of the contact electrode 152 can be approximately 100 nm or less. The cover electrode 162 can be formed to have a thickness t3 that ensures light reflection efficiency. The thickness t3 of the cover electrode 162 in the vertical direction Z can be greater than the thickness t1 of the central portion 152a. The thickness t3 of the cover electrode 162 can be approximately 100 nm or greater, but this disclosure is not limited thereto.

[0050] like Figure 4B As shown, the planar shape of the cover electrode 162 can be substantially the same as the planar shape of the contact electrode 152 defined by the first lower surface S1 and the second lower surface S2. Such a configuration can be achieved using a process that forms the contact electrode 152 using the cover electrode 162 and the capping layer 165 as a mask (see [link to documentation]). Figure 14F and Figure 15E This can be implemented by means of a method that allows the cover electrode 162 to largely overlap with the lower surface of the contact electrode 152. The area of ​​the cover electrode 162 can be in the range of approximately 60% or more (e.g., approximately 60% to approximately 90%) of the area of ​​the contact electrode 152.

[0051] A capping layer 165 may cover at least a portion of each of the cover electrode 162 and the contact electrode 152. The capping layer 165 may surround a side surface of the cover electrode 162 and may protect the cover electrode 162 during the process of forming LED cells LC1, LC2, and LC3. The capping layer 165 may include at least one of SiO, SiN, SiON, TiO, HfO, AlN, AlO, and ZrO. The capping layer 165 may include a first capping layer 161 overlapping the cover electrode 162 in the vertical direction Z and a second capping layer 163 surrounding a side surface of the cover electrode 162. The first capping layer 161 may have contact holes connected to the lower surface of the cover electrode 162. The second capping layer 163 may extend along the side surfaces of the first capping layer 161 and the cover electrode 162. The second capping layer 163 may fill the trench region GR formed around the contact electrode 152. The thickness t4 of the first capping layer 161 in the vertical direction may be greater than the thickness t5 of the second capping layer 163 in the horizontal direction Y. The thickness t5 of the second capping layer 163 can be approximately 100 nm or less, for example, in the range of 100 nm to 10 nm.

[0052] According to this example embodiment, the first to third LED units LC1, LC2, and LC3 may have side surfaces that are inclined relative to the lower surface of the first conductivity type semiconductor substrate layer 112B. For example, the side surfaces of the first to third LED units LC1, LC2, and LC3 may have an inclination angle of 85° to 95°. The side surfaces of the first to third LED units LC1, LC2, and LC3 can be formed by an etching process that removes the damaged layer on the side surface of the LED unit (see [link to example]). Figure 15E and Figure 15F This is obtained by etching. Defective areas causing leakage current can be removed by an etching process. Due to material differences (e.g., differences in indium content) between the layers included in the first to third LED units LC1, LC2, and LC3, it is possible to remove these defects during the aforementioned etching process (see [link to etching process]). Figure 15E and Figure 15FDuring this period, there is a difference in tilt angle between the side surfaces of the first LED unit to the third LED units LC1, LC2, and LC3. The first conductivity type semiconductor layer 112, active layers 114R, 114G, and 114B, and the second conductivity type semiconductor layer 116 can have side surfaces with different tilt angles. For example, the second conductivity type semiconductor layer 116 and the active layers 114R, 114G, and 114B can taper upwards. The average width of the second conductivity type semiconductor layer 116 can be greater than the average width of each of the active layers 114R, 114G, and 114B. For example, the minimum width of the second conductivity type semiconductor layer 116 can be greater than or equal to the maximum width of each of the corresponding active layers 114R, 114G, and 114B.

[0053] In some example embodiments, the lower surface (or the upper surface of the growth substrate) of the first conductivity type semiconductor substrate layer 112B can be a (0001) crystal plane, and the side surfaces of the LED units LC1, LC2, and LC3 can be m-planes. In some example embodiments, the passivation layer can be formed to cover the side and lower surfaces of the first to third LED units LC1, LC2, and LC3 (see [link to documentation]). Figures 6 to 9 , Figure 12 and Figure 13 ).

[0054] The pixel array 100 may include a reflective structure configured to emit light onto the upper surfaces of the first to third LED units LC1, LC2, and LC3. According to this example embodiment, the reflective structure may include a spacer 160 having a sloped outer sidewall 160S and a reflective electrode 130 connected to a first conductivity type semiconductor substrate layer 112B. The sloped outer sidewall 160S may have a curved boundary surface. In some example embodiments, the spacer 160 may be omitted, and the reflective electrode 130 may be formed along the side surfaces of the LED units LC1, LC2, and LC3 (see [link to example]). Figure 8 and Figure 9 ).

[0055] Spacers 160 may be formed on the side surfaces of the plurality of LED cells LC1, LC2, and LC3 to provide inclined outer sidewalls 160S. The inclined outer sidewalls 160S may have a curved, slide-like profile, thereby forming a non-linear inclined surface between its side and bottom surfaces. The curve of the inclined outer sidewalls 160S may be concave and inwardly curved. According to one or more example embodiments, spacers 160 may extend upward to the lower surfaces of the plurality of LED cells LC1, LC2, and LC3. For example, spacers 160 may cover the lower surface of capping layer 165, and connecting electrodes 155 may pass through spacers 160.

[0056] The reflective electrode 130 may extend along the outer wall 160S of the spacer 160. The reflective electrode 130 may form a reflective portion 130R with a bowl-shaped structure. The reflective electrode 130 can effectively capture light generated from LED cells LC1, LC2, and LC3 into a desired region. The reflective electrode 130 may extend to a region of the first conductivity type semiconductor substrate layer 112B located between the plurality of LED cells LC1, LC2, and LC3 to serve as a first electrode for driving the LED cells LC1, LC2, and LC3. The first electrode may be a P-type electrode or a P-type transparent electrode. However, embodiments of this disclosure are not limited to these configurations. The first electrode may be implemented as an N-type electrode or an opaque electrode. The reflective electrode 130 may have a contact portion 130C connected to this region of the first conductivity type semiconductor substrate layer 112B.

[0057] The contact portion 130C of the reflective electrode 130, which is configured as the first electrode, can be connected along the region between the plurality of LED units LC1, LC2, and LC3. For example... Figure 2 As shown in the plan view, the reflective electrode 130 (specifically, the contact portion 130C) may have a grid or mesh structure in which the contact portion 130C extends and connects in the X and Y directions. The side cross-section of the reflective electrode 130 may have an inverted U-shape between adjacent LED cells LC1, LC2, and LC3. The reflective electrode 130 may include a reflective electrode material, such as at least one selected from silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W). In some example embodiments, the reflective electrode 130 may include a single-layer structure or a multi-layer structure.

[0058] The reflective electrode 130 may have an extension 130E extending from the display area DA to the peripheral area PA. In the connection area CR, a common electrode 145 may be disposed on the extension 130E of the reflective electrode 130. A pad electrode 147 may be located in the pad area PAD, may be located on the gap-filling insulating layer 141 in a similar manner to the common electrode 145, and may be connected to a bonding pad 199 on the pad electrode 147 for connection to external circuitry.

[0059] The pixel array 100 may further include a gap-filling insulating layer 141 disposed on the lower surface of the semiconductor stack 110, the gap-filling insulating layer 141 covering the reflective electrode 130. The gap-filling insulating layer 141 may have contact holes through the capping layer 165, the contact holes connecting to a region of the capping electrode 162. Connecting electrodes 155 may be electrically connected to the contact electrodes 152 of the plurality of LED units LC1, LC2, and LC3 respectively through the contact holes. The connecting electrodes 155 may be configured as separate electrodes for independently driving the plurality of LED units LC1, LC2, and LC3.

[0060] The pixel array 100 may include an upper bonding insulating layer 191 disposed on the lower surface of the gap-filling insulating layer 141, and upper bonding electrodes 195A, 195B, 195C, and 195D electrically connected to the reflective electrode 130 and the connecting electrode 155, respectively. The upper bonding electrodes 195A, 195B, 195C, and 195D may be electrically connected to the reflective electrode 130 and the connecting electrode 155. The upper bonding electrodes 195A, 195B, 195C, and 195D may have a columnar shape (e.g., an elongated cylindrical form). The lower surface of the upper bonding electrodes 195A, 195B, 195C, and 195D may be a flat surface substantially coplanar with the lower surface of the upper bonding insulating layer 191. The coplanar surface may be the lower surface of the pixel array 100 and may be configured as a bonding surface for bonding to the circuit board 200. The upper bonding electrodes 195A, 195B, 195C, and 195D may include a conductive material, such as copper (Cu). For example, the upper bonding insulating layer 191 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0061] As described above, the common electrode 145 and the pad electrode 147 can be respectively disposed in the connection area CR and the pad area PAD. The common electrode 145 can be configured together with the reflective electrode 130 as a common electrode structure for driving LED units LC1, LC2, and LC3. The pad electrode 147 can be disposed in the pad area PAD and can be connected to the bonding pad 199 on the pad electrode 147 for connection with external circuitry.

[0062] The common electrode 145 and the pad electrode 147 may include a conductive material, such as at least one selected from silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), and gold (Au). For example, the bonding pad 199 may include at least one selected from gold (Au), silver (Ag), and nickel (Ni).

[0063] In this example embodiment, depending on the connection target, the upper bonding electrodes 195A, 195B, 195C, and 195D may include a first upper bonding electrode 195A electrically connected to the reflective electrode 130, a second upper bonding electrode 195B electrically connected to the connection electrode 155, and a third upper bonding electrode 195C connected to the pad electrode 147. Figure 3 As shown, the first upper bonding electrode 195A can pass through the upper bonding insulating layer 191 and the gap-filling insulating layer 141 and land on the common electrode 145. It can be connected to one side of each of the LED units LC1, LC2, and LC3 (specifically, the first conductivity type semiconductor substrate layer 112B) through the common electrode 145 and the reflective electrode 130. The second upper bonding electrode 195B can pass through the upper bonding insulating layer 191 and land on the connection electrode 155. It can be connected to the other side of each of the LED units LC1, LC2, and LC3 (specifically, the second conductivity type semiconductor layer 116) through the first connection electrode 155, the cover electrode 162, and the contact electrode 152. Furthermore, the third upper bonding electrode 195C can pass through the upper bonding insulating layer 191 and the gap-filling insulating layer 141 and land on the pad electrode 147. It can be connected to the bonding pad 199 for connection with external circuitry through the pad electrode 147.

[0064] The circuit board 200 according to this example embodiment may include a device board 201 on which a driving circuit 220 is disposed, and lower bonding structures 291, 295A, 295B, 295C, and 295D disposed on the device board 201. The circuit board 200 may include an interlayer connection structure 230 located between the device board 201 and the lower bonding structures 291, 295A, 295B, 295C, and 295D. The interlayer connection structure 230 may include an interconnect insulating layer 231 on the device board 201, and interconnect circuits 235 electrically connected to the driving circuit 220 in the interconnect insulating layer 231. The driving circuit 220 may include a thin-film transistor (TFT) unit.

[0065] Device board 201 may be a semiconductor board having impurity regions with source / drain regions 205. Device board 201 may include, for example, semiconductors (such as silicon (Si) or germanium (Ge)) or compound semiconductors (such as SiGe, SiC, GaAs, InAs, or InP). Semiconductor substrate 201 may also include through-hole electrodes 250 (such as through-silicon vias (TSVs)) connected to driving circuitry, and first substrate wiring 261 and second substrate wiring 262 connected to through-hole electrodes 250. Driving circuitry 220 may control the driving of pixels (specifically, sub-pixels). The source region 205 of the TFT cell may be electrically connected to one side of each of the LED cells LC1, LC2, and LC3 via interlayer interconnect structure 230 and lower bonding structures 291, 295A, 295B, 295C, and 295D. For example, the drain region 205 of the TFT cell may be connected to a data line via interconnect circuitry 235. The gate electrode of the TFT cell may be connected to a gate line via interconnect circuitry 235. Reference will be made below. Figure 5 Describe the circuit's construction and operation in more detail.

[0066] The lower bonding structures 291, 295A, 295B, 295C, and 295D may include a lower bonding insulating layer 291 and lower bonding electrodes 295A, 295B, 295C, and 295D disposed in the lower bonding insulating layer 291. The lower bonding electrodes 295A, 295B, 295C, and 295D are electrically connected to the driving circuit 220. The lower bonding electrodes 295A, 295B, 295C, and 295D may be electrically connected to the driving circuit 220 via interconnection circuit 235. For example, the lower bonding electrodes 295A, 295B, 295C, and 295D may be configured as pillar structures. The upper surfaces of the lower bonding electrodes 295A, 295B, 295C, and 295D may be flat surfaces that are substantially coplanar with the upper surface of the lower bonding insulating layer 291. The coplanar surface may be configured as the upper surface of the circuit board 200 for bonding to the pixel array 100. The lower bonding electrodes 295A, 295B, 295C, and 295D may include a conductive material, such as copper (Cu). For example, the lower bonding insulating layer 291 may include at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0067] The lower bonding electrodes 295A, 295B, 295C, and 295D of the circuit board 200 and the upper bonding electrodes 195A, 195B, 195C, and 195D of the pixel array 100 can be bonded to each other to provide an electrical connection path between the circuit board 200 and the pixel array 100. Furthermore, the upper bonding insulating layer 191 of the pixel array 100 can be bonded to the lower bonding insulating layer 291 of the circuit board 200.

[0068] As described, the circuit board 200 and the pixel array 100 can be coupled to each other via bonding between lower bonding electrodes 295A, 295B, 295C, and 295D and upper bonding electrodes 195A, 195B, 195C, and 195D, and bonding between lower bonding insulating layer 291 and upper bonding insulating layer 191. The bonding between the lower bonding electrodes 295A, 295B, 295C, and 295D and upper bonding electrodes 195A, 195B, 195C, and 195D can be, for example, copper (Cu)-copper (Cu) bonding, and the bonding between lower bonding insulating layer 291 and upper bonding insulating layer 191 can be dielectric-dielectric bonding, such as a dielectric-dielectric bonding like SiCN-SiCN bonding. The circuit board 200 and the pixel array 100 can be coupled to each other via a hybrid bonding including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding, and can be coupled to each other without an adhesive layer.

[0069] Depending on the connection target, the lower bonding electrodes 295A, 295B, 295C, and 295D can be divided into first to third lower bonding electrodes 295A, 295B, and 295C, respectively, in a manner similar to that of the upper bonding electrodes 195A, 195B, 195C, and 195D. Specifically, the first lower bonding electrode 295A can be bonded to the first upper bonding electrode 195A, such that each of the reflective electrodes 130 can be electrically connected to the drive circuit 220 via the common electrode 145. The second lower bonding electrode 295B can be bonded to the second upper bonding electrode 195B to electrically connect the connection electrode 155 (a separate electrode) to the drive circuit 220.

[0070] As described, multiple LED units LC1, LC2, and LC3 can be connected to the driving circuit 220 via a connection between the first upper bonding electrode 195A and the first lower bonding electrode 295A, and a connection between the second upper bonding electrode 195B and the second lower bonding electrode 295B, so that the multiple LED units LC1, LC2, and LC3 can be driven individually. Furthermore, a third lower bonding electrode 295C can be bonded to the third upper bonding electrode 195C to electrically connect the bonding pad 199 to the driving circuit 220 via the pad electrode 147.

[0071] In this example embodiment, the lower bonding electrodes 295A, 295B, 295C, and 295D may further include a lower dummy bonding electrode 295D that is not connected to the driving circuit 220. Similarly, the upper bonding electrodes 195A, 195B, 195C, and 195D may further include an upper dummy bonding electrode 195D connected to the lower dummy bonding electrode 295D, which is not connected to the plurality of LED cells LC1, LC2, and LC3. The upper dummy bonding electrodes 195D and the lower dummy bonding electrodes 295D may be arranged at regular intervals with the other bonding electrodes 195A, 195B, 195C, 295A, 295B, and 295C over the entire area. In some example embodiments, the upper dummy bonding electrode 195D may be formed on a dummy pad 155D that is not connected to the plurality of LED cells LC1, LC2, and LC3, and the dummy pad 155D may be formed together with the connection electrode 155.

[0072] Microlenses 180 can be disposed on LED units LC1, LC2, and LC3 respectively to converge light emitted from LED units LC1, LC2, and LC3. Microlenses 180 can be configured to adjust the orientation angle of the light emitted from LED units LC1, LC2, and LC3. In this example embodiment, microlenses 180 can be disposed on a first conductivity type semiconductor substrate layer 112B. For example, microlenses 180 can have a diameter larger than the width of LED units LC1, LC2, and LC3 in the X and Y directions.

[0073] The microlens 180 may be formed of, for example, a transparent photoresist material or a transparent thermosetting resin film. The microlens 180 according to this example embodiment may have the same shape and size. However, in some example embodiments, the microlens 180 may have different shapes and / or sizes depending on the area of ​​the first to third LED units LC1, LC2, and LC3.

[0074] Figure 5 It is a driving circuit implemented in a display device according to one or more example embodiments of the present disclosure.

[0075] Reference Figure 5 The diagram shows a circuit diagram of a display device 10 in which n×n sub-pixels are arranged. The first to third sub-pixels SP1, SP2, and SP3 can each receive data signals via data lines D1 to Dn (paths in the vertical direction, for example, the column direction). The first to third sub-pixels SP1, SP2, and SP3 can receive control signals (i.e., gate signals) via gate lines G1 to Gn (paths in the horizontal direction, for example, the row direction).

[0076] Multiple pixels PX, including first sub-pixels to third sub-pixels SP1, SP2, and SP3, can provide a display area DA, and the display area DA (active area) can be set as the user's display area. A passive area NA (or peripheral area PA) can be formed along one or more edges of the display area DA. The passive area NA can extend along the outer periphery of the panel of the display device 10.

[0077] The first driver circuit 12 and the second driver circuit 13 can be used to control the operation of pixels PX (i.e., the first sub-pixels to the third sub-pixels SP1, SP2, and SP3). Part or all of the first driver circuit 12 and the second driver circuit 13 can be implemented in the circuit board 200. The first driver circuit 12 and the second driver circuit 13 can be configured as integrated circuits, thin-film transistor panel circuits, or other suitable circuits, and can be disposed in the passive region NA of the display device 10. The first driver circuit 12 and the second driver circuit 13 may include a microprocessor, a memory such as a storage unit, processing circuitry, and communication circuitry.

[0078] To display an image via pixels PX, the first driver circuit 12 can supply image data to data lines D1 to Dn and can send clock signals and other control signals to the second driver circuit 13 (gate driver circuit). The second driver circuit 13 can be implemented using integrated circuits and / or thin-film transistor circuits. Gate signals for controlling the first to third sub-pixels SP1, SP2, and SP3 arranged in the row direction can be transmitted via the gate lines G1 to Gn of the display device 10.

[0079] Figure 6 This is a schematic cross-sectional view of a display device 10A according to one or more exemplary embodiments of the present disclosure. Figure 7 yes Figure 6 A partially enlarged cross-sectional view of part "B1" of the display device 10A.

[0080] Reference Figure 6 and Figure 7 Apart from adding a passivation layer 120 to the surfaces of the plurality of LED units LC1, LC2, and LC3 and having a recess R in the first conductivity type semiconductor substrate layer 112B, the display device 10A according to this example embodiment can be understood as being similar to... Figures 1 to 5 The display device 10 shown is similar. Furthermore, unless otherwise described, reference may be made to... Figures 1 to 5 The components of this example embodiment are understood by referring to the description of the same or similar components of the display device 10 shown in the figure.

[0081] The display device 10A according to this example embodiment may further include a passivation layer 120 covering the side and bottom surfaces of each of the plurality of LED units LC1, LC2, and LC3 below the spacer 160. The passivation layer 120 may be formed to cover the side and bottom surfaces of the first to third LED units LC1, LC2, and LC3. In this example embodiment, the passivation layer 120 may be formed on the portion of the first conductivity type semiconductor substrate layer 112B located between the first to third LED units LC1, LC2, and LC3. Furthermore, the passivation layer 120 may extend to the region of the first conductivity type semiconductor substrate layer 112B located in the connection region CR. For example, the passivation layer 120 may be disposed in the connection region CR to cover the bottom surface of the first conductivity type semiconductor substrate layer 112B. The passivation layer 120 may include an insulating material, such as at least one of SiO, SiN, SiCN, SiOC, SiON, SiOCN, HfO, AlO, ZrO, and AlN. In some example embodiments, the passivation layer 120 may include two or more insulating layers.

[0082] like Figure 7 As shown, the region of the first conductivity type semiconductor substrate layer 112B located between the plurality of LED cells LC1, LC2, and LC3 may have a recess R. The reflective electrode 130 may have a contact portion 130C' connected to the bottom of the recess R. The first conductivity type semiconductor layer (e.g., n-type semiconductor substrate layer) is highly doped. + (GaN) can be exposed at the bottom of the recess R. In this example embodiment, the recess R can be defined as the region between adjacent spacers 160. The region of the first conductivity type semiconductor substrate layer 112B between the plurality of LED cells LC1, LC2, and LC3 may include the region where the spacers 160 are located and the recess R located between these regions. The reflective electrode 130 may be connected to the bottom of the recess R along the outer sidewall 160S of the spacers 160.

[0083] As described above, in this example embodiment, even when the LED units LC1, LC2, and LC3 are formed with a relatively small height b1, the contact portion 130C' can still be exposed by additional etching during the formation of the recess. The depth b from the lower surface of the second conductivity type semiconductor layer 116 to the desired contact portion 130C' can be the sum of the height b1 of the plurality of LED units LC1, LC2, and LC3 and the depth b2 of the recess R. As a result, the plurality of LED units LC1, LC2, and LC3 can be formed with a relatively small aspect ratio. For example, the aspect ratio b1 / a of the plurality of LED units LC1, LC2, and LC3 can be 1 or less. Adjacent spacers 160 can be used as masks to form the recess R.

[0084] Figure 8 This is a schematic cross-sectional view of a display device 10B according to one or more exemplary embodiments of the present disclosure. Figure 9 yes Figure 8 A magnified cross-sectional view of part "B2" of the display device 10B.

[0085] Reference Figure 8 and Figure 9 Except for adding a passivation layer 120 to the surfaces of the plurality of LED units LC1, LC2 and LC3 and omitting the spacer 160, the display device 10B according to this example embodiment can be understood as being similar to... Figures 1 to 5 The display device 10 shown is similar. Furthermore, unless otherwise described, reference may be made to... Figures 1 to 7 The components of this example embodiment are understood by referring to the description of the same or similar components of the display devices 10 and 10A shown in the figure.

[0086] In this example embodiment, the passivation layer 120 may be formed to cover the side and bottom surfaces of the first to third LED units LC1, LC2, and LC3. The reflective electrode 130 may extend along the bottom surface of the passivation layer 120. The reflective electrode 130 may pass through the passivation layer 120 in the region between the plurality of LED units LC1, LC2, and LC3 and may be connected to the first conductivity type semiconductor substrate layer 112B. In some example embodiments, the reflective electrode 130 may extend to the bottom surface of the first to third LED units LC1, LC2, and LC3.

[0087] Figure 10 This is a schematic cross-sectional view of a display device 10C according to one or more exemplary embodiments of the present disclosure. Figure 11 yes Figure 10 A partially enlarged cross-sectional view of part "B3" of the display device 10C.

[0088] Reference Figure 10 and Figure 11 Except that the spacer 160' has an extension 160E located between the plurality of LED units LC1, LC2 and LC3, the reflective electrode 130' serves as part of a second electrode structure, the plurality of LED units LC1, LC2 and LC3 are separated from each other, and the first electrode 135 is connected to the upper surface of the plurality of LED units LC1, LC2 and LC3, the display device 10C according to this exemplary embodiment can be understood as being with Figures 1 to 5 The display device 10 shown is similar. Furthermore, unless otherwise described, reference may be made to... Figures 1 to 9 The components of this example embodiment are understood by describing the same or similar components of the display devices 10, 10A and 10B shown.

[0089] In this example embodiment, unlike previous example embodiments, each of the plurality of LED units LC1, LC2, and LC3 may include semiconductor stacks 110 that are separated from each other. Each of the plurality of LED units LC1, LC2, and LC3 may include a first conductivity type semiconductor layer 112 having an upper surface configured as a light-emitting surface, and an active layer 114R, 114G, and 114B and a second conductivity type semiconductor layer 116 sequentially stacked on the lower surface of the first conductivity type semiconductor layer 112.

[0090] Similar to the previous example embodiment, spacer 160' may cover the side surface of each of the plurality of LED cells LC1, LC2, and LC3. However, in this example embodiment, spacer 160' may have an extension 160E located between the plurality of LED cells LC1, LC2, and LC3. The extension 160E of spacer 160' may prevent electrical connection between reflective electrode 130' and first conductivity type semiconductor layer 112.

[0091] In this example embodiment, the reflective electrode 130' may be disposed on the spacer 160' and serve as part of the second electrode structure. The reflective electrodes 130' may be separate from each other and disposed respectively on LED units LC1, LC2, and LC3. The reflective electrode 130' may extend to the contact holes of the cap layer 165 and may be connected to the cover electrode 162. The connecting electrode 155 may be connected to the reflective electrode 130' respectively through the contact holes of the gap-filled insulating layer 141. As described, the reflective electrode 130', together with the connecting electrode 155, may serve as a separate electrode for driving LED units LC1, LC2, and LC3.

[0092] In this example embodiment, the multiple LED units LC1, LC2, and LC3 can be separated from each other. During the process of removing the growth substrate, etc. (see...) Figure 16B Subsequently, the unit separation structure can be implemented by an additional etching process for separating the first conductivity type semiconductor substrate layer 112B into multiple LED units LC1, LC2 and LC3.

[0093] In this example embodiment, the first electrode 135 may be disposed on the upper surface of the pixel array 100. The first electrode 135 may be connected to a portion (specifically, the edge) of the upper surface of the plurality of LED units LC1, LC2, and LC3 along the region between the plurality of LED units LC1, LC2, and LC3. The first electrode 135 may serve as a common electrode between the plurality of LED units LC1, LC2, and LC3. The first electrode 135 may have an edge region 135E extending to the connection region CR. The edge region 135E of the first electrode 135 may be connected to the common electrode 145. In a manner similar to the previous example embodiment, the first electrode 135 may have a grid or mesh shape in a planar view.

[0094] Figure 12 This is a schematic cross-sectional view of a display device 10D according to one or more exemplary embodiments of the present disclosure. Figure 13 yes Figure 12 A magnified cross-sectional view of part "B4" of the display device 10D.

[0095] Reference Figure 12 and Figure 13 Except that the spacer 160' has an extension 160E located between the plurality of LED units LC, the reflective electrode 130' serves as part of the second electrode structure, the plurality of LED units LC1, LC2, and LC3 are configured to emit light with the same wavelength, and the conductive partition wall structure 135' is configured as a partition wall structure and has a wavelength conversion structure for the first sub-pixel to the third sub-pixel, the display device 10D according to this example embodiment can be understood as being related to Figures 1 to 5 The display device 10 shown is similar. Furthermore, unless otherwise described, reference may be made to... Figures 1 to 11 The components of this example embodiment are understood by referring to the description of the same or similar components of the display devices 10, 10A, 10B and 10C shown.

[0096] In this example embodiment, with Figure 10 and Figure 11 In a similar manner to the example embodiment shown, the spacer 160' may have an extension 160E located between the plurality of LED cells LC1, LC2, and LC3. The extension 160E of the spacer 160' prevents electrical connection between the reflective electrode 130' and the first conductivity type semiconductor substrate layer 112B. Furthermore, the reflective electrode 130' may be disposed on the spacer 160' and serve as part of a second electrode structure. Connecting electrodes 155 may be connected to the reflective electrode 130' through contact holes in the gap-filled insulating layer 141, respectively. As described, the reflective electrode 130', together with the connecting electrode 155, may serve as a separate electrode for driving the LED cells LC.

[0097] In this example embodiment, the multiple LED cells LC may include the same semiconductor stack to emit light with the same wavelength (e.g., blue). For example, the active layer 114 of the multiple LED cells LC may have a multiple quantum well (MQW) structure configured to emit light with the same wavelength.

[0098] Multiple LED units LC can be interconnected via a first conductivity type semiconductor substrate layer 112B. The upper surface of the first conductivity type semiconductor substrate layer 112B can be configured as a contact area. A conductive partition structure 135' can be disposed on the upper surface of the first conductivity type semiconductor substrate layer 112B and can be in direct contact with the first conductivity type semiconductor substrate layer 112B. In such an arrangement, the conductive partition structure 135' can be configured as a first electrode for each LED unit LC. The conductive partition structure 135' can include a metallic material for ohmic contact with the first conductivity type semiconductor substrate layer 112B. The conductive partition structure 135' formed of the metallic material can be configured as a light-blocking structure to prevent light interference between sub-pixels SP1, SP2, and SP3. For example, the conductive partition structure 135' can include Ag, Cr, Ni, Ti, Al, Rh, Ru, or combinations thereof. The conductive partition structure 135' can be configured as a single-layer structure or a multi-layer structure.

[0099] The conductive partition wall structure 135' may have a grid shape or mesh shape extending in the X and Y directions along the region between sub-pixels SP1, SP2 and SP3 on the upper surface of the semiconductor stack 110. The conductive partition wall structure 135' may be in contact with and electrically connected to the first conductivity type semiconductor substrate layer 112B in the region between LED cells LC.

[0100] The conductive partition structure 135' may have a peripheral region PA (i.e., an edge region 135E' extending to the connection region CR) located on the side of the display region DA where the pixels PX are arranged. As described above, the conductive partition structure 135' may be in direct contact with the first conductivity type semiconductor substrate layer 112B, and the edge region 135E' of the conductive partition structure 135' may be connected to the common electrode 145 through the interconnection portion 132.

[0101] In this example embodiment, a transparent insulating layer 181 may be formed on the upper surface and sidewalls of the conductive partition wall structure 135'. For example, the transparent insulating layer 181 may include at least one of SiO2 and MgF2. Each of the wavelength conversion units 160R, 160G, and 160B for the colors of sub-pixels SP1, SP2, and SP3 may be formed in the sub-pixel space of the conductive partition wall structure 135' in which the transparent insulating layer 181 is formed. The wavelength conversion units 160R, 160G, and 160B may be configured to correspond to the LED unit LC. The wavelength conversion units 160R, 160G, and 160B may include a wavelength conversion material that converts the wavelength of light emitted from the LED unit LC to produce final light with the desired color from the respective sub-pixels SP1, SP2, and SP3. The wavelength conversion material may include phosphors and / or quantum dots, and the wavelength conversion units 160R, 160G, and 160B may be obtained by filling the respective sub-pixel spaces with a liquid adhesive resin in which the wavelength conversion material is dispersed and then curing them.

[0102] When the active layers 114 of the multiple LED units LC are respectively configured to emit blue light, the first wavelength conversion unit 160R can be configured to convert blue light into red light, and the second wavelength conversion unit 160G can be configured to convert blue light into green light. However, the third wavelength conversion unit 160B applied to the subpixel space for the blue subpixel can be replaced with a transparent material such as transparent resin.

[0103] Encapsulation layer 182 can be configured to cover the upper surfaces of wavelength conversion units 160R, 160G, and 160B. Encapsulation layer 182 can serve as a protective layer to prevent degradation of wavelength conversion units 160R, 160G, and 160B. In some example embodiments, encapsulation layer 182 can be omitted. Color filters 180R and 180G can be disposed on wavelength conversion units 160R and 160G in the second sub-pixel SP2 and the third sub-pixel SP3. Color filters 180R and 180G can improve the color purity of light emitted through the first wavelength conversion unit 160R and the second wavelength conversion unit 160G. In some example embodiments, color filters can also be disposed on the third wavelength conversion unit 160B.

[0104] The planarization layer 184 can be configured to cover the color filters 180R and 180G and the upper surface of the encapsulation layer 182. The planarization layer 184 can be a transparent layer. Furthermore, microlenses 180 can be disposed on the planarization layer 184 to correspond to the wavelength conversion units 160R, 160G, and 160B, respectively. The microlenses 180 can converge light incident from the wavelength conversion units 160R, 160G, and 160B. The microlenses 180 can have a diameter larger than the width of each of the LED units LC (e.g., in the X and Y directions). The microlenses 180 can be formed of, for example, a transparent photoresist material or a transparent thermosetting resin layer.

[0105] Figures 14A to 14I This is a cross-sectional view of the main process in a method of manufacturing a display device according to one or more exemplary embodiments of the present disclosure.

[0106] Figures 15A to 15L yes Figures 14A to 14F Cross-sectional view of the main process.

[0107] Reference Figure 14A A semiconductor substrate 111, a first conductivity type semiconductor base layer 112B, a first conductivity type semiconductor layer 112, an active layer 114, and a second conductivity type semiconductor layer 116 can be sequentially formed on the growth substrate 101. Therefore, a contact electrode layer 152', a cover electrode layer 162', and a hard mask layer 161' can be sequentially formed on the second conductivity type semiconductor layer 116.

[0108] The growth substrate 101 can be a substrate for nitride single crystal growth and may include at least one of sapphire, Si, SiC, MgAl2O4, MgO, LiAlO2, LiGaO2, and GaN. The semiconductor underlayer 111, the first conductivity type semiconductor substrate layer 112B, the active layer 114, and the second conductivity type semiconductor layer 116 can be formed using, for example, metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0109] In some example embodiments, the semiconductor substrate 111 may include a buffer layer and an undoped nitride layer (e.g., GaN). The buffer layer may be configured to mitigate lattice defects in the first conductivity type semiconductor layer 112 and may include undoped nitride semiconductors (such as undoped GaN, undoped AlN, and undoped InGaN). The first conductivity type semiconductor substrate layer 112B and the first conductivity type semiconductor layer 112 may be N-type nitride semiconductor layers such as N-type GaN. The first conductivity type semiconductor substrate layer 112B may include a high concentration of N-type GaN providing contact regions. The second conductivity type semiconductor layer 116 may be a P-type nitride semiconductor layer such as P-type GaN / P-type AlGaN. The first to third active layers 114R, 114G, and 114B may have a single quantum well structure or a multi-quantum well structure such as InGaN / GaN.

[0110] The contact electrode layer 152', the cover electrode layer 162', and the hard mask layer 161' can be formed using deposition processes such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). The contact electrode layer 152' may include a transparent electrode or a high-reflectivity ohmic contact layer. The cover electrode layer 162' may include a high-reflectivity material, such as Ag, Al, Au, Rh, etc. The hard mask layer 161' may include an insulating material such as SiO2. In some example embodiments, a thin metal film may also be formed on the hard mask layer 161' for reasons such as adhesion between the hard mask layer 161' and the photoresist, and prevention of deformation of the hard mask layer 161'.

[0111] Reference Figure 14B and Figure 15A A first capping layer 161 can be formed. The first capping layer 161 can be formed by removing a portion of the hard mask layer 161' using a dry etching process employing a patterned photoresist PR. The first capping layer 161 can be formed with upwardly sloping side surfaces. The cover electrode layer 162' can include a material that has etch selectivity relative to the hard mask layer 161'.

[0112] Reference Figure 14C and Figure 15BA cover electrode 162 can be formed. The cover electrode 162 can be formed by removing a portion of the cover electrode layer 162' using a dry etching process employing photoresist PR and a first capping layer 161. The cover electrode 162 can be formed with an upwardly inclined side surface. The dry etching process performed on the cover electrode layer 162' can be stopped after removing a portion of the contact electrode layer 152'. The dry etching process performed on the cover electrode layer 162' can be performed using the contact electrode layer 152'. In this case, the contact electrode layer 152' can be used as an etching stop during the dry etching process. As a result, a trench region GR can be formed in the portion of the contact electrode layer 152' located between the cover electrodes 162.

[0113] Reference Figure 14D and Figure 15C The insulating liner 163' can be formed after the photoresist PR is removed. Atomic layer deposition (ALD) can be used to form the insulating liner 163'. The insulating liner 163' can be conformally formed in the trench region GR of the contact electrode layer 152' and on the surfaces of the cover electrode 162 and the first capping layer 161. The insulating liner 163' can comprise a material similar to or the same as the material of the first capping layer 161.

[0114] Reference Figure 14E and Figure 15D A second capping layer 163 can be formed. The second capping layer 163 can be formed by partially removing the insulating liner 163' using a dry etching process. The second capping layer 163 can cover a portion of the side surface of the first capping layer 161, the side surface of the cover electrode 162, and the side surface of the trench region GR. The first capping layer 161 and the second capping layer 163 can prevent damage to the cover electrode 162 in subsequent processes. The second capping layer 163 can have an upwardly sloping outer surface.

[0115] Reference Figure 14F and Figure 15E Contact electrodes 152 and LED units LC1, LC2, and LC3 can be formed. Contact electrodes 152 and LED units LC1, LC2, and LC3 can be formed by etching a multilayer structure consisting of a first conductivity type semiconductor layer 112, an active layer 114, a second conductivity type semiconductor layer 116, and a contact electrode layer 152'. Contact electrodes 152 can be formed on the second conductivity type semiconductor layer 116. Contact electrode 152 may include a central portion 152a and a peripheral portion 152b surrounding the central portion 152a and defining a trench region GR. LED units LC1, LC2, and LC3 can be formed using a dry etching process using a capping layer 165 as a mask. In this process, LED units LC1, LC2, and LC3 may have damaged regions DR in which crystal defects occur.

[0116] Reference Figure 14G , Figure 15F and Figure 15G The damaged regions DR of LED cells LC1, LC2, and LC3 can be removed, and subsequently, spacers 160 can be formed covering the LED cells LC1, LC2, and LC3 from which the damaged regions DR have been removed. The damaged regions DR can be selectively removed using, for example, wet etching. As a result, nonradiative recombination caused by the damaged regions DR can be reduced, thereby improving brightness. A first conductivity type semiconductor layer 112, an active layer 114, and a second conductivity type semiconductor layer 116 can be etched so that the first conductivity type semiconductor layer 112, the active layer 114, and the second conductivity type semiconductor layer 116 have different widths due to differences in etching rates. For example, the average width of the active layer 114 can be smaller than the average width of the second conductivity type semiconductor layer 116, and the average width of the first conductivity type semiconductor layer 112 can be smaller than the average width of the active layer 114. The spacers 160 can be formed around the side surfaces of the plurality of LED cells LC1, LC2, and LC3. The spacers 160 can be formed using deposition processes, anisotropic etching processes, etch-back processes, etc.

[0117] Reference Figure 14H and Figures 15H to 15L A reflective electrode 130 can be formed on each of the LED units LC1, LC2, and LC3, and a common electrode 145 and a pad electrode 147 can be formed. Subsequently, a gap-filling insulating layer 141 can be formed, and a connection electrode 155 connected to the cover electrode 162 can be formed.

[0118] First, a reflective electrode 130 can be formed on the spacer 160 and the region of the first conductivity type semiconductor substrate layer 112B located between the spacer 160 (see...). Figure 15H The reflective electrode 130 may have a bowl-shaped reflective structure along the inclined outer wall of the spacer 160. The reflective electrode 130 may be electrically connected to the region of the first conductivity type semiconductor substrate layer 112B located between the plurality of LED cells LC1, LC2, and LC3. Subsequently, a common electrode 145 may be connected to the first conductivity type semiconductor substrate layer 112B. The common electrode 145 may be formed on the extension 130E of the reflective electrode 130. The common electrode 145 and the pad electrode 147 may be formed together using the same process.

[0119] Subsequently, the portion of the reflective electrode 130 located on the upper part of the plurality of LED units LC1, LC2 and LC3 can be removed (see...). Figure 15IThe area where the reflective electrode is partially removed can be configured as the path for forming the second electrode structure. Subsequently, a gap-filling insulating layer 141 can be formed to cover the upper portions of the plurality of LED units LC1, LC2, and LC3 on which the reflective electrode 130 is formed. Then, a planarization process, such as chemical mechanical polishing (CMP) or etching back, can be used to planarize the gap-filling insulating layer 141 (see [link to relevant documentation]). Figure 15J For example, the gap-filling insulating layer 141 can be a low-κ material such as silicon oxide.

[0120] Subsequently, contact holes O1 can be formed to allow contact holes O1 to pass through the gap, fill the insulating layer 141, and open the cover electrode 162 (see...). Figure 15K Furthermore, a connecting electrode 155 can be formed on the gap-filling insulating layer 141 to fill the contact hole O1 with a conductive material (see [link]). Figure 15L The connecting electrode 155 can be connected to the contact electrode 152 through the contact hole O1.

[0121] Reference Figure 14I An upper bonding insulating layer 191 and upper bonding electrodes 195A, 195B, 195C, and 195D can be formed. The upper bonding electrodes 195A, 195B, 195C, and 195D can be formed by forming vias through the upper bonding insulating layer 191 and / or gap-filling insulating layer 141 and subsequently filling the vias with a conductive material. The upper bonding electrodes 195A, 195B, 195C, and 195D can be formed to connect to the connection electrode 155, the common electrode 145, and the pad electrode 147.

[0122] Figures 16A to 16C This is a cross-sectional view of the main process in a method of manufacturing a display device according to one or more exemplary embodiments of the present disclosure.

[0123] Reference Figure 16AA pixel array structure 100' comprising first to third LED units LC1, LC2, and LC3 can be bonded to a circuit board 200. The circuit board 200 can be fabricated using a separate process. The pixel array 100' and the circuit board 200 can be bonded to each other at the wafer level using a wafer bonding method (e.g., the hybrid bonding described above). As described above, the circuit board 200 may include a lower bonding insulating layer 291 and lower bonding electrodes 295A, 295B, 295C, and 295D. The lower bonding electrodes 295A, 295B, 295C, and 295D can be bonded to upper bonding electrodes 195A, 195B, 195C, and 195D, and the lower bonding insulating layer 291 can be bonded to the upper bonding insulating layer 191. As described, the pixel array 100' comprising LED units LC1, LC2, and LC3, and the circuit board 200, can be bonded to each other without an adhesive layer.

[0124] Reference Figure 16B The growth substrate 101 and the semiconductor underlayer 111 can be removed. Various processes, such as laser lift-off, mechanical polishing, mechanical-chemical polishing, or etching, can be used to remove the growth substrate 101. The semiconductor underlayer 111 can be partially removed, allowing the thickness of the semiconductor underlayer 111 to be reduced to a predetermined thickness using a polishing process, such as CMP. After removing the semiconductor underlayer 111, a first conductivity type semiconductor substrate layer 112B can be exposed.

[0125] Reference Figure 16C It can also remove the first conductivity type semiconductor substrate layer 112B located in the pad region, and can also form microlenses 180 and bonding pads 199, thereby manufacturing Figures 3 to 4B The display device 10 shown in the figure.

[0126] Figure 17 This is a schematic diagram of an electronic device 1000 including a display device 10 according to one or more exemplary embodiments of the present disclosure.

[0127] Reference Figure 17 The electronic device 1000 according to this example embodiment may be an eyeglass display or a wearable device. The electronic device 1000 may include a pair of temples 1100, a pair of optical coupling lenses 1200, and a nose bridge 1300. The electronic device 1000 may also include a display device 10 having an image generating unit.

[0128] The electronic device 1000 may be a head-mounted, glasses-type, or goggle-type virtual reality (VR), augmented reality (AR), or mixed reality (MR) device capable of providing virtual reality or both virtual images and actual external scenes.

[0129] Temples 1100 may extend in one direction. Temples 1100 may be spaced apart from each other and may extend parallel to each other. Temples 1100 may be folded toward bridge 1300 using hinged connecting units. Bridge 1300 may be disposed between optical coupling lenses 1200 to connect the optical coupling lenses 1200 to each other. Optical coupling lenses 1200 may include light guide plates. Display device 10 may be disposed on each of the portions of temples 1100 adjacent to optical coupling lenses 1200 and may generate images on optical coupling lenses 1200. In some example embodiments, display device 10 may be disposed in some portions of optical coupling lenses 1200.

[0130] According to an example embodiment of this disclosure, a display device with light emission efficiency can be provided by introducing a cover electrode that covers the transparent electrode of each of the micro-sized LED units.

[0131] Although exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A display device, comprising: A pixel array, wherein pixel units are arranged in the pixel array, and each pixel unit has multiple sub-pixels. The pixel array includes: A semiconductor stack includes a first conductivity type semiconductor substrate layer and a plurality of light-emitting diode units. The first conductivity type semiconductor substrate layer has an upper surface that is configured as a light-emitting surface. The plurality of light-emitting diode units are disposed on a lower surface of the first conductivity type semiconductor substrate layer. Each of the plurality of light-emitting diode units has at least an active layer, a second conductivity type semiconductor layer and a transparent electrode. The transparent electrode has a first lower surface and a second lower surface offset from the first lower surface to form a step. Covering electrodes, which are stacked on the first lower surface of the transparent electrodes of each of the plurality of light-emitting diode units; A capping layer that covers the lower surface of the capping electrode and the second lower surface of the transparent electrode; A reflective electrode extending on at least one side surface of each of the plurality of light-emitting diode units; and A connecting electrode, which passes through a contact hole in the cover layer, is electrically connected to the cover electrode located on each of the plurality of light-emitting diode units.

2. The display device according to claim 1, wherein, The transparent electrode includes a central portion providing a first lower surface and a peripheral portion providing a second lower surface, the peripheral portion surrounding the central portion, and The thickness of the central portion in the vertical direction is greater than the thickness of the peripheral portion in the vertical direction.

3. The display device according to claim 2, wherein, The thickness of the covering electrode in the vertical direction is greater than the thickness of the central portion.

4. The display device according to claim 1, wherein, The capping layer includes a first capping layer and a second capping layer, the first capping layer vertically overlapping the covering electrode, and the second capping layer extending along the side surface of the first capping layer and the side surface of the covering electrode.

5. The display device according to claim 4, wherein, The thickness of the first cover layer in the vertical direction is greater than the thickness of the second cover layer in the horizontal direction.

6. The display device according to claim 5, wherein, The thickness of the second capping layer is less than or equal to 100 nm.

7. The display device according to claim 1, wherein, The planar shape of the cover electrode is the same as the planar shape of the transparent electrode defined by the first lower surface and the second lower surface.

8. The display device according to claim 1, wherein, The area of ​​the cover electrode is greater than or equal to 60% of the area of ​​the transparent electrode defined by the first lower surface and the second lower surface.

9. The display device according to claim 1, wherein, The transparent electrode comprises a transparent conductive oxide, and The covering electrode includes at least one of silver (Ag), nickel (Ni), aluminum (Al), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), ruthenium (Ru), magnesium (Mg), zinc (Zn), platinum (Pt), gold (Au), copper (Cu), titanium (Ti), tantalum (Ta), and tungsten (W).

10. The display device according to claim 9, wherein, The transparent conductive oxide includes at least one of indium tin oxide (ITO), zinc indium tin oxide (ZITO), zinc indium oxide (ZIO), gallium indium oxide (GIO), zinc oxide (ZnO), zinc tin oxide (ZTO), fluorine-doped tin oxide (FTO), gallium tin oxide (GTO), aluminum-doped zinc oxide (AZO), and gallium-doped zinc oxide (GZO).

11. The display device according to claim 1, wherein, The capping layer includes at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), titanium oxide (TiO), hafnium oxide (HfO), aluminum nitride (AlN), aluminum oxide (AlO), and zirconium oxide (ZrO).

12. The display device according to claim 1, wherein, The width of the covering electrode is greater than the upper width of the connecting electrode that contacts the covering electrode, and less than the width of the transparent electrode.

13. The display device according to claim 12, wherein, The difference between the width of the covering electrode and the width of the transparent electrode is less than or equal to 200 nm.

14. The display device according to claim 1, wherein, The second conductivity type semiconductor layer and the active layer taper upwards, and The average width of the second conductivity type semiconductor layer is greater than the average width of the active layer.

15. The display device according to claim 14, wherein, The minimum width of the second conductivity type semiconductor layer is greater than or equal to the maximum width of the active layer.

16. The display device according to claim 1, further comprising: A spacer that covers the side surfaces of the plurality of light-emitting diode units and includes an inclined outer sidewall. The reflective electrode extends along the inclined outer wall of the spacer.

17. The display device according to claim 1, in, The first conductivity type semiconductor substrate layer has a recess located between the plurality of light-emitting diode units, and The reflective electrode is electrically connected to the first type of conductive semiconductor substrate layer exposed at the bottom of the recess.

18. The display device according to claim 1, in, The first conductivity type semiconductor substrate layer is configured as a first conductivity type semiconductor layer stacked on the active layer of each of the plurality of light-emitting diode units, and the first conductivity type semiconductor layers are separated from each other. The reflective electrodes are configured to extend into the contact holes of the cover layer, and the reflective electrodes are separated from each other. The connecting electrode is electrically connected to the covering electrode through the reflective electrode in the contact hole.

19. A display device comprising: A pixel array, comprising: Multiple light-emitting diode units, each including a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, and a contact electrode; A cover electrode that contacts the first lower surface of the contact electrode of the plurality of light-emitting diode units; A first capping layer covers the capping electrode; The second capping layer is in contact with the second lower surface of the contact electrode, the side surface of the first capping layer, and the side surface of the covering electrode; A reflective electrode extending at least on the side surfaces of the plurality of light-emitting diode units; and A connecting electrode, which passes through a contact hole in the first cap layer and connects to a connection area on the lower surface of the cover electrode. The area of ​​the first lower surface of the contact electrode is greater than the area of ​​the second lower surface of the contact electrode and the area of ​​the connection region of the covering electrode.

20. A display device, comprising: A pixel array, comprising: Multiple light-emitting diode units, each including a first conductivity type semiconductor layer, an active layer, a second conductivity type semiconductor layer, and a contact electrode; A cover electrode is located on the lower surface of the contact electrode of the plurality of light-emitting diode units; A capping layer that covers at least a portion of each of the cover electrode and the contact electrode; A reflective electrode extending at least on the side surfaces of the plurality of light-emitting diode units; and A connecting electrode, which passes through a contact hole in the cap layer and connects to the lower surface of the cover electrode, The contact electrode includes a central portion and a peripheral portion. The central portion overlaps with the covering electrode in the vertical direction, and the peripheral portion defines a trench region around the central portion. The capping layer fills the trench area.

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