Display device

Abstract

A display device according to an aspect of the disclosure includes a substrate in which a plurality of sub-pixels are defined, a plurality of reflective electrodes disposed on the substrate, a plurality of bonding layers disposed on the plurality of reflective electrodes, a plurality of light emitting diodes disposed on the plurality of bonding layers to respectively correspond to the plurality of bonding layers, a plurality of conductive layers disposed to protrude to the outside from side surfaces of the plurality of light emitting diodes and spaced apart from each other, and at least one connection electrode disposed on the plurality of light emitting diodes. Accordingly, a short circuit caused by a patterning defect of the plurality of bonding layers can be suppressed.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0174036, filed on November 28, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to a display device, and more particularly, to a display device including a light-emitting diode disposed on a bonding layer comprising a conductive material. Background Technology

[0004] Display devices used as displays for computers, televisions, or cellular phones include organic light-emitting display devices (OLEDs) which are self-emissive devices and liquid crystal display devices (LCDs) that require a separate light source.

[0005] The applications of display devices have diversified to include personal digital assistants and computer and television displays, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Furthermore, display devices, including those using light-emitting diodes (LEDs), have recently garnered attention as next-generation display devices. Because LEDs are formed from inorganic rather than organic materials, they offer superior reliability, resulting in a longer lifespan compared to liquid crystal displays or organic light-emitting displays. In addition, LEDs feature fast illumination speed, excellent luminous efficiency, and strong shock resistance, leading to excellent stability and the ability to display high-brightness images. Summary of the Invention

[0007] Another objective of this disclosure is to provide a display device that suppresses short circuits caused by patterning defects in the bonding layer and connecting electrodes.

[0008] Another objective of this disclosure is to provide a display device that suppresses short circuits caused by patterning defects in multiple electrodes corresponding to multiple light-emitting diodes.

[0009] Another objective achieved by this disclosure is to provide a display device with improved luminous efficiency.

[0010] The purpose of this disclosure is not limited to the above-described purposes, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] A display device according to one aspect of this disclosure includes: a substrate defining a plurality of sub-pixels; a plurality of reflective electrodes disposed on the substrate; a plurality of bonding layers disposed on the plurality of reflective electrodes; a plurality of light-emitting diodes disposed on the plurality of bonding layers, each corresponding to one of the bonding layers; a plurality of conductive layers configured to protrude from the side surfaces of the plurality of light-emitting diodes to the outside and spaced apart from each other; and at least one connecting electrode disposed on the plurality of light-emitting diodes. Therefore, short circuits caused by patterning defects in the plurality of bonding layers can be suppressed.

[0012] A display device according to another aspect of this disclosure includes: a substrate; a power line disposed on the substrate; a plurality of transistors disposed on the substrate; a first reflective electrode connected to the power line; a plurality of second reflective electrodes respectively connected to the plurality of transistors; a plurality of bonding layers disposed on the first reflective electrode and the plurality of second reflective electrodes; a plurality of light-emitting diodes disposed on the plurality of bonding layers; a plurality of conductive layers surrounding a portion of the side surfaces of the plurality of light-emitting diodes and protruding outward beyond the plurality of bonding layers; and at least one connecting electrode connected to the first reflective electrode or the plurality of second reflective electrodes. Therefore, short circuits caused by patterning defects in the plurality of bonding layers or at least one connecting electrode can be suppressed.

[0013] Further details of the exemplary embodiments are included in the detailed description and the accompanying drawings.

[0014] According to this disclosure, in a display device, when multiple bonding layers are formed to correspond to multiple light-emitting diodes respectively, short-circuit defects caused by multiple bonding layers that are not completely separated can be suppressed.

[0015] According to this disclosure, in a display device, during the process of patterning a plurality of connecting electrodes to correspond to a plurality of light-emitting diodes respectively, short-circuit defects caused by the plurality of connecting electrodes not being completely separated can be suppressed.

[0016] According to this disclosure, in a display device, light emitted from a plurality of light-emitting diodes is reflected upward by a plurality of conductive layers protruding from the side surfaces of the light-emitting diodes to improve luminous efficiency.

[0017] According to this disclosure, in the display device, light emitted from the light-emitting diode is reflected upwards to improve light extraction efficiency. Therefore, the display device of this disclosure can be driven with lower power.

[0018] The effects of this disclosure are not limited to those illustrated above, and many more effects are included in this specification.

[0019] The objectives achieved by this disclosure, the apparatus for achieving these objectives, and the effects of the above disclosure do not specify the essential features of the claims; therefore, the scope of the claims is not limited to the content of this disclosure. Attached Figure Description

[0020] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0021] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 2 This is a plan view of the pixels of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 3 yes Figure 2 A cross-sectional view of A-A';

[0024] Figures 4A to 4F This is a process diagram illustrating a method for manufacturing pixels of a display device according to exemplary embodiments of the present disclosure;

[0025] Figure 5 This is a plan view of the pixels of a display device according to another exemplary embodiment of the present disclosure;

[0026] Figure 6 yes Figure 5 A cross-sectional view of B-B';

[0027] Figures 7A to 7G This is a process diagram illustrating a method for manufacturing pixels of a display device according to another exemplary embodiment of the present disclosure;

[0028] Figure 8 This is a cross-sectional view of the pixels of a display device according to yet another exemplary embodiment of the present disclosure; and

[0029] Figure 9 This is a cross-sectional view of the pixels of a display device according to yet another exemplary embodiment of the present disclosure. Detailed Implementation

[0030] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0031] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, the same reference numerals generally denote the same elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0032] Even without explicit explanation, components are interpreted as including the normal tolerance range.

[0033] When using terms such as “above,” “over,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0034] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted on or between the other element.

[0035] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below can be the second component in the technical concept of this disclosure.

[0036] Throughout the specification, the same reference numerals generally denote the same elements.

[0037] For ease of description, the dimensions and thicknesses of the various components shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thicknesses of the components shown.

[0038] Features of the various embodiments of this disclosure may be combined or integrated with each other in part or in whole, and may be interconnected and operated in a variety of technical ways, and embodiments may be implemented independently of or in association with each other.

[0039] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure.

[0041] exist Figure 1 For ease of description, only the display panel PN, gate driver GD, data driver DD, and timing controller TC are shown among the various components of the display device 100.

[0042] Reference Figure 1 The display device 100 includes: a display panel PN, including a plurality of sub-pixels SP; a gate driver GD and a data driver DD, supplying various signals to the display panel PN; and a timing controller TC, controlling the gate driver GD and the data driver DD.

[0043] The gate driver GD supplies multiple scan signals to multiple scan lines SL based on multiple gate control signals supplied from the timing controller TC. Although in Figure 1 The diagram shows a gate driver GD configured to be spaced apart from one side of the display panel PN, but the number of gate drivers GDs and their arrangement are not limited to this.

[0044] The data driver DD converts image data input from the timing controller TC into a data voltage using a reference gamma voltage based on multiple data control signals supplied from the timing controller TC. The data driver DD can then supply the converted data voltage to multiple data lines DL.

[0045] The timing controller TC aligns externally input image data to supply the image data to the data driver DD. The timing controller TC can use externally input synchronization signals (e.g., dot clock signals, data enable signals, and horizontal / vertical synchronization signals) to generate gate control signals and data control signals. Furthermore, the timing controller TC supplies the generated gate control signals and data control signals to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0046] The display panel PN is configured to display an image to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and the multiple subpixels SP are respectively connected to the scan lines SL and data lines DL. Additionally, even if not shown in the figure, each of the multiple subpixels SP can be connected to a high-potential power line, a low-potential power line, and a reference line.

[0047] In the display panel PN, an active region AA and a non-active region NA surrounding the active region AA can be defined.

[0048] The active area AA is the area in the display device 100 where an image is displayed. Within the active area AA, multiple sub-pixels SP constituting multiple pixels PX and circuitry for driving the multiple sub-pixels SP can be provided. The multiple sub-pixels SP are the smallest units constituting the active area AA, and n sub-pixels SP form one pixel PX. In each of the multiple sub-pixels SP, a light-emitting diode (LED) and a thin-film transistor (TFT) for driving the LED can be provided. Depending on the type of the display panel PN, the multiple LEDs can be defined in different ways. For example, when the display panel PN is an inorganic light-emitting display panel PN, the LEDs can be LEDs or micro LEDs.

[0049] In the active region AA, multiple signal lines are provided to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines include multiple data lines DL supplying data voltage to each of the multiple sub-pixels SP and multiple scan lines SL supplying gate voltage to each of the multiple sub-pixels SP. The multiple scan lines SL extend in one direction in the active region AA to connect to the multiple sub-pixels SP, and the multiple data lines DL extend in the active region AA in a direction different from that direction to connect to the multiple sub-pixels SP. In addition, low-potential power lines and high-potential power lines may be further provided in the active region AA, but are not limited thereto.

[0050] The non-active region NA is the area where no image is displayed, allowing it to be defined as an area extending from the active region AA. Within the non-active region NA, there may be link lines, pad electrodes, or driver ICs (such as gate driver ICs or data driver ICs) that transmit signals to the sub-pixels SP of the active region AA.

[0051] Meanwhile, the non-active region NA can be located on the rear surface of the display panel PN, that is, the surface on which no sub-pixels SP are provided, or it can be omitted, and is not limited to what is shown in the figure.

[0052] Meanwhile, drivers such as gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be mounted in the non-active region NA as a gate in-panel (GIP) or between multiple sub-pixels SP in the active region AA as a gate in-active region (GIA). For example, the data driver DD and timing controller TC are formed in separate flexible films and printed circuit boards, and are electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-active region NA of the display panel PN. If the gate driver GD is mounted in a GIP manner, and the data driver DD and timing controller TC transmit signals to the display panel PN through the pad electrodes of the non-active region NA, it is necessary to ensure the area of ​​the non-active region NA used for setting the gate driver GD and the pad electrodes. Doing so may increase the bezel.

[0053] Conversely, when the gate driver GD is mounted in the active region AA in a GIA configuration and forms a side line connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the non-active region NA on the front surface of the display panel PN can be minimized. That is, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN as described above, a virtually bezel-less design can be achieved.

[0054] Multiple subpixels SP can form a single pixel. Furthermore, multiple subpixels SP can be composed of subpixels SP to emit different colors of light. For example, multiple subpixels SP may include red subpixels, green subpixels, and blue subpixels. However, this disclosure is not limited thereto; multiple subpixels SP may also include subpixels SP that emit different colors of light.

[0055] At least a portion of the multiple sub-pixels SP can each include two light-emitting diodes (LEDs). In this case, the two LEDs can emit light of the same color. For example, a red sub-pixel can contain two LEDs emitting red light, a green sub-pixel can contain two LEDs emitting green light, and a blue sub-pixel can contain two LEDs emitting blue light.

[0056] Figure 2 This is a plan view of the pixels of a display device according to an exemplary embodiment of the present disclosure. Figure 3 yes Figure 2 A cross-sectional view of line A-A'. For example, Figure 2 This is an enlarged plan view of a portion of pixels PX of a display device 100 according to an exemplary embodiment of the present disclosure. Furthermore, Figure 3This is a cross-sectional view of a pixel PX of a display device 100 according to an exemplary embodiment of the present disclosure.

[0057] Simultaneously refer to Figure 2 and Figure 3 The display device 100 according to an exemplary embodiment of the present disclosure includes a substrate 110, a buffer layer 111, a gate insulating layer 112, an interlayer insulating layer 113, a first planarization layer 114, a second planarization layer 115, a third planarization layer 116, a fourth planarization layer 117, a transistor TR, a plurality of light-emitting diodes LED, a plurality of bonding layers BL, a plurality of conductive layers CL, a plurality of reflective electrodes RE, a power line VL, a connection electrode CE, and a black embankment BB.

[0058] First, the substrate 110 is a component used to support various parts included in the display device 100, and can be formed of an insulating material. For example, the substrate 110 can be formed of glass or resin. Furthermore, the substrate 110 can be configured to contain polymers or plastics, or can be formed of a flexible material.

[0059] A light-shielding layer LS may be disposed on the substrate 110. The light-shielding layer LS blocks light incident from the lower part of the substrate 110 onto the active layer ACT of the transistor TR, which will be described below. The light incident onto the active layer ACT of the transistor TR is blocked by the light-shielding layer LS to minimize leakage current.

[0060] Furthermore, a power line VL can be disposed on the substrate 110. Specifically, the power line VL can be disposed on the same layer as the light-shielding layer LS and spaced apart from it. Furthermore, the power line VL is formed of the same material as the light-shielding layer LS, but is not limited thereto. In the display device 100 according to an exemplary embodiment of the present disclosure, the power line VL can be a low-potential power line and can be supplied with a low-potential voltage, but is not limited thereto; the power line VL can be a high-potential power line supplied with a high-potential voltage.

[0061] A buffer layer 111 may be disposed on the power line VL and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor TR, the buffer layer 111 may be omitted, but is not limited thereto. The buffer layer 111 may include a contact hole, as described below, through which the first reflective electrode RE1 and the power line VL are connected.

[0062] Multiple transistors TR can be disposed on buffer layer 111. Transistor TR may include active layer ACT, gate GE, source SE, and drain DE.

[0063] The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be formed of a semiconductor material, such as oxide semiconductor, amorphous silicon, or polycrystalline silicon, but is not limited thereto.

[0064] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer used to insulate the active layer ACT from the gate GE. Therefore, the gate insulating layer 112 is disposed only between the gate GE and the active layer ACT, but is not limited thereto. For example, the maximum width of the gate insulating layer 112 may be less than the maximum width of the active layer ACT. Furthermore, the gate insulating layer 112 may completely overlap the active layer ACT. Furthermore, the gate insulating layer 112 may be spaced apart from the source SE and drain DE, which will be described below. For example, the gate insulating layer 112 may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0065] The gate GE can be disposed on the gate insulating layer 112. The gate GE can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0066] Interlayer insulating layer 113 may be disposed on gate insulating layer 112. Interlayer insulating layer 113 may include contact holes for connecting source SE and active layer ACT. Furthermore, interlayer insulating layer 113 may include contact holes for connecting drain DE and active layer ACT. Interlayer insulating layer 113 is an insulating layer protecting components beneath it, and may be composed of a single layer or double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0067] The source electrode SE and drain electrode DE, which are electrically connected to the active layer ACT, can be disposed on the interlayer insulating layer 113. The source electrode SE and drain electrode DE can be disposed on the same layer and spaced apart from each other. The source electrode SE can be connected to the active layer ACT through contact holes included in the interlayer insulating layer 113. The drain electrode DE can be connected to the active layer ACT through contact holes included in the interlayer insulating layer 113. The source electrode SE and drain electrode DE can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0068] The first planarization layer 114 can be disposed on the source SE and drain DE. The first planarization layer 114 can planarize the upper part of the pixel circuit including the transistor TR. The first planarization layer 114 can be composed of a single layer or two layers, for example, composed of benzocyclobutene or acrylic organic materials, but is not limited thereto.

[0069] Multiple reflective electrodes RE are disposed on the first planarization layer 114. Furthermore, the multiple reflective electrodes RE include first reflective electrodes RE1 and second reflective electrodes RE2. The first reflective electrodes RE1 and second reflective electrodes RE2 may be spaced apart from each other. In the display device 100 according to an exemplary embodiment of the present disclosure, in a pixel PX, a single first reflective electrode RE1 overlaps with all of the multiple light-emitting diodes (LEDs). The multiple second reflective electrodes RE2 are configured to be as numerous as the number of LEDs. In this case, the multiple second reflective electrodes RE2 and the multiple LEDs may be spaced apart from each other. Furthermore, the multiple second reflective electrodes RE2 may be spaced apart from each other.

[0070] The first reflective electrode RE1 can be connected to the power line VL through contact holes in the first planarization layer 114, the interlayer insulating layer 113, and the buffer layer 111. Furthermore, the first reflective electrode RE1 can contact the plurality of bonding layers BL, which will be described below. Therefore, the first reflective electrode RE1 can electrically connect the power line VL and the plurality of bonding layers BL, as well as the plurality of light-emitting diodes (LEDs), as described below.

[0071] Multiple second reflective electrodes RE2 can be connected to multiple transistors TR respectively through contact holes in the first planarization layer 114. For example, the multiple second reflective electrodes RE2 can be connected to the drain DE of multiple transistors TR respectively, but are not limited thereto. In addition, the second reflective electrodes RE2 can be electrically connected to the second electrodes E2 of multiple light-emitting diodes (LEDs) respectively through multiple connection electrodes CE described below.

[0072] By taking into account light reflection efficiency and resistance, the first reflective electrode RE1 and the second reflective electrode RE2 may include various conductive layers. For example, the first reflective electrode RE1 and the second reflective electrode RE2 may use both opaque conductive layers (e.g., silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or alloys thereof) and transparent conductive layers (e.g., indium tin oxide (ITO)), but are not limited thereto.

[0073] Multiple bonding layers BL are disposed on the first reflective electrode RE1. Furthermore, multiple light-emitting diodes (LEDs) are disposed on the multiple bonding layers BL, each corresponding to one of the multiple bonding layers BL. Therefore, the multiple bonding layers BL are used to fix the multiple light-emitting diodes (LEDs), which will be described below.

[0074] In a planar view, the area of ​​the bonding layer BL can be larger than the area of ​​the LED. In a cross-sectional view, the maximum width of the bonding layer BL can be larger than the maximum width of the LED. Therefore, the LED can completely overlap with the bonding layer BL. For example, multiple LEDs can be disposed within the bonding layer BL without deviating from the bonding layer BL. The planar shape of the bonding layer BL can correspond to, but is not limited to, the planar shape of the LED.

[0075] In a plan view, at least some of the multiple bonding layers BL can be positioned on the same row and spaced apart from each other. For example, at least some of the multiple bonding layers BL can be spaced apart from each other at a constant interval, but are not limited thereto. As another example, at least some of the multiple bonding layers BL can be spaced apart from each other at different intervals.

[0076] The bonding layer BL can be configured to surround the side surface of the first electrode E1 of the light-emitting diode (LED). For example, the bonding layer BL can be configured to surround the entire side surface of the first electrode E1. Specifically, the bonding layer BL includes a recess on its top surface, and the first electrode E1 is inserted into the recess of the bonding layer BL. The bonding layer BL is in contact with a portion of the bottom surface of the first semiconductor layer L1 of the LED, but is not limited thereto.

[0077] The bonding layer BL may contain a conductive material and also a black material. Therefore, the bonding layer BL may be black. For example, the conductive material may contain carbon. For example, the bonding layer BL can be formed by dispersing a carbon-containing conductive material in an acrylic resin, but is not limited thereto. As described above, the bonding layer BL contains a conductive material to electrically connect the first reflective electrode RE1 and the first electrode E1.

[0078] Within a pixel (PX), multiple light-emitting diodes (LEDs) can emit light of different colors. For example, within a pixel (PX), multiple LEDs may include a red LED that emits red light, a green LED that emits green light, and a blue LED that emits blue light.

[0079] In a plan view, at least some of the multiple light-emitting diodes (LEDs) can be arranged in the same row. Furthermore, at least some of the multiple LEDs can be arranged to be spaced apart from each other at the same interval, but are not limited thereto. For example, at least some of the multiple LEDs can be arranged to be spaced apart from each other at different intervals.

[0080] A light-emitting diode (LED) may include a first electrode E1, a first semiconductor layer L1, a light-emitting layer EL, a second semiconductor layer L2, and a second electrode E2.

[0081] In the display device 100 according to an exemplary embodiment of the present disclosure, the first electrode E1 may be a cathode for injecting electrons into the light-emitting layer EL. Furthermore, the first electrode E1 is a cathode and also serves as a reflective layer that reflects light emitted from the light-emitting layer EL upwards. The first electrode E1 may be made of a conductive material, such as a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or a reflective conductive material (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof), but is not limited thereto.

[0082] A first semiconductor layer L1 is disposed on the first electrode E1. In the display device 100 according to an exemplary embodiment of the present disclosure, the first semiconductor layer is a layer formed by doping with an n-type impurity. For example, the first semiconductor layer L1 may be a layer formed by doping an n-type impurity into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The n-type impurity may be silicon (Si), germanium, or tin (Sn), but is not limited thereto.

[0083] The width of the bottom surface of the first semiconductor layer L1 can be greater than the width of the top surface of the first electrode E1. Therefore, at least a portion of the bottom surface of the first semiconductor layer L1 can be exposed by the first electrode E1. As described above, a portion of the exposed bottom surface of the first semiconductor layer L1 can be bonded to the bonding layer BL.

[0084] Meanwhile, the width of the bottom surface of the first semiconductor layer L1 can be equal to the width of the top surface of the first electrode E1. In this case, the bottom surface of the first semiconductor layer L1 does not contact the bonding layer BL. Therefore, the bottom surface and side surface of the first electrode E1 are bonded to the bonding layer BL to fix the light-emitting diode (LED).

[0085] A light-emitting layer EL is disposed on a first semiconductor layer L1. The light-emitting layer EL is supplied with holes and electrons from the first semiconductor layer L1 and the second semiconductor layer L2 to emit light. The light-emitting layer EL can be formed of a single-layer or multiple quantum well (MQW) structure, and can be formed, for example, of indium gallium nitride (InGaN), gallium arsenide (GaAs), or gallium nitride (GaN), but is not limited thereto.

[0086] A second semiconductor layer L2 is disposed on the light-emitting layer EL. In the display device 100 according to an exemplary embodiment of the present disclosure, the second semiconductor layer L2 is a layer formed by doping a p-type impurity into a specific material. For example, the second semiconductor layer L2 may be a layer formed by doping a p-type impurity into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In this case, the p-type impurity may be magnesium, zinc (Zn), or beryllium (Be), but is not limited thereto.

[0087] The second electrode E2 is disposed on the second semiconductor layer L2. In the display device 100 according to an exemplary embodiment of the present disclosure, the second electrode E2 may be an anode for injecting holes into the light-emitting layer EL. The second electrode E2 may be made of a conductive material such as a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof), but is not limited thereto.

[0088] The maximum width of the second electrode E2 can be smaller than the width of the top surface of the second semiconductor layer L2. Therefore, at least a portion of the top surface of the second semiconductor layer L2 can be exposed by the second electrode E2.

[0089] Next, an encapsulation film PAS can be set to surround the first semiconductor layer L1, the light-emitting layer EL, the second semiconductor layer L2, and the second electrode E2.

[0090] The encapsulation film PAS is formed of an insulating material to protect the first semiconductor layer L1, the light-emitting layer EL, and the second semiconductor layer L2. Furthermore, contact holes are formed in the encapsulation film PAS to expose the second electrode E2 for electrical connection to the connection electrode CE and the second electrode E2, which will be described below.

[0091] The second planarization layer 115 can be disposed on the plurality of bonding layers BL. The second planarization layer 115 can planarize the upper part of the first reflective electrode RE1, the second reflective electrode RE2, and the plurality of bonding layers BL disposed therebelow.

[0092] The second planarization layer 115 may cover at least a portion of the first reflective electrode RE1, the second reflective electrode RE2, and the plurality of bonding layers BL. For example, the second planarization layer 115 may cover at least a portion of the top surface of the plurality of bonding layers BL. Furthermore, the second planarization layer 115 may cover the entire side surface of the plurality of bonding layers BL. Therefore, the second planarization layer 115 may be configured to surround the plurality of bonding layers BL.

[0093] The second planarization layer 115 can be configured to surround a plurality of light-emitting elements (LEDs). For example, the second planarization layer 115 can be configured to surround a portion of the side surface of the plurality of light-emitting elements (LEDs). Furthermore, the second planarization layer 115 can be in contact with at least a portion of the side surface of the first semiconductor layer L1 exposed by the encapsulation film PAS.

[0094] The second planarization layer 115 may include a plurality of first holes PAC1_H formed between a plurality of light-emitting diodes (LEDs). The second planarization layer 115 may be spaced apart between the plurality of LEDs through the plurality of first holes PAC1_H. Therefore, the first reflective electrode RE1 may be exposed between the plurality of LEDs through the plurality of first holes PAC1_H. In addition, the second planarization layer 115 may also include a plurality of contact holes CH, which connect the plurality of connection electrodes CE and the plurality of second reflective electrodes RE2, which will be described below.

[0095] Multiple conductive layers CL are disposed on the second planarization layer 115. The conductive layers CL are configured to protrude outwards from the side surfaces of the multiple light-emitting diodes (LEDs). The conductive layers CL may be configured to contact the top surface of the second planarization layer 115. Furthermore, the conductive layers CL may contact the side surfaces of the LEDs. For example, a portion of the conductive layer CL in contact with the side surfaces of the LEDs may have the maximum thickness. Therefore, the top surface of the conductive layers CL may be formed by two regions with different heights. Additionally, the top surface of the conductive layers CL may include at least one step.

[0096] In the cross-sectional view, at least one end of the plurality of conductive layers CL may protrude outward beyond one end of the second planarization layer 115. Specifically, between the plurality of light-emitting diodes (LEDs), one end of the plurality of conductive layers CL may protrude outward beyond one end of the second planarization layer 115. Therefore, between the plurality of light-emitting diodes (LEDs), the second planarization layer 115 can form an undercut structure through the protruding plurality of conductive layers CL.

[0097] Furthermore, the end of the conductive layer CL may protrude outwards than the end of the bonding layer BL. Therefore, in a plan view, the outline of the conductive layer CL has a shape that surrounds the outline of the bonding layer BL. Unless otherwise stated in this specification, "outer" refers to the direction away from the light-emitting diode (LED), while "inner" refers to the direction closer to the LED.

[0098] Multiple conductive layers CL are spaced apart from each other. Specifically, the multiple conductive layers CL are spaced apart from each other on the first hole PAC1_H formed between the multiple light-emitting diodes (LEDs). Therefore, at least a portion of the first reflective electrode RE1 can be exposed by the multiple conductive layers CL that are spaced apart from each other.

[0099] The multiple conductive layers CL can be conductive materials such as transparent conductive materials (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)), or reflective metallic materials, but are not limited thereto, and can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx) as inorganic films.

[0100] A third planarization layer 116 can be disposed on a plurality of conductive layers CL. The third planarization layer 116 can contact at least a portion of the top surface of the plurality of conductive layers CL. Therefore, the plurality of conductive layers CL can be disposed between the second planarization layer 115 and the third planarization layer 116. Furthermore, the third planarization layer 116 can cover at least a portion of the ends of the conductive layers CL. Additionally, the third planarization layer 116 can cover the uppermost edge of the plurality of conductive layers CL. Together, the third planarization layer 116 can contact at least a portion of the side surfaces of the plurality of light-emitting elements LED. Furthermore, the third planarization layer 116 can be configured to surround the plurality of light-emitting elements LED. Therefore, the third planarization layer 116 can fix and protect the plurality of light-emitting diodes LED.

[0101] The third planarization layer 116 may include a second aperture PAC2_H located between a plurality of light-emitting diodes (LEDs). The third planarization layer 116 may be spaced apart from each other between the plurality of LEDs through the second aperture PAC2_H. The second aperture PAC2_H may overlap with the first aperture PAC1_H. Furthermore, the second aperture PAC2_H may overlap with regions of the plurality of conductive layers CL that are spaced apart from each other. Therefore, the first reflective electrode RE1 may be exposed between the plurality of LEDs.

[0102] One end of the third planarization layer 116 may be disposed inside one end of one of the multiple conductive layers CL between the multiple light-emitting diodes (LEDs). Therefore, between the multiple LEDs, one end of the multiple conductive layers CL may protrude outwards than one end of the second planarization layer 115 and one end of the third planarization layer 116. The side surface of the third planarization layer 116 may protrude downwards and outwards. Therefore, the third planarization layer 116 has a tapered shape and the second hole PAC2_H has an inverted tapered shape, but is not limited to this.

[0103] The third planarization layer 116 may further include a contact hole CH connecting the connecting electrode CE and the second reflective electrode RE2, as described below. In this case, the contact hole CH of the third planarization layer 116 is connected to the contact hole CH of the second planarization layer 115 to form a single contact hole CH.

[0104] For example, the first planarization layer 114, the second planarization layer 115, and the third planarization layer 116 may be composed of benzocyclobutene or acrylic-based organic materials, but are not limited thereto. The first planarization layer 114, the second planarization layer 115, and the third planarization layer 116 may be formed of different materials, but are not limited thereto, and may also be formed of the same material.

[0105] In the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of connection electrodes CE are disposed on a third planarization layer 116. The plurality of connection electrodes CE can electrically connect a plurality of light-emitting diodes (LEDs) and a plurality of second reflective electrodes RE2, respectively. For example, a second reflective electrode RE2 and a light-emitting diode (LED) can be electrically connected through a single connection electrode CE.

[0106] One end of a plurality of connection electrodes CE is connected to a plurality of light-emitting diodes (LEDs), and the other end is connected to a plurality of second reflective electrodes RE2 through contact holes CH. As described above, the connection electrodes CE can be connected to the second reflective electrodes RE2 through the contact holes CH of the second planarization layer 115 and the third planarization layer 116. Furthermore, the connection electrodes CE can be connected to the second electrode E2 exposed through the encapsulation film PAS. Therefore, the connection electrodes CE can electrically connect the drain DE of the transistor TR and the second electrode E2 of the light-emitting diodes (LEDs).

[0107] The ends of the multiple connecting electrodes CE can be disposed inside the ends of the multiple conductive layers CL. Furthermore, the multiple connecting electrodes CE can be spaced apart from each other. Specifically, the multiple connecting electrodes CE can be configured to correspond to multiple light-emitting diodes (LEDs) respectively, and can be spaced apart from each other among the LEDs. The multiple connecting electrodes CE do not overlap with the second hole PAC2_H.

[0108] The connecting electrode CE can be made of conductive materials such as transparent conductive materials (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or opaque conductive materials (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu) or alloys thereof), but is not limited thereto.

[0109] The black dam BB can be disposed on the third planarization layer 116 and multiple connecting electrodes CE. The black dam BB is a component used to distinguish adjacent sub-pixels SP. The black dam BB can be configured not to overlap with the light-emitting layer EL of the light-emitting diode LED. The black dam BB can cover one end of the connecting electrode CE. Therefore, the black dam BB can cover at least a portion of the upper surface of the connecting electrode CE. Furthermore, the black dam BB can fill the contact hole CH of the connecting electrode CE.

[0110] The black embankment BB can be formed from acrylic resin, benzocyclobutene (BCB) resin or polyimide, and may also include, but is not limited to, a black component.

[0111] A fourth planarization layer 117 can be disposed on the black embankment BB. The fourth planarization layer 117 covers the third planarization layer 116, the plurality of connecting electrodes CE, and the black embankment BB to protect the configuration disposed beneath it. Furthermore, the fourth planarization layer 117 can fill the first hole PAC1_H and the second hole PAC2_H. Therefore, the fourth planarization layer 117 can contact the top surface of the first reflective electrode RE1 exposed by the first hole PAC1_H and the second hole PAC2_H between the plurality of light-emitting diodes (LEDs). Additionally, the fourth planarization layer 117 fills the first hole PAC1_H between the plurality of bonding layers BL, such that the plurality of bonding layers BL are completely spaced apart from each other.

[0112] The fourth planarization layer 117 may consist of a single layer or two layers, and may be formed, for example, by a photoresist or an acrylic-based organic material, but is not limited thereto.

[0113] In the following text, reference will be made to Figures 4A to 4F A method for manufacturing a display device 100 according to an exemplary embodiment of the present disclosure is described in detail.

[0114] Figures 4A to 4F This is a process diagram illustrating a method for manufacturing pixels of a display device according to exemplary embodiments of the present disclosure.

[0115] First, refer to Figure 4A First reflective electrode RE1 and second reflective electrode RE2 can be disposed on substrate 110. Next, a bonding material for forming a plurality of bonding layers BL is coated on first reflective electrode RE1. At this time, the bonding material may include a conductive material. Furthermore, the coated bonding material is patterned to form a plurality of bonding layers BL. As described above, in the display device 100 according to an exemplary embodiment of the present disclosure, the plurality of bonding layers BL does not include conductive balls, so that the size of each of the plurality of bonding layers BL can be further reduced. Therefore, the overall size of the pixel PX including the plurality of bonding layers BL can be reduced. Furthermore, as described above, reducing the size of the pixel PX makes it possible to provide more pixels PX in the same area, thereby enabling the display device 100 with high resolution.

[0116] Next, multiple light-emitting diodes (LEDs) can be transferred onto each of the multiple formed bonding layers BL. At this time, the first electrode E1 of each of the multiple LEDs is inserted into the bonding layer BL to be bonded. Furthermore, each of the multiple bonding layers BL can be formed to be wider than each of the multiple LEDs. Therefore, even if alignment errors occur during the transfer process of the multiple LEDs, the multiple LEDs can be stably transferred onto the multiple bonding layers BL. Next, a material for forming the second planarization layer 115 can be applied. At this time, the height of the top surface of the second planarization layer 115 can be formed to be higher than the top surface of the multiple bonding layers BL. Furthermore, the height of the top surface of the second planarization layer 115 can be formed to be lower than the height of the top surface of the multiple LEDs. Therefore, the second planarization layer 115 can be formed to cover the side surfaces and top surfaces of the multiple bonding layers BL. Furthermore, a portion of the side surfaces and top surfaces of the multiple LEDs can be exposed through the second planarization layer 115.

[0117] Next, refer to Figure 4B A conductive layer CL can be disposed on the second planarization layer 115 and on a plurality of light-emitting diodes (LEDs) exposed by the second planarization layer 115. Furthermore, a photoresist PR for patterning the conductive layer CL can be disposed. In this case, the photoresist PR is patterned to cover each of the plurality of LEDs. The plurality of patterned photoresist PRs can be configured to cover the top and side surfaces of each of the plurality of LEDs on the conductive layer CL. Therefore, a portion of the conductive layer CL can be exposed by the plurality of photoresist PRs.

[0118] Next, refer to Figure 4C The process of etching multiple photoresists (PRs) can be performed. As described above, the multiple photoresists (PRs) are etched to form a top surface height lower than the top surface height of the multiple light-emitting diodes (LEDs). Therefore, a portion of the side surface and a portion of the conductive layer (CL) covering the top surface of the multiple light-emitting diodes (LEDs) can be exposed by the etched multiple photoresists (PRs).

[0119] Next, refer to Figure 4D This process allows for etching of the conductive layer CL exposed by multiple photoresists PR. Therefore, the conductive layer CL in areas not covered by the multiple photoresists PR can be removed. Furthermore, the conductive layer CL can be retained only in the portion of the surface in contact with the side surfaces of the multiple light-emitting diodes (LEDs).

[0120] Next, refer to Figure 4EThe material used to form the third planarization layer 116 can be coated onto the second planarization layer 115, the conductive layer CL, and the light-emitting diodes (LEDs). Furthermore, a patterning process for removing the third planarization layer 116 can be performed between the multiple LEDs. Therefore, the third planarization layer 116 between the multiple LEDs can be removed. At this time, the ends of the third planarization layer 116 between the multiple LEDs can be located on the multiple conductive layers CL. Therefore, the top surface of the second planarization layer 115 can be exposed between the multiple LEDs.

[0121] Next, refer to Figure 4F The etching process of the third planarization layer 116 can be performed. By reducing the height of the top surface of the third planarization layer 116 through the etching process, the top surfaces of the multiple light-emitting diodes (LEDs) can be exposed. The second planarization layer 115 exposed between the multiple LEDs can be etched together with the third planarization layer 116. Therefore, between the multiple LEDs, the first hole PAC1_H is formed in the second planarization layer 115, and the second hole PAC2_H can be formed in the third planarization layer 116. At this time, the multiple conductive layers CL are not etched by the etchant used to etch the third planarization layer 116, allowing the multiple conductive layers CL to be used as a pattern mask. Therefore, the second planarization layer 115 not covered by the multiple conductive layers CL between the multiple LEDs can be removed. Furthermore, a portion of the etchant can penetrate the lower part of the multiple conductive layers CL, allowing the portion of the second planarization layer 115 covered by the multiple conductive layers CL to be removed together. Therefore, the conductive layers CL and the second planarization layer 115 form an undercut structure in the first hole PAC1_H between the multiple LEDs.

[0122] Next, multiple connection electrodes CE can be disposed on the multiple light-emitting diodes (LEDs) exposed by the third planarization layer 116. At this time, the multiple connection electrodes CE can be configured to completely cover the top surface of the multiple LEDs exposed by the third planarization layer 116. Furthermore, the multiple connection electrodes CE can be configured to correspond to each of the multiple LEDs. At this time, the multiple connection electrodes CE apply different signals to each of the multiple LEDs, requiring the multiple connection electrodes CE to be completely separated from each other. However, for high resolution, the size of the LEDs needs to be further reduced, and the reduced spacing between them makes the space for separating the connection electrodes narrower. Therefore, during the patterning process for separating the connection electrodes, a patterning defect may occur where adjacent connection electrodes are not completely separated. As described above, when a patterning defect occurs, a short-circuit defect may occur in the electrical connection between adjacent connection electrodes. However, in the display device 100 according to an exemplary embodiment of the present disclosure, the connection electrodes CE are disposed after the undercut structure of the second planarization layer 115 is formed between the multiple LEDs. Therefore, the connection electrodes CE can be completely disconnected between the multiple LEDs.

[0123] Specifically, a light-emitting diode (LED) is a semiconductor light-emitting diode that converts electric current into light and is used to realize various display devices. To achieve high resolution in a display device, more pixels need to be placed in a limited space. Therefore, the size of the pixels needs to be small, and the LEDs in the sub-pixels within those pixels also need to be small.

[0124] As described above, the smaller size and denser formation of light-emitting diodes (LEDs) necessitate more precise patterning of the connection electrodes to which different signals are applied to each LED. Specifically, in a p-up structure where the anode of the LED is located at the top, the anode of each of the multiple LEDs needs to be connected to each of the multiple transistors. Therefore, a display device with a p-up structure can include multiple connection electrodes that electrically connect the anodes of the multiple LEDs to the multiple transistors, respectively. Since the multiple LEDs need to emit different colors, the multiple connection electrodes need to apply different signals to the multiple LEDs. Therefore, the connection electrodes need to be patterned to be spaced apart from each other to correspond to each of the multiple LEDs. Simultaneously, during the LED transfer process, misalignment defects may occur, such as LEDs not being transferred to the desired position. As described above, by considering the possibility of LED misalignment, the connection electrodes connected to the LEDs can be patterned to be wider than the LEDs. However, to achieve high resolution in the display device, with small and densely arranged LEDs, it is difficult to ensure sufficient space for the connection electrodes to be patterned and placed in an area wider than the LEDs. As mentioned above, if sufficient space is not ensured between multiple connection electrodes, the patterning process for spacing the multiple connection electrodes needs to be performed more precisely, which may increase the probability of defects. If a patterning defect occurs during the connection electrode formation process, the resulting residue of the connection electrode may remain in the area between the multiple light-emitting diodes. Therefore, multiple connection electrodes that need to be spaced apart from each other are electrically connected, which may lead to short-circuit defects.

[0125] Therefore, the display device 100 according to an exemplary embodiment of the present disclosure includes a plurality of conductive layers CL, which protrude outward from the side surfaces of a plurality of light-emitting diodes (LEDs) and are spaced apart from each other. The plurality of conductive layers CL can be used as a pattern mask, which inhibits the etching of the second planarization layer 115 disposed beneath it. Therefore, the second planarization layer 115 blocked by the plurality of conductive layers CL between the plurality of LEDs can be removed, and a portion of the second planarization layer 115 blocked by the plurality of conductive layers CL can be left unremoved. Therefore, the second planarization layer 115 includes a plurality of first holes PAC1_H, having an undercut structure between the plurality of LEDs. Therefore, a plurality of connection electrodes CE, respectively corresponding to the plurality of LEDs, can be completely disconnected between the plurality of LEDs through the undercut structure of the second planarization layer 115.

[0126] Figure 5 This is a plan view of the pixels of a display device according to another exemplary embodiment of the present disclosure. Figure 6 yes Figure 5A cross-sectional view of B-B'. Besides the power line VL, multiple light-emitting diodes (LEDs), multiple reflective electrodes (REs), and connecting electrodes (CE), Figure 5 and Figure 6 The display device has the same Figures 1 to 4F The display device 100 has a basically the same configuration, so redundant descriptions will be omitted.

[0127] Refer to together Figure 5 and Figure 6 In a display device 200 according to another exemplary embodiment of the present disclosure, in a pixel PX, a single first reflective electrode RE1 is spaced apart from a plurality of light-emitting diodes (LEDs). Furthermore, a plurality of second reflective electrodes RE2 may be arranged to be spaced apart from each other as many times as the number of LEDs. Additionally, the plurality of second reflective electrodes RE2 may each overlap with a plurality of LEDs. For example, only one LED may be disposed on one second reflective electrode RE2.

[0128] The first reflective electrode RE1 can be connected to the power line VL through contact holes in the first planarization layer 114, the interlayer insulating layer 113, and the buffer layer 111. In a display device 200 according to another exemplary embodiment of the present disclosure, the power line VL can be a high-potential power line and can be supplied with a high-potential voltage, but is not limited thereto; the power line VL can also be a low-potential power line supplied with a low-potential voltage. Furthermore, the first reflective electrode RE1 can be connected to all of the plurality of light-emitting diodes (LEDs) through the connecting electrode CE. For example, in a pixel PX, the plurality of light-emitting diodes (LEDs) can be electrically connected to a first reflective electrode RE1.

[0129] A plurality of second reflective electrodes RE2 may be spaced apart from the first reflective electrode RE1. Furthermore, the plurality of second reflective electrodes RE2 may be configured to be spaced apart from each other. Specifically, in a display device 200 according to another exemplary embodiment of the present disclosure, the plurality of second reflective electrodes RE2 overlapping with a plurality of light-emitting diodes (LEDs) may be configured to be spaced apart from each other between the plurality of LEDs. Furthermore, in a display device 200 according to another exemplary embodiment of the present disclosure, the regions of the plurality of second reflective electrodes RE2 spaced apart from each other between the plurality of LEDs are included in the first aperture PAC1_H; therefore, the regions of the plurality of second reflective electrodes RE2 spaced apart from each other between the plurality of LEDs may overlap with the second aperture PAC2_H. A portion of the top surface of the first planarization layer 114 may be exposed between the plurality of LEDs through the spaced-apart second reflective electrodes RE2.

[0130] Multiple second reflective electrodes RE2 can be configured to correspond to multiple bonding layers BL, respectively. Furthermore, the second reflective electrodes RE2 can overlap with each of the bonding layers BL. In this case, the multiple second reflective electrodes RE2 can contact each of the bonding layers BL. Additionally, the multiple second reflective electrodes RE2 can be connected to the drain DE of each of the multiple transistors TR. Therefore, multiple light-emitting diodes (LEDs) can be electrically connected to the multiple transistors TR through the correspondingly configured second reflective electrodes RE2.

[0131] In a display device 200 according to another exemplary embodiment of the present disclosure, the first electrode E1 of the light-emitting diode (LED) can be an anode for injecting holes into the light-emitting layer EL. Furthermore, the first electrode E1 is not only an anode but also serves as a reflective layer that reflects light emitted from the light-emitting layer EL upwards. The first electrode E1 can be made of a conductive material, such as a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or an opaque conductive material (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof), but is not limited thereto.

[0132] Furthermore, the first semiconductor layer L1 can be a layer formed by doping a p-type impurity into a specific material. For example, the first semiconductor layer L1 can be a layer formed by doping a p-type impurity into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In this case, the p-type impurity can be magnesium, zinc (Zn), or beryllium (Be), but is not limited to these.

[0133] Furthermore, the second semiconductor layer L2 can be a layer formed by doping with an n-type impurity. For example, the second semiconductor layer L2 can be a layer formed by doping an n-type impurity into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The n-type impurity can be silicon (Si), germanium, or tin (Sn), but is not limited to these.

[0134] Next, the second electrode E2 can be a cathode for injecting electrons into the light-emitting layer EL. Furthermore, the second electrode E2, being a cathode, can also serve as a reflective layer that reflects light emitted from the light-emitting layer EL upwards. The second electrode E2 can be made of, but is not limited to, a conductive material such as a transparent conductive material (e.g., indium tin oxide (ITO) or indium zinc oxide (IZO)) or a reflective conductive material (e.g., titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof).

[0135] In a display device 200 according to another exemplary embodiment of the present disclosure, a connection electrode CE can be provided in a pixel PX. Furthermore, a connection electrode CE can be connected to a plurality of light-emitting diodes (LEDs). Specifically, a connection electrode CE can be connected to the second electrode E2 of the plurality of LEDs. The connection electrode CE can be connected to the first reflective electrode RE1 through the contact holes CH of the second planarization layer 115 and the third planarization layer 116. Therefore, the connection electrode CE can electrically connect the plurality of LEDs and the first reflective electrode RE1. As described above, the plurality of LEDs can be electrically connected to the power line VL through the connection electrode CE and the first reflective electrode RE1.

[0136] Meanwhile, the connecting electrode CE may not be positioned between the multiple light-emitting diodes (LEDs). Therefore, one connecting electrode CE is spaced apart from each other among the multiple LEDs. In this case, at least a portion of the area where the connecting electrodes CE are spaced apart from each other can overlap with the area where the multiple second reflective electrodes RE2 are spaced apart from each other.

[0137] In the following text, reference will be made to Figures 7A to 7G A method for manufacturing a display device 200 according to another exemplary embodiment of the present disclosure is described in detail.

[0138] Figures 7A to 7G This is a process diagram illustrating a method for manufacturing pixels of a display device according to another exemplary embodiment of the present disclosure.

[0139] First, refer to Figure 7A A reflective electrode RE is disposed on the substrate 110 and is patterned to form a first reflective electrode RE1 and a plurality of second reflective electrodes RE2. At this time, the first reflective electrode RE1 and the plurality of second reflective electrodes RE2 can be configured to be spaced apart from each other by the patterning process.

[0140] Next, refer to Figure 7B A bonding material for forming multiple bonding layers BL can be coated onto the first reflective electrode RE1 and the second reflective electrode RE2. In this case, the bonding material may include a conductive material. As described above, in the display device 200 according to another exemplary embodiment of the present disclosure, the multiple bonding layers BL do not include conductive balls, allowing for a further reduction in the size of each of the multiple bonding layers BL. Therefore, the overall size of the pixel PX, including the multiple bonding layers BL, can be reduced. Furthermore, as described above, reducing the size of the pixel PX allows for the placement of more pixels PX in the same area, thereby enabling the display device 200 to achieve a high resolution.

[0141] Next, the coated bonding material is patterned to form multiple bonding layers BL only on the multiple second reflective electrodes RE2. Then, multiple light-emitting diodes (LEDs) can be transferred onto the formed multiple bonding layers BL. At this time, the first electrode E1 of each of the multiple LEDs is inserted into the bonding layer BL to be bonded. Furthermore, each of the multiple bonding layers BL can be formed to be wider than each of the multiple LEDs. Therefore, even if alignment errors occur during the process of transferring the multiple LEDs, the multiple LEDs can be stably transferred onto the multiple bonding layers BL.

[0142] Next, refer to Figure 7C The material used to form the second planarization layer 115 can be coated. At this time, the height of the top surface of the second planarization layer 115 can be formed to be higher than the top surface of the plurality of bonding layers BL. Furthermore, the height of the top surface of the second planarization layer 115 can be formed to be lower than the height of the top surface of the plurality of light-emitting diodes (LEDs). Next, a conductive layer CL can be disposed on the second planarization layer 115 and the plurality of light-emitting diodes (LEDs) exposed by the second planarization layer 115. Furthermore, a photoresist PR for patterning the conductive layer CL can be disposed. At this time, the photoresist PR can be patterned to cover each of the plurality of light-emitting diodes (LEDs). The patterned plurality of photoresist PRs can be configured to cover the top and side surfaces of each of the plurality of light-emitting diodes (LEDs) on the conductive layer CL.

[0143] Next, refer to Figure 7D The process of etching multiple photoresists (PRs) can be performed. As described above, the multiple photoresists (PRs) are etched to form a top surface height lower than the top surface height of the multiple light-emitting diodes (LEDs). Therefore, a portion of the side surface and a portion of the conductive layer (CL) covering the top surface of the multiple light-emitting diodes (LEDs) can be exposed by the etched multiple photoresists (PRs).

[0144] Next, refer to Figure 7E A process of etching the conductive layer CL exposed by multiple photoresist PRs can be performed. Therefore, the conductive layer CL in areas not covered by the multiple photoresist PRs can be removed. Next, a material for forming the third planarization layer 116 can be coated onto the second planarization layer 115, the conductive layer CL, and the light-emitting diodes (LEDs). Furthermore, a patterning process for removing the third planarization layer 116 is performed between the multiple LEDs. Therefore, the third planarization layer 116 between the multiple LEDs can be removed. At this time, the ends of the third planarization layer 116 between the multiple LEDs can be located on the multiple conductive layers CL. Therefore, the top surface of the second planarization layer 115 can be exposed between the multiple LEDs.

[0145] Next, refer to Figure 7F The etching process of the third planarization layer 116 can be performed. By reducing the height of the top surface of the third planarization layer 116 through the etching process, the top surfaces of the multiple light-emitting diodes (LEDs) can be exposed. The second planarization layer 115 exposed between the multiple LEDs can be etched together with the third planarization layer 116 during the etching process. Therefore, between the multiple LEDs, the first via PAC1_H is formed in the second planarization layer 115, and the second via PAC2_H can be formed in the third planarization layer 116. At this time, the multiple conductive layers CL are not etched by the etchant used to etch the third planarization layer 116, allowing the multiple conductive layers CL to be used as a pattern mask. Therefore, the second planarization layer 115 not covered by the multiple conductive layers CL between the multiple LEDs can be removed. Furthermore, a portion of the etchant penetrates the lower part of the multiple conductive layers CL, allowing the portion of the second planarization layer 115 covered by the multiple conductive layers CL to be removed together. Therefore, the second planarization layer 115 forms an undercut structure between the multiple LEDs. In addition, the residue of the bonding layer BL that may remain between multiple light-emitting diodes (LEDs) can be removed together with the etching process of the third planarization layer 116.

[0146] Specifically, in the case of an n-up structure where the cathode of a light-emitting diode (LED) is located on the upper part, the anode located in the lower part of multiple LEDs needs to be connected to each of the multiple transistors. In a pixel, multiple LEDs need to emit different light, so the multiple bonding layers that electrically connect the multiple transistors and the multiple LEDs should not be electrically connected. Therefore, the multiple bonding layers need to be patterned to be completely spaced apart from each other among the multiple LEDs. Simultaneously, considering the possibility of LED misalignment, the bonding layer corresponding to the LED can be patterned to be wider than the LED. However, to achieve high resolution in the display device, when the LEDs are small and densely arranged, it is difficult to ensure sufficient space for spacing the bonding layers that will be patterned to be placed in an area wider than the LED. As mentioned above, if sufficient spacing is not ensured between the multiple bonding layers, the patterning process for spacing the multiple bonding layers needs to be performed more precisely, which may increase the probability of patterning defects. If a patterning defect occurs during the bonding layer formation process, residues of the bonding layer due to the patterning defect may remain in the area between the multiple LEDs. Therefore, multiple bonding layers that need to be spaced apart from each other are electrically connected, which may lead to short-circuit defects.

[0147] Therefore, the display device 200 according to another exemplary embodiment of the present disclosure includes a plurality of conductive layers CL, which protrude outward from the side surfaces of a plurality of light-emitting diodes (LEDs) and are spaced apart from each other. Furthermore, during the etching process of the third planarization layer 116, a second planarization layer 115 that is not blocked by the plurality of conductive layers CL used as a pattern mask between the plurality of LEDs can be removed. As described above, during the process of removing the second planarization layer 115, residues of bonding layers BL that were not removed between the plurality of LEDs due to patterning defects can be removed together. Therefore, the plurality of bonding layers BL between the plurality of LEDs can be completely removed.

[0148] Finally, refer to Figure 7G The connecting electrode CE can be disposed on the plurality of light-emitting diodes (LEDs) exposed by the third planarization layer 116. In this case, the connecting electrode CE can be spaced apart between the plurality of LEDs through the second hole PAC2_H.

[0149] Figure 8 This is a cross-sectional view of the pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 8 The display device 300 and Figures 1 to 3 The only difference between the display devices 100 is the reflective layer RL, but the other configurations are basically the same, so redundant descriptions will be omitted.

[0150] In a display device 300 according to yet another exemplary embodiment of the present disclosure, the plurality of conductive layers CL may be reflective layers RL comprising reflective material. The reflective layers RL may be configured to be lower than the light-emitting layers EL of the plurality of light-emitting diodes (LEDs). For example, the uppermost edge of the reflective layers RL may be disposed below the bottom surface of the light-emitting layers EL. Furthermore, the uppermost edge of the reflective layers RL may be configured to be lower than the uppermost edge of the first semiconductor layer L1.

[0151] Simultaneously, the active layer of the LED emits light. At this time, the light emitted from the active layer is not only emitted towards the top of the substrate. A portion of the light emitted from the active layer travels towards the side and bottom surfaces of the active layer. As mentioned above, the light emitted towards the side and bottom surfaces of the active layer is invisible to the user. Therefore, the problem is that the more light emitted towards the side and bottom surfaces of the active layer, the worse the luminous efficiency of the LED.

[0152] Therefore, the display device 300 according to another exemplary embodiment of this disclosure may include a plurality of reflective layers RL protruding outward from the side surface of the light-emitting diode (LED). Furthermore, the plurality of reflective layers RL may be configured to be lower than the light-emitting layer EL of the LED. In this case, considering light reflection efficiency, the reflective layers RL may contain a material with high reflectivity. For example, the reflective layers may use metallic materials such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, but are not limited thereto.

[0153] As described above, in the display device 300 according to another exemplary embodiment of the present disclosure, a reflective layer RL is provided that contacts the side surface of the light-emitting diode (LED). Therefore, light lost from the light-emitting layer EL to the side and bottom surfaces can be reflected back to the upper part of the substrate 110. This further improves the light extraction efficiency of the LED.

[0154] In a display device 300 according to yet another exemplary embodiment of the present disclosure, the plurality of bonding layers BL may be configured to be wider than the plurality of light-emitting diodes (LEDs). Therefore, even if alignment errors occur during the process of transferring the plurality of LEDs, the plurality of LEDs can be transferred more stably onto the plurality of bonding layers BL.

[0155] In a display device 300 according to yet another exemplary embodiment of the present disclosure, the plurality of bonding layers BL may comprise conductive material. Therefore, in the display device 300 according to yet another exemplary embodiment of the present disclosure, the bonding layers BL do not include conductive balls, allowing for a further reduction in the size of each bonding layer BL. Furthermore, the overall size of the pixel PX, which includes the plurality of bonding layers BL, can be reduced. As described above, reducing the size of the pixel PX allows for the placement of more pixels PX in the same area, thereby enabling a display device 300 with a higher resolution.

[0156] In a display device 300 according to yet another exemplary embodiment of the present disclosure, the second planarization layer 115 can form an undercut structure between a plurality of light-emitting diodes (LEDs) via the reflective layer RL. Therefore, the connection electrode CE can be completely disconnected between the plurality of LEDs via the undercut structure of the second planarization layer 115.

[0157] Figure 9 This is a cross-sectional view of the pixels of a display device according to yet another exemplary embodiment of the present disclosure. Figure 9 The display device 400 and Figure 5 The only difference between the display devices 200 is the reflective layer RL, but the other configurations are essentially the same, so redundant descriptions will be omitted. Furthermore, Figure 9 The reflective layer RL of the display device 400 and Figure 8The reflective layer RL of the display device 300 is basically the same, so redundant descriptions will be omitted.

[0158] A display device 400 according to another exemplary embodiment of the present disclosure may include a plurality of reflective layers RL protruding outward from the side surface of a light-emitting diode (LED). Furthermore, the plurality of reflective layers RL may be configured to be lower than the light-emitting layers EL of the plurality of LEDs. As described above, in the display device 400 according to another exemplary embodiment of the present disclosure, a reflective layer RL is provided that contacts the side surface of the LED. Therefore, light lost from the light-emitting layer EL to the side and bottom surfaces can be reflected again to the upper part of the substrate 110. This further improves the light extraction efficiency of the LED.

[0159] In a display device 400 according to yet another exemplary embodiment of the present disclosure, the plurality of bonding layers BL may be configured to be wider than the plurality of light-emitting diodes (LEDs). Therefore, even if alignment errors occur during the process of transferring the plurality of LEDs, the plurality of LEDs can be transferred more stably onto the plurality of bonding layers BL.

[0160] In a display device 400 according to yet another exemplary embodiment of the present disclosure, the plurality of bonding layers BL may comprise conductive material. Therefore, in the display device 400 according to yet another exemplary embodiment of the present disclosure, the bonding layers BL do not include conductive balls, allowing for a further reduction in the size of each bonding layer BL. Furthermore, the overall size of the pixel PX, which includes the plurality of bonding layers BL, can be reduced. As described above, reducing the size of the pixel PX allows for the placement of more pixels PX in the same area, thereby enabling a display device 400 with a higher resolution.

[0161] In a display device 400 according to yet another exemplary embodiment of the present disclosure, the second planarization layer 115 can form an undercut structure between multiple light-emitting diodes (LEDs) via multiple reflective layers RL. In this case, during the etching process of the second planarization layer 115, residues of the bonding layer BL that may remain between the multiple LEDs due to patterning defects can be removed simultaneously. Therefore, the multiple bonding layers BL corresponding to the multiple LEDs can be completely disconnected.

[0162] Exemplary embodiments of this disclosure can also be described as follows:

[0163] A display device according to one aspect of the present disclosure includes: a substrate defining a plurality of sub-pixels; a plurality of reflective electrodes disposed on the substrate; a plurality of bonding layers disposed on the plurality of reflective electrodes; a plurality of light-emitting diodes disposed on the plurality of bonding layers to correspond to the plurality of bonding layers respectively; a plurality of conductive layers configured to protrude outward from the side surfaces of the plurality of light-emitting diodes and spaced apart from each other; and at least one connecting electrode disposed on the plurality of light-emitting diodes.

[0164] The display device according to one aspect of this application may further include a first planarization layer and a second planarization layer. The first planarization layer may be disposed below a plurality of conductive layers and may be configured to surround a plurality of light-emitting diodes and a plurality of bonding layers. The second planarization layer is disposed above the first planarization layer. Each of the first planarization layer and the second planarization layer may include a plurality of holes disposed between the plurality of light-emitting diodes.

[0165] Multiple conductive layers can be configured to contact the top surface of the first planarization layer.

[0166] At least one end of the plurality of conductive layers may protrude outward from at least one end of the first planarization layer.

[0167] At least one end of the multiple conductive layers may protrude outward from at least one end of the second planarization layer.

[0168] The display device according to one aspect of the present disclosure may further include a third planarization layer disposed on a plurality of light-emitting diodes, wherein the third planarization layer fills a plurality of holes.

[0169] The top of the multiple conductive layers can be located below the active layers of the multiple light-emitting diodes, and the multiple conductive layers can contain reflective material.

[0170] Multiple bonding layers may contain conductive black material.

[0171] The ends of multiple conductive layers may protrude outwards than the ends of multiple bonding layers.

[0172] The display device according to one aspect of this application may further include a power line and a plurality of transistors disposed on a substrate, wherein the plurality of reflective electrodes may include: a first reflective electrode that can be electrically connected to the power line and can contact a plurality of bonding layers; and a plurality of second reflective electrodes that can be spaced apart from the first reflective electrode and can be electrically connected to the plurality of transistors respectively.

[0173] At least one connecting electrode can be multiple, and multiple second reflective electrodes and multiple light-emitting diodes are electrically connected.

[0174] The display device according to one aspect of this application may further include a power line and a plurality of transistors disposed on a substrate, wherein the plurality of reflective electrodes may include: a first reflective electrode connected to the power line; and a plurality of second reflective electrodes spaced apart from the first reflective electrode, which may be electrically connected to the plurality of transistors and may be in contact with the plurality of bonding layers.

[0175] At least one connecting electrode can electrically connect the first reflective electrode and multiple light-emitting diodes.

[0176] At least one connecting electrode can be spaced apart from each other among multiple light-emitting diodes.

[0177] A display device according to another aspect of this application includes: a substrate; a power line disposed on the substrate; a plurality of transistors disposed on the substrate; a first reflective electrode connected to the power line; a plurality of second reflective electrodes respectively connected to the plurality of transistors; a plurality of bonding layers disposed on the first reflective electrode and the plurality of second reflective electrodes; a plurality of light-emitting diodes disposed on the plurality of bonding layers; a plurality of conductive layers surrounding a portion of the side surfaces of the plurality of light-emitting diodes and protruding outward beyond the plurality of bonding layers; and at least one connecting electrode connected to the first reflective electrode or the plurality of second reflective electrodes.

[0178] According to another aspect of this application, the display device may further include: a first planarization layer, which may be configured to cover the side surfaces of a plurality of bonding layers; and a second planarization layer, disposed above the first planarization layer, wherein each of the first planarization layer and the second planarization layer may be spaced apart from each other between at least a portion of the plurality of light-emitting diodes.

[0179] Multiple conductive layers can be disposed between the first planarization layer and the second planarization layer.

[0180] The first planarization layer may include an undercut structure formed between multiple light-emitting diodes beneath multiple conductive layers.

[0181] The first reflective electrode and a plurality of second reflective electrodes may be spaced apart from each other, a plurality of bonding layers may be in contact with the first reflective electrode, at least one connecting electrode may be a plurality of electrodes, and the plurality of connecting electrodes may electrically connect the plurality of second reflective electrodes and the plurality of light-emitting diodes.

[0182] The first reflective electrode and a plurality of second reflective electrodes may be spaced apart from each other, a plurality of bonding layers may be configured to correspond to a plurality of second reflective electrodes respectively, and at least one connecting electrode is electrically connected to the first reflective electrode and a plurality of light-emitting diodes.

[0183] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and are not limiting of the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: substrate; Multiple reflective electrodes are located on the substrate; Multiple bonding layers are located on at least one of the multiple reflective electrodes; Multiple light-emitting diodes are respectively located on the multiple bonding layers; Multiple conductive layers are spaced apart from each other and protrude outward from the side surfaces of the multiple light-emitting diodes, respectively; as well as At least one connection electrode is located on the plurality of light-emitting diodes.

2. The display device according to claim 1, further comprising: A first planarization layer is disposed beneath the plurality of conductive layers and at least partially covers the side surfaces of the plurality of light-emitting diodes and the side surfaces of the plurality of bonding layers; as well as A second planarization layer is disposed above the first planarization layer and partially covers the side surfaces of the plurality of light-emitting diodes. Each of the first planarization layer and the second planarization layer includes a plurality of holes located between the plurality of light-emitting diodes.

3. The display device of claim 2, wherein, The plurality of conductive layers are in contact with the top surface of the first planarization layer.

4. The display device according to claim 2, wherein One end of one of the plurality of conductive layers protrudes outward from the side surface of the corresponding light-emitting diode among the plurality of light-emitting diodes compared to the adjacent end of the first planarization layer.

5. The display device according to claim 2, wherein One end of one of the plurality of conductive layers protrudes outward from the side surface of the corresponding light-emitting diode among the plurality of light-emitting diodes compared to the adjacent end of the second planarization layer.

6. The display device according to claim 2, further comprising: The third planarization layer is located on the plurality of light-emitting diodes. The third planarization layer fills the plurality of holes in the first planarization layer and the second planarization layer.

7. The display device according to claim 1, wherein, The uppermost end of one of the plurality of conductive layers is disposed below the light-emitting layer of the corresponding light-emitting diode among the plurality of light-emitting diodes, and The plurality of conductive layers contain reflective material.

8. The display device according to claim 1, wherein, The plurality of bonding layers contain a conductive black material.

9. The display device according to claim 1, wherein, The end of one of the plurality of conductive layers protrudes outward from the side surface of the corresponding light-emitting diode among the plurality of light-emitting diodes, compared to the end of the corresponding bonding layer among the plurality of bonding layers.

10. The display device according to claim 1, further comprising: Power lines and multiple transistors are located on the substrate. The plurality of reflective electrodes include: A first reflective electrode is electrically connected to the power line and contacts the plurality of bonding layers; and A plurality of second reflective electrodes are spaced apart from the first reflective electrode and are electrically connected to the plurality of transistors, respectively.

11. The display device according to claim 10, wherein, The at least one connecting electrode includes a plurality of connecting electrodes, which respectively electrically connect the plurality of second reflective electrodes to the plurality of light-emitting diodes.

12. The display device according to claim 1, further comprising: Power lines and multiple transistors are located on the substrate. The plurality of reflective electrodes include: A first reflective electrode is connected to the power line; and A plurality of second reflective electrodes, spaced apart from the first reflective electrode, are electrically connected to the plurality of transistors respectively, and are in contact with the plurality of bonding layers respectively.

13. The display device according to claim 12, wherein, The at least one connecting electrode is electrically connected to the first reflective electrode and the plurality of light-emitting diodes.

14. The display device according to claim 13, wherein, The at least one connecting electrode includes one or more gaps between the plurality of light-emitting diodes.

15. A display device, comprising: substrate; The power cord is located on the substrate; Multiple transistors are located on the substrate; The first reflective electrode is connected to the power line; Multiple second reflective electrodes are respectively connected to the multiple transistors; Multiple bonding layers are located on the first reflective electrode or respectively on the multiple second reflective electrodes; Multiple light-emitting diodes are respectively located on the multiple bonding layers; Multiple conductive layers cover a portion of the side surface of the multiple light-emitting diodes, and the end of one of the multiple conductive layers protrudes outward from the side surface of the corresponding light-emitting diode than the end of the corresponding bonding layer in the multiple bonding layers. as well as At least one connecting electrode is connected to the first reflective electrode or to each of the plurality of second reflective electrodes.

16. The display device according to claim 15, further comprising: A first planarization layer covers the side surfaces of the plurality of bonding layers; as well as A second planarization layer is located above the first planarization layer and partially covers the side surfaces of the plurality of light-emitting diodes. Each of the first planarization layer and the second planarization layer includes a hole between adjacent light-emitting diodes in the plurality of light-emitting diodes.

17. The display device according to claim 16, wherein, The plurality of conductive layers are disposed between the first planarization layer and the second planarization layer.

18. The display device according to claim 16, wherein, The first planarization layer includes an undercut structure between adjacent light-emitting diodes located beneath one of the plurality of conductive layers.

19. The display device according to claim 15, wherein, The first reflective electrode is spaced apart from the plurality of second reflective electrodes. The plurality of bonding layers are in contact with the first reflective electrode, and The at least one connecting electrode includes a plurality of connecting electrodes, which respectively electrically connect the plurality of second reflective electrodes to the plurality of light-emitting diodes.

20. The display device according to claim 15, wherein, The first reflective electrode is spaced apart from the plurality of second reflective electrodes. The plurality of bonding layers are respectively located on the plurality of second reflective electrodes, and The at least one connecting electrode is electrically connected to the first reflective electrode and the plurality of light-emitting diodes.

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