Display device

Abstract

According to an aspect of the disclosure, the display device includes a substrate in which a plurality of sub-pixels are defined, a plurality of driving transistors in each of the plurality of sub-pixels, a plurality of light emitting diodes in each of the plurality of sub-pixels, a first connection electrode covering a portion of a lower side surface of the plurality of light emitting diodes and formed of a reflective conductive material, and a second connection electrode in contact with a top surface of the plurality of light emitting diodes and formed of a transparent conductive material. Accordingly, light extraction efficiency in a front direction can be improved.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0172622, filed with the Korean Intellectual Property Office on November 27, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices, and more specifically to display devices for improving front brightness. Background Technology

[0004] As display devices used for computers, televisions, or cellular phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0005] The applications of display devices have diversified to include personal digital assistants and computer and television displays, and research is underway on display devices with large display areas and reduced size and weight.

[0006] Furthermore, display devices, including those using light-emitting diodes (LEDs), have recently garnered attention as next-generation display devices. Because LEDs are formed from inorganic rather than organic materials, they offer superior reliability, resulting in a longer lifespan compared to liquid crystal displays or organic light-emitting displays. In addition, LEDs possess fast emission speed, excellent luminous efficiency, and strong shock resistance, leading to excellent stability and the ability to display high-brightness images. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display device with improved front brightness.

[0008] The purpose of this disclosure is to provide a display device with improved light extraction efficiency.

[0009] The purpose of this disclosure is to provide a display device that saves processing costs and time by reducing the number of masks required for manufacturing processes.

[0010] The purpose of this disclosure is not limited to the purposes mentioned above, and other purposes not mentioned above can be clearly understood by those skilled in the art based on the following description.

[0011] According to one aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of driving transistors in each of the plurality of sub-pixels; a plurality of light-emitting diodes in each of the plurality of sub-pixels; a first connecting electrode covering a portion of the lower side surface of the plurality of light-emitting diodes and formed of a reflective conductive material; and a second connecting electrode contacting the top surface of the plurality of light-emitting diodes and formed of a transparent conductive material.

[0012] According to another aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of driving transistors in each of the plurality of sub-pixels; a first planarization layer on the plurality of driving transistors; a plurality of light-emitting diodes on the first planarization layer in each of the plurality of sub-pixels; a first connection electrode electrically connected to the plurality of light-emitting diodes and formed of a reflective conductive material; a second connection electrode electrically connected to the plurality of light-emitting diodes and formed of a transparent conductive material; and a second planarization layer between the first connection electrode and the second connection electrode, wherein the second planarization layer comprises a black material.

[0013] Other specific details of the exemplary implementation are included in the detailed description and accompanying drawings.

[0014] According to an exemplary embodiment of this disclosure, the number of planarization layer formation processes is reduced to reduce the number of masks required for the process, thereby saving processing costs and time and achieving processing optimization.

[0015] According to an exemplary embodiment of this disclosure, processing optimization is achieved by using a planarization layer as a mask to reduce the number of processes.

[0016] According to an exemplary embodiment of this disclosure, laterally traveling light is reflected toward the front direction to improve frontal brightness, thereby driving with low power.

[0017] According to exemplary embodiments of this disclosure, the problem of light being trapped in the light-emitting diode is improved to improve light extraction efficiency, thereby enabling low-power driving.

[0018] The effects of this disclosure are not limited to those exemplified above, and many other effects are included in this specification. Attached Figure Description

[0019] The above and other aspects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0020] Figure 1This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 2 This is an enlarged cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0022] Figures 3A to 3E This is a view used to illustrate a method of manufacturing a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 4 This is a graph showing the brightness of a display device according to a viewing angle, based on an exemplary embodiment of the present disclosure;

[0024] Figure 5 This is an enlarged cross-sectional view of a display device according to another exemplary embodiment of the present disclosure;

[0025] Figures 6A to 6D This is a view used to illustrate a method of manufacturing a display device according to another exemplary embodiment of the present disclosure; and

[0026] Figure 7 This is an enlarged cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure. Detailed Implementation

[0027] The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail below with reference to the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure.

[0028] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0029] Even if not explicitly stated, components are interpreted as including a general tolerance range.

[0030] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be positioned between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0031] When an element or layer is placed "on" another element or layer, the other layer or element can be directly inserted onto or between the other elements.

[0032] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component referred to below can be the second component.

[0033] Throughout the specification, similar reference numerals generally denote similar elements.

[0034] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0035] Features of various embodiments of this disclosure may be partially or completely dependent on or combined with each other and may be technically interlocked and operated in various ways, and these embodiments may be performed independently or in relation to each other.

[0036] The present disclosure will be described in detail below with reference to the accompanying drawings.

[0037] Figure 1 This is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 For ease of description, among the various components of the display device 100, only the display panel PN, gate driver GD, data driver DD, and timing controller TC are shown.

[0038] Reference Figure 1 The display device 100 includes a display panel PN having multiple sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0039] Drivers such as gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-active area NA as a gate in panel (GIP) or between multiple sub-pixels SP in the active area AA as a gate in active area (GIA).

[0040] The display panel PN is a configuration for displaying images to the user and includes multiple subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and the multiple subpixels SP are respectively connected to the scan lines SL and data lines DL. Additionally, although not shown in the accompanying drawings, each of the multiple subpixels SP can be connected to a high-potential power line, a low-potential power line, and a reference line.

[0041] In the display panel PN, an active area AA and a non-active area NA surrounding the active area AA can be defined.

[0042] The active area AA is the area in the display device 100 where an image is displayed. Within the active area AA, multiple sub-pixels SP constituting multiple pixels and circuitry for driving the multiple sub-pixels SP can be provided. A sub-pixel SP is the smallest unit constituting the active area AA, and n sub-pixels SP can form one pixel. In each of the multiple sub-pixels SP, a light-emitting diode (LED) and a thin-film transistor (TFT) for driving that LED can be provided. The multiple LEDs can be defined in different ways depending on the type of the display panel PN. For example, when the display panel PN is an inorganic light-emitting display panel, the LEDs can be LEDs or miniature LEDs.

[0043] In the active region AA, multiple signal lines are provided to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines include multiple data lines DL supplying data voltage to each of the multiple sub-pixels SP and multiple scan lines SL supplying gate voltage to each of the multiple sub-pixels SP. The multiple scan lines SL extend in one direction within the active region AA to connect to the multiple sub-pixels SP, and the multiple data lines DL extend in the active region AA in a direction different from the aforementioned direction to connect to the multiple sub-pixels SP. Additionally, low-potential power lines and high-potential power lines may also be provided in the active region AA, but are not limited to these.

[0044] In the non-active region NA, no image is displayed, but links, pad electrodes, or driver ICs such as gate driver ICs or data driver ICs can be set to transmit signals to the sub-pixel SP of the active region AA.

[0045] The display panel PN comprises a plurality of pixels formed by a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light-emitting diode (LED) and pixel circuitry to independently emit light. A pixel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. For example, a pixel may consist of a pair of first sub-pixels, a pair of second sub-pixels, and a pair of third sub-pixels. In this case, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel, but is not limited thereto.

[0046] Multiple light-emitting diodes (LEDs) can be set in multiple sub-pixels SP. Specifically, the multiple LEDs include a first LED, a second LED, and a third LED. A first LED can be set in the first sub-pixel, a second LED in the second sub-pixel, and a third LED in the third sub-pixel. For example, the first LED can be a red LED, the second LED can be a green LED, and the third LED can be a blue LED.

[0047] Figure 2 This is an enlarged cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2 This is a cross-sectional view of a sub-pixel SP of a display device 100 according to an exemplary embodiment of the present disclosure.

[0048] In each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to an exemplary embodiment of the present disclosure, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113a, a second interlayer insulating layer 113b, a passivation layer 114, a first planarization layer 115, an adhesive layer AD, a second planarization layer 116, a third planarization layer 117, a fourth planarization layer 118, a driving transistor DT, a light-emitting diode LED, a reflective electrode RE, a light-shielding layer LS, an auxiliary electrode LE, a first connection electrode CE1, a second connection electrode CE2, a capacitor Cst, and an intermediate electrode TM may be provided.

[0049] First, the substrate 110 is a component for supporting various parts included in the display device 100, and can be formed of an insulating material. For example, the substrate 110 can be formed of glass or resin. Furthermore, the substrate 110 can be configured to include polymers or plastics, or can be formed of a flexible material.

[0050] A light-shielding layer LS can be provided in each of the plurality of sub-pixels SP on the substrate 110. The light-shielding layer LS blocks light incident from the lower part of the substrate 110 onto the active layer ACT of the driving transistor DT, which will be described below. The light incident onto the active layer ACT of the driving transistor DT is blocked by the light-shielding layer LS to minimize leakage current. The light-shielding layer LS can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0051] A buffer layer 111 can be provided on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0052] A driving transistor DT can be disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0053] An active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be formed of a semiconductor material such as oxide semiconductor, amorphous silicon or polycrystalline silicon, but is not limited thereto.

[0054] A gate insulating layer 112 may be disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that insulates the active layer ACT from the gate electrode GE, and may be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0055] A gate electrode GE may be disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0056] A first interlayer insulating layer 113a and a second interlayer insulating layer 113b can be formed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113a and the second interlayer insulating layer 113b, through which the source electrode SE and the drain electrode DE connect to the active layer ACT. The first interlayer insulating layer 113a and the second interlayer insulating layer 113b are insulating layers used to protect the components beneath them, and can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but are not limited thereto.

[0057] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT can be disposed on the second interlayer insulating layer 113b. The source electrode SE and the drain electrode DE can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0058] This specification describes the provision of a first interlayer insulating layer 113a and a second interlayer insulating layer 113b, i.e., multiple insulating layers, between the gate electrode GE and the source electrode SE and drain electrode DE. However, only one insulating layer may be provided between the gate electrode GE and the source electrode SE and drain electrode DE, but this disclosure is not limited thereto.

[0059] Furthermore, although not shown in the accompanying drawings, the pixel circuit may include, but is not limited to, a switching transistor, a sensing transistor, and an emission control transistor in addition to the driving transistor DT.

[0060] Simultaneously, an intermediate electrode TM can be disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The intermediate electrode TM is configured to overlap with the gate electrode GE of the driving transistor DT, with the first interlayer insulating layer 113a between them, to form a capacitor together with the gate electrode GE of the driving transistor DT, but is not limited thereto. The intermediate electrode TM can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0061] An auxiliary electrode LE can be provided on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-shielding layer LS below the buffer layer 111 to either the source electrode SE or the drain electrode DE of the driving transistor DT on the second interlayer insulating layer 113b. For example, the light-shielding layer LS can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT via the auxiliary electrode LE so that it does not operate as a floating gate. Therefore, the threshold voltage fluctuation of the driving transistor DT caused by the floating light-shielding layer LS can be minimized. Although the light-shielding layer LS is connected to the source electrode SE of the driving transistor DT in the figures, the light-shielding layer LS can also be connected to the drain electrode DE of the driving transistor DT, but is not limited thereto.

[0062] The auxiliary electrode LE can be formed of the same material as the gate electrode GE, but is not limited thereto. The auxiliary electrode LE can be made of conductive materials such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0063] A capacitor Cst can be disposed on the gate insulating layer 112. The capacitor Cst may include a first capacitor electrode Cst1 and a second capacitor electrode Cst2.

[0064] First, the first capacitor electrode Cst1 can be disposed on the gate insulating layer 112. The first capacitor electrode Cst1 is disposed on the same layer as the gate electrode GE and the auxiliary electrode LE, and can be formed of the same material as the gate electrode GE and the auxiliary electrode LE, but is not limited thereto. The first capacitor electrode Cst1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0065] The second capacitor electrode Cst2 may be disposed on the first interlayer insulating layer 113a. The second capacitor electrode Cst2 is disposed on the same layer as the intermediate electrode TM and may be formed of the same material as the intermediate electrode TM, but is not limited thereto. The second capacitor electrode Cst2 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto. The second capacitor electrode Cst2 may be disposed overlapping the first capacitor electrode Cst1, with the first interlayer insulating layer 113a between them. The second capacitor electrode Cst2 may be connected to the source electrode SE of the driving transistor DT.

[0066] A power line VDD can be disposed on the second interlayer insulating layer 113b. The power line VDD, together with the driving transistor DT, is electrically connected to the light-emitting diode (LED) so that the LED can emit light. For example, the power line VDD can be a high-potential power line, but is not limited thereto. The power line VDD is disposed on the same layer as the source electrode SE and the drain electrode DE, and is formed of the same material as the source electrode SE and the drain electrode DE, but is not limited thereto. The power line VDD can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but is not limited thereto.

[0067] A passivation layer 114 can be provided on the driving transistor DT and the power line VDD. The passivation layer 114 can protect the driving transistor DT and the power line VDD from the penetration of moisture or impurities. For example, the passivation layer 114 can be composed of a single layer or a double layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the passivation layer 114 can be omitted, but is not limited thereto.

[0068] A first planarization layer 115 may be disposed on the passivation layer 114. The first planarization layer 115 can planarize the upper part of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 115 may be composed of a single layer or two layers, and may be formed, for example, by a photoresist or an acrylic-based organic material, but is not limited thereto.

[0069] Multiple reflective electrodes RE, spaced apart from each other, can be disposed on the first planarization layer 115. The multiple reflective electrodes RE electrically connect the light-emitting diode (LED) to the power line VDD and the driving transistor DT, and can also serve as a reflector to reflect light emitted from the LED to the top of the LED. The multiple reflective electrodes RE are formed of a conductive material with excellent reflective properties to reflect light emitted from the LED toward the top of the LED. Therefore, considering light reflection efficiency and resistance, the multiple reflective electrodes RE can include various conductive layers. For example, the reflective electrodes RE can use opaque conductive layers such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), or alloys thereof, and transparent conductive layers such as indium tin oxide (ITO), but the structure and material of the reflective electrodes RE are not limited to these.

[0070] The plurality of reflective electrodes RE may include a first reflective electrode RE1 and a second reflective electrode RE2. The first reflective electrode RE1 can electrically connect the driving transistor DT and the light-emitting diode LED. The first reflective electrode RE1 can be connected to the source electrode SE or drain electrode DE of the driving transistor DT through contact holes formed in the passivation layer 114 and the first planarization layer 115. In addition, the first reflective electrode RE1 can be electrically connected to the first electrode 124 of the light-emitting diode LED through the first connection electrode CE1.

[0071] The second reflective electrode RE2 can electrically connect the power line VDD and the light-emitting diode (LED). The second reflective electrode RE2 can be connected to the power line VDD through contact holes formed in the passivation layer 114 and the first planarization layer 115, and can be electrically connected to the second electrode 125 of the LED through the second connection electrode CE2, which will be described below.

[0072] An adhesive layer AD is formed on the front surface of the substrate 110 over a plurality of reflective electrodes RE to fix a light-emitting diode (LED) disposed on the adhesive layer AD. The adhesive layer AD can be formed of a photocurable adhesive material or a thermosetting adhesive material that is cured by heat or light. For example, the adhesive layer AD can be formed of an acrylic-based material containing a photoresist, but is not limited thereto.

[0073] Multiple light-emitting diodes (LEDs) can be disposed in each of multiple sub-pixels (SPs) on the adhesive layer AD. Multiple LEDs are elements that emit light through current, and can include LEDs that emit red, green, and blue light, and through combinations thereof, achieve various colors of light, including white. For example, the multiple LEDs can be light-emitting diodes (LEDs) or micro-LEDs, but are not limited to these.

[0074] Each of the plurality of light-emitting diodes (LEDs) may include a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and an encapsulation film 126.

[0075] A first semiconductor layer 121 can be disposed on the adhesive layer AD, and a second semiconductor layer 123 can be disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 can be layers formed by doping n-type and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 can be layers doped with n-type and p-type impurities into materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). Furthermore, the p-type impurities can be magnesium (Mg), zinc (Zn), and beryllium (Be), and the n-type impurities can be silicon (Si), germanium (Ge), and tin (Sn), but are not limited thereto.

[0076] A portion of the first semiconductor layer 121 may be configured to protrude outward from the second semiconductor layer 123. The top surface of the first semiconductor layer 121 is formed by a portion overlapping the bottom surface of the second semiconductor layer 123 and a portion disposed on the outer side of the bottom surface of the second semiconductor layer 123. The light-emitting diode (LED) may be a lateral light-emitting diode (LED). However, the dimensions and shapes of the first semiconductor layer 121 and the second semiconductor layer 123 may be modified in various ways, but are not limited thereto.

[0077] For example, the first semiconductor layer 121 may protrude outward from the second semiconductor layer 123 in some directions. The first semiconductor layer 121 may protrude from a portion of the edge of the second semiconductor layer 123 to the outside of the second semiconductor layer 123. A portion of the first semiconductor layer 121 may protrude outward from the second semiconductor layer 123 in a specific direction.

[0078] A light-emitting layer 122 may be disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light.

[0079] The light-emitting layer 122 can be formed by a single-layer or multiple quantum well (MQW) structure, and can be formed, for example, by indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0080] A first electrode 124 may be disposed on the first semiconductor layer 121. The first electrode 124 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material such as a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or alloys thereof, but is not limited thereto.

[0081] Meanwhile, the first electrode 124 can be positioned closer to the substrate 110 than the light-emitting layer 122. For example, the thickness of the first semiconductor layer 121 in the region overlapping with the light-emitting layer 122 is greater than its thickness in the region overlapping with the first electrode 124. Therefore, in a cross-sectional view, the first electrode 124 and the light-emitting layer 122 are disposed on different planes.

[0082] A second electrode 125 may be disposed on the second semiconductor layer 123. The second electrode 125 may also be disposed on the top surface of the second semiconductor layer 123. In this case, the second semiconductor layer 123 is disposed on the first semiconductor layer 121, such that the second electrode 125 disposed on the top surface of the second semiconductor layer 123 can be disposed higher than the first electrode 124 disposed on the top surface of the first semiconductor layer 121. The second electrode 125 is an electrode that electrically connects the electric field line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material such as a transparent conductive material like indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0083] Next, an encapsulation film 126 can be formed covering the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is formed of an insulating material to protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Furthermore, contact holes are formed in the encapsulation film 126 to expose the first electrode 124 and the second electrode 125, so that the first connection electrode CE1 and the second connection electrode CE2, which will be formed later, can be electrically connected to the first electrode 124 and the second electrode 125, respectively.

[0084] The adhesive layer AD and the light-emitting diode (LED) can be configured to be in direct contact with the first connection electrode CE1 on the adhesive layer AD and the LED. The first connection electrode CE1 is an electrode disposed in each of the plurality of sub-pixels SP to electrically connect the LED and the driving transistor DT. The first connection electrode CE1 can be connected to the first reflective electrode RE1 through a contact hole formed in the adhesive layer AD. Therefore, the first connection electrode CE1 can be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the first reflective electrode RE1. For example, the first connection electrode CE1 can connect the first electrode 124 of the LED to the source electrode SE of the driving transistor DT, but is not limited thereto.

[0085] The first connecting electrode CE1 can be made of a reflective conductive material. For example, the first connecting electrode CE1 can be formed of an opaque reflective conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0086] The first connecting electrode CE1 can be configured to cover a portion of the lower side surface of the light-emitting diode (LED) while being in direct contact with it. For example, the first connecting electrode CE1 can be configured to extend from the top surface of the first electrode 124 to cover the encapsulation film 126 disposed on the lower edge of the LED. For example, the first connecting electrode CE1 can cover the side surface of the first semiconductor layer 121 disposed below the light-emitting layer 122. In this case, the first connecting electrode CE1 can be configured to cover the side surface of the first semiconductor layer 121 but not the side surface of the light-emitting layer 122. That is, the top of the first connecting electrode CE1 can be located between the top surface of the first electrode 124 and the bottom surface of the light-emitting layer 122. Furthermore, the first connecting electrode CE1 extends from the lower side surface of the LED to contact the top surface of the adhesive layer AD.

[0087] A second planarization layer 116 can be disposed on the first connecting electrode CE1 and the light-emitting diodes (LEDs). The second planarization layer 116 is configured to cover a portion of the side surfaces of the plurality of LEDs to fix and protect the plurality of LEDs.

[0088] The second planarization layer 116 can be disposed on the first connection electrode CE1 to cover the side surface of the light-emitting diode (LED). In this case, the second planarization layer 116 can have a thickness smaller than that of the LED. For example, the second planarization layer 116 can cover the side surface of the first semiconductor layer 121 disposed below the light-emitting layer 122.

[0089] Furthermore, a second planarization layer 116 can be disposed above the first electrode 124. For example, the second planarization layer 116 can cover the top surface of the first connecting electrode CE1 disposed above the first electrode 124. Therefore, the second planarization layer 116 can be configured to overlap with a portion of the side surface of the first electrode 124 and the side surface of the light-emitting diode LED. Simultaneously, the second planarization layer 116 can be configured to cover the side surface of the first semiconductor layer 121, but not the side surface of the light-emitting layer 122. That is, the top surface of the second planarization layer 116 can be located between the top surface of the first electrode 124 and the bottom surface of the light-emitting layer 122.

[0090] The top surface of the second planarization layer 116 can expose one surface of the first connection electrode CE1 disposed on the side surface of the light-emitting diode (LED). For example, refer to... Figure 2 The top surface of the second planarization layer 116 is disposed on the same plane as the surface of the first connecting electrode CE1 disposed at the top. Therefore, the surface of the first connecting electrode CE1 disposed at the top can be exposed by the second planarization layer 116.

[0091] The top surface of the second planarization layer 116 and the top of the first connecting electrode CE1 can be configured to be lower than the bottom surface of the light-emitting layer 122 of the LED. By doing so, the light output from the light-emitting layer 122 of the LED is not limited by the first connecting electrode CE1. Therefore, the first connecting electrode CE1 is configured not to restrict the light path of the LED, thereby improving the luminous efficiency of the LED. However, this disclosure is not limited thereto, and depending on the position of the light-emitting layer 122 in the LED and the lateral structure of the LED, the top surface of the second planarization layer 116 and the top of the first connecting electrode CE1 can be configured to be higher than the bottom surface of the light-emitting layer 122 of the LED.

[0092] The second planarization layer 116 can expose the side surface of the first connecting electrode CE1 disposed on the adhesive layer AD. For example, refer to Figure 2 The width of the bottom surface of the second planarization layer 116 is equal to the width of the top surface of the first connecting electrode CE1, and the side surfaces of the second planarization layer 116 and the first connecting electrode CE1 can be disposed on the same plane. Therefore, in a planar view, the planar shape of the second planarization layer 116 and the planar shape of the first connecting electrode CE1 can be the same, and the side surface of the first connecting electrode CE1 can be exposed by the second planarization layer 116.

[0093] The second planarization layer 116 may include a black material. For example, the second planarization layer 116 may include a black component with a high light absorption rate. Therefore, the second planarization layer 116 can suppress color mixing that may occur between light-emitting diodes (LEDs) emitting different colors of light and suppress external light reflection.

[0094] A third planarization layer 117 is disposed on the adhesive layer AD, the first connecting electrode CE1, and the second planarization layer 116. The third planarization layer 117 is configured to cover a portion of the side surfaces of the plurality of light-emitting diodes (LEDs) to fix and protect the plurality of LEDs. Furthermore, the third planarization layer 117 is disposed between the second planarization layer 116 and the second connecting electrode CE2 to planarize the upper portion of the second planarization layer 116 and the lower portion of the second connecting electrode CE2.

[0095] The third planarization layer 117 covers the upper part of the second planarization layer 116 and a portion of the upper side surface of the light-emitting diode (LED) exposed by the second planarization layer 116. The top surface of the third planarization layer 117 is configured to be higher than the light-emitting layer 122 of the LED, and may be configured to be equal to or lower than the top surface of the second semiconductor layer 123. For example, the top surface of the third planarization layer 117 may be disposed between the top surface of the light-emitting layer 122 and the top surface of the second semiconductor layer 123, or may be disposed on the same plane as the top surface of the second semiconductor layer 123.

[0096] Furthermore, the third planarization layer 117 extends from the upper part of the second planarization layer 116 to cover the side surface of the second planarization layer 116 and the side surface of the first connecting electrode CE1. Additionally, the third planarization layer 117 may cover the top surface of the adhesive layer AD disposed on the outer side of the second planarization layer 116.

[0097] The third planarization layer 117 can be composed of a single layer or two layers. The third planarization layer 117 can be formed, for example, by a photoresist or an acrylic-based organic material, but is not limited thereto.

[0098] A second connection electrode CE2 can be disposed on the third planarization layer 117. The second connection electrode CE2 is an electrode used to electrically connect the light-emitting diode (LED) and the power line VDD. The second connection electrode CE2 can be connected to the second reflective electrode RE2 through contact holes formed in the third planarization layer 117 and the adhesive layer AD. Therefore, the second connection electrode CE2 can be electrically connected to the power line VDD through the second reflective electrode RE2. For example, the second connection electrode CE2 can connect the second electrode 125 of the LED to the power line VDD, but is not limited thereto.

[0099] The second connecting electrode CE2 can be formed of a different material than the first connecting electrode CE1. For example, the second connecting electrode CE2 can be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0100] A fourth planarization layer 118 may be disposed on the third planarization layer 117 and the second connecting electrode CE2. The fourth planarization layer 118 planarizes the upper part of the substrate 110 on which the light-emitting diode (LED) is disposed, thereby fixing and protecting the LED. Therefore, the fourth planarization layer 118 may also be referred to as a protective layer or a cover layer, but is not limited thereto. The fourth planarization layer 118 may be composed of a single layer or two layers, and may be formed, for example, by a photoresist or an acrylic-based organic material, but is not limited thereto.

[0101] In the following text, we will refer to... Figures 3A to 3E This disclosure describes a method for manufacturing a display device according to an exemplary embodiment.

[0102] Figures 3A to 3E This is a view used to illustrate a method of manufacturing a display device according to an exemplary embodiment of the present disclosure.

[0103] First, refer to Figure 3A The light-emitting diode (LED) is disposed on the adhesive layer AD, and the metal layer ML is formed on the adhesive layer AD to cover the LED.

[0104] A metal layer ML can be disposed on the entire substrate 110 and cover the top surface of the adhesive layer AD, as well as the top and side surfaces of the light-emitting diode (LED). Furthermore, the metal layer ML covers the surface of the LED encapsulation film 126 and can cover the first electrode 124 and the second electrode 125 exposed through the contact holes of the encapsulation film 126. Additionally, the metal layer ML can cover the first reflective electrode RE1 exposed through the contact holes of the passivation layer 114 and the first planarization layer 115.

[0105] Reference Figure 3B An initial second planarization layer 116' containing a photosensitive material is formed on the metal layer ML. The initial second planarization layer 116' is formed to cover a portion of the metal layer ML. For example, the initial second planarization layer 116' is formed to cover the metal layer ML, extending from the contact holes of the passivation layer 114 and the first planarization layer 115 through which the source electrode SE of the driving transistor DT is exposed, to cover the top and side surfaces of the light-emitting diode LED.

[0106] Reference Figure 3CA portion of the initial second planarization layer 116' is removed to form the second planarization layer 116. For example, the initial second planarization layer 116' undergoes an ashing process to remove the portion of the initial second planarization layer 116' covering the upper part of the light-emitting diode (LED). The ashing process is performed such that the second planarization layer 116 can cover the top surface of the metal layer ML on the first electrode 124 and the portion of the metal layer ML disposed on the lower side surface of the LED, but exposes the top surface of the metal layer ML on the second electrode 125 and the portion of the metal layer ML disposed on the upper side surface of the LED.

[0107] Next, refer to Figure 3D The metal layer ML disposed in the region that does not overlap with the second planarization layer 116 is removed to form the first connection electrode CE1. For example, light processing can be performed, and the second planarization layer 116 can be used as a mask for the first connection electrode CE1. Therefore, the metal layer ML covering the second electrode 125 and the metal layer ML covering the upper side surface of the light-emitting diode (LED) above the second planarization layer 116 are removed to form the first connection electrode CE1.

[0108] Next, refer to Figure 3E A third planarization layer 117, a second connection electrode CE2, and a fourth planarization layer 118 are sequentially formed on the first connection electrode CE1. The third planarization layer 117 is formed to cover a portion of the upper side surface of the light-emitting diode (LED) exposed from the second planarization layer 116. At this time, the third planarization layer 117 is formed to expose the second electrode 125. Next, the second connection electrode CE2 and the fourth planarization layer 118 are formed on the third planarization layer 117. The second connection electrode CE2 is formed to cover the top surface of the second electrode 125 exposed from the third planarization layer 117, and extends from the second electrode 125 to the third planarization layer 117. Furthermore, the second connection electrode CE2 may cover the second reflective electrode RE2 exposed from the contact hole of the third planarization layer 117. Thereafter, the fourth planarization layer 118 is formed to cover the top surface of the second connection electrode CE2.

[0109] In the following text, reference will be made to Figure 4 To confirm the brightness of the display device 100 according to the exemplary embodiment of the present disclosure based on the viewing angle.

[0110] Figure 4 This is a graph illustrating the brightness of a display device according to an exemplary embodiment of the present disclosure, based on a viewing angle. The example is a display device 100 according to an exemplary embodiment of the present disclosure, and the difference between the display device according to a comparative embodiment and the display device 100 according to the exemplary embodiment of the present disclosure is that the first connecting electrode CE1 is formed of a transparent conductive material.

[0111] exist Figure 4 In the center, the X-axis indicates the viewpoint. Figure 4 In the image, the Y-axis indicates brightness. Figure 4 In the comparative embodiment, the brightness in the frontal direction, i.e., at a viewing angle of 0°, is 100%, and its relative brightness is represented by the reference symbol %.

[0112] Reference Figure 4 It has been confirmed that, in both the comparative and implementation embodiments, high brightness can be achieved in the frontal direction and in the lateral direction from 50° to 70°. Furthermore, it has been confirmed that, at a viewing angle of 0°, the brightness of the implementation is approximately 108%, and the frontal brightness is increased by approximately 8% compared to the comparative embodiment.

[0113] In the display device 100 according to an exemplary embodiment of the present disclosure, the second connection electrode CE2 comprises a transparent conductive material, while the first connection electrode CE1 comprises a reflective conductive material. Therefore, light emitted from the light-emitting diode (LED) directed toward the direction where the first connection electrode CE1 is disposed can be reflected by the first connection electrode CE1. For example, light emitted from the LED directed toward the side surface of the first semiconductor layer 121 and the first electrode 124 can be reflected by the first connection electrode CE1. Therefore, the light reflected by the first connection electrode CE1 is again reflected by the first reflective electrode RE1 disposed below the LED, traveling to an area not covered by the first connection electrode CE1. Therefore, the light reflected by the first connection electrode CE1 and the first reflective electrode RE1 travels toward the direction where the second semiconductor layer 125 of the LED is disposed, and can pass through the second electrode 125 and the second connection electrode CE2 formed of transparent conductive material. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, compared to an example where both the first connection electrode CE1 and the second connection electrode CE2 are formed of transparent conductive material, front brightness can be improved. Therefore, as the brightness of the front of the display device 100 is improved, low-power driving can be achieved.

[0114] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, the second planarization layer 116 covering the side surface of the light-emitting diode (LED) comprises a black material. Therefore, the second planarization layer 116 fixes the LED and insulates the LED from peripheral components, and suppresses color mixing and external light reflection. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, it is not necessary to separately provide a structure including a black matrix, such as a black dam, above the LED. Therefore, the thickness of the display device 100 can be reduced, and the processing of forming the black dam and the number of masks required for that processing can be reduced. Therefore, processing optimization can be achieved by reducing processing costs and time.

[0115] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, a second planarization layer 116 covering the side surface of the light-emitting diode (LED) serves as a mask for the first connection electrode CE1. For example, in the display device 100 according to an exemplary embodiment of the present disclosure, the second planarization layer 116 is formed to correspond to the first connection electrode CE1 to pattern the first connection electrode CE1. Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, no light processing or masking processing for forming the first connection electrode CE1 is performed, thereby reducing processing costs and time. By doing so, processing optimization can be achieved.

[0116] Figure 5 This is an enlarged cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 5 Display device 500 and Figures 1 to 4 The difference of the display device 100 is that it does not have a third planarization layer 117. Only the second planarization layer 516 is different, while the other structures are basically the same. Therefore, redundant descriptions will be omitted.

[0117] Reference Figure 5 A second planarization layer 516 is disposed on the first connecting electrode CE1 and the light-emitting diode LED.

[0118] The second planarization layer 516 is disposed on the first connecting electrode CE1 to cover the side surface of the light-emitting diode (LED) and to be in direct contact with the side surface of the LED. In this case, the top surface of the second planarization layer 516 is configured to be higher than the light-emitting layer 122, and may be configured to be equal to or lower than the top surface of the second semiconductor layer 123. For example, the top surface of the second planarization layer 516 may be disposed between the top surface of the light-emitting layer 122 and the top surface of the second semiconductor layer 123, or on the same plane as the top surface of the second semiconductor layer 123.

[0119] The second planarization layer 516 can cover the top surface of the first connecting electrode CE1 disposed above the first electrode 124, and is in direct contact with the top surface of the first connecting electrode CE1. Furthermore, the second planarization layer 516 can cover the side surface of the first connecting electrode CE1. For example, the second planarization layer 516 can cover the side surface of the first connecting electrode CE1 disposed on the side surface of the light-emitting diode (LED), and can also cover the upper side surface of the LED disposed above the first connecting electrode CE1. Additionally, the second planarization layer 516 can cover the surface of the first connecting electrode CE1 disposed at the top of the first connecting electrode CE1.

[0120] The second planarization layer 516 can cover the side surface of the first connecting electrode CE1 disposed above the adhesive layer AD, and is in direct contact with the side surface of the first connecting electrode CE1. For example, in a plan view, the area of ​​the second planarization layer 516 can be larger than the area of ​​the first connecting electrode CE1. Therefore, the second planarization layer 516 extends from the top of the first connecting electrode CE1 to the top surface covering the adhesive layer AD.

[0121] The second planarization layer 516 may include a black material. Therefore, the second planarization layer 516 can suppress color mixing that may occur between light-emitting diodes (LEDs) emitting different colors of light and suppress external light reflection.

[0122] Furthermore, the bottom surface of the second planarization layer 516 contacts the top surface of the first connecting electrode CE1, and the top surface of the second planarization layer 516 is positioned below the top surface of the second electrode 125 and can contact the bottom surface of the second connecting electrode CE2. For example, the second planarization layer 516 is formed of an insulating material to suppress electrical connection between the first connecting electrode CE1 and the second connecting electrode CE2.

[0123] The second planarization layer 516 may include a plurality of contact holes that expose the top surface of the second reflective electrode RE2. The second connecting electrode CE2 can then be disposed within the contact holes of the second planarization layer 516. Therefore, the second connecting electrode CE2 can be connected to the second reflective electrode RE2 through the contact holes formed in the second planarization layer 516 and the adhesive layer AD.

[0124] In the following text, we will refer to... Figures 6A to 6D To describe a method of manufacturing a display device according to another exemplary embodiment of the present disclosure.

[0125] Figures 6A to 6D This is a view used to illustrate a method of manufacturing a display device according to another exemplary embodiment of the present disclosure.

[0126] First, refer to Figure 6AThe light-emitting diode (LED) is disposed on the adhesive layer AD, and the metal layer ML is formed on the adhesive layer AD to cover the LED.

[0127] A metal layer ML is disposed on the entire substrate 110 and can cover the top surface of the adhesive layer AD as well as the top and side surfaces of the light-emitting diode (LED). Furthermore, the metal layer ML covers the surface of the LED encapsulation film 126 and can cover the first electrode 124 and the second electrode 125 exposed through the contact holes of the encapsulation film 126.

[0128] Reference Figure 6B A photoresist PR containing a photosensitive material is formed on the metal layer ML. The photoresist PR is formed to cover a portion of the metal layer ML. For example, the photoresist PR is formed to cover the metal layer ML, extending from the contact holes of the passivation layer 114 and the first planarization layer 115 through which the source electrode SE of the driving transistor DT is exposed, to cover the top and side surfaces of the light-emitting diode LED.

[0129] Reference Figure 6C The photoresist PR is used as a mask for the metal layer ML to form the first connection electrode CE1. For example, the photoresist PR undergoes an ashing process to remove the portion of the photoresist PR covering the upper part of the light-emitting diode (LED). For example, the top surface of the metal layer ML on the second electrode 125 and the portion of the metal layer ML disposed on the upper side surface of the LED can be exposed by the ashing process. Thereafter, the first connection electrode CE1 is formed by removing the metal layer ML disposed in the region that does not overlap with the photoresist PR. Next, the top surface of the first connection electrode CE1 is exposed by removing the photoresist PR.

[0130] Next, refer to Figure 6D A second planarization layer 516, a second connection electrode CE2, and a fourth planarization layer 118 are formed on the first connection electrode CE1. The second planarization layer 516 is formed to cover the top and side surfaces of the first connection electrode CE1. Furthermore, the second planarization layer 516 is formed to cover the upper side surface of the light-emitting diode (LED) exposed from the top of the first connection electrode CE1. At this time, the second planarization layer 516 is formed to expose the second electrode 125.

[0131] Next, a second connection electrode CE2 and a fourth planarization layer 118 are formed on the second planarization layer 516. The second connection electrode CE2 is formed to cover the top surface of the second electrode 125 exposed from the second planarization layer 516, and extends on the second electrode 125 to the second planarization layer 516. Thereafter, a fourth planarization layer 118 is formed to cover the top surface of the second connection electrode CE2.

[0132] In another exemplary embodiment of the display device 500 according to this disclosure, the second connecting electrode CE2 comprises a transparent conductive material, while the first connecting electrode CE1 comprises a reflective conductive material. Therefore, light reflected from the first connecting electrode CE1 and the first reflective electrode RE1 travels towards the front of the light-emitting diode (LED), improving the front brightness of the display device 500 and enabling low-power driving.

[0133] Furthermore, in another exemplary embodiment of the display device 500 according to this disclosure, the second planarization layer 516 covering the side surface of the light-emitting diode (LED) comprises a black material. Therefore, in the display device 500 according to another exemplary embodiment of this disclosure, it is not necessary to separately provide a black dam, thereby reducing the thickness of the display device 500 and reducing the number of processes and masks required, thus saving processing costs and time.

[0134] Furthermore, in another exemplary embodiment of the display device 500 according to this disclosure, instead of forming a separate planarization layer over the second planarization layer 516, a second connection electrode CE2 is provided. Therefore, in the display device 500 according to another exemplary embodiment of this disclosure, a separate process for forming an insulating layer is not required, thereby reducing not only the number of processes and masks, but also saving processing costs and time.

[0135] Figure 7 This is an enlarged cross-sectional view of a display device according to yet another exemplary embodiment of the present disclosure. Figure 5 Compared to the display device 500, Figure 7 The only differences between the display device 700 and the display device 700 are the adhesive layer AD, the second planarization layer 716 and the first connecting electrode CE1, while the other structures are basically the same, so redundant descriptions will be omitted.

[0136] Reference Figure 7 An adhesive layer AD is disposed on multiple reflective electrodes RE. The adhesive layer AD may include multiple contact holes CH that respectively surround multiple light-emitting diodes (LEDs). For example, each of the multiple contact holes CH may have a closed-loop shape. In this case, each of the multiple contact holes CH has a shape that surrounds the outer diameter of the light-emitting diodes (LEDs), but is not limited thereto.

[0137] Multiple contact holes CH can expose the top surface of the first reflective electrode RE1 disposed beneath the adhesive layer AD. For example, the adhesive layer AD is formed of an island pattern corresponding to the shape of each of the multiple light-emitting diodes (LEDs) and a layer disposed on the outside of the multiple LEDs to surround the island pattern.

[0138] A light-emitting diode (LED) and a first connecting electrode CE1 are disposed on an adhesive layer AD. The first connecting electrode CE1 extends from the side surface of the LED to the top surface covering the adhesive layer AD. The first connecting electrode CE1 can be disposed in one of the multiple contact holes CH of the adhesive layer AD. Therefore, the first connecting electrode CE1 can contact the top surface of the first reflective electrode RE1 in one of the multiple contact holes CH of the adhesive layer AD. Thus, the adhesive layer AD disposed below the LED can be covered by the first connecting electrode CE1, the LED, and the first reflective electrode RE1. In other words, except for the surface in contact with the LED, the adhesive layer AD disposed below the LED can be covered by a reflective conductive material.

[0139] A second planarization layer 716 is disposed on the first connecting electrode CE1 and the light-emitting diode LED. The second planarization layer 716 can planarize the upper part of the first connecting electrode CE1. For example, the second planarization layer 716 is disposed in a plurality of contact holes CH of the adhesive layer AD to planarize the upper part of the adhesive layer AD.

[0140] In another exemplary embodiment of the display device 700 according to this disclosure, the second connection electrode CE2 comprises a transparent conductive material, while the first connection electrode CE1 may comprise a reflective conductive material. Therefore, light reflected from the first connection electrode CE1 and the first reflective electrode RE1 travels towards the front of the light-emitting diode (LED), improving the front brightness of the display device 700 and enabling low-power driving.

[0141] Furthermore, in another exemplary embodiment of the display device 700 according to this disclosure, the second planarization layer 716 surrounding the side surface of the light-emitting diode (LED) comprises a black material. Therefore, in the display device 700 according to another exemplary embodiment of this disclosure, it is not necessary to separately provide a black dam, thereby reducing the thickness of the display device 700 and reducing the number of processes and masks, thus saving processing costs and time.

[0142] Furthermore, in another exemplary embodiment of the display device 700 according to this disclosure, instead of forming a separate planarization layer over the second planarization layer 716, a second connection electrode CE2 is provided. Therefore, in another exemplary embodiment of the display device 700 according to this disclosure, a separate process for forming an insulating layer is not required, thereby reducing not only the number of processes and masks, but also saving processing costs and time.

[0143] Furthermore, in another exemplary embodiment of the display device 700 according to this disclosure, the adhesive layer AD includes a plurality of contact holes CH that respectively surround a plurality of light-emitting diodes (LEDs). Therefore, except for the surface in contact with the LEDs, the adhesive layer AD disposed below the LEDs can be covered by the first connecting electrode CE1 and the first reflecting electrode RE1. Therefore, in the light emitted from the LEDs, light traveling in the direction in which the adhesive layer AD is disposed is reflected by the first connecting electrode CE1 and the first reflecting electrode RE1 to travel to the top of the LEDs. Therefore, the problem of light emitted from the LEDs being guided within the adhesive layer AD and not being extracted to the outside can be suppressed. Therefore, in another exemplary embodiment of the display device 700 according to this disclosure, the overall brightness and front brightness of the LEDs are improved, enabling low-power driving.

[0144] Furthermore, in another exemplary embodiment of the display device 700 according to this disclosure, the first connecting electrode CE1 and the first reflecting electrode RE1 are electrically connected in each of the plurality of contact holes CH in the adhesive layer AD. Therefore, the contact area between the first connecting electrode CE1 and the first reflecting electrode RE1 can be increased, and the line resistance between the first connecting electrode CE1 and the first reflecting electrode RE1, and between the first connecting electrode CE1 and the driving transistor DT, can be reduced.

[0145] Exemplary embodiments of this disclosure can also be described as follows:

[0146] According to one aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of driving transistors in each of the plurality of sub-pixels; a plurality of light-emitting diodes in each of the plurality of sub-pixels; a first connecting electrode covering a portion of a lower side surface of the plurality of light-emitting diodes and formed of a reflective conductive material; and a second connecting electrode contacting a top surface of the plurality of light-emitting diodes and formed of a transparent conductive material.

[0147] The display device may further include: a first planarization layer on a plurality of driving transistors; and a second planarization layer between a first connection electrode and a second connection electrode, the second planarization layer having a thickness thinner than the thickness of the plurality of light-emitting diodes. The second planarization layer may include a black material.

[0148] The display device may further include: power lines on a substrate; a plurality of first reflective electrodes connected to a plurality of driving transistors; a plurality of second reflective electrodes connected to the power lines; and an adhesive layer on the plurality of first reflective electrodes and the plurality of second reflective electrodes. A first connecting electrode may contact the top surface of the adhesive layer.

[0149] The display device may also include a third planarization layer between the second planarization layer and the second connecting electrode.

[0150] The third planarization layer can cover the side surface of the second planarization layer and the side surface of the first connecting electrode.

[0151] The third planarization layer may include a plurality of contact holes that expose a portion of the top surface of a plurality of second reflective electrodes, and the second connecting electrode and the plurality of second reflective electrodes may be electrically connected in the plurality of contact holes of the third planarization layer.

[0152] The width of the bottom surface of the second planarization layer can be equal to the width of the top surface of the first connecting electrode.

[0153] The second planarization layer can cover the side surface of the first connecting electrode.

[0154] The top surface of the second planarization layer can contact the bottom surface of the second connecting electrode.

[0155] The adhesive layer may include multiple contact holes surrounding each of the multiple light-emitting diodes.

[0156] The multiple contact holes in the adhesive layer allow a portion of the top surface of the multiple first reflective electrodes to be exposed, and the first connecting electrode can contact the top surface of the multiple first reflective electrodes in the multiple contact holes of the adhesive layer.

[0157] According to another aspect of this disclosure, a display device includes: a substrate defining a plurality of sub-pixels; a plurality of driving transistors in each of the plurality of sub-pixels; a first planarization layer on the plurality of driving transistors; a plurality of light-emitting diodes (LEDs) on the first planarization layer in each of the plurality of sub-pixels; a first connection electrode electrically connected to the plurality of LEDs and formed of a reflective conductive material; a second connection electrode electrically connected to the plurality of LEDs and formed of a transparent conductive material; and a second planarization layer between the first connection electrode and the second connection electrode. The second planarization layer comprises a black material.

[0158] Each of the plurality of light-emitting diodes may include: a first semiconductor layer; a light-emitting layer on the first semiconductor layer; a second semiconductor layer on the light-emitting layer; a first electrode on the first semiconductor layer; and a second electrode on the second semiconductor layer. A first connecting electrode may be electrically connected to the first electrode, and a second connecting electrode may be electrically connected to the second electrode.

[0159] The second planarization layer can be disposed on the first connecting electrode, and the second planarization layer can overlap with the first electrode, but may not overlap with the light-emitting layer.

[0160] The display device may further include a third planarization layer that covers a portion of the upper side surface of the plurality of light-emitting diodes exposed by the second planarization layer. The third planarization layer may cover both the top and side surfaces of the second planarization layer.

[0161] The planar shape of the second planarization layer can be the same as the planar shape of the first connecting electrode.

[0162] The second planarization layer may include multiple contact holes, and the second connecting electrode may be disposed in the multiple contact holes.

[0163] The display device may further include: power lines on a substrate; and an adhesive layer on the power lines and a plurality of driving transistors. The adhesive layer may include a plurality of contact holes surrounding each of the plurality of light-emitting diodes.

[0164] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; Multiple driving transistors in each of the plurality of sub-pixels; Multiple light-emitting diodes in each of the plurality of sub-pixels; A first connecting electrode covers a portion of the lower side surface of the plurality of light-emitting diodes and is formed of a reflective conductive material; as well as The second connecting electrode is in contact with the top surface of the plurality of light-emitting diodes and is formed of a transparent conductive material.

2. The display device according to claim 1, further comprising: A first planarization layer on the plurality of driving transistors; as well as A second planarization layer is provided between the first connecting electrode and the second connecting electrode, and the second planarization layer has a thickness thinner than the thickness of the plurality of light-emitting diodes. The second planarization layer comprises a black material.

3. The display device according to claim 2, further comprising: Electric power lines on the substrate; Multiple first reflective electrodes connected to the plurality of driving transistors; Multiple second reflective electrodes connected to the power line; as well as An adhesive layer on the plurality of first reflective electrodes and the plurality of second reflective electrodes; The first connecting electrode is in contact with the top surface of the adhesive layer.

4. The display device according to claim 3, further comprising: A third planarization layer between the second planarization layer and the second connection electrode.

5. The display device according to claim 4, wherein, The third planarization layer covers the side surface of the second planarization layer and the side surface of the first connecting electrode.

6. The display device according to claim 4, wherein, The third planarization layer includes a plurality of contact holes that expose a portion of the top surface of the plurality of second reflective electrodes, and the second connecting electrode and the plurality of second reflective electrodes are electrically connected in the plurality of contact holes of the third planarization layer.

7. The display device according to claim 3, wherein, The width of the bottom surface of the second planarization layer is equal to the width of the top surface of the first connecting electrode.

8. The display device according to claim 3, wherein, The second planarization layer covers the side surface of the first connecting electrode.

9. The display device according to claim 3, wherein, The top surface of the second planarization layer is in contact with the bottom surface of the second connecting electrode.

10. The display device according to claim 3, wherein, The adhesive layer includes a plurality of contact holes surrounding each of the plurality of light-emitting diodes.

11. The display device according to claim 10, wherein, The plurality of contact holes in the adhesive layer expose a portion of the top surface of the plurality of first reflective electrodes, and the first connecting electrode contacts the top surface of the plurality of first reflective electrodes in the plurality of contact holes in the adhesive layer.

12. A display device, comprising: A substrate, wherein a plurality of sub-pixels are defined in the substrate; Multiple driving transistors in each of the plurality of sub-pixels; A first planarization layer on the plurality of driving transistors; Multiple light-emitting diodes on the first planarization layer in each of the plurality of sub-pixels; A first connecting electrode is electrically connected to the plurality of light-emitting diodes and is formed of a reflective conductive material; A second connecting electrode is electrically connected to the plurality of light-emitting diodes and is formed of a transparent conductive material; as well as A second planarization layer between the first connecting electrode and the second connecting electrode. The second planarization layer comprises a black material.

13. The display device according to claim 12, wherein, Each of the plurality of light-emitting diodes includes: First semiconductor layer; A light-emitting layer on the first semiconductor layer; A second semiconductor layer on the light-emitting layer; The first electrode on the first semiconductor layer; and The second electrode on the second semiconductor layer, and Wherein, the first connecting electrode is electrically connected to the first electrode, and the second connecting electrode is electrically connected to the second electrode.

14. The display device according to claim 13, wherein, The second planarization layer is disposed on the first connecting electrode, and the second planarization layer overlaps with the first electrode, but does not overlap with the light-emitting layer.

15. The display device according to claim 13, further comprising: A third planarization layer covers a portion of the upper side surface of the plurality of light-emitting diodes exposed by the second planarization layer. The third planarization layer covers the top and side surfaces of the second planarization layer.

16. The display device according to claim 15, wherein, The planar shape of the second planarization layer is the same as the planar shape of the first connecting electrode.

17. The display device according to claim 13, wherein, The second planarization layer includes a plurality of contact holes, and the second connection electrode is disposed in the plurality of contact holes.

18. The display device according to claim 17, further comprising: Electric power lines on the substrate; as well as An adhesive layer on the power lines and the plurality of drive transistors, and The adhesive layer includes a plurality of contact holes surrounding each of the plurality of light-emitting diodes.

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