Display panel, method for manufacturing display panel, and display device

Abstract

The application provides a display panel, a preparation method of the display panel and a display device. The display panel comprises a display area and a non-display area surrounding the display area. The non-display area comprises a binding area, a plurality of pads are arranged in the binding area, at least one pad in the plurality of pads comprises a substrate, a metal layer and an insulating layer, the metal layer comprises a first metal layer and a second metal layer, and the insulating layer comprises a first insulating layer and a second insulating layer. The first metal layer is arranged on the substrate, the first insulating layer is arranged on the substrate and the first metal layer, and the first insulating layer has a first opening exposing part of the first metal layer. The second metal layer is electrically connected with the first metal layer through the first opening and extends from the first opening to cover part of the first insulating layer in a direction away from the substrate. The second insulating layer covers the first insulating layer and part of the second metal layer. According to the embodiments of the application, the surface flatness of the pad in the display panel can be solved, and the reliability of the display panel as a whole can be improved.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to display panels, methods for manufacturing display panels, and display devices. Background Technology

[0002] In recent years, with technological advancements, displays have become an indispensable part of people's lives, work, and leisure. Among them, active-matrix light-emitting diodes (AMLEDs) are a promising new flat panel display technology that has attracted significant attention from the industry. AMLEDs offer advantages such as light weight, high luminous efficiency, low power consumption, self-illumination, good low-temperature performance, and flexibility.

[0003] As display panels evolve towards higher integration, narrower bezels, and greater flexibility, the design of the pad area is becoming increasingly dense, making the challenges of surface flatness and compatibility with subsequent processes more severe. Therefore, improving the surface morphology of the pads while ensuring reliable electrical connections, in order to eliminate their interference with subsequent bonding processes and automated production identification, has become a prominent and urgent technical challenge in this field. Summary of the Invention

[0004] This application provides a display panel, a method for manufacturing the display panel, and a display device, which can solve the problem of surface flatness of the pads in the display panel, thereby improving the overall reliability of the display panel.

[0005] In a first aspect, a display panel is provided, including a display area and a non-display area surrounding the display area; the non-display area includes: a bonding area, in which a plurality of pads are disposed, at least one of the plurality of pads including a substrate, a metal layer and an insulating layer, the metal layer including a first metal layer and a second metal layer, the insulating layer including a first insulating layer and a second insulating layer; the first metal layer is disposed on the substrate, the first insulating layer is disposed on the substrate and the first metal layer, and the first insulating layer has a first opening exposing a portion of the first metal layer; the second metal layer is electrically connected to the first metal layer through the first opening, and extends from the first opening in a direction away from the substrate to cover a portion of the first insulating layer; the second insulating layer covers the first insulating layer and a portion of the second metal layer.

[0006] In the embodiment of this application, by designing a first opening in the first insulating layer that exposes a portion of the first metal layer, and the second metal layer being electrically connected to the first metal layer through the first opening and extending from the first opening away from the substrate to cover a portion of the first insulating layer, the second insulating layer covers the first insulating layer and a portion of the second metal layer, thereby reducing the step difference formed in the pads. This can effectively improve the surface smoothness of the bonding area, reduce the risk of bubbles or poor bonding in subsequent bonding processes, and help improve the clarity and stability of the optical features on the bonding area surface. This improves the recognition success rate and process reliability of the display panel during manufacturing processes (such as optical alignment, inspection, and final module assembly), thereby enhancing the overall reliability of the display panel.

[0007] In conjunction with the first aspect, in some implementations of the first aspect, the portion of the second metal layer covered by the second insulating layer is closer to the substrate than the portion of the second metal layer not covered by the second insulating layer.

[0008] In the embodiment of this application, the design of the portion of the second metal layer covered by the second insulating layer being closer to the substrate than the portion of the second metal layer not covered by the second insulating layer naturally forms a step or buffer area composed of an insulating layer at the edge of the pad. This step structure can physically block and mechanically guide the over-insertion or lateral offset of external conductive components (such as test probes or bonding pins) during crimping, effectively preventing mechanical damage to the underlying substrate or other film layers, thereby widening the tolerance window of the crimping process and improving the reliability and repeatability of the connection process. Secondly, the second insulating layer provides an additional electrical protection layer for the internal metal traces, preventing accidental short circuits during testing or bonding.

[0009] In conjunction with the first aspect, in some implementations of the first aspect, the exposed portion of the second metal layer has a strip pattern spaced at multiple intervals on a surface away from the substrate.

[0010] In the embodiment of this application, the exposed portion of the second metal layer has a plurality of spaced strip patterns on the surface away from the substrate. These patterns can be pressed with external conductive devices (such as test probes or bonding pins) to illuminate the display panel.

[0011] In conjunction with the first aspect, in some implementations of the first aspect, the metal layer further includes a third metal layer, and the insulating layer further includes a third insulating layer; the second insulating layer is disposed on the first insulating layer and the second metal layer, and has a second opening that exposes a portion of the second metal layer; the third metal layer is electrically connected to the second metal layer through the second opening, and extends from the second opening in a direction away from the substrate to cover a portion of the second insulating layer; the third insulating layer covers the second insulating layer and a portion of the third metal layer.

[0012] In the embodiment of this application, by designing a first opening in the first insulating layer that exposes a portion of the first metal layer, and the second metal layer being electrically connected to the first metal layer through the first opening and extending from the first opening away from the substrate to cover a portion of the first insulating layer, the second insulating layer covers the first insulating layer and a portion of the second metal layer, thereby reducing the step difference formed in the pads. This can effectively improve the surface smoothness of the bonding area, reduce the risk of bubbles or poor bonding in subsequent bonding processes, and help improve the clarity and stability of the optical features on the bonding area surface. This improves the recognition success rate and process reliability of the display panel during manufacturing processes (such as optical alignment, inspection, and final module assembly), thereby enhancing the overall reliability of the display panel.

[0013] In conjunction with the first aspect, in some implementations of the first aspect, the first opening and the second opening are at least partially offset in the direction perpendicular to the thickness of the display panel.

[0014] In the embodiments of this application, by designing that the first opening and the second opening are at least partially staggered in the direction perpendicular to the thickness of the display panel, stress concentration can be avoided, the structural reliability of the bonding area can be improved, and thus the overall structural reliability of the display panel can be improved.

[0015] In conjunction with the first aspect, in some implementations of the first aspect, the insulating layer is an inorganic insulating layer, and the material of the inorganic insulating layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0016] In the embodiments of this application, at least one of silicon nitride, silicon oxide, or silicon oxynitride is used to form an inorganic insulating layer, which not only achieves the required planarization function, but also provides reliable mechanical protection for the underlying metal. In addition, the dense thin film structure serves as a highly efficient water, oxygen, and ion barrier layer, enhancing the resistance of the pads and even the entire display panel to environmental corrosion.

[0017] In conjunction with the first aspect, in some implementations of the first aspect, the insulating layer is an organic planarization layer.

[0018] In the embodiments of this application, by setting the insulating layer as an organic planarization layer, flatness can be achieved and water and oxygen can be prevented from entering. At the same time, the thickness of the organic planarization layer is lower, which can further reduce the step difference formed in the pad. This can effectively improve the surface flatness of the bonding area, reduce the risk of bubbles or poor bonding in subsequent bonding processes, and help improve the clarity and stability of the optical features on the bonding area surface. This improves the recognition success rate and process reliability of the display panel during the manufacturing process (such as optical alignment, inspection and final module assembly), thereby improving the overall reliability of the display panel.

[0019] In conjunction with the first aspect, in some implementations of the first aspect, the display area includes multiple sub-pixels and multiple data lines, the multiple sub-pixels being electrically connected to the multiple data lines; the non-display area also includes a detection circuit and multiple detection signal lines; wherein, the multiple data lines extend from the display area to the non-display area and are electrically connected to the detection circuit; the multiple detection signal lines are respectively electrically connected to the detection circuit and corresponding pads in the multiple pads, the multiple pads being configured to transmit detection signals to the multiple sub-pixels through the multiple detection signal lines, the detection circuit, and the multiple data lines during the detection phase of the display panel.

[0020] In the solution of this application embodiment, by placing the detection circuit in the non-display area and extending the data line to this area to connect with the detection circuit, the need to divide the space inside the display area for arranging complex detection-related circuits is avoided. Simultaneously, the detection signal line, acting as a bridge connecting the detection circuit and the pads, can have its wiring path flexibly planned according to the space of the non-display area. This structure effectively integrates the line density in the bezel area, avoiding an increase in the width of the non-display area due to messy arrangement of detection lines, thereby contributing to the narrow bezel design of the display panel and improving the screen-to-body ratio.

[0021] In a second aspect, a method for fabricating a display panel is provided. The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a bonding area, and a pad is disposed within the bonding area. The fabrication method is applied to the pad. The fabrication method includes: providing a substrate; forming a first metal layer on the substrate; forming a first insulating layer on the substrate and the first metal layer, wherein the first insulating layer has a first opening that exposes a portion of the first metal layer; forming a second metal layer on the first insulating layer, the second metal layer being electrically connected to the first metal layer through the first opening and extending from the first opening in a direction away from the substrate to cover a portion of the first insulating layer; and forming a second insulating layer on the first metal layer and a portion of the second metal layer.

[0022] Thirdly, a display device is provided, the display device including a display panel as described in the first aspect or any embodiment of the first aspect. Attached Figure Description

[0023] Figure 1 A schematic diagram of the reverse side of a display panel is shown.

[0024] Figure 2 This is a front plan view of a display panel according to an embodiment of this application.

[0025] Figure 3 This is a plan view of a display panel proposed in an embodiment of this application.

[0026] Figure 4 This is a plan view of another display panel proposed in the embodiments of this application.

[0027] Figure 5 This is a plan view of another display panel proposed in the embodiments of this application.

[0028] Figure 6 This is a plan view of another display panel proposed in the embodiments of this application.

[0029] Figure 7 This is a plan view of another display panel proposed in the embodiments of this application.

[0030] Explanation of reference numerals in the attached figures: Display panel 100; display area 101; non-display area 102; gate drive circuit 104; bonding area 107; bending area 1021; test circuit 106; pad 103; substrate 108; metal layer 109; insulating layer 110; first metal layer 1091; second metal layer 1092; third metal layer 1093; fourth metal layer 1094; first insulating layer 1101; second insulating layer 1102; third insulating layer 1103; first opening 1104; second opening 1105; sub-pixel 1011; data line 1012; detection circuit 1022; detection signal line 1023. Detailed Implementation

[0031] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0032] This application will present various aspects, embodiments, or features relating to a system comprising multiple devices, components, modules, etc. It should be understood and appreciated that individual systems may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches are also possible.

[0033] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate that they are examples, illustrations, or descriptions. Any embodiment or design scheme described as "exemplary" in the embodiments of this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of the term "exemplary" is intended to present the concept in a concrete manner.

[0034] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0035] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0036] In this application embodiment, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple.

[0037] Figure 1 A schematic diagram of the reverse side of a display panel 100 is shown. Figure 2 This is a front plan view of a display panel 100 according to an embodiment of this application.

[0038] like Figure 1 and Figure 2 As shown, the display panel 100 may include a display area 101 and a non-display area 102. The display area 101 includes at least a plurality of regularly arranged sub-pixels 1011. These sub-pixels 1011 can be arranged in an array along a first direction X and a second direction Y, and the first and second directions X and Y can intersect each other. For example, the first and second directions X and Y can be perpendicular to each other. The first direction X can be referred to as the row direction, and the second direction Y as the column direction. The plurality of sub-pixels 1011 are configured to display dynamic or still images. The display area 101 may include a plurality of data lines 1012 extending along the first direction X. Each data line 1012 can be electrically connected to a single column of sub-pixels 1011, and the data lines 1012 can extend along the first direction X and then enter the non-display area 102. In an exemplary embodiment, the display panel 100 may be deformable, for example, it can be rolled up, bent, folded, or rolled up.

[0039] The non-display area 102 of the display panel 100 includes a bonding area 107, which may include a bonding pin area BD and a test pin area ET. At least one bonding pin area BD is located on one side of the display area 101. Each bonding pin area BD has multiple pads P1, which can be subsequently bonded to a flexible printed circuit (FPC) to directly or indirectly provide electrical signals to multiple sub-pixels 1011 of the display area 101, enabling the display panel 100 to display normally. The display area 101 also includes multiple first power lines Ld, each of which is connected to a column of sub-pixels 1011. On the side of at least one bonding pin area BD near the display area 101, the display panel 100 also has a first power bus VDD and at least one first power branch VDD1. The first power bus VDD extends along the second direction Y and is electrically connected to the multiple first power lines Ld. At least one first power branch line VDD1 extends along a first direction X and is electrically connected to a first power bus VDD, and each first power branch line VDD1 is connected to at least one pad P1. The first power line Ld can provide a first power signal to the display panel 100, which can be a positive voltage signal. The display panel 100 also includes a second power bus VSS1 and at least one second power branch line VSS. The second power bus VSS1 is located in the non-display area 102 and at least partially surrounds the display area 101. The at least one second power branch line VSS is located between the display area 101 and at least one bonding pin area BD, and the second power bus VSS1 and the at least one second power branch line VSS are electrically connected. At least one pad P1 is provided in at least one bonding pin area BD, and the pad P1 is connected to at least one second power branch line VSS. At least one pad 103 is also provided in at least one test pin area ET, and the at least one pad 103 is configured to transmit a first power test signal to a plurality of sub-pixels 1011 through at least one pad P1 during the testing phase of the display panel 100. The first power test signal can be provided to the pixel driving circuit of the display panel 100, and the first power test signal can be a negative voltage signal.

[0040] Each of the multiple test pin areas ET has multiple pads 103. These pads 103 can be used to directly or indirectly provide test signals to multiple sub-pixels 1011 during the testing phase of the display panel 100, thereby performing electrical tests (ET) on the display panel 100, such as light-on tests, including light-on tests in an electric vehicle environment (EVEN), automated visual inspection (AVI), including automated visual inspection under enhanced area coverage or enhanced accuracy control, and lifetime aging tests. At least one test pin area ET and at least one bonding pin area BD are located in the same row in the second direction Y.

[0041] The non-display area 102 of the display panel 100 may include a gate driving circuit area, within which a gate driving circuit 104 is disposed. The gate driving circuit area may be located on at least one side of the display area 101 along the second direction Y. Figure 2 As shown, the display panel 100 may include two gate driving circuit areas, which may be respectively disposed on both sides of the display area 101 along the second direction Y. For example, multiple gate driving circuits 104 in the two gate driving circuit areas may be arranged symmetrically along the first axis of symmetry. Each gate driving circuit 104 may include multiple shift register circuits, and two shift registers of the same level on the left and right sides may be connected to the same row of sub-pixels 1011.

[0042] The display panel 100 also includes a detection circuit 1022, which is located on the side of the bonding area 107 near the display area 101.

[0043] At least one test pin area ET is provided with multiple pads 103. The non-display area 102 also includes multiple detection signal lines 1023 and multiple data lines 1012 extending from the display area 101 to the non-display area 102 and electrically connected to the detection circuit 1022. The multiple detection signal lines 1023 are electrically connected to the detection circuit 1022 and the corresponding pads 103 among the multiple pads 103. The multiple pads 103 are configured to transmit detection signals to multiple sub-pixels 1011 through the multiple detection signal lines 1023, the detection circuit 1022, and the multiple data lines 1012 during the detection phase of the display panel 100. By placing the detection circuit 1022 in the non-display area 102 and extending the data lines 1012 to this area to connect with the detection circuit 1022, the need to divide space inside the display area 101 for arranging complex detection-related circuitry is avoided. Meanwhile, the detection signal line 1023 serves as a bridge connecting the detection circuit 1022 and the pad 103. Its wiring path can be flexibly planned according to the space of the non-display area 102. This structure effectively integrates the line density of the bezel area and avoids the increase in the width of the non-display area 102 caused by the messy arrangement of detection lines, thereby helping to achieve the narrow bezel design of the display panel 100 and improve the screen ratio.

[0044] In an exemplary embodiment, some of the pads 103 of the plurality of pads 103 in the test pin area ET can be connected to the detection circuit 1022.

[0045] In an exemplary embodiment, the display panel 100 further includes an integrated circuit (IC) between the detection circuit 1022 and the bonding pin area BD. The IC is electrically connected to multiple sub-pixels 1011 via multiple data lines 1012. The IC can generate driving signals required to drive the sub-pixels 1011, such as data signals controlling the brightness of the sub-pixels 1011. The detection circuit 1022 may also include an electrostatic discharge (ESD) circuit to prevent static electricity from affecting signal transmission.

[0046] In an exemplary embodiment, after the display panel 100 successfully passes the test, integrated circuits (ICs), flexible circuit boards, and other structures are bonded to the display panel 100. The display panel 100 after the bonding is completed can be referred to as a display module.

[0047] In an exemplary embodiment, the non-display area 102 further includes a bent area 1021 located on the side of the display area 101 near the detection circuit 1022 and extending along the second direction Y. The subsequent display panel 100 can be bent along the bent area 1021, causing the integrated circuit IC to bend below the display area 101, thus achieving a narrow bezel.

[0048] The pad 103 structure typically consists of multiple layers of alternating metal and insulating layers, inevitably creating microscopic steps and height differences on the surface of the bonding area 107. In later stages of the display panel 100 manufacturing process, it is often necessary to apply coatings (such as protective films, polarizing films, touch sensor films, etc.) or other functional layers to the display panel surface. When these subsequent processing layers cover the bonding area 107, the surface undulations of the underlying pad 103 can hinder tight bonding between interfaces, easily leading to localized bubbles or bonding voids due to gas residue. In automated production lines, the bonding area 107 is the area for optical alignment, visual inspection, and robotic arm operation. The bonding defects caused by the aforementioned surface morphology can distort or obscure optical recognition features, causing the alignment system to fail to accurately identify the position of the pad 103, resulting in bonding deviations, inspection failures, or robotic arm malfunctions, thereby reducing the overall production yield and manufacturing efficiency of the display panel 100.

[0049] Based on this, how can the surface flatness problem of the pads 103 in the display panel 100 be solved to improve the overall reliability of the display panel 100?

[0050] Figure 3 This is a plan view of a display panel 100 according to an embodiment of this application. For example, Figure 3 As shown Figure 2 The diagram shows a cross-sectional view of the display panel 100 along section line A-A'. Figure 3 It shows Figure 2 A partial cross-sectional view of the Central African display area 102, namely Figure 3 It is the XOZ plane. Figure 4 This is a plan view of another display panel 100 proposed in an embodiment of this application, wherein, Figure 4 for Figure 3 Top view.

[0051] In some possible embodiments, such as Figures 2 to 4As shown, the display panel 100 includes a display area 101 and a non-display area 102 surrounding the display area; the non-display area 102 includes a bonding area 107, in which a plurality of pads 103 are disposed, at least one of the plurality of pads 103 including a substrate 108, a metal layer 109 and an insulating layer 110, the metal layer 109 including a first metal layer 1091 and a second metal layer 1092, and the insulating layer 110 including a first insulating layer 1101 and a second insulating layer 1102; the first metal layer 1091 is disposed On the substrate 108, a first insulating layer 1101 is disposed on the substrate 108 and a first metal layer 1091, and the first insulating layer 1101 has a first opening 1104 that exposes a portion of the first metal layer 1091; a second metal layer 1092 is electrically connected to the first metal layer 1091 through the first opening 1104, and extends from the first opening 1104 in a direction away from the substrate 108 to cover a portion of the first insulating layer 1101; the second insulating layer 1102 covers the first insulating layer 1101 and a portion of the second metal layer 1092. By designing a first opening 1104 in the first insulating layer 1101 to expose a portion of the first metal layer 1091, and electrically connecting the second metal layer 1092 to the first metal layer 1091 through the first opening 1104, and extending from the first opening 1104 in a direction away from the substrate 108 to cover a portion of the first insulating layer 1101, the second insulating layer 1102 covers the first insulating layer 1101 and a portion of the second metal layer 1092, thereby reducing the step difference formed within the pad 103, such as... Figure 3 The D in the model can effectively improve the surface smoothness of the bonding area 107, reduce the risk of bubbles or poor bonding in subsequent bonding processes, and help improve the clarity and stability of the optical features on the surface of the bonding area 107. This improves the recognition success rate and process reliability of the display panel 100 during the manufacturing process (such as optical alignment, inspection and final module assembly), thereby improving the overall reliability of the display panel 100.

[0052] It should be understood that during the manufacturing process of the display panel 100, if the height difference (i.e., discontinuity) between different film layers on the surface of the display panel 100 is large, and a temporary protective film needs to be applied to this area (e.g., for surface protection during transportation, cutting, or some processes), this protective film needs to be removed in subsequent processes. During film removal, due to the electrostatic effect and airflow disturbance generated by high-speed peeling, tiny contaminant particles, such as dust, fibers, resin debris, and metal powder, can easily accumulate in the corners and edges of the discontinuity structure, in airflow quiet areas and cleaning blind spots. These accumulated contaminant particles can cause serious process and product risks. Furthermore, if contaminant particles accumulate on or around the pad 103, during subsequent crimping and bonding of driver chips or flexible circuit boards, the particles may cause short circuits between adjacent pins or poor contact between conductive particles and the pad 103, resulting in abnormal signal transmission and functional failure. In addition, the presence of particles may directly lead to defects such as bubbles and local peeling during optical adhesive bonding.

[0053] The design scheme provided by the embodiments of this application can effectively reduce the height and steepness of the drop. It reduces airflow dead zones, allowing the cleaning airflow and the dust-collecting rollers to more effectively remove contaminants; it also reduces the concentrated adsorption effect of static electricity at corners; thereby helping to avoid the accumulation of tiny contaminant particles at the drop and improving the overall process yield.

[0054] Furthermore, during the protective film lamination process, if air bubbles form between the protective film and the panel due to defects, particles, or other reasons, these bubbles may obscure the alignment marks used for precise positioning on the four sides of the display panel 100. If the alignment marks are obscured, subsequent cutting equipment cannot accurately identify the panel boundaries, leading to a decrease in cutting accuracy. If air bubbles obscure the markings used for crimping alignment in the pad 103 area, it will cause difficulties or deviations in alignment for the lighting test equipment. Inaccurate alignment may prevent the test probe from accurately contacting the pad 103, resulting in display abnormalities, bright lines, and other misjudgments, increasing unnecessary re-inspection and repair costs. If the protective film is a permanent lamination type (such as certain cover films or encapsulation layers), the air bubbles may expand due to changes in ambient temperature, humidity, or mechanical stress during subsequent module encapsulation or product use, leading to encapsulation failure, delamination, and in severe cases, directly causing product scrap.

[0055] The solution provided in this application embodiment can be used to accurately locate the alignment marks of the display panel 100 or the markings in the pad 103 area for crimping alignment, thereby improving the overall process yield of the display panel 100.

[0056] The second insulating layer 1102 covers a portion of the second metal layer 1092, and a step structure is formed between the covered area of ​​the second insulating layer 1102 and the exposed area of ​​the second metal layer 1092. The height of the step is the step difference. The step structure is used to provide mechanical limiting and / or optical alignment reference for external conductive elements.

[0057] The first metal layer 1091 and the second metal layer 1092 in the metal layer 109 can be source and drain metal layers. The first metal layer 1091 can extend from the display area 101 of the display panel 100 to the bonding area 107, or it can be set separately.

[0058] Alternatively, the first metal layer 1091 in the metal layer 109 can be a gate metal layer, and the second metal layer 1092 can be a source / drain metal layer. In this case, the second metal layer 1092 can extend from the display area 101 of the display panel 100 to the bonding area 107, or it can be set separately.

[0059] The first metal layer 1091 is disposed on the substrate 108. The first metal layer 1091 may completely cover the substrate 108, or the first metal layer 1091 may partially cover the substrate 108.

[0060] The first insulating layer 1101 is disposed on the substrate 108 and the first metal layer 1091, and the first insulating layer 1101 has a first opening 1104 that exposes a portion of the first metal layer 1091. In other words, the first insulating layer 1101 covers the substrate 108 and a portion of the first metal layer 1091, and the first metal layer 1091 is partially exposed.

[0061] The second metal layer 1092 is electrically connected to the first metal layer 1091 through the first opening 1104, and extends from the first opening 1104 in a direction away from the substrate 108 to cover part of the first insulating layer 1101. That is, the second metal layer 1092 first fills the first opening 1104, and on this basis, extends in the thickness direction of the display panel 100 beyond the first insulating layer 1101 and partially covers the first insulating layer 1101.

[0062] The first opening 1104 can be created during the laying of the first insulating layer 1101. This process eliminates the need for subsequent steps of separately creating openings in the first insulating layer 1101 (such as dry / wet etching), allowing the first insulating layer 1101 and the first opening 1104 structure to be formed in one step, shortening the process flow. In addition, since it is not necessary to etch openings on the complete first insulating layer 1101, the over-etching or physical damage that the etching process may cause to the underlying first metal layer 1091 (especially thin metal or sensitive metal) is reduced.

[0063] Figure 5 This is a plan view of another display panel 100 proposed in the embodiments of this application.

[0064] like Figure 5As shown, the first insulating layer 1101 can directly cover the first metal layer 1091. After the layer is laid, a first opening 1104 is formed by drilling holes, and the first metal layer 1091 and the second metal layer 1092 are electrically connected through the first opening 1104. The first insulating layer 1101 can be deposited uniformly in one go, ensuring overall thickness and density, and avoiding uneven deposition caused by reserved openings. In addition, in designs that require high-density interconnection, the drilling design of the first insulating layer 1101 allows for flexible adjustment of the opening position and size to adapt to complex layouts.

[0065] In some possible embodiments, reference may continue to be made to Figures 2 to 5 The portion of the second metal layer 1092 covered by the second insulating layer 1102 is closer to the substrate 108 than the portion of the second metal layer 1092 not covered by the second insulating layer 1102.

[0066] In the embodiment of this application, the design of the portion of the second metal layer 1092 covered by the second insulating layer 1102 being closer to the substrate 108 than the portion of the second metal layer 1092 not covered by the second insulating layer 1102 naturally forms a step or buffer area composed of the insulating layer 110 at the edge of the pad 103. This step structure can physically block and mechanically guide the over-insertion or lateral offset of external conductive components (such as test probes or bonding pins) during crimping, effectively preventing mechanical damage to the underlying substrate 108 or other film layers, thereby widening the tolerance window of the crimping process and improving the reliability and repeatability of the connection process. Secondly, the second insulating layer 1102 provides an additional electrical protection layer for the internal metal traces, preventing accidental short circuits during testing or bonding.

[0067] It should be understood that the materials and thicknesses of the first insulating layer 1101 and the second insulating layer 1102 can be the same, or they can be set according to design requirements.

[0068] In some possible embodiments, the insulating layer 110 can be an inorganic insulating layer, and the material of the inorganic insulating layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. Using at least one of silicon nitride, silicon oxide, or silicon oxynitride to form the inorganic insulating layer not only achieves the required planarization function, but also provides reliable mechanical protection for the underlying metal layer 109; in addition, the dense thin film structure acts as a highly efficient water, oxygen, and ion barrier layer, enhancing the resistance of the pads 103 and even the entire display panel 100 to environmental corrosion.

[0069] In some possible embodiments, the insulating layer 110 is an organic planarization layer. By setting the insulating layer 110 as an organic planarization layer, flatness and prevention of water and oxygen ingress can be achieved. At the same time, the thickness of the organic planarization layer is lower, which can further reduce the step difference formed in the pad 103. This can effectively improve the surface flatness of the bonding area 107, reduce the risk of bubbles or poor bonding in subsequent bonding processes, and help improve the clarity and stability of the optical features on the surface of the bonding area 107. This improves the recognition success rate and process reliability of the display panel 100 during the manufacturing process (such as optical alignment, inspection and final module assembly), thereby improving the overall reliability of the display panel 100.

[0070] The materials of the first insulating layer 1101 and the second insulating layer 1102 can be the same, for example, both can be inorganic insulating layers. The materials of the first insulating layer 1101 and the second insulating layer 1102 can also be different. For example, the material of the first insulating layer 1101 is an inorganic insulating layer, and the material of the second insulating layer 1102 can be an organic planarization layer.

[0071] In some possible embodiments, reference may continue to be made to Figures 2 to 5 The second metal layer 1092 can completely fill the first opening 1104, rather than partially contact it, to improve the reliability of the connection.

[0072] Alternatively, after the second metal layer 1092 partially fills the first opening 1104, the second insulating layer 1102 completely fills the first opening 1104. That is, the second metal layer 1092 and the second insulating layer 1102 completely fill the first opening 1104, ensuring the flatness of the film structure while improving the reliability of the connection.

[0073] In some possible embodiments, the exposed portion of the second metal layer 1092 has a plurality of spaced stripe patterns on the surface away from the substrate 108. In the embodiment of this application, the exposed portion of the second metal layer 1092 has a plurality of spaced stripe patterns on the surface away from the substrate 108, which can be pressed with an external conductive device (such as a test probe or bonding pin) to illuminate the display panel 100.

[0074] Specifically, these strip patterns serve as external electrical contact terminals of the display panel 100, forming a test and signal access interface. These strip patterns can also be referred to as a "PIN array," "pad array," or "contact pad array." Each strip pattern, through its underlying second metal layer 1092, first opening 1104, and first metal layer 1091, ultimately forms an independent electrical path with specific functional circuits (such as pixel driving circuits, gate lines, data lines, power lines, or signal input lines) inside the display panel 100.

[0075] Each strip pattern appears as a slender rectangle in the top view, and its length direction is usually parallel to one of the edges of the panel (such as the top or bottom edge), which can maximize the use of the overall space and facilitate alignment.

[0076] In addition, the width and spacing of the strip pattern can be determined based on the area of ​​the exposed portion of the second metal layer 1092 to meet the requirements of electrical insulation (to prevent short circuits), current carrying capacity, and mechanical matching with external connectors.

[0077] Optionally, to ensure good contact reliability, the exposed surface of the strip pattern can be specially treated. For example, an oxidation-resistant, low-contact-resistance metal layer 109, such as a nickel-gold, tin, or conductive polymer coating, can be deposited or plated on it. The surface is generally kept flat and clean, without residual photoresist or passivation layer covering.

[0078] Optionally, during the intermediate / final testing stage after the display panel 100 is manufactured but before module assembly, the metal probe card of the automated testing equipment will be precisely aligned and pressed onto the PIN array. Each probe contacts a strip pattern, thereby inputting test signals (such as gate scan signals, data voltage signals, common electrode voltage, etc.) into the panel to drive the pixels to emit light, in order to detect defects such as short circuits, open circuits, and uneven brightness.

[0079] Optionally, during the module assembly stage, the driver integrated circuit or flexible printed circuit board uses anisotropic conductive adhesive film or thermoforming process to permanently bond its own output pins to the corresponding strip pattern of this PIN array, thereby realizing the formal input of the display drive signal.

[0080] It should be understood that a PIN array can be a Fan-Out Panel (FOP) solution or an Edge Tail / Edge Taper (ET) solution. FOP is a design method and area for fan-out wiring of chip micro-pitch pins on a panel glass substrate, while ET is a pin array with fan-out wiring already completed and attached to a flexible thin film carrier.

[0081] Figure 6 This is a plan view of another display panel 100 proposed in the embodiments of this application.

[0082] In some possible embodiments, such as Figure 6As shown, the metal layer 109 further includes a third metal layer 1093, and the insulating layer 110 further includes a third insulating layer 1103; the second insulating layer 1102 is disposed on the first insulating layer 1101 and the second metal layer 1092, and has a second opening 1105 that exposes a portion of the second metal layer 1092; the third metal layer 1093 is electrically connected to the second metal layer 1092 through the second opening 1105, and extends from the second opening 1105 in a direction away from the substrate 108 to cover a portion of the second insulating layer 1102; the third insulating layer 1103 covers the second insulating layer 1102 and a portion of the third metal layer 1093. By designing a first opening 1104 with an exposed portion of the first metal layer 1091 in the first insulating layer 1101, and the second metal layer 1092 being electrically connected to the first metal layer 1091 through the first opening 1104, and extending from the first opening 1104 in a direction away from the substrate 108 to cover a portion of the first insulating layer 1101, the second insulating layer 1102 covers the first insulating layer 1101 and a portion of the second metal layer 1092, thereby reducing the step difference formed in the pad 103, effectively improving the surface smoothness of the bonding area 107, reducing the risk of bubbles or poor bonding in subsequent bonding processes, and helping to improve the clarity and stability of the optical features on the surface of the bonding area 107, thereby improving the recognition success rate and process reliability of the display panel 100 during the manufacturing process (such as optical alignment, inspection and final module assembly), and thus improving the overall reliability of the display panel 100.

[0083] It should be understood that in the case of three metal layers 109, the function of the exposed portion of the third metal layer 109 and the surface design are the same as those of the second metal layer 1092 in the case of two metal layers 109, and will not be repeated here.

[0084] Specifically, during the testing phase, the metal probe of the external device is pressed down vertically to contact the exposed surface of the third metal layer 1093, completing signal injection and testing.

[0085] During the bonding phase, the flexible printed circuit board (PCB) is aligned so that its leads align with the stripe pattern on the third metal layer 1093. An anisotropic conductive adhesive film is placed between the PCB and the display panel 100. Under heat and pressure, the insulating adhesive in the anisotropic conductive adhesive film melts and flows, while the dispersed tiny conductive gold balls are flattened and vertically pressed between the PCB leads and the pads 103 of the third metal layer 1093, forming vertically conductive metal pillars to achieve electrical connection. Simultaneously, the horizontally conductive balls are isolated from each other to prevent short circuits between the pads 103. Cooling is maintained under pressure, and the anisotropic conductive adhesive film solidifies, forming a permanent mechanical fixation and electrical connection.

[0086] The first metal layer 1091 can be a film layer for signals such as data lines and power lines extending from the display area 101.

[0087] Optionally, the thicknesses of the first metal layer 1091, the second metal layer 1092, and the third metal layer 1093 may be different, wherein the third metal layer 1093 may be the thickest of all the metal layers 109. For example, the thickness of the third metal layer 1093 may be greater than 1 μm to withstand friction and indentation.

[0088] It should be understood that the first metal layer 1091 serves as the anchoring base layer for the pad 103, the second metal layer 1092 covers and connects to the first metal layer 1091 through the first opening 1104, and serves as a stress buffer and current spreading layer, and the third metal layer 1093 covers and connects to the second metal layer 1092 through the second opening 1105. Its upper surface serves as the final pressure bonding surface and contacts the conductive particles of the anisotropic conductive adhesive film. This structure transmits signals vertically from the inside to the surface, while providing good mechanical strength and electrical redundancy.

[0089] In some possible embodiments, the first opening 1104 and the second opening 1105 are at least partially offset in the direction perpendicular to the thickness of the display panel 100. By designing that the first opening 1104 and the second opening 1105 are at least partially offset in the direction perpendicular to the thickness of the display panel 100, stress concentration can be avoided, the structural reliability of the bonding area 107 can be improved, and thus the overall structural reliability of the display panel 100 can be improved.

[0090] Figure 7 This is a plan view of another display panel 100 proposed in the embodiments of this application.

[0091] Optionally, such as Figure 7 As shown, the metal layer 109 further includes a first metal layer 1091, a second metal layer 1092, a third metal layer 1093, and a fourth metal layer 1094, wherein the first metal layer 1091, the second metal layer 1092, and the third metal layer 1093 are connected to the metal layer 1094. Figure 6 The corresponding embodiments have the same function and location. The first metal layer 1091, the second metal layer 1092, and the third metal layer 1093 can all be source / drain metal layers. The first metal layer 1091 can extend from the display area 101 of the display panel 100. The fourth metal layer 1094 can be a gate metal layer, located between the first metal layer 1091 and the substrate 108.

[0092] The fourth metal layer 1094 can be connected to the gate driving circuit of the non-display area 102 in the display panel 100. An insulating layer 110 can be provided between the fourth metal layer 1094 and the first metal layer 1091. The insulating layer 110 can be electrically connected between the first metal layer 1091 and the fourth metal layer 1094 by drilling holes. This application also provides a method for manufacturing a display panel 100. The display panel 100 includes a display area 101 and a non-display area 102 surrounding the display area 101. The non-display area 102 includes a bonding area 107, and a pad 103 is disposed in the bonding area 107. The manufacturing method is applied to the pad 103. The manufacturing method includes: providing a substrate 108; forming a first metal layer 1091 on the substrate 108; forming a first insulating layer 1101 on the substrate 108 and the first metal layer 1091, wherein the first insulating layer 1101 has a first opening 1104 that exposes a portion of the first metal layer 1091; forming a second metal layer 1092 on the first insulating layer 1101, the second metal layer 1092 being electrically connected to the first metal layer 1091 through the first opening 1104, and extending from the first opening 1104 in a direction away from the substrate 108 to cover a portion of the first insulating layer 1101; and forming the second insulating layer 1102 on the first metal layer 1091 and a portion of the second metal layer 1092.

[0093] It should be understood that the embodiments of display panel 100 are also applicable to the manufacturing method of display panel 100, and will not be repeated here.

[0094] It should also be understood that the preparation process of the three-layer metal layer 109 is similar to that of the two-layer metal layer 109, and will not be described in detail here.

[0095] During the process of each insulating layer 110, a larger area of ​​the metal layer 109 film is exposed. The next metal layer 109 film is stacked from the previous metal layer and continuously laid on top of the insulating film layer. The above process is repeated until all metal layers 109 are laid.

[0096] Taking a stacked structure of three metal layers 109 as an example, the fabrication process of the film layer of the pad 103 of the display panel 100 is explained as follows: 1. Lay a first metal layer 1091 film layer on the substrate 108.

[0097] 2. A first insulating layer 1101 is laid on the first metal layer 1091, and a portion of the first metal layer 1091 is exposed.

[0098] 3. The second metal layer 1092 is stacked starting from the exposed area of ​​the first metal layer 1091 and continues to be laid on the first insulating layer 1101.

[0099] 4. A second insulating layer 1102 is laid on the second metal layer 1092, and part of the second metal layer 1092 is exposed.

[0100] 5. The third metal layer 1093 is stacked starting from the exposed area of ​​the second metal layer 1092 and continues to be laid on the second insulating layer 1102.

[0101] 6. Lay a third insulating layer 1103 on the third metal layer 1093, leaving the third metal layer 1093 exposed for crimping.

[0102] The step difference between the surface of the third insulating layer 1103 away from the substrate 108 and the surface of the third metal layer 1093 away from the substrate 108, or the step difference between the surface of the third insulating layer 1103 away from the substrate 108 and the crimping pin surface of the third metal layer 1093, is about 1 / 4 of that in the prior art.

[0103] It should be understood that in existing solutions, metal layers 109 are typically stacked directly, with each metal layer 109 partially covered by an insulating layer 110.

[0104] This application also provides a display device, which includes the display panel 100 in any of the above embodiments.

[0105] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0106] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0107] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0108] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0109] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0110] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0111] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a non-display area surrounding the display area; The non-display area includes: A bonding area is provided in which multiple pads are provided. At least one of the multiple pads includes a substrate, a metal layer and an insulating layer. The metal layer includes a first metal layer and a second metal layer. The insulating layer includes a first insulating layer and a second insulating layer. The first metal layer is disposed on the substrate, the first insulating layer is disposed on the substrate and the first metal layer, and the first insulating layer has a first opening that exposes a portion of the first metal layer; The second metal layer is electrically connected to the first metal layer through the first opening, and extends from the first opening in a direction away from the substrate to cover a portion of the first insulating layer; The second insulating layer covers the first insulating layer and a portion of the second metal layer.

2. The display panel according to claim 1, characterized in that, The portion of the second metal layer covered by the second insulating layer is closer to the substrate than the portion of the second metal layer not covered by the second insulating layer.

3. The display panel according to claim 1 or 2, characterized in that, The exposed portion of the second metal layer has a plurality of spaced stripe patterns on the surface away from the substrate.

4. The display panel according to claim 1 or 2, characterized in that, The metal layer further includes a third metal layer, and the insulating layer further includes a third insulating layer; The second insulating layer is disposed on the first insulating layer and the second metal layer, and has a second opening that exposes a portion of the second metal layer; The third metal layer is electrically connected to the second metal layer through the second opening, and extends from the second opening in a direction away from the substrate to cover a portion of the second insulating layer; The third insulating layer covers the second insulating layer and part of the third metal layer.

5. The display panel according to claim 4, characterized in that, The first opening and the second opening are at least partially offset in a direction perpendicular to the thickness of the display panel.

6. The display panel according to any one of claims 1 to 5, characterized in that, The insulating layer is an inorganic insulating layer, and the material of the inorganic insulating layer includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

7. The display panel according to any one of claims 1 to 6, characterized in that, The insulating layer is an organic planarization layer.

8. The display panel according to any one of claims 1 to 7, characterized in that, The display area includes multiple sub-pixels and multiple data lines, and the multiple sub-pixels are electrically connected to the multiple data lines; The non-display area also includes a detection circuit and multiple detection signal lines; The multiple data lines extend from the display area to the non-display area and are electrically connected to the detection circuit. The plurality of detection signal lines are electrically connected to the detection circuit and the corresponding pads among the plurality of pads, respectively. The plurality of pads are configured to transmit detection signals to the plurality of sub-pixels via the plurality of detection signal lines, the detection circuit, and the plurality of data lines during the detection phase of the display panel.

9. A method for manufacturing a display panel, characterized in that, The display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a bonding area, and pads are disposed in the bonding area. The fabrication method is applied to the pads. The preparation method includes: Provide a base; A first metal layer is formed on the substrate; A first insulating layer is formed on the substrate and the first metal layer, wherein the first insulating layer has a first opening that exposes a portion of the first metal layer; A second metal layer is formed on the first insulating layer, the second metal layer being electrically connected to the first metal layer through the first opening, and extending from the first opening in a direction away from the substrate to cover a portion of the first insulating layer; A second insulating layer is formed on the first metal layer and a portion of the second metal layer.

10. A display device, characterized in that, The display device includes a display panel as claimed in any one of claims 1-8.

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