Parameter closed-loop optimized wafer preparation method, system, electronic device, medium

Abstract

The present application relates to a wafer preparation method, system, electronic device and medium of parameter closed-loop optimization. An intelligent feedback mechanism based on defect identification results is constructed. After the defect identification results are obtained through the relatively accurate detection of the image difference defect identification algorithm and the double defect detection path of the defect identification intelligent model, it is further judged whether the detection recipe optimization condition is met based on the defect identification results. If the detection recipe optimization condition is not met, it is directly judged whether the wafer preparation process needs to be optimized based on the defect identification results. If the detection recipe optimization condition is met, the wafer detection recipe parameters are optimized first, that is, only when it is ensured that the detection recipe parameters can accurately detect the defect identification results, the optimization problem of the preparation process parameters is considered, and then the dynamic self-adaptive closed-loop optimization of the wafer detection recipe parameters and the preparation process parameters is reasonably realized, so as to significantly improve the automation level and yield control ability of the wafer manufacturing process.

Description

Technical Field

[0001] Several embodiments in this specification relate to the field of semiconductor manufacturing, specifically to wafer fabrication methods, systems, electronic devices, and dielectrics with parameter closed-loop optimization. Background Technology

[0002] In recent years, as semiconductor manufacturing processes have continued to evolve towards smaller linewidths and higher integration levels, defect control during wafer fabrication has become a critical aspect. As one of the most essential quality inspection devices on the wafer manufacturing line, the wafer defect detection system plays a vital role in discovering, classifying, and statistically analyzing various wafer surface defects. Its detection results directly impact chip yield and production costs.

[0003] Traditional wafer defect detection technologies primarily rely on optical microscopy and static image analysis algorithms. By comparing differences in optical reflection or changes in surface texture, the system can detect common defects such as particles, scratches, and residues. However, with increasing process complexity and the introduction of multi-patterning processes, the types of defects on the wafer surface exhibit more complex feature distributions, and the size of defects tends to be miniaturized (nanometer-scale or even sub-nanometer-scale). This places higher demands on the sensitivity, resolution, and algorithm adaptability of the detection system.

[0004] With the rapid development of artificial intelligence (AI) and machine vision technologies, researchers have begun to apply deep learning, image feature extraction, and self-learning optimization algorithms to the field of wafer inspection. Some defect recognition models based on convolutional neural networks (CNN) or Transformers have improved the automation and accuracy of inspection to some extent. However, these methods mostly focus on the "identification stage" and have not formed a closed-loop control system of detection-feedback-optimization, thus failing to achieve automated adjustment of detection parameters and algorithm strategies. Current inspection systems mostly use fixed detection formulas and algorithm models, with manual adjustments of detection thresholds, exposure parameters, light source intensity, and image comparison strategies based on experience. This manual parameter tuning method has the following shortcomings:

[0005] The parameter optimization process relies on experience, is time-consuming, and is not repeatable.

[0006] The inability of defect feature feedback to be applied to algorithm optimization in real time leads to fluctuations in false detection or false negative rates.

[0007] Furthermore, during wafer fabrication, adjusting the fabrication process is even more crucial for preventing wafer defects. Therefore, if only the optimization of defect detection is focused on while neglecting the source control of fabrication process parameters, even if defects are accurately identified, subsequent batches of wafers will still exhibit the same quality problems. Thus, analyzing defect identification results to guide the adjustment of fabrication process parameters and reducing defect generation at the source is key to ensuring consistently stable wafer yield.

[0008] Therefore, how to construct an intelligent feedback mechanism based on defect identification results to achieve dynamic adaptive closed-loop optimization of wafer inspection formulation parameters and fabrication process parameters has become an important research direction and innovation breakthrough in this field. Summary of the Invention

[0009] This specification provides a wafer fabrication method, system, electronic device, and medium with parameter closed-loop optimization. It constructs an intelligent feedback mechanism based on defect identification results, which can reasonably realize dynamic adaptive closed-loop optimization of wafer inspection formula parameters and fabrication process parameters.

[0010] The technical solution is as follows:

[0011] Firstly, embodiments of this specification provide a wafer fabrication method with parameter closed-loop optimization, including:

[0012] S1. Use the current fabrication process parameters to fabricate the wafer to obtain the current wafer;

[0013] S2. Take an image of the current wafer obtained by the current image acquisition parameters to obtain the current initial wafer image;

[0014] S3. Process the current initial wafer image using the current image preprocessing parameters to obtain the current processed wafer image;

[0015] S4. Based on the current image differential defect recognition algorithm model, the current defect recognition intelligent model, and the current processed wafer image, obtain the current defect recognition result, which includes the current defect information and the image information corresponding to the current processed wafer image.

[0016] S5. Based on the current defect identification results, determine whether the conditions for optimizing the detection formula are met. If not, proceed to step S6; if so, proceed to step S7.

[0017] S6. Based on the current defect identification results, determine whether the preparation process optimization conditions are met. If not, return directly to step S1. If met, return to step S1 after optimizing the current preparation process parameters based on the current defect identification results.

[0018] S7. Based on the current defect identification results, optimize the current image acquisition parameters, current image preprocessing parameters, current image differential defect identification algorithm model parameters, and current defect identification intelligent model parameters, and return to step S2 after optimization.

[0019] As a preferred embodiment, the current defect information includes whether it is a defect result information, defect type information, defect morphological feature information, and defect spatial location distribution information.

[0020] As a preferred embodiment, the step of obtaining the current defect identification result based on the current image differential defect identification algorithm model, the current defect identification intelligent model, and the currently processed wafer image includes:

[0021] Based on the image differential defect recognition algorithm, adaptive threshold segmentation algorithm, and connected component analysis algorithm in the current image differential defect recognition algorithm model, the defect region in the currently processed wafer image is extracted to obtain the defect region extraction result;

[0022] Based on the current intelligent defect recognition model, the defect region extraction results are used to identify defects in the processed wafer image, and the current defect recognition results are output.

[0023] As a preferred embodiment, the step of extracting defect regions from the currently processed wafer image based on the image differential defect recognition algorithm, adaptive threshold segmentation algorithm, and connected component analysis algorithm in the current image differential defect recognition algorithm model to obtain defect region extraction results includes:

[0024] Image differential defect recognition algorithms using die-to-die or die-to-database differential are used to obtain the differential image corresponding to the currently processed wafer image;

[0025] An adaptive threshold segmentation algorithm is used to binarize the difference image to obtain a binarized image;

[0026] A connected component analysis algorithm is used to extract the defect region in the binarized image to obtain the defect region extraction result.

[0027] As a preferred approach, in steps S6 and S7, the parameters are optimized based on the current defect identification results and the Bayesian optimization algorithm or reinforcement learning model.

[0028] As a preferred approach, in steps S6 and S7, the parameters are optimized based on the current defect identification results, a pre-constructed parameter optimization rule library containing the mapping relationship between defect identification result parameters and optimization rules, and a Bayesian optimization algorithm or reinforcement learning model.

[0029] As a preferred embodiment, the optimization of parameters based on the current defect identification results, a pre-constructed parameter optimization rule base containing the mapping relationship between defect identification result parameters and optimization rules, and a Bayesian optimization algorithm or reinforcement learning model includes:

[0030] Based on the current defect identification results and a pre-built parameter optimization rule library containing the mapping relationship between defect identification result parameters and optimization rules, the first parameter optimization scheme is obtained;

[0031] Based on the current defect identification results and the Bayesian optimization algorithm or reinforcement learning model, obtain the second parameter optimization scheme;

[0032] The parameters are optimized based on the first parameter optimization scheme and the second parameter optimization scheme.

[0033] Secondly, embodiments of this specification provide a parameter-closed-loop optimized wafer fabrication system for implementing the parameter-closed-loop optimized wafer fabrication method described in the first aspect, comprising:

[0034] The wafer fabrication module uses the current fabrication process parameters to fabricate the wafer and obtain the current wafer.

[0035] The image acquisition module uses the current image acquisition parameters to capture an image of the currently prepared wafer to obtain the current initial wafer image;

[0036] The image processing module processes the current initial wafer image using the current image preprocessing parameters to obtain the current processed wafer image;

[0037] The defect identification module obtains the current defect identification result based on the current image differential defect identification algorithm model, the current defect identification intelligent model, and the current processed wafer image. The current defect identification result includes the current defect information and the image information corresponding to the current processed wafer image.

[0038] The first judgment module determines whether the conditions for optimizing the detection formula are met based on the current defect identification results.

[0039] The second judgment module determines whether the preparation process optimization conditions are met based on the current defect identification result when the current defect identification result does not meet the detection formula optimization conditions.

[0040] The first optimization module optimizes the current image acquisition parameters, current image preprocessing parameters, current image differential defect recognition algorithm model parameters, and current defect recognition intelligent model parameters based on the current defect recognition results when the current defect identification results meet the detection formula optimization conditions.

[0041] The second optimization module optimizes the current manufacturing process parameters based on the current defect identification results when the current defect identification results meet the conditions for manufacturing process optimization.

[0042] Thirdly, embodiments of this specification provide an electronic device, including a processor and a memory; the processor is connected to the memory; the memory is used to store executable program code; the processor reads the executable program code stored in the memory to run a program corresponding to the executable program code, so as to perform the steps described in the first aspect of the above embodiments.

[0043] Fourthly, embodiments of this specification provide a computer storage medium storing a plurality of instructions adapted for loading by a processor and executing the steps described in the first aspect of the above embodiments.

[0044] The beneficial effects of the technical solutions provided in some embodiments of this specification include at least the following:

[0045] An intelligent feedback mechanism based on defect identification results was constructed. After obtaining relatively accurate defect identification results through the dual defect detection path of image differential defect identification algorithm and intelligent defect identification model, the mechanism further judges whether the detection formula optimization conditions are met based on the defect identification results. If the detection formula optimization conditions are not met, the mechanism directly judges whether the wafer fabrication process needs to be optimized based on the defect identification results. If the detection formula optimization conditions are met, the wafer detection formula parameters are optimized first. That is, the optimization of the fabrication process parameters is only considered on the basis that the detection formula parameters can accurately detect the defect identification results. Thus, the dynamic adaptive closed-loop optimization of wafer detection formula parameters and fabrication process parameters is reasonably realized, which significantly improves the automation level and yield control capability of the wafer manufacturing process. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 A schematic flowchart of a wafer fabrication method with parameter closed-loop optimization according to some embodiments of the present disclosure is shown.

[0048] Figure 2 A schematic diagram of the structure of a wafer fabrication system with parameter closed-loop optimization according to some embodiments of the present disclosure is shown.

[0049] Figure 3 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown. Detailed Implementation

[0050] The technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings.

[0051] The terms "first," "second," "third," etc., in the description, claims, and accompanying drawings are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0052] The following description provides examples and does not limit the scope, applicability, or examples set forth in the claims. Changes may be made to the function and arrangement of the described elements without departing from the scope of this specification. Various processes or components may be appropriately omitted, substituted, or added to the examples. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Furthermore, features described with respect to some examples may be combined into other examples.

[0053] Figure 1 A schematic flowchart of a wafer fabrication method with parameter closed-loop optimization according to some embodiments of this disclosure is shown. It should be understood that the numbers in the flowchart do not indicate the order in which these steps are performed; some or all of these steps can be performed in parallel, or their order can be interchanged, and this disclosure does not limit this. Furthermore, Figure 1 The methods described may also include additional steps not shown and / or the steps shown may be omitted, and the scope of this disclosure is not limited in this respect.

[0054] like Figure 1 As shown, the wafer fabrication method with parameter closed-loop optimization can include at least:

[0055] S1. Use the current fabrication process parameters to fabricate the wafer to obtain the current wafer;

[0056] S2. Take an image of the current wafer obtained by the current image acquisition parameters to obtain the current initial wafer image;

[0057] S3. Process the current initial wafer image using the current image preprocessing parameters to obtain the current processed wafer image;

[0058] S4. Based on the current image differential defect recognition algorithm model, the current defect recognition intelligent model, and the current processed wafer image, obtain the current defect recognition result, which includes the current defect information and the image information corresponding to the current processed wafer image.

[0059] S5. Based on the current defect identification results, determine whether the conditions for optimizing the detection formula are met. If not, proceed to step S6; if so, proceed to step S7.

[0060] S6. Based on the current defect identification results, determine whether the preparation process optimization conditions are met. If not, return directly to step S1. If met, return to step S1 after optimizing the current preparation process parameters based on the current defect identification results.

[0061] S7. Based on the current defect identification results, optimize the current image acquisition parameters, current image preprocessing parameters, current image differential defect identification algorithm model parameters, and current defect identification intelligent model parameters, and return to step S2 after optimization.

[0062] In the embodiments of this specification, an intelligent feedback mechanism based on defect identification results is constructed. After obtaining the defect identification result relatively accurately through the dual defect detection path of image differential defect identification algorithm and defect identification intelligent model, the mechanism further determines whether the detection formula optimization conditions are met based on the defect identification result. If the detection formula optimization conditions are not met, the mechanism directly determines whether the wafer fabrication process needs to be optimized based on the defect identification result. If the detection formula optimization conditions are met, the wafer detection formula parameters are optimized first. That is, the optimization of the fabrication process parameters is only considered on the basis of ensuring that the detection formula parameters can accurately detect the defect identification result. This reasonably realizes the dynamic adaptive closed-loop optimization of wafer detection formula parameters and fabrication process parameters, so as to significantly improve the automation level and yield control capability of the wafer manufacturing process.

[0063] Specifically, step S1 includes:

[0064] After the equipment is ready, the wafer is photographed according to the current image acquisition parameters to acquire a high-resolution initial wafer image. The image acquisition parameters may include, but are not limited to, exposure time parameters (how long the shutter is open), gain parameters (signal amplification factor), and light intensity parameters (light source brightness).

[0065] The image processing involved in step S2 may include, but is not limited to, black level / white level correction, illumination normalization, image enhancement and denoising, thereby outputting a processed wafer image, which is a high-quality image with uniform brightness and no noise.

[0066] Therefore, it can be understood that the image preprocessing parameters mentioned in step S2 may include, but are not limited to, the parameters involved in black level / white level correction, illumination normalization, image enhancement and denoising operations.

[0067] In step S4, a dual-path detection design is adopted to improve the accuracy of defect identification results. The process of obtaining the current defect identification result based on the current image differential defect identification algorithm model, the current intelligent defect identification model, and the currently processed wafer image includes:

[0068] Differential Enhancement Path: Based on the current image differential defect recognition algorithm model (note: die-to-die or die-to-database differential can be used), adaptive threshold segmentation algorithm, and connected component analysis algorithm, the defect region in the currently processed wafer image is extracted to obtain the defect region extraction result (note: the image differential defect recognition algorithm model parameters include the parameters involved in the image differential defect recognition algorithm, adaptive threshold segmentation algorithm, and connected component analysis algorithm).

[0069] Deep learning path: Based on the current defect recognition intelligent model (e.g., a CNN network, whose backbone can be ResNet50+FPN or U-Net++) and the defect region extraction results obtained from the differential enhancement path, perform defect recognition on the current processed wafer image and output the current defect recognition result (Note: the parameters of the defect recognition intelligent model include the parameters involved in the model).

[0070] In some embodiments of this specification, the extraction of defect regions from the currently processed wafer image based on the image differential defect recognition algorithm, adaptive threshold segmentation algorithm, and connected component analysis algorithm in the current image differential defect recognition algorithm model to obtain defect region extraction results includes:

[0071] Image differential defect recognition algorithms using die-to-die or die-to-database differential are used to obtain the differential image corresponding to the currently processed wafer image;

[0072] An adaptive threshold segmentation algorithm is used to binarize the difference image to obtain a binarized image;

[0073] A connected component analysis algorithm is used to extract the defect region in the binarized image to obtain the defect region extraction result.

[0074] In some embodiments, the image processing in step S2 may also include a subpixel-level fine alignment operation to output a mapping matrix from pixels to physical coordinates. This allows the system to know which real physical coordinate on the wafer corresponds to each pixel in the image. Consequently, the defect identification of the differential enhancement path in step S4 can be performed with reference to this mapping matrix, thereby improving the accuracy of the defect identification results.

[0075] Understandably, the differential enhancement path only identifies candidate defect regions in the image. The deep learning path, however, needs to output not only pixel-level defect probability maps and candidate defect regions, but also defect type information, defect morphological feature information, defect spatial distribution information, and image information corresponding to the currently processed wafer image. This image information may include, but is not limited to, one or more of the following: image contrast, signal-to-noise ratio (SNR), mean grayscale value, root mean square error (RMSE), sharpness, and brightness distribution histogram.

[0076] The determination of whether the detection formula optimization conditions and the preparation process optimization conditions are met can be performed by a pre-trained intelligent model for optimization judgment. For training the intelligent model for optimization judgment, a training dataset is first required. The training dataset includes multiple training samples. Each training sample includes corresponding defect information, image information, information on whether the detection formula optimization conditions and the preparation process optimization conditions are met. Then, an intelligent model for optimization judgment can be trained using the training dataset. It can output whether the detection formula optimization conditions and the preparation process optimization conditions are met based on the input defect information and image information.

[0077] Understandably, the current defect identification results may also include detection environment parameters (such as temperature and humidity), the current wafer fabrication process stage, relevant machine numbers, etc., which can be set according to the actual situation and needs.

[0078] Understandably, the current defect identification results can also include defect statistical parameters obtained through statistics, such as the overall defect rate parameter, defect classification probability parameter, etc., to provide more reference information when making subsequent judgments on whether parameter optimization is needed and obtaining parameter optimization schemes.

[0079] In some embodiments of this specification, in steps S6 and S7, the parameters are optimized based on the current defect identification result and the Bayesian optimization algorithm or reinforcement learning model (Note: that is, one of the Bayesian optimization algorithm or reinforcement learning model is selected to optimize the parameters).

[0080] In some embodiments of this specification, steps S6 and S7 are performed to optimize the parameters based on the current defect identification result, a pre-built parameter optimization rule library containing the mapping relationship between defect identification result parameters and optimization rules, and a Bayesian optimization algorithm or reinforcement learning model.

[0081] The optimization of parameters based on the current defect identification results, a pre-constructed parameter optimization rule base containing the mapping relationship between defect identification result parameters and optimization rules, and a Bayesian optimization algorithm or reinforcement learning model includes:

[0082] Based on the current defect identification results and a pre-built parameter optimization rule library containing the mapping relationship between defect identification result parameters and optimization rules, the first parameter optimization scheme is obtained;

[0083] Based on the current defect identification results and the Bayesian optimization algorithm or reinforcement learning model, obtain the second parameter optimization scheme;

[0084] The parameters are optimized based on the first parameter optimization scheme and the second parameter optimization scheme.

[0085] The parameter optimization rule base, which contains the mapping relationship between defect identification result parameters and optimization rules, can be set based on historical data and expert experience (note: this parameter optimization rule base can also be updated in real time during wafer fabrication). Understandably, in some embodiments of this specification, a two-stage optimization approach of fast rule candidate + AI intelligent calculation is adopted for parameter optimization. AI intelligent calculation can output parameter optimization schemes based on the input defect identification result parameters, but its output may have uncontrollable risks or lack physical interpretability; therefore, fast rule candidate is used as a safety fallback. After obtaining the first parameter optimization scheme and the second parameter optimization scheme, the confidence level and estimated benefit (e.g., the expected reduction in defect rate) of each can be further obtained. Furthermore, based on the confidence level and estimated benefit of the first and second parameter optimization schemes, the final target parameter optimization scheme can be determined, and the parameters can be optimized based on the target parameter optimization scheme.

[0086] Regarding the acquisition of confidence level:

[0087] In AI intelligent computing: it originates from the algorithm model itself (such as the variance of the posterior distribution in Bayesian optimization, or the action probability of a reinforcement learning agent). The smaller the variance and the higher the probability, the more certain the model is about the solution, and the higher the confidence level.

[0088] In the fast rule candidate: based on the degree of matching between the current defect identification result and the corresponding defect identification result parameter of the rule, the higher the matching degree, the higher the confidence degree.

[0089] Regarding the acquisition of estimated returns:

[0090] In AI intelligent computing: Proxy models or Q networks are used to directly predict estimated revenue.

[0091] In the fast rule candidate: the results are obtained based on the historical returns of the parameter optimization rule.

[0092] In some embodiments of this specification, the first parameter optimization scheme may include multiple parameter optimization sub-schemes. Therefore, it is necessary to obtain the confidence level and estimated benefit corresponding to each of the multiple parameter optimization sub-schemes, and determine the final target parameter optimization scheme based on the second parameter optimization scheme and the confidence level and estimated benefit corresponding to each of the multiple parameter optimization sub-schemes.

[0093] In some embodiments of this specification, after obtaining the target parameter optimization scheme, a security verification can be further performed on the target parameter optimization scheme, which may include, but is not limited to, the following security verification operations:

[0094] Verification Operation 1: Device security boundaries (whether the parameters exceed hardware limits);

[0095] Verification Operation 2: Simulation Prediction (using fast image simulation or historical data to simulate results and estimate the risk of changes).

[0096] Figure 2 Schematic diagrams of the structure of a wafer fabrication system with parameter closed-loop optimization according to some embodiments of this disclosure are shown. The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of the parameter closed-loop optimization wafer fabrication system are basically similar to the embodiments of the parameter closed-loop optimization wafer fabrication method, so the description is relatively simple, and relevant parts can be referred to the descriptions of the embodiments of the parameter closed-loop optimization wafer fabrication method.

[0097] like Figure 2 As shown, a wafer fabrication system with parameter closed-loop optimization can include at least:

[0098] The wafer fabrication module uses the current fabrication process parameters to fabricate the wafer and obtain the current wafer.

[0099] The image acquisition module uses the current image acquisition parameters to capture an image of the currently prepared wafer to obtain the current initial wafer image;

[0100] The image processing module processes the current initial wafer image using the current image preprocessing parameters to obtain the current processed wafer image;

[0101] The defect identification module obtains the current defect identification result based on the current image differential defect identification algorithm model, the current defect identification intelligent model, and the current processed wafer image. The current defect identification result includes the current defect information and the image information corresponding to the current processed wafer image.

[0102] The first judgment module determines whether the conditions for optimizing the detection formula are met based on the current defect identification results.

[0103] The second judgment module determines whether the preparation process optimization conditions are met based on the current defect identification result when the current defect identification result does not meet the detection formula optimization conditions.

[0104] The first optimization module optimizes the current image acquisition parameters, current image preprocessing parameters, current image differential defect recognition algorithm model parameters, and current defect recognition intelligent model parameters based on the current defect recognition results when the current defect identification results meet the detection formula optimization conditions.

[0105] The second optimization module optimizes the current manufacturing process parameters based on the current defect identification results when the current defect identification results meet the conditions for manufacturing process optimization.

[0106] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this specification are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in or transmitted through a computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium accessible to a computer or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., Digital Versatile Discs (DVDs)), or semiconductor media (e.g., Solid State Disks (SSDs)).

[0107] Figure 3 A block diagram of an electronic device 300 that can implement various embodiments of the present disclosure is shown. For example... Figure 3 As shown, the electronic device 300 includes a processor 310, a disk drive 320, an input / output interface 330, a network interface 340, and a memory 350. The processor 310, disk drive 320, input / output interface 330, network interface 340, and memory 350 can communicate with each other via a communication bus 360.

[0108] The processor 310 can be implemented using a general-purpose CPU, microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits to execute relevant programs in order to implement the technical solution provided in this application.

[0109] The memory 350 can be implemented in the form of ROM (Read Only Memory), RAM (Read Access Memory), static memory, dynamic storage devices, etc. The memory 350 can store the operating system 351 used to control the operation of the electronic device 300, and the basic input / output system (BIOS) 352 used to control the low-level operations of the electronic device 300. Additionally, it can store a web browser 353, a data storage management system 354, etc. In summary, when the technical solution provided in this application is implemented through software or firmware, the relevant program code is stored in the memory 350 and is called and executed by the processor 310.

[0110] Input / output interface 330 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components in the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touch screens, microphones, various sensors, etc., and output devices may include displays, speakers, vibrators, indicator lights, etc.

[0111] Network interface 340 is used to connect a communication module (not shown in the figure) to enable communication and interaction between the device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0112] Bus 360 includes a pathway for transmitting information between various components of the device, such as processor 310, disk drive 320, input / input interface 330, network interface 340, and memory 350.

[0113] It should be noted that although the above-described device only shows the processor 310, disk drive 320, input / output interface 330, network interface 340, memory 350, bus 360, etc., in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the method of this application, and does not necessarily include all the components shown in the figures.

[0114] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0115] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing. Furthermore, although operations are depicted in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the foregoing discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0116] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A wafer fabrication method with parameter closed-loop optimization, characterized in that, include: S1. Use the current fabrication process parameters to fabricate the wafer to obtain the current wafer; S2. Take an image of the current wafer obtained by the current image acquisition parameters to obtain the current initial wafer image; S3. Process the current initial wafer image using the current image preprocessing parameters to obtain the current processed wafer image; S4. Based on the current image differential defect recognition algorithm model, the current defect recognition intelligent model, and the current processed wafer image, obtain the current defect recognition result, which includes the current defect information and the image information corresponding to the current processed wafer image. S5. Based on the current defect identification results, determine whether the conditions for optimizing the detection formula are met. If not, proceed to step S6; if so, proceed to step S7. S6. Based on the current defect identification results, determine whether the preparation process optimization conditions are met. If not, return directly to step S1. If they are met, return to step S1 after optimizing the current preparation process parameters based on the current defect identification results. S7. Based on the current defect identification results, optimize the current image acquisition parameters, current image preprocessing parameters, current image differential defect identification algorithm model parameters, and current defect identification intelligent model parameters, and return to step S2 after optimization.

2. The wafer fabrication method with parameter closed-loop optimization according to claim 1, characterized in that, The current defect information includes whether it is a defect result, defect type information, defect morphological feature information, and defect spatial location distribution information.

3. The wafer fabrication method with parameter closed-loop optimization according to claim 2, characterized in that, The process of obtaining the current defect identification result based on the current image differential defect identification algorithm model, the current defect identification intelligent model, and the currently processed wafer image includes: Based on the image differential defect recognition algorithm, adaptive threshold segmentation algorithm, and connected component analysis algorithm in the current image differential defect recognition algorithm model, the defect region in the currently processed wafer image is extracted to obtain the defect region extraction result; Based on the current intelligent defect recognition model, the defect region extraction results and the current processed wafer image are used to output the current defect recognition results.

4. The wafer fabrication method with parameter closed-loop optimization according to claim 3, characterized in that, The image differential defect recognition algorithm, adaptive threshold segmentation algorithm, and connected component analysis algorithm in the current image differential defect recognition algorithm model are used to extract defect regions in the currently processed wafer image to obtain defect region extraction results, including: Image differential defect recognition algorithms using die-to-die or die-to-database differential are used to obtain the differential image corresponding to the currently processed wafer image; An adaptive threshold segmentation algorithm is used to binarize the difference image to obtain a binarized image; A connected component analysis algorithm is used to extract the defect region in the binarized image to obtain the defect region extraction result.

5. The wafer fabrication method with parameter closed-loop optimization according to claim 1, characterized in that, In steps S6 and S7, the parameters are optimized based on the current defect identification results and the Bayesian optimization algorithm or reinforcement learning model.

6. The wafer fabrication method with parameter closed-loop optimization according to claim 5, characterized in that, In steps S6 and S7, the parameters are optimized based on the current defect identification results, a pre-built parameter optimization rule library containing the mapping relationship between defect identification result parameters and optimization rules, and a Bayesian optimization algorithm or reinforcement learning model.

7. The wafer fabrication method with parameter closed-loop optimization according to claim 6, characterized in that, The optimization of parameters based on the current defect identification results, a pre-constructed parameter optimization rule base containing the mapping relationship between defect identification result parameters and optimization rules, and a Bayesian optimization algorithm or reinforcement learning model includes: Based on the current defect identification results and a pre-built parameter optimization rule library containing the mapping relationship between defect identification result parameters and optimization rules, the first parameter optimization scheme is obtained; Based on the current defect identification results and the Bayesian optimization algorithm or reinforcement learning model, obtain the second parameter optimization scheme; The parameters are optimized based on the first parameter optimization scheme and the second parameter optimization scheme.

8. A parameter-closed-loop optimized wafer fabrication system, based on the parameter-closed-loop optimized wafer fabrication method according to any one of claims 1 to 7, characterized in that, include: The wafer fabrication module uses the current fabrication process parameters to fabricate the wafer and obtain the current wafer. The image acquisition module uses the current image acquisition parameters to capture an image of the currently prepared wafer to obtain the current initial wafer image; The image processing module processes the current initial wafer image using the current image preprocessing parameters to obtain the current processed wafer image; The defect identification module obtains the current defect identification result based on the current image differential defect identification algorithm model, the current defect identification intelligent model, and the current processed wafer image. The current defect identification result includes the current defect information and the image information corresponding to the current processed wafer image. The first judgment module determines whether the conditions for optimizing the detection formula are met based on the current defect identification results. The second judgment module determines whether the preparation process optimization conditions are met based on the current defect identification result when the current defect identification result does not meet the detection formula optimization conditions. The first optimization module optimizes the current image acquisition parameters, current image preprocessing parameters, current image differential defect recognition algorithm model parameters, and current defect recognition intelligent model parameters based on the current defect recognition results when the current defect identification results meet the detection formula optimization conditions. The second optimization module optimizes the current manufacturing process parameters based on the current defect identification results when the current defect identification results meet the conditions for manufacturing process optimization.

9. An electronic device, characterized in that, include: One or more processors, and A memory associated with the one or more processors, the memory being used to store program instructions that, when read and executed by the one or more processors, perform the steps of the method according to any one of claims 1-7.

10. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 1-7.

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