Mask assembly, method of manufacturing the same, and method of manufacturing semiconductor device

Abstract

The application discloses a mask assembly and a preparation method thereof, and a preparation method of a semiconductor device, the mask assembly being used for being in contact with a film layer to be annealed in an annealing process, the mask assembly comprising an antireflection layer and an antireflection functional layer, the antireflection layer comprising at least one first dielectric layer; the antireflection functional layer is stacked with the antireflection layer and comprises a plurality of second dielectric layers stacked along the thickness direction of the antireflection layer, the refractive indexes of adjacent second dielectric layers are different, the antireflection functional layer comprises an antireflection functional part and a first opening part, and the first opening part exposes the antireflection layer; wherein the mask assembly comprises a strong annealing area and a weak annealing area, the strong annealing area is opposite to the first opening part and the antireflection layer exposed through the first opening part, and the weak annealing area is opposite to the part of the antireflection functional part and the antireflection layer stacked together. In the mask assembly provided by the application, the annealing areas with different annealing intensity requirements in the film layer to be annealed can achieve uniform annealing effect, and the problems of underannealing of the annealing area and overannealing of the nonannealing area are improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and particularly relates to a mask assembly and its fabrication method, and a semiconductor device fabrication method. Background Technology

[0002] Currently, with the miniaturization of transistor feature sizes, laser processing of patterned films with high aspect ratio trench structures presents challenges due to the height difference in the film layer caused by the patterning effect, leading to the coexistence of insufficient annealing and film layer ablation. Taking DRAM as an example, when using existing laser technology to irradiate the annealed film layer with a uniform laser beam, the film layer in the memory array area is thicker and requires a higher light intensity, making it a strong annealing region; the film layer in the peripheral circuit area is thinner, and irradiating with the same light intensity will cause film layer ablation, making it a weak annealing region. After annealing, the annealed film layer exhibits the problem of under-annealing in the annealed areas and over-annealing in the non-annealed areas, which not only affects subsequent processing but also significantly impacts device yield. This coexistence of under-annealing and over-annealing results in an excessively small process window. Summary of the Invention

[0003] The purpose of this application is to at least improve the uniformity of patterned films in laser processing and increase the process window. This purpose is achieved through the following technical solution:

[0004] Taking laser annealing as an example, the first aspect of this application proposes a mask assembly for contacting the film layer to be annealed during the annealing process, the mask assembly comprising:

[0005] An antireflective layer, comprising at least one first dielectric layer;

[0006] An anti-reflective functional layer is stacked with the anti-reflective layer and includes multiple layers of second dielectric layers stacked along the thickness direction of the anti-reflective layer. Adjacent second dielectric layers have different refractive indices. The anti-reflective functional layer includes an anti-reflective functional portion and a first opening portion, the first opening portion exposing the anti-reflective layer.

[0007] The mask assembly includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening and the antireflection layer exposed through the first opening. The weak annealing region is opposite to the antireflection function part and the portion of the antireflection layer that are stacked together.

[0008] The mask assembly provided in this application is used to contact the film layer to be annealed during the annealing process and to regionally control the laser intensity acting on the film layer. Specifically, the mask assembly provided in this application includes a stacked antireflection layer and an antireflection layer. The antireflection layer includes at least one first dielectric layer, which has an antireflection effect on light, specifically by reducing the reflection of the annealing laser beam. The antireflection layer is stacked with the antireflection layer. The antireflection layer includes multiple layers of second dielectric layers stacked along the thickness direction of the mask assembly. By stacking second dielectric layers with alternating high and low refractive indices, the reflected light from the annealing laser beam passing through the composite antireflection layer and the antireflection layer can interfere and superimpose, thereby enhancing reflection and reducing the transmittance of the annealing laser beam. The antireflective layer includes an antireflective functional portion and a first opening. The first opening exposes the antireflective layer, resulting in the first opening region containing only the antireflective layer. This region has high transmittance to the annealing laser beam, thus serving as a strong annealing region suitable for annealing areas within the film layer requiring strong annealing laser beam intensity. The region where the antireflective layer and the antireflective functional portion are stacked along the thickness direction of the mask assembly exhibit strong reflection of the annealing laser beam, meaning this region has low transmittance to the annealing laser beam. This region serves as a weak annealing region suitable for annealing non-annealed areas or areas with weaker annealing laser beam intensity requirements within the film layer. The mask assembly provided in this application can achieve a uniform annealing effect in annealed areas with different annealing intensity requirements within the film layer, improving the problems of under-annealing in annealed areas and over-annealing in non-annealed areas.

[0009] In some embodiments of this application, the refractive index of the first dielectric layer ranges from 1.1 to 2.5; and / or,

[0010] The optical thickness range of the first dielectric layer is k1λ, 0≤k1≤1, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed; and / or,

[0011] The extinction coefficient of the first dielectric layer ranges from 0 to 0.1; and / or,

[0012] The refractive index of the second dielectric layer is in the range of 1.3-3.0; and / or,

[0013] The absolute value of the refractive index difference between adjacent second dielectric layers ranges from 0.3 to 1.3; and / or,

[0014] The optical thickness range of the second dielectric layer is k2λ, 0≤k2≤1, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed; and / or,

[0015] The extinction coefficient of the second dielectric layer ranges from 0 to 0.1.

[0016] In some embodiments of this application, a light flux adjustment layer is further included. The light flux adjustment layer is located on the side of the antireflective functional layer away from the antireflective layer. The light flux adjustment layer has a second opening that communicates with the first opening. The refractive index of the light flux adjustment layer is greater than the refractive index of the second dielectric layer.

[0017] In some embodiments of this application, the refractive index of the luminous flux adjustment layer is in the range of 2.0-3.5; and / or,

[0018] The optical thickness range of the light flux adjustment layer is k3λ, 0≤k3≤0.25, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed; and / or,

[0019] The extinction coefficient of the light flux adjustment layer ranges from 0 to 0.1.

[0020] In some embodiments of this application, the etching rate selection ratio between the light flux adjustment layer and the second dielectric layer is less than 1.

[0021] In some embodiments of this application, a first insulating layer is also included, which is located on the side of the antireflective layer opposite to the antireflective functional layer, and the first insulating layer includes at least one first sublayer.

[0022] In some embodiments of this application, a second insulating layer is further included, which is located between the antireflective layer and the antireflective functional layer. The second insulating layer includes a third opening communicating with the first opening, and the second insulating layer includes at least one second sublayer.

[0023] In some embodiments of this application, the etching rate ratio between the first dielectric layer and the second insulating layer is less than 1.

[0024] In some embodiments of this application, a luminous flux adjustment layer is further included. The luminous flux adjustment layer is located on the side of the antireflective functional layer away from the antireflective layer. The luminous flux adjustment layer has a second opening that communicates with the first opening. The refractive index of the luminous flux adjustment layer is greater than the refractive index of the second dielectric layer. The second opening communicates with the third opening. The etching rate selectivity ratio between the luminous flux adjustment layer and the second insulating layer is less than 1.

[0025] The second aspect of this application also provides a method for fabricating any of the mask components provided in the first aspect of this application, comprising:

[0026] An antireflection layer is formed, the antireflection layer comprising at least one first dielectric layer;

[0027] An anti-reflective functional layer is formed on one side of the anti-reflection layer. The anti-reflective functional layer includes multiple layers of second dielectric layers stacked along the thickness direction of the anti-reflection layer. Adjacent second dielectric layers have different refractive indices. The anti-reflective functional layer includes an anti-reflective functional portion and a first opening. The first opening exposes the anti-reflection layer, so that the mask assembly includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening and the anti-reflection layer exposed through the first opening. The weak annealing region is opposite to the portion of the anti-reflective functional portion and the anti-reflection layer stacked together.

[0028] A second aspect of this application also provides a method for fabricating a semiconductor device, comprising:

[0029] A semiconductor structure layer is provided, the semiconductor structure layer including a first surface and a trench structure formed by recesses in the first surface;

[0030] An annealing film layer is formed on one side of the first surface, wherein part of the annealing film layer is located on the first surface and part is located within the trench structure;

[0031] An antireflection layer is formed on the side of the film layer to be annealed away from the semiconductor structure layer, and the antireflection layer includes at least one first dielectric layer;

[0032] An anti-reflection functional layer is formed on the side of the anti-reflection layer opposite to the film layer to be annealed. The anti-reflection functional layer includes multiple layers of second dielectric layers stacked along the thickness direction of the anti-reflection layer. Adjacent second dielectric layers have different refractive indices. A first opening is formed in the anti-reflection functional layer so that the anti-reflection functional layer includes an anti-reflection functional portion and the first opening. The first opening exposes the anti-reflection layer to form a mask assembly. The mask assembly includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening and the anti-reflection layer exposed through the first opening. The weak annealing region is opposite to the portion of the anti-reflection functional portion and the anti-reflection layer stacked together.

[0033] In some embodiments of this application, the step of forming the film layer to be annealed on one side of the first surface and the step of forming an antireflection layer on the side of the film layer to be annealed away from the semiconductor structure layer further include:

[0034] A first insulating layer is formed on the surface of the film layer to be annealed, on the side opposite to the semiconductor structure layer.

[0035] In some embodiments of this application, the step of forming an antireflection layer on the side of the film layer to be annealed away from the semiconductor structure layer and the step of forming an antireflection functional layer on the side of the antireflection layer away from the film layer to be annealed further include:

[0036] A second insulating layer is formed on the surface of the antireflection layer opposite to the semiconductor structure layer. The second insulating layer includes a third opening that exposes the antireflection layer.

[0037] The first opening is connected to the third opening.

[0038] In some embodiments of this application, after the step of forming an antireflective functional layer on the side of the antireflective layer opposite to the film layer to be annealed, the method further includes:

[0039] A light flux adjustment layer is formed on the side of the antireflective functional layer away from the film layer to be annealed. The light flux adjustment layer is located on the side of the antireflective functional layer away from the antireflective layer. The light flux adjustment layer has a second opening that communicates with the first opening. The refractive index of the light flux adjustment layer is greater than the refractive index of the second dielectric layer adjacent to the light flux adjustment layer in the antireflective functional layer. Attached Figure Description

[0040] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0041] Figure 1 This is a schematic diagram of the structure of a mask assembly provided in this application;

[0042] Figure 2 This is a schematic diagram of another mask assembly provided in this application;

[0043] Figure 3 This is a schematic diagram of another mask assembly provided in this application;

[0044] Figure 4 This is a schematic diagram of another mask assembly provided in this application;

[0045] Figure 5 This is a flowchart of a mask assembly fabrication method provided in this application;

[0046] Figure 6 This is a flowchart of a method for fabricating a semiconductor device provided in this application;

[0047] Figures 7 to 18 This is a schematic diagram of the film structure in a method for fabricating a semiconductor device provided in this application;

[0048] Figure 19This is a schematic diagram showing the relationship between the optical thickness ratio of the first insulating layer and the first dielectric layer at position A and the transmittance of a mask assembly provided in this application during application.

[0049] Figure 20 This is a schematic diagram showing the relationship between the optical thickness of the light flux adjustment layer at position B and its transmittance, absorptivity, and reflectivity during the application of a mask assembly provided in this application.

[0050] The attached figures are labeled as follows:

[0051] 1. Mask assembly; 11. Antireflection layer; 111. First dielectric layer; 12. Antireflection layer; 120. First opening; 121. Second dielectric layer; 122. Antireflection section; 13. Luminous flux adjustment layer; 130. Second opening; 14. First insulating layer; 15. Second insulating layer; 150. Third opening; 2. Semiconductor structure layer; 20. First surface; 21. Trench structure; 3. Film layer to be annealed; 4. Second dielectric material layer; 5. Luminous flux adjustment material layer; 6. Second insulating material layer; 7. Etching sacrificial layer; 8. Photoresist layer; 81. Body section; 82. Opening. Detailed Implementation

[0052] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0053] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0054] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0055] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented as "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0056] Research has shown that as semiconductor device manufacturing processes have advanced, the structure of transistors has evolved from traditional planar structures to vertical channels and gate stacking due to limitations in transistor feature size. This has led to the introduction of new annealing processes for high aspect ratio trench structures.

[0057] Whether using traditional overall annealing or emerging localized annealing with laser beams, or whether employing solid-state non-melting annealing or liquid-state molten recrystallization annealing, the patterned trench structure results in significant height differences in the film to be annealed filling the trenches. With existing laser technology, using a uniform laser beam to irradiate the film results in insufficient energy absorption within the trench area due to the film's thickness, leading to incomplete annealing – a process known as under-annealing. Meanwhile, the areas surrounding the trench region are weakly annealed, absorbing excessive energy and causing ablation – a process known as over-annealing. This not only affects subsequent processing but also significantly impacts device yield. This coexistence of under-annealing and over-annealing severely affects the yield of the annealed film.

[0058] Furthermore, the choice of annealing laser is greatly limited, resulting in a small process window. Due to the deep trench area and the need to accommodate the annealing effect of the film layer to be annealed located in the outer periphery of the trench, it is not conducive to the application of laser technology in annealing processes where under-annealing and over-annealing coexist.

[0059] like Figure 1 As shown, according to an embodiment of this application, a mask assembly 1 is proposed for contacting the film layer to be annealed during the annealing process. The mask assembly 1 includes an antireflection layer 11 and an antireflective layer 12. The antireflection layer 11 includes at least one first dielectric layer 111. The antireflective layer 12 is stacked with the antireflection layer 11 and includes multiple layers of second dielectric layers 121 stacked along the thickness direction of the antireflection layer 11. Adjacent second dielectric layers 121 have different refractive indices. The antireflective layer 12 includes an antireflective portion 122 and a first opening 120, the first opening 120 exposing the antireflection layer 11. The mask assembly 1 includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening 120 and the antireflection layer 11 exposed through the first opening 120, and the weak annealing region is opposite to the portion of the antireflective portion 122 and the stacked antireflection layer.

[0060] Specifically, the mask assembly 1 includes a strong annealing region opposite to the first opening 120 and a weak annealing region opposite to the antireflection function 122. The strong annealing region includes only the antireflection layer 11, which has high transmittance for the annealed laser light. Specifically, the inner film layer of the antireflection layer 11 and the medium adjacent to the upper and lower surfaces of the antireflection layer 11 interact, causing the reflected light after the annealed laser passes through the antireflection layer 11 to interfere and cancel each other out, thereby achieving the antireflection effect. The weak annealing region (the annealing effect of the weak annealing region is lower than that of the strong annealing region, and the weak annealing region may not be annealed) includes the antireflection function 122 and the antireflection layer 11 stacked together. The annealed laser interferes and superimposes with the reflected light after passing through the stacked antireflection function 122 and the antireflection layer 11, thereby achieving enhanced reflection.

[0061] Specifically, the reflective enhancement layer 12 can have reflective enhancement function on its own, or the reflective enhancement layer 12 can be the main film layer used to make the weak annealing zone reflective, and the reflective enhancement layer 12 can have reflective enhancement function when superimposed with other film layers (including but not limited to the antireflection layer 11) in the mask assembly.

[0062] The mask assembly 1 provided in this application is used to contact the film layer 3 to be annealed during the annealing process, and to regionally control the laser intensity acting on the film layer 3. Specifically, the mask assembly 1 provided in this application includes a stacked antireflection layer 11 and an antireflection layer 12. The antireflection layer 11 includes at least one first dielectric layer 111, which has an antireflection effect on light, specifically by reducing the reflection of the annealing laser beam. The antireflection layer 12 is stacked with the antireflection layer 11. The antireflection layer 12 includes multiple layers of second dielectric layers 121 stacked along the thickness direction of the mask assembly 1. By stacking second dielectric layers 121 with alternating high and low refractive indices, the reflected light after the annealing laser beam passes through the composite antireflection layer 11 and the antireflection layer 12 can interfere and superimpose, thereby enhancing reflection and reducing the transmittance of the annealing laser beam. The reflective layer 12 includes a reflective portion 122 and a first opening 120. The first opening 120 exposes the antireflective layer 11, so that only the antireflective layer 11 exists in the area of ​​the first opening 120. This area has high transmittance to the annealing laser beam, thus serving as a strong annealing area, which can be used for annealing areas in the film layer 3 that require strong annealing laser beams. The area where the antireflective layer 11 and the reflective portion 122 are stacked along the thickness direction of the mask assembly 1 has a strong reflection effect on the annealing laser beam, meaning that this area has low transmittance to the annealing laser beam, thus serving as a weak annealing area, which can be used for annealing non-annealed areas or areas in the film layer 3 that require weak annealing laser beams. The mask assembly 1 provided in this application can achieve a uniform annealing effect in annealed areas with different annealing intensity requirements in the film layer 3, improving the problems of under-annealing in annealed areas and over-annealing in non-annealed areas.

[0063] The mask assembly 1 provided in this application can solve the problems of insufficient annealing in the trench structure 21 area and over-annealing in other areas when the film layer to be annealed covers a trench structure 21 with a high aspect ratio. Simultaneously, since the weak annealing area has low transmittance to the annealing laser, a stronger laser can be used to anneal the film layer to be annealed without damaging the weak annealing area. This improves the annealing effect on the strong annealing area and provides a wide process window, allowing the use of annealing lasers with different wavelength ranges. This mask assembly 1 can be applied to laser processing of high-depth, wide-aperture structures. In the mask assembly 1 provided in this application, during use, the antireflection layer 11 can be located on the side of the antireflection functional layer 12 facing towards or away from the film layer to be annealed; this application does not impose any particular limitation on this. When the antireflection layer 11 is located on the side of the antireflection layer 12 away from the film layer to be annealed, the portion of the antireflection layer 11 opposite to the first opening 120 enters the inside of the first opening 120 and directly contacts the film layer to be annealed, thereby improving the antireflection effect and thus increasing the utilization rate of the annealing laser. This application mainly uses the example of the antireflection layer 11 being located on the side of the antireflection layer 12 closer to the film layer to be annealed for illustration.

[0064] In one feasible implementation, the refractive index of the first dielectric layer 111 is in the range of 1.1-2.5.

[0065] In the above embodiments, in order to maximize the energy utilization and light transmittance of the annealing laser, the first dielectric layer 111 in the antireflection layer 11 has a low refractive index, which ranges from 1.1 to 2.5.

[0066] Specifically, the refractive index of the first dielectric layer 111 can be 1.1, 1.3, 1.4, 1.9, 2.1, 2.3, 2.5, etc.

[0067] In one feasible implementation, the material of the first dielectric layer 111 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, titanium nitride, and tantalum nitride.

[0068] In the above embodiments, the antireflection layer 11 includes one or more first dielectric layers 111. When multiple first dielectric layers 111 are included, the materials of the different first dielectric layers 111 may be the same or different.

[0069] In one feasible implementation, the optical thickness of the first dielectric layer 111 is in the range of k1λ, 0≤k1≤1, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed.

[0070] Preferably, the range of k1 is 0-0.25.

[0071] In one feasible implementation, the extinction coefficient of the first dielectric layer 111 is in the range of 0-0.1.

[0072] The thermal effect generated by excessive absorption of annealing laser by the antireflection layer 11 can easily cause damage to the mask assembly 1 by the annealing laser beam spot. In order to reduce the absorption of the annealing laser beam by the antireflection layer 11 in the mask assembly 1, the first dielectric layer 111 has a low extinction coefficient for the annealing laser, thereby improving the yield of the antireflection layer 11.

[0073] Specifically, the smaller the extinction coefficient is in the range of 0 to 0.1, the better.

[0074] In one feasible implementation, the refractive index of the second dielectric layer 121 is in the range of 1.3-3.0.

[0075] The second dielectric layer 121 has multiple layers, such as... Figure 1As shown, it includes two second dielectric layers 121. The refractive indices of adjacent second dielectric layers 121 are different. By stacking second dielectric layers 121 with alternating high and low refractive indices, the reflected light from the annealed laser beam passing through multiple layers of second dielectric layers 121 and the antireflection layer 11 stacked with multiple layers of second dielectric layers 121 can interfere and superimpose, thereby achieving the effect of enhanced reflection and reduced transmission, and thus reducing the transmittance of the annealed laser beam.

[0076] Specifically, in order to minimize the light transmittance of the annealing laser, the second dielectric layer 121 has a higher refractive index compared to the first dielectric layer 111. The refractive index of the second dielectric layer 121 can be 1.3, 1.4, 1.5, 1.9, 2.6, 2.8, 3.0, etc.

[0077] In one feasible implementation, the absolute value of the refractive index difference between adjacent second dielectric layers 121 ranges from 0.3 to 1.3.

[0078] Specifically, the refractive index of at least a portion of the second dielectric layer 121 may gradually increase or decrease along the direction away from the antireflection layer 11. Alternatively, the refractive indices of the multiple second dielectric layers 121 may be alternately set at high and low along the direction away from the antireflection layer 11.

[0079] Specifically, the absolute value of the refractive index difference between adjacent second dielectric layers 121 can be 0.3, 0.4, 0.5, 0.7, 0.9, 1.0, 1.2 or 1.3.

[0080] In one feasible implementation, the material of the second dielectric layer 121 includes at least one of silicon oxide, silicon nitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, yttrium oxide, hafnium oxide, zirconium oxide, gallium nitride, calcium fluoride, tantalum nitride, and magnesium fluoride.

[0081] Specifically, the materials of different first dielectric layers 111 may be the same or different.

[0082] In one feasible implementation, the optical thickness of the second dielectric layer 121 is in the range of k2λ, 0≤k2≤1, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed.

[0083] In the above embodiments, to minimize the total thickness of the stacked multilayer second dielectric layers 121, thereby reducing the total thickness of the mask assembly 1 and weakening the influence of the patterned mask assembly 1 itself on the laser annealing process, the range of k2 can be 0 ≤ k2 ≤ 0.25. Here, optical thickness equals the product of physical thickness and refractive index. When the optical thickness of the second dielectric layer 121 is less than 1, the physical thickness of the second dielectric layer 121 can be smaller. When k2 is in the range of 0-0.25, the physical thickness of the second dielectric layer 121 can be further reduced. Simultaneously, when k2 is in the range of 0-0.25, the reflectivity of the annealing laser can be adjusted. Specifically, 0-0.25 represents one cycle of reflectivity and transmittance variation. When k2 is in the range of 0-0.25, the reflectivity of the anti-reflection functional unit 122 can vary within the range of 80%-5%, thus allowing the optical thickness of the anti-reflection functional unit 122 to be adjusted according to actual annealing requirements, thereby adjusting the reflectivity of the anti-reflection functional unit 122.

[0084] In one feasible implementation, the extinction coefficient of the second dielectric layer 121 is in the range of 0-0.1.

[0085] When the reflective enhancement layer 12 absorbs too much annealing laser light, the thermal effect generated within the reflective enhancement layer 12 can easily cause damage to the mask assembly 1 due to the annealing laser beam spot. In order to reduce the absorption of annealing laser light by the reflective enhancement layer 12 in the mask assembly 1, the second dielectric layer 121 has a lower extinction coefficient for annealing laser light, thereby improving the yield of the reflective enhancement layer 12.

[0086] Specifically, the smaller the extinction coefficient of the second dielectric layer 121, the smaller its absorption effect on the annealing laser. Therefore, the smaller the extinction coefficient of the second dielectric layer 121 is in the range of 0 to 0.1, the better.

[0087] In one feasible implementation, the thickness of the reflective layer 12 ranges from 100 nm to 500 nm.

[0088] In the above embodiments, in order to minimize the total thickness of the stacked multilayer second dielectric layer 121, thereby reducing the total thickness of the mask assembly 1 and weakening the influence of the patterned mask assembly 1 itself on the laser annealing process, the thickness of the reflective functional layer 12 is preferably in the range of 100nm-500nm.

[0089] In one feasible implementation, such as Figure 2As shown, the mask assembly also includes a light flux adjustment layer 13, which is located on the side of the antireflective layer 12 away from the antireflective layer 11. That is, the antireflective layer 11, the antireflective layer 12, and the light flux adjustment layer 13 are stacked along the thickness direction of the mask assembly 1. The light flux adjustment layer 13 has a second opening 130 communicating with the first opening 120, and the refractive index of the light flux adjustment layer 13 is greater than the refractive index of the second dielectric layer 121.

[0090] In the above embodiments, the connection between the first opening 120 and the second opening 130 means that the projection of the first opening 120 in the thickness direction of the mask assembly 1 and the projection of the second opening 130 in the thickness direction of the mask assembly 1 at least partially overlap, wherein the thickness direction of the mask assembly 1 is the stacking direction of the antireflective layer 12 and the antireflective layer 11.

[0091] In the mask assembly 1 provided in this application, for different annealing requirements of the film layer 3 to be annealed, the transmittance of the annealing laser through the antireflection layer 11 and the reflectance of the annealing laser after passing through the antireflection layer 12 and the antireflection layer 11 stacked together can be adjusted by adjusting the parameters of the antireflection layer 11 and the antireflection layer 12, thereby adjusting the transmittance of the annealing laser to the strong annealing area and the weak annealing area, so as to achieve a uniform annealing effect for the film layer 3 to be annealed.

[0092] When the mask assembly 1 includes a light flux adjustment layer 13, the transmittance of the weak reflection region to the annealing light can be adjusted by adjusting the light flux of the light flux adjustment layer 13, thereby eliminating the need to adjust the anti-reflection functional layer 12 and reducing the fabrication difficulty. Specifically, the light flux of the weak annealing region can be adjusted by adjusting the optical thickness of the light flux adjustment layer 13, thereby adjusting the transmittance of the weak annealing region.

[0093] In the above embodiment, the light flux adjustment layer 13 is located on the side of the antireflection functional layer 12 away from the antireflection layer 11. The light flux adjustment layer 13 has a second opening 130 that communicates with the first opening 120. The second opening 130 exposes the antireflection layer 11. The strong annealing region is opposite to the first opening 120 and the second opening 130, and only the antireflection layer 11 is provided there. Therefore, the light flux adjustment layer 13 only adjusts the weak annealing region.

[0094] Specifically, the orthographic projection of the second opening 130 onto the antireflection layer 11 covers the orthographic projection of the first opening 120 onto the antireflection layer 11.

[0095] Preferably, the orthographic projection of the second opening 130 on the antireflection layer 11 coincides with the orthographic projection of the first opening 120 on the antireflection layer 11, so that the strong annealing zone contains only the antireflection layer 11, and the weak annealing zone includes the stacked antireflection layer 11 and the antireflection function part 122.

[0096] In the above embodiment, the refractive index of the light flux adjustment layer 13 is greater than that of the second dielectric layer 121. This allows the reflected light from the annealing laser beam to interfere and superimpose after passing through the stacked light flux adjustment layer 13, the antireflection function unit 122, and the antireflection layer 11, thereby achieving the effect of enhanced reflection and reduced transmission, and further reducing the transmittance of the annealing laser beam.

[0097] In one feasible implementation, the material of the luminous flux adjustment layer 13 includes at least one of silicon oxide, silicon nitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, yttrium oxide, hafnium oxide, zirconium oxide, gallium nitride, calcium fluoride, tantalum nitride, and magnesium fluoride.

[0098] In one feasible implementation, the refractive index of the luminous flux adjustment layer 13 is in the range of 2.0-3.5.

[0099] In one feasible embodiment, the optical thickness range of the luminous flux adjustment layer 13 is k3λ, 0≤k3≤0.25, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed. In the above embodiment, in order to reduce the total thickness of the mask assembly 1 and thus weaken the influence of the patterned mask assembly 1 itself on the laser annealing process, the range of k3 is 0-0.25. Here, optical thickness equals the product of physical thickness and refractive index. When k3 is in the range of 0-0.25, the physical thickness of the luminous flux adjustment layer 13 can be lower. Simultaneously, when the optical thickness is in the range of 0-0.25, the transmittance and reflectance of the annealing laser by the mask assembly 1 can be adjusted. Specifically, changing k3 within the range of 0-0.25 allows the transmittance of the weak annealing region to vary from 20% to 98.5%, thereby allowing the optical thickness of the luminous flux adjustment layer 13 to be adjusted according to the actual annealing requirements, thereby adjusting the transmittance and reflectance of the weak annealing region, and ultimately adjusting the transmittance of the weak annealing region.

[0100] In one feasible implementation, the extinction coefficient of the luminous flux adjustment layer 13 is in the range of 0-0.1.

[0101] In the above embodiments, when the light flux adjustment layer 13 absorbs excessive amounts of annealing laser light, the thermal effect generated within the light flux adjustment layer 13 can easily cause damage to the mask assembly 1 due to the annealing laser beam spot. To reduce the absorption of annealing laser light by the light flux adjustment layer 13 in the mask assembly 1, the light flux adjustment layer 13 has a low extinction coefficient for the annealing laser light, thereby improving the yield of the light flux adjustment layer 13.

[0102] Specifically, the smaller the extinction coefficient of the light flux adjustment layer 13, the smaller its absorption effect on the annealing laser. Therefore, the smaller the extinction coefficient of the light flux adjustment layer 13 is in the range of 0 to 0.1, the better.

[0103] In one feasible implementation, the etching rate selection ratio of the light flux adjustment layer 13 to the second dielectric layer 121 is less than 1.

[0104] In the above embodiment, during the fabrication of the mask assembly 1, a first dielectric layer 111, a second dielectric material layer 4, and a light flux adjustment material layer 5 are first sequentially formed in a stacked manner. The first dielectric layer 111, the second dielectric material layer 4, and the light flux adjustment material layer 5 are all integrally fabricated film layers. Then, the second dielectric material layer 4 and the light flux adjustment material layer 5 are patterned to form a first opening 120 in the second dielectric material layer 4, thereby forming a patterned second dielectric layer 121, and a second opening 130 in the light flux adjustment material layer 5, thereby forming a patterned light flux adjustment layer 13. The second opening 130 is connected to the first opening 120. The first opening 120 and the second opening 130 can be fabricated using the same process, thereby reducing the fabrication process and lowering the fabrication cost.

[0105] During the patterning process, since the etching rate selectivity ratio between the luminous flux adjustment layer 13 and the second dielectric layer 121 is less than 1, that is, the etching rate of the luminous flux adjustment layer 13 is less than the etching rate of the second dielectric layer 121, the continued etching of the luminous flux adjustment material layer 5 during the patterning of the luminous flux adjustment material layer 5 and the second dielectric material layer 4 on the surface of the luminous flux adjustment material layer 5 away from the second dielectric material layer 4 after the patterning of the luminous flux adjustment material layer 5 is completed can be reduced, thereby reducing the error rate of the second opening 130 and improving the fabrication yield.

[0106] In one feasible implementation, such as Figure 3 As shown, it also includes a first insulating layer 14, located on the side of the antireflective layer 11 opposite to the antireflective functional layer 12.

[0107] In the above embodiment, the first insulating layer 14 is used to directly contact the film layer 3 to be annealed. The first insulating layer 14 has a buffering function, used to buffer the stress between the film layer 3 to be annealed and the antireflection layer 11. Specifically, since the materials of the film layer 3 to be annealed and the antireflection layer 11 are different, it is easy to cause the problem of lattice constant mismatch. During the hot annealing process, the antireflection layer 11 is prone to warping, cracking, peeling and other phenomena due to internal stress, which leads to mask failure. By setting the first insulating layer 14, the stress can be buffered, thereby improving the yield of the mask assembly 1 in the annealing process, and thus improving the annealing quality.

[0108] In one feasible implementation, the thickness of the first insulating layer 14 ranges from 5 nm to 100 nm.

[0109] If the thickness of the first insulating layer 14 is too thin, it will affect its buffering effect. If the thickness of the first insulating layer 14 is too thick, it will affect the transmittance of the annealing laser and increase the material cost. Therefore, setting the thickness of the first insulating layer 14 in the range of 5 nanometers to 50 nanometers can achieve a balance between buffering effect, anti-reflection effect and manufacturing cost.

[0110] Specifically, the thickness of the first insulating layer 14 ranges from 5nm, 15nm, 21nm, 33nm, 41nm, 45nm, 49nm, 50nm, 65nm, 73nm, 82nm, 90nm, 100nm, etc.

[0111] In one feasible implementation, the first insulating layer 14 includes at least one first sublayer, the material of which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon germanium.

[0112] In the above embodiments, the number of first sub-layers in the first insulating layer 14 is one or more. When multiple first sub-layers are included, the materials of the different first sub-layers may be the same or different.

[0113] In one feasible implementation, such as Figure 4 As shown, it also includes a second insulating layer 15, which is located between the antireflective layer 11 and the antireflective functional layer 12. The second insulating layer 15 includes a third opening 150 that communicates with the first opening 120.

[0114] In the above embodiments, the connection between the first opening 120 and the third opening 150 means that the projection of the first opening 120 in the thickness direction of the mask assembly 1 and the projection of the third opening 150 in the thickness direction of the mask assembly 1 at least partially overlap, wherein the thickness direction of the mask assembly 1 is the stacking direction of the antireflective layer 12 and the antireflective layer 11.

[0115] In the above embodiments, the second insulating layer 15 serves as a buffer layer between the antireflection layer 11 and the antireflection functional layer 12. It is used to buffer the stress between the antireflection layer 11 and the antireflection functional layer 12, reduce the probability of deformation and cracking of the mask assembly 1 caused by thermal effects during laser annealing, thereby improving the yield of the mask assembly 1 and the yield of the annealing of the film layer 3 to be annealed.

[0116] In the above embodiment, the second insulating layer 15 has a third opening 150 that communicates with the first opening 120. The third opening 150 exposes the anti-reflection layer 11. The strong annealing zone is opposite to the first opening 120 and the third opening 150 and is only provided with the anti-reflection layer 11. The weak annealing zone is provided with the second insulating layer 15, the anti-reflection layer 11 and the anti-reflection functional layer 12 stacked together.

[0117] Specifically, the orthographic projection of the third opening 150 onto the antireflection layer 11 covers the orthographic projection of the first opening 120 onto the antireflection layer 11.

[0118] Preferably, the orthographic projection of the third opening 150 on the antireflection layer 11 coincides with the orthographic projection of the first opening 120 on the antireflection layer 11, so that the strong annealing region contains only the antireflection layer 11, and the weak annealing region includes the stacked second insulating layer 15, the antireflection layer 11, and the antireflection layer 12. At this time, the reflected light after the annealing laser passes through the stacked antireflection layer 12, the second insulating layer 15, and the antireflection layer 11 will interfere and superimpose, thereby achieving the effect of enhanced reflection and reduced transmission.

[0119] In one feasible implementation, the thickness of the second insulating layer 15 ranges from 5 nm to 50 nm.

[0120] If the thickness of the second insulating layer 15 is too thin, it will affect its buffering effect. If the thickness of the second insulating layer 15 is too thick, it will affect the reduction of the total thickness of the mask assembly 1, thus making the mask assembly 1 itself have a poor effect on the laser annealing process. On the other hand, it will increase the material cost. Therefore, setting the thickness of the second insulating layer 15 in the range of 5 nanometers to 50 nanometers can achieve a balance between buffering effect, anti-reflection effect and manufacturing cost.

[0121] Specifically, the thickness of the second insulating layer 15 ranges from 5nm, 15nm, 21nm, 33nm, 41nm, 45nm, 49nm, 50nm, etc.

[0122] In one feasible embodiment, the second insulating layer 15 includes at least one second sublayer, the material of which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and germanium silicon.

[0123] In the above embodiments, the second insulating layer 15 includes one or more second sub-layers. When multiple second sub-layers are included, the materials of the different second sub-layers may be the same or different.

[0124] In one feasible implementation, the etching rate selection ratio of the first dielectric layer 111 to the second insulating layer 15 is less than 1.

[0125] The etching rate of the first dielectric layer 111 is lower than that of the second insulating layer 15. Therefore, during the patterning process of fabricating the third opening 150 in the second insulating layer 15, the etching damage to the first dielectric layer 111 can be reduced, the probability of over-etching of the first dielectric layer 111 can be reduced, and the yield of the first dielectric layer 111 can be improved.

[0126] In one feasible embodiment, a light flux adjustment layer 13 is further included. The light flux adjustment layer 13 is located on the side of the antireflective functional layer 12 away from the antireflective layer 11. The light flux adjustment layer 13 has a second opening 130 that communicates with the first opening 120. The refractive index of the light flux adjustment layer 13 is greater than the refractive index of the second dielectric layer 121. The second opening 130 communicates with a third opening 150. The etching rate selectivity ratio between the light flux adjustment layer 13 and the second insulating layer 15 is less than 1.

[0127] In the above embodiments, the mask assembly 1 includes a first dielectric layer 111 and a second insulating layer 15, a second dielectric layer 121 and a light flux adjustment layer 13 sequentially stacked along a direction away from the first dielectric layer 111.

[0128] In the above embodiments, the connection between the second opening 130 and the third opening 150 means that the projection of the second opening 130 in the thickness direction of the mask assembly 1 and the projection of the third opening 150 in the thickness direction of the mask assembly 1 at least partially overlap, wherein the thickness direction of the mask assembly 1 is the stacking direction of the anti-reflective functional layer 12 and the anti-reflective layer 11.

[0129] Preferably, the projections of the first opening 120, the second opening 130, and the third opening 150 in the thickness direction of the mask assembly 1 coincide, so that the strong annealing region contains only the anti-reflection layer 11, and the weak annealing region includes the second insulating layer 15, the anti-reflection layer 11, the anti-reflective functional layer 12, and the light flux adjustment layer 13 stacked together.

[0130] In the above embodiment, since the etching rate selection ratio of the luminous flux adjustment layer 13 to the second insulating layer 15 is less than 1, that is, the etching rate of the luminous flux adjustment layer 13 is less than the etching rate of the second insulating layer 15, during the process of forming the first opening 120 and the third opening 150 after the formation of the second opening 130, since the third opening 150 is formed after the second opening 130, in order to reduce the probability of continuing to etch the luminous flux adjustment layer 13 during the etching process of forming the second opening 130, the etching rate selection ratio of the luminous flux adjustment layer 13 to the second insulating layer 15 is set to be less than 1. This can reduce the fabrication error of the luminous flux adjustment layer 13 and the error of the second opening 130, thereby improving the fabrication yield.

[0131] This application also provides a method for preparing a mask assembly 1, such as... Figure 5 As shown, it includes:

[0132] S20, forming an antireflection layer 11, the antireflection layer 11 including at least one first dielectric layer 111.

[0133] S40, an anti-reflection functional layer 12 is formed on one side of the anti-reflection layer 11. The anti-reflection functional layer 12 includes multiple layers of second dielectric layers 121 stacked along the thickness direction of the anti-reflection layer 11. Adjacent second dielectric layers 121 have different refractive indices. The anti-reflection functional layer 12 includes an anti-reflection functional portion 122 and a first opening portion 120. The first opening portion 120 exposes the anti-reflection layer 11 so that the mask assembly 1 includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening portion 120 and the anti-reflection layer 11 exposed through the first opening portion 120. The weak annealing region is opposite to the portion of the anti-reflection functional portion 122 and the anti-reflection layer 11 stacked together.

[0134] In the above embodiments, the mask assembly 1 can be prepared on the film layer 3 to be annealed.

[0135] The mask assembly 1 is fabricated on the film layer 3 to be annealed, which improves the contact tightness between the mask assembly 1 and the film layer 3 and reduces the gap between them, thereby improving the masking effect. Specifically, fabricating the mask assembly 1 on the film layer 3 ensures that there is no air gap between the mask assembly 1 and the film layer 3, facilitating the setting of the inner film layer parameters of the mask assembly 1, and thus facilitating the design and fabrication of the mask assembly 1.

[0136] During the fabrication process, the first dielectric layer 111 and the second dielectric layer 121 can be formed using a deposition process. During the deposition of the first dielectric layer 111 and the second dielectric layer 121, the thickness error of each layer must be strictly controlled to avoid excessive loss from the annealing laser. The wavelength of the annealing laser is λ, and to obtain optimal annealing depth and effect, the wavelength λ ranges from 193 nm to 10.6 μm.

[0137] Specifically, during the fabrication process, appropriate materials, optical thickness, extinction coefficient, and physical thickness can be selected according to the wavelength of the annealing laser, thereby realizing a mask assembly 1 that integrates strong and weak annealing regions. That is, by changing the parameters of the inner film layer of the mask assembly 1, laser micro-nano processing with controllable light flux can be achieved, integrating high-transmittance and low-transmittance regions. Compared to existing technologies that add a mask plate device to the optical path, the direct contact between the mask assembly 1 and the film layer 3 to be annealed in this invention solves the problem of poor uniformity caused by light diffraction in patterned thin films processed by long-annealing-wavelength lasers. Furthermore, the mask assembly 1 has both strong and weak annealing regions, enabling selective annealing processing with adjustable light flux, thus better matching process requirements and widening the process window.

[0138] This application also provides a method for fabricating a semiconductor device, such as... Figure 6 As shown, it includes:

[0139] S200, such as Figure 7 As shown, a semiconductor structure layer 2 is provided, which includes a first surface 20 and a trench structure 21 formed by recesses in the first surface 20.

[0140] Specifically, the aforementioned semiconductor structure layer 2 can be a semiconductor substrate, which provides a process platform for subsequent processing of the semiconductor device. The material of the semiconductor substrate can include monocrystalline silicon, polycrystalline silicon, or amorphous bulk silicon. The material of the semiconductor substrate can also include silicon-on-insulator, germanium, gallium arsenide, or germanium-silicon compounds, or other semiconductor materials. This application uses monocrystalline silicon as an example to illustrate this. The semiconductor structure layer 2 can include one or more combinations of source, drain, or gate structures. When the semiconductor device is a memory semiconductor device, the semiconductor structure layer 2 includes one or more combinations of logic regions and memory regions (not shown in the figure).

[0141] Specifically, when the semiconductor structure layer 2 is a semiconductor substrate, the trench structure 21 may include a shallow trench isolation structure. Other structures may also be included in the trench structure 21, which are not specifically limited in this application.

[0142] Specifically, the trench structure 21 may also include vertically stacked channels for logic devices, memory devices, and power devices, wherein the channels are for providing carrier channels to the source and drain; the trench structure 21 may also include vertical contact structures for interconnecting discrete components, or may include interlayer interconnection contact holes for back-end copper interconnects.

[0143] Specifically, the above-mentioned trench structure 21 can be formed by etching with a photomask.

[0144] Specifically, the trench structure 21 has a high aspect ratio, for example, greater than 5:1. The trench structure 21 can have an even higher aspect ratio, for example, 50:1, but this application does not impose any particular limitation.

[0145] S400, such as Figure 8 As shown, an annealing film layer 3 is formed on one side of the first surface 20. Part of the annealing film layer 3 is located on the first surface 20, and part is located in the groove structure 21.

[0146] Specifically, the film layer 3 to be annealed can be an undoped or doped amorphous silicon, polycrystalline silicon, germanium silicon, silicon carbide, etc. When it is a doped film layer, the doping element can be phosphorus, arsenic, or boron, etc. The film layer 3 to be annealed can also be a copper, tungsten, indium gallium zinc oxide, silicon nitride, etc.

[0147] Specifically, the film layer to be annealed can be formed by chemical vapor deposition or atomic layer deposition.

[0148] Specifically, the annealing layer 3 in this application can be an in-situ phosphorus-doped amorphous silicon film layer formed by atomic layer deposition. Since the annealing layer 3 has a high step coverage, only a thin layer is needed to completely cover the trench structure 21. In order to improve the filling efficiency and maintain a thin thickness, the deposition thickness of the annealing layer 3 is at least greater than half the width of the trench.

[0149] S600, such as Figure 9 As shown, an antireflection layer 11 is formed on the side of the film layer 3 to be annealed away from the semiconductor structure layer 2. The antireflection layer 11 includes at least one first dielectric layer 111.

[0150] S800, such as Figure 9 As shown, an antireflective functional layer 12 is formed on the side of the antireflection layer 11 away from the film layer 3 to be annealed. The antireflective functional layer 12 includes multiple layers of second dielectric layers 121 stacked along the thickness direction of the antireflection layer 11. The refractive indices of adjacent second dielectric layers 121 are different. A first opening 120 is formed in the antireflective functional layer 12 so that the antireflective functional layer 12 includes an antireflective functional portion 122 and a first opening 120. The first opening 120 exposes the antireflection layer 11 to form a mask assembly 1. The mask assembly 1 includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening 120 and the antireflection layer 11 exposed through the first opening 120. The weak annealing region is opposite to the portion of the antireflective functional portion 122 and the antireflection layer 11 stacked together.

[0151] Specifically, such as Figure 10 As shown, when the mask assembly 1 is formed on the side of the film layer 3 facing away from the semiconductor structure layer 2, at least one first dielectric layer 111 and multiple layers of second dielectric material layers 4 can be sequentially formed on the surface of the film layer 3 facing away from the semiconductor structure layer 2, such as... Figure 11 As shown, the second dielectric material layer 4 is patterned to form a first opening 120, thereby forming the second dielectric layer 121. Figure 12 As shown, in order to pattern the second dielectric material layer 4, an etching sacrificial layer 7 and a photoresist layer 8 can be sequentially formed on the side of the second dielectric material layer 4 away from the first dielectric layer 111. The photoresist layer 8 has a patterned structure, which includes a body portion 81 and an opening portion 82. The opening portion 82 is disposed opposite to the trench structure 21, that is, the orthogonal projection of the opening portion 82 on the semiconductor structure layer 2 coincides with or nearly coincides with the trench structure 21.

[0152] Specifically, the photomask used in step S200 can be used as a photomask for patterning the photoresist layer 8, transferring the trench structure 21 in the semiconductor structure onto the photoresist coating to form a photoresist layer 8 having a body portion 81 and an opening portion 82. On the one hand, this can save the cost of the photomask, and on the other hand, it can improve the matching degree between the photoresist layer 8 and the semiconductor substrate pattern, that is, improve the dimensional accuracy and alignment accuracy of the opening portion 82 and the trench structure 21. The patterning of the photoresist layer 8 includes photolithography processes such as coating, baking, exposure and development, which will not be described in detail here.

[0153] In the above preparation method, a mask is used to pattern the semiconductor structure layer 2 to form a trench structure 21, and the mask is used as a medium for pattern transfer during the manufacturing process of the mask assembly 1. Thus, the manufacturing of the mask assembly 1 is achieved without adding a mask. The mask assembly 1 enables controllable adjustment of the laser intensity during the annealing process of the film layer 3 to be annealed.

[0154] Specifically, the first dielectric layer 111 has an extremely low etching rate selectivity for the second dielectric layer 121 and the sacrificial layer. On the one hand, the first dielectric layer 111 serves as a stop layer for patterning the second dielectric layer 121, reducing the probability of over-etching the first dielectric layer 111, thereby reducing the probability of mask assembly 1 failure and preventing etching damage to the film layer 3 to be annealed. On the other hand, the extremely low etching rate selectivity of the first dielectric layer 111 for the second dielectric layer 121 and the sacrificial layer allows the sacrificial layer to be removed by dry etching after patterning the second dielectric layer 121, reducing damage to the first dielectric layer 111 exposed through the first opening 120 during dry etching.

[0155] Specifically, the photoresist layer 8 includes a photoresist layer. Alternatively, the photoresist layer 8 is formed by a composite of inorganic and organic materials and photoresist, such as photoresist, a silicon-containing anti-reflective coating, and a spin-coated organic carbon layer. This can effectively reduce the reflection of ultraviolet light by the photoresist and improve the selectivity of step transfer etching of the photolithographic pattern.

[0156] Specifically, the etch sacrificial layer 7 includes at least one semiconductor thin film, and the second dielectric layer 121 has a very high etching rate selectivity for the etch sacrificial layer 7. The etch sacrificial layer 7 is used as the top etch mask material layer when patterned by plasma dry etching process to form mask assembly 1, so as to improve the fabrication yield of mask assembly 1.

[0157] During the formation of the first opening 120, a plasma dry etching process can be used to pattern the sacrificial layer 7 and the second dielectric layer 121 to form the first opening 120 that exposes the first dielectric layer 111. Since this step uses the photoresist layer 8 as a mask, the first opening 120 is opposite to the opening 82 in the photoresist layer 8, and the opening 82 is opposite to the trench structure 21. Therefore, the first opening 120 and the trench structure 21 can have the same shape, that is, self-alignment with the semiconductor structure is achieved when the mask structure is formed.

[0158] Preferably, the orthographic projection of the first opening 120 on the semiconductor structure layer 2 covers the trench structure 21, specifically including the edge of the trench structure 21 coinciding with the edge of the orthographic projection of the first opening 120 on the semiconductor structure layer 2.

[0159] The above preparation method also includes removing the etch sacrificial layer 7 and the photoresist layer 8, thereby completing the preparation of the mask assembly 1.

[0160] The above preparation method also includes annealing the film layer 3 to be annealed by a laser beam located on the side of the mask assembly 1 away from the film layer 3 to be annealed. In this step, the hard mask assembly 1 is used as the light flux control structure of the laser annealing process, which can control the light flux of the annealing laser, thereby improving the annealing yield of the film layer 3 to be annealed.

[0161] In the semiconductor device fabrication method provided in this application, before annealing the film layer 3 to be annealed, a mask assembly 1 is formed on the surface of the film layer 3 to be annealed. The mask assembly 1 includes a strong annealing region and a weak annealing region. Since part of the film layer 3 to be annealed is located inside the trench structure 21, it requires a large light flux of the annealing laser. Therefore, the area of ​​the film layer 3 covering the trench structure 21 is positioned opposite the strong annealing region to achieve a strong annealing effect at that location. Other areas of the film layer 3 to be annealed have a smaller light flux requirement for the annealing laser and are therefore weakly annealed or non-annealed. This allows other areas to be positioned opposite the weak annealing region in the mask assembly 1. By adjusting the light transmittance of the weak annealing region, the annealing effect of the film layer 3 to be annealed is adjusted to improve the annealing yield of the film layer 3 to be annealed.

[0162] Specifically, the annealing laser used in the laser annealing process can be pulsed or continuous, single-wavelength or multi-wavelength, single-beam or multi-beam, or any combination of any wavelength. Usually, the wavelength parameters of the annealing laser are determined during the laser annealing process. The parameters of the mask assembly 1 (including optical thickness, physical thickness, extinction coefficient, material, and refractive index, etc.) can be determined according to the annealing laser and the annealing intensity requirements of the film layer 3 to be annealed.

[0163] In the above preparation method, since a mask assembly with a matching shape is directly formed according to the trench structure shape of the semiconductor structure layer 2 during the preparation process, the matching degree and accuracy of the mask assembly are high. Furthermore, the direct preparation of the mask assembly can eliminate the replacement step, save time between replacements, and eliminate the maintenance process, resulting in lower process complexity.

[0164] In one feasible implementation, the method further includes the following step between step S400 and step S600:

[0165] A first insulating layer 14 is formed on the surface of the film layer 3 facing away from the semiconductor structure layer 2.

[0166] Specifically, the first insulating layer 14 is located between the annealed film layer 3 and the anti-reflection layer 11, and is in contact with the annealed film layer 3 and the anti-reflection layer 11.

[0167] In the above embodiments, such as Figure 13 As shown, a first insulating layer 14 is formed before the formation of the antireflection layer 11. The first insulating layer 14 can directly contact the film layer 3 to be annealed. The first insulating layer 14 has a buffering effect, used to buffer the stress between the film layer 3 to be annealed and the antireflection layer 11. Specifically, since the materials of the film layer 3 to be annealed and the antireflection layer 11 are different, it is easy to cause the problem of lattice constant mismatch. During the hot annealing process, the antireflection layer 11 is prone to warping, cracking, peeling and other phenomena due to internal stress, which leads to mask failure. By setting the first insulating layer 14, the stress can be buffered, thereby improving the yield of the mask assembly 1 in the annealing process, and thus improving the annealing quality.

[0168] Specifically, the parameters of the first insulating layer 14 can be prepared according to the parameters of the first insulating layer 14 in any of the mask assembly 1 provided in the above embodiments of this application, and will not be described again in this application.

[0169] In one feasible implementation, between step S600 and step S800, a second insulating layer 15 is formed on the side surface of the antireflection layer 11 facing away from the semiconductor structure layer 2. The second insulating layer 15 includes a third opening 150, which exposes the antireflection layer 11. The first opening 120 is connected to the third opening 150.

[0170] Specifically, the second insulating layer 15 is located between the antireflection layer 11 and the antireflection functional layer 12 and is in contact with the antireflection layer 11 and the antireflection functional layer 12.

[0171] In the above embodiments, such as Figure 14As shown, after the antireflection layer 11 is formed, a second insulating layer 15 is formed, followed by an antireflection layer 12. The second insulating layer 15 serves as a buffer layer between the antireflection layer 11 and the antireflection layer 12, buffering the stress between them and reducing the probability of deformation and cracking of the mask assembly 1 caused by thermal effects during laser annealing. This improves the yield of the mask assembly 1 and the yield of the annealed film layer 3.

[0172] In the above embodiments, the etching rate selection ratio of the first dielectric layer 111 to the second insulating layer 15 is less than 1.

[0173] In the above embodiments, such as Figure 15 As shown, a first dielectric layer 111, a second insulating material layer 6, and a second dielectric material layer 4 are first sequentially formed, wherein the first dielectric layer 111, the second insulating material layer 6, and the second dielectric material layer 4 are all integrally prepared film layers. Then, as... Figure 16 As shown, the second dielectric material layer 4 and the second insulating material layer 6 are patterned so that the second dielectric material layer 4 forms a first opening 120, thereby forming a patterned second dielectric layer 121, and the second insulating material layer 6 forms a third opening 150 communicating with the first opening 120, as shown. Figure 14 As shown, a patterned second insulating layer 15 is thus formed. The first opening 120 and the third opening 150 can be fabricated using the same process, thereby reducing the number of fabrication processes and lowering fabrication costs.

[0174] During the patterning process, since the etching rate selection ratio between the first dielectric layer 111 and the second insulating layer 15 is less than 1, that is, the etching rate of the first dielectric layer 111 is less than the etching rate of the second insulating material layer 6, the etching damage to the first dielectric layer 111 can be reduced and the probability of over-etching of the first dielectric layer 111 can be reduced during the patterning of the second insulating material layer 6 on the surface of the second insulating material layer 6 away from the first dielectric layer 111, thereby improving the yield of the first dielectric layer 111.

[0175] Specifically, the parameters of the second insulating layer 15 can be prepared according to the parameters of the second insulating layer 15 in any of the mask assembly 1 provided in the above embodiments of this application, and will not be described again in this application.

[0176] In one feasible implementation, after step S800, a light flux adjustment layer 13 is formed on the side of the antireflective functional layer 12 away from the annealed film layer 3. The light flux adjustment layer 13 is located on the side of the antireflective functional layer 12 away from the antireflective layer 11. The light flux adjustment layer 13 has a second opening 130 that communicates with the first opening 120. The refractive index of the light flux adjustment layer 13 is greater than the refractive index of the second dielectric layer 121 adjacent to the light flux adjustment layer 13 in the antireflective functional layer 12.

[0177] In the mask assembly 1 provided in this application, the transmittance of the annealing laser through the antireflection layer 11 and the reflectance of the annealing laser through the antireflection layer 12 can be adjusted by adjusting the parameters of the antireflection layer 11 and the antireflection layer 12 to adjust the transmittance of the annealing laser in the strong annealing region and the weak annealing region, so as to achieve a uniform annealing effect for the annealing film layer 3.

[0178] like Figure 17 As shown, when the mask assembly 1 includes a light flux adjustment layer 13, the transmittance of the weak annealing region can be adjusted by regulating the light flux of the light flux adjustment layer 13, thereby eliminating the need to adjust the anti-reflection functional layer 12 and reducing the fabrication difficulty. Specifically, the light flux of the light flux adjustment layer 13 can be adjusted by regulating its optical thickness, thereby adjusting the transmittance of the weak annealing region. That is, when different mask assemblies 1 are formed on one side of the film layer 3 to be annealed, the parameters of the anti-reflection functional layer 12 can be the same, and the transmittance of the weak annealing region can be adjusted only by regulating the parameters of the light flux adjustment layer, thus simplifying the fabrication method.

[0179] In the above embodiments, the etching rate selection ratio of the light flux adjustment layer 13 to the second insulating layer 15 is less than 1.

[0180] In the above embodiments, such as Figure 17 As shown, during the fabrication process, a first dielectric layer 111, a second insulating material layer 6, a second dielectric material layer 4, and a light flux adjustment material layer 5 are sequentially formed, wherein the first dielectric layer 111, the second insulating material layer 6, the second dielectric material layer 4, and the light flux adjustment material layer 5 are all integrally fabricated film layers. Then, as... Figure 18 As shown, the luminous flux adjustment material layer 5, the second dielectric material layer 4, and the second insulating material layer 6 are patterned to form a second opening 130 in the luminous flux adjustment material layer 5, thereby forming a patterned luminous flux adjustment layer 13. The second dielectric material layer 4 forms a first opening 120 communicating with the second opening 130, thereby forming a patterned second dielectric layer 121. The second insulating material layer 6 forms a third opening 150 communicating with the first opening 120, thereby forming a patterned second insulating layer 15. The luminous flux adjustment material layer 5, the second dielectric material layer 4, and the second insulating layer 6 can be patterned using the same process; that is, the first opening 120, the second opening 130, and the third opening 150 can be fabricated using the same process, thereby reducing the number of fabrication processes and lowering the fabrication cost.

[0181] During the patterning process, since the etching rate selection ratio between the luminous flux adjustment layer 13 and the second insulating layer 15 is less than 1 (i.e., the etching rate of the luminous flux adjustment layer 13 is less than that of the second insulating layer 15), it is necessary to first pattern the luminous flux adjustment material layer 5 on the side facing away from the first dielectric layer 111 to form the second opening 130, and then pattern the second dielectric material layer 4 to form the first opening 120. Finally, the second insulating material layer 6 is patterned to form the third opening 150, i.e., the third opening 150 is formed after the second opening 130. To reduce the probability of continuing to etch the luminous flux adjustment layer 13 during the etching of the second insulating material layer 6, the etching rate selection ratio between the luminous flux adjustment layer 13 and the second insulating layer 15 is set to be less than 1. This can reduce the fabrication error of the luminous flux adjustment layer 13 and the error of the second opening 130, thereby improving the fabrication yield.

[0182] In the above embodiments, the etching rate selection ratio between the luminous flux adjustment layer 13 and the second dielectric layer 121 is less than 1, that is, the etching rate of the luminous flux adjustment layer 13 is less than the etching rate of the second dielectric layer 121, and the etching rate selection ratio between the luminous flux adjustment layer 13 and the second insulating layer 15 is less than 1, that is, the etching rate of the luminous flux adjustment layer 13 is less than the etching rate of the second insulating layer 15, that is, the etching rates of the second insulating layer 15 and the second dielectric layer 121 are both greater than the etching rate of the luminous flux adjustment layer 13. Specifically, the etching rate selection ratio between the second insulating layer 15 and the luminous flux adjustment layer 13 is greater than 5:1, and the etching rate selection ratio between the second dielectric layer 121 and the luminous flux adjustment layer 13 is greater than 5:1, thereby reducing the error of the luminous flux adjustment layer 13 during the patterning process. In the above embodiments, the first dielectric layer 111 has a lower etching rate selectivity to the second insulating layer 15, which is less than 1 / 4. It should include at least one first dielectric layer 111 adjacent to the second insulating layer 15. The first dielectric layer 111 has a low etching rate selectivity to the second insulating layer 15, which can reduce the risk of over-etching of the first dielectric layer 111 and help improve the preparation yield of the first dielectric layer 111.

[0183] Specifically, the parameters of the light flux adjustment layer 13 can be prepared according to the parameters of the light flux adjustment layer 13 in any of the mask components 1 provided in the above embodiments of this application, and will not be described again in this application.

[0184] The method for fabricating the semiconductor device provided in this application further includes: sequentially removing each film layer within the mask assembly 1 by etching or chemical polishing processes; and also removing part of the annealed film layer, retaining only the annealed film layer within the trench structure 21. Finally, the process proceeds to the subsequent fabrication of other components or interconnects within the semiconductor device.

[0185] In one feasible implementation, as shown in Table 1, this application uses the parameter settings of a mask assembly 1 during application as an example for illustration:

[0186]

[0187] Table 1. Parameters of each film layer in the mask assembly

[0188] The parameters in Table 1 are based on test data at a wavelength of 532nm under normal temperature and pressure. The refractive index of air is 1 and the extinction coefficient is 0.

[0189] The mask assembly 1 is located on the surface of the film layer 3 to be annealed. The refractive index of the film layer 3 to be annealed is 4.3851 and the extinction coefficient is 0.6534.

[0190] The mask assembly 1 includes a first insulating layer 14, an antireflective layer 11, a second insulating layer 15, an antireflective layer 12, and a light flux adjustment layer 13, which are stacked sequentially. The first insulating layer 14 has a refractive index of 1.4607, an extinction coefficient of 0, and an optical thickness of 0.05 nm. The antireflective layer 11 includes a first dielectric layer 111 with a refractive index of 2.0528, an extinction coefficient of 0.0018, and an optical thickness of 0.17 nm. The second insulating layer 15 has a refractive index of 1.4607, an extinction coefficient of 0, and a physical thickness of 10 nm. The reflective enhancement layer 12 comprises three second dielectric layers 121. Along the direction away from the second insulating layer 15, the first second dielectric layer 121 has a refractive index of 2.469, an extinction coefficient of 0, and an optical thickness of 0.25; the second second dielectric layer 121 has a refractive index of 1.461, an extinction coefficient of 0, and an optical thickness of 0.25; and the third second dielectric layer 121 has a refractive index of 2.0528, an extinction coefficient of 0.0018, and an optical thickness of 0.25. The luminous flux adjustment layer 13 has a refractive index of 3.4972, an extinction coefficient of 0.0007, and an optical thickness of 0-0.25.

[0191] like Figure 9 As shown, this application selects two positions (position A and position B) on the surface of the mask assembly 1 in contact with the film layer 3 to be annealed for description. Position A is located on the surface of the mask assembly 1 in the strong heat penetration zone in contact with the film layer 3 to be annealed, and position B is located on the surface of the mask assembly 1 in the weak heat penetration zone in contact with the film layer 3 to be annealed. Combined with Figure 19 and Figure 20 As shown, Figure 19 This is a schematic diagram showing the relationship between the optical thickness ratio of the first insulating layer 14 and the first dielectric layer 111 at location A and the change in transmittance. Figure 19As can be seen, the lower left region of the figure contains an area with high transmittance, which allows the transmittance to be increased from 59% to 99% with a relatively small optical thickness. For example, the optical thickness of the first insulating layer 14 is 0.05 mm, and the optical thickness of the first dielectric layer 111 is 0.17 mm. This antireflection layer 11 greatly increases the utilization rate of annealing laser energy in the strong annealing region.

[0192] Figure 20 This is a schematic diagram showing the relationship between the optical thickness of the luminous flux adjustment layer 13 and its transmittance, absorptivity, and reflectivity at location B. Figure 20 It can be seen that varying the optical thickness of the flux adjustment layer 13 within the range of 0 to 0.25 mm can achieve a transmittance in the weakly annealed region ranging from 20% to 98.5%. Furthermore, the absorption curve shows that within the optical thickness range of 0 to 0.25 mm, the absorption rate of the flux adjustment layer 13 for the annealing laser is almost zero. Combined with... Figure 19 and Figure 20 The mask assembly 1 has very high thermal stability and low light loss rate, and exhibits excellent performance in semiconductor device annealing processes.

[0193] The above are merely preferred embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A mask assembly, characterized in that, The mask assembly is used to contact the film layer to be annealed during the annealing process, and includes: An antireflective layer, comprising at least one first dielectric layer; An anti-reflective functional layer is stacked with the anti-reflective layer and includes multiple layers of second dielectric layers stacked along the thickness direction of the anti-reflective layer. Adjacent second dielectric layers have different refractive indices. The anti-reflective functional layer includes an anti-reflective functional portion and a first opening portion, the first opening portion exposing the anti-reflective layer. The mask assembly includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening and the antireflection layer exposed through the first opening. The weak annealing region is opposite to the antireflection function part and the portion of the antireflection layer that are stacked together.

2. The mask assembly according to claim 1, characterized in that, The refractive index of the first dielectric layer is in the range of 1.1-2.5; and / or, The optical thickness range of the first dielectric layer is k1λ, 0≤k1≤1, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed; And / or, The extinction coefficient of the first dielectric layer ranges from 0 to 0.1; and / or, The refractive index of the second dielectric layer is in the range of 1.3-3.0; and / or, The absolute value of the refractive index difference between adjacent second dielectric layers ranges from 0.3 to 1.3; and / or, The optical thickness range of the second dielectric layer is k2λ, 0≤k2≤1, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed; and / or, The extinction coefficient of the second dielectric layer ranges from 0 to 0.

1.

3. The mask assembly according to claim 1, characterized in that, It also includes a luminous flux adjustment layer, which is located on the side of the antireflective layer away from the antireflective layer. The luminous flux adjustment layer has a second opening that communicates with the first opening. The refractive index of the luminous flux adjustment layer is greater than the refractive index of the second dielectric layer.

4. The mask assembly according to claim 3, characterized in that, The refractive index of the light flux adjustment layer is in the range of 2.0-3.5; and / or, The optical thickness range of the light flux adjustment layer is k3λ, 0≤k3≤0.25, where λ is the wavelength of the annealing laser used to anneal the film layer to be annealed; and / or, The extinction coefficient of the light flux adjustment layer ranges from 0 to 0.

1.

5. The mask assembly according to claim 4, characterized in that, The etching rate selection ratio between the light flux adjustment layer and the second dielectric layer is less than 1.

6. The mask assembly according to claim 1, characterized in that, It also includes a first insulating layer, which is located on the side of the antireflective layer opposite to the antireflective functional layer, and the first insulating layer includes at least one first sublayer.

7. The mask assembly according to claim 1, characterized in that, It also includes a second insulating layer, which is located between the antireflective layer and the antireflective functional layer. The second insulating layer includes a third opening that communicates with the first opening. The second insulating layer includes at least one second sublayer.

8. The mask assembly according to claim 7, characterized in that, The etching rate selection ratio between the first dielectric layer and the second insulating layer is less than 1.

9. The mask assembly according to claim 7, characterized in that, It also includes a luminous flux adjustment layer, which is located on the side of the antireflective functional layer away from the antireflective layer. The luminous flux adjustment layer has a second opening that communicates with the first opening. The refractive index of the luminous flux adjustment layer is greater than the refractive index of the second dielectric layer. The second opening communicates with the third opening. The etching rate selectivity ratio between the luminous flux adjustment layer and the second insulating layer is less than 1.

10. A method for preparing a mask assembly as described in any one of claims 1-9, characterized in that, include: An antireflection layer is formed, the antireflection layer comprising at least one first dielectric layer; An anti-reflective functional layer is formed on one side of the anti-reflection layer. The anti-reflective functional layer includes multiple layers of second dielectric layers stacked along the thickness direction of the anti-reflection layer. Adjacent second dielectric layers have different refractive indices. The anti-reflective functional layer includes an anti-reflective functional portion and a first opening. The first opening exposes the anti-reflection layer, so that the mask assembly includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening and the anti-reflection layer exposed through the first opening. The weak annealing region is opposite to the portion of the anti-reflective functional portion and the anti-reflection layer stacked together.

11. A method for fabricating a semiconductor device, characterized in that, include: A semiconductor structure layer is provided, the semiconductor structure layer including a first surface and a trench structure formed by recesses in the first surface; An annealing film layer is formed on one side of the first surface, wherein part of the annealing film layer is located on the first surface and part is located within the trench structure; An antireflection layer is formed on the side of the film layer to be annealed away from the semiconductor structure layer, and the antireflection layer includes at least one first dielectric layer; An anti-reflection functional layer is formed on the side of the anti-reflection layer opposite to the film layer to be annealed. The anti-reflection functional layer includes multiple layers of second dielectric layers stacked along the thickness direction of the anti-reflection layer. Adjacent second dielectric layers have different refractive indices. A first opening is formed in the anti-reflection functional layer so that the anti-reflection functional layer includes an anti-reflection functional portion and the first opening. The first opening exposes the anti-reflection layer to form a mask assembly. The mask assembly includes a strong annealing region and a weak annealing region. The strong annealing region is opposite to the first opening and the anti-reflection layer exposed through the first opening. The weak annealing region is opposite to the portion of the anti-reflection functional portion and the anti-reflection layer stacked together.

12. The method for fabricating a semiconductor device according to claim 11, characterized in that, The step of forming the film layer to be annealed on one side of the first surface and the step of forming an antireflection layer on the side of the film layer to be annealed away from the semiconductor structure layer further include: A first insulating layer is formed on the surface of the film layer to be annealed, on the side opposite to the semiconductor structure layer.

13. The method for fabricating a semiconductor device according to claim 11, characterized in that, Between the step of forming an antireflection layer on the side of the film layer to be annealed away from the semiconductor structure layer and the step of forming an antireflection layer on the side of the antireflection layer away from the film layer to be annealed, the method further includes: A second insulating layer is formed on the surface of the antireflection layer opposite to the semiconductor structure layer. The second insulating layer includes a third opening that exposes the antireflection layer. The first opening is connected to the third opening.

14. The method for fabricating a semiconductor device according to claim 11, characterized in that, After the step of forming the antireflective functional layer on the side of the antireflective layer opposite to the film layer to be annealed, the method further includes: A light flux adjustment layer is formed on the side of the antireflective functional layer away from the film layer to be annealed. The light flux adjustment layer is located on the side of the antireflective functional layer away from the antireflective layer. The light flux adjustment layer has a second opening that communicates with the first opening. The refractive index of the light flux adjustment layer is greater than the refractive index of the second dielectric layer adjacent to the light flux adjustment layer in the antireflective functional layer.

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