Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor device includes a first stack pair and a connection unit. The first stack pair includes a first repeating unit and a second repeating unit. The first repeating unit includes a first dielectric layer, a first device surrounded by the first dielectric layer, and a first interconnect structure including a first metal layer that covers the first device and is surrounded by the first dielectric layer. The first metal layer is electrically coupled to the first device. The second repeating unit includes a second dielectric layer, a second interconnect structure including a second metal layer that is bonded to the first metal layer, and a second device. The second device is surrounded by the second dielectric layer and is electrically coupled to the second metal layer. The connection unit includes a contact pad that is electrically coupled to the first metal layer and the second metal layer. A method of fabricating a semiconductor structure is also disclosed.

Description

Technical Field

[0001] This invention relates to semiconductor structures, and more specifically, to a bonded semiconductor structure. Background Technology

[0002] Currently, an increasing number of electronic products are adopting three-dimensional (3D) semiconductor bonding technology to improve system performance, integrated density, signal transmission speed, and data processing capabilities. This technology includes chip-on-chip stacking, chip-on-wafer (CoW) stacking, and wafer-on-wafer (WoW) stacking. For example, wafer-to-wafer stacking allows for vertical connections between multiple wafers, achieving a vertical integration of multiple chips.

[0003] However, existing semiconductor bonding or stacking structures still present many challenges. For example, precise alignment of the two semiconductor structures to be bonded is crucial but often difficult to achieve. Therefore, it is necessary to improve semiconductor manufacturing methods to form semiconductor structures with better electrical performance. Summary of the Invention

[0004] One embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes a first stacked pair and interconnect units. The first stacked pair includes a first repeating unit and a second repeating unit. The first repeating unit includes a first dielectric layer, a first device surrounded by the first dielectric layer, and a first interconnect structure. The first interconnect structure includes a first metal layer covering the first device and surrounded by the first dielectric layer, the first metal layer being electrically coupled to the first device. The second repeating unit includes a second dielectric layer, a second interconnect structure including a second metal layer bonded to the first metal layer, and a second device surrounded by the second dielectric layer and electrically coupled to the second metal layer. The interconnect unit includes a contact pad electrically coupled to the first metal layer and the second metal layer.

[0005] One embodiment of the present invention provides another semiconductor structure. The semiconductor structure includes a substrate and N stacked pairs stacked on top of each other on the substrate. Each of the N stacked pairs includes a first repeating unit and a second repeating unit. In each of the N stacked pairs, the first repeating unit includes a first capacitor structure comprising a first node, a second node, and a first metal layer formed in a first interconnect structure; the second repeating unit includes a second capacitor structure comprising a first node, a second node, and a second metal layer formed in a second interconnect structure. The first nodes of the first and second capacitor structures are electrically connected through a bonding between the first and second metal layers, and the second nodes of the first and second capacitor structures are electrically connected through a bonding between the first and second metal layers, where N is an integer and ≥1.

[0006] Another aspect of the present invention provides a method for manufacturing a semiconductor structure. The method includes: providing a first wafer including a first substrate, a first dielectric layer on the first substrate, a first device located within the first dielectric layer, and a first metal layer covering the first device and partially exposed through the first dielectric layer; providing a second wafer including a second substrate, a second dielectric layer on the second substrate, a second device located within the second dielectric layer, and a second metal layer covering the second device and partially exposed through the second dielectric layer; and bonding the second wafer to the first wafer, wherein the second wafer is disposed covering the first wafer, the second metal layer is bonded to the first metal layer, and the second dielectric layer is bonded to the first dielectric layer. Attached Figure Description

[0007] A more complete understanding of the invention can be obtained by referring to the detailed description and claims when considered in conjunction with the accompanying drawings, wherein like reference numerals refer to similar elements throughout the drawings.

[0008] Figure 1A Semiconductor structures according to some embodiments of the present invention are shown.

[0009] Figure 1B Show Figure 1A A device with a semiconductor structure and a capacitor structure.

[0010] Figure 1C Show Figure 1B Enlarged view of the area enclosed by the dashed line.

[0011] Figure 1D Show Figure 1A Enlarged view of the semiconductor structure and metal layer in the diagram.

[0012] Figure 1E Another semiconductor structure is shown according to some embodiments of the present invention.

[0013] Figure 2 This illustrates the manufacturing process according to some embodiments of the present invention. Figure 1A The flowchart shows the method for constructing semiconductor structures.

[0014] Figures 3A to 3L This illustrates some embodiments according to the present invention. Figure 2 A schematic cross-sectional diagram illustrating the operational sequence of the methods described.

[0015] Figure 4 This illustrates the manufacturing process according to some embodiments of the present invention. Figure 1E The flowchart shows the method for constructing semiconductor structures.

[0016] Figures 5A to 5I This illustrates some embodiments according to the present invention. Figure 4 A schematic cross-sectional diagram illustrating the operational sequence of the methods described. Detailed Implementation

[0017] The following description is accompanied by accompanying drawings, which are incorporated in and constitute a part of this specification. Figure 1 and Figure 2 Embodiments of the invention are shown, but the invention is not limited to these embodiments. Furthermore, the following embodiments may be suitably combined to complete another embodiment.

[0018] References to "single embodiment," "one embodiment," "exemplary embodiment," "other embodiment," "another embodiment," etc., indicate that embodiments of the invention described as such may include specific features, structures, or characteristics, but not every embodiment must include such specific features, structures, or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, although it may refer to the same embodiment.

[0019] To ensure a complete understanding of the present invention, detailed steps and structures are provided below. It is clear that the implementation of the present invention does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps will not be described in detail again to avoid unnecessarily limiting the present invention. Preferred embodiments of the present invention are described in detail below. However, in addition to the detailed description, the present invention can be widely implemented in other embodiments. The scope of the present invention is not limited to the detailed description but is defined by the claims.

[0020] Hybrid bonding processes bond two or more semiconductor structures by adding additional hybrid bonding layers on each semiconductor structure. The hybrid bonding layers include bonding metals and bonding dielectrics. The bonding metals on the semiconductor structures are bonded to each other, and the bonding dielectrics on the semiconductor structures are bonded to each other. This bonding process can present several challenges. For example, aligning the bonding metals can be challenging due to their small size. Misalignment of the bonded semiconductor structures can lead to electrical failures. This invention provides a method for bonding two or more semiconductor structures without the need for additional hybrid bonding layers. The method provided by this invention reduces the risk of bonding misalignment in the semiconductor structures.

[0021] Figure 1A A semiconductor structure 101A according to some embodiments of the present invention is shown. The semiconductor structure 101A includes a first substrate 100, a first stack pair 15 disposed on the first substrate 100, and a connection unit 25 disposed on the first stack pair 15. The first stack pair 15 includes a first repeating unit 10A bonded to a second repeating unit 20A. The first repeating unit 10A and the second repeating unit 20A are stacked in a face-to-face direction.

[0022] The first repeating unit 10A includes a first dielectric layer 110, a first device 120, and a first interconnect structure 130. In some embodiments, the first repeating unit 10A is supported by a first substrate 100. The first dielectric layer 110, the first device 120, and the first interconnect structure 130 are disposed covering the first substrate 100. The first device 120 and the first interconnect structure 130 are electrically connected to each other and surrounded by the first dielectric layer 110. In some embodiments, the first substrate 100 is located below the first repeating unit 10A and connected to the first dielectric layer 110.

[0023] The second repeating unit 20A covers the first repeating unit 10A. The second repeating unit 20A includes a second dielectric layer 210, a second device 220, and a second interconnect structure 230. The second device 220 and the second interconnect structure 230 are electrically connected to each other and are surrounded by the second dielectric layer 210.

[0024] The first substrate 100 may be a semiconductor substrate such as a bulk silicon (Si) wafer. In some embodiments, the first substrate 100 is a grain-scale silicon substrate. In some embodiments, the first substrate 100 is a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, etc. In some embodiments, the first substrate 100 includes at least one of germanium (Ge), gallium (Ga), arsenic (As), phosphorus (P), indium (In), antimony, SiGe, SiC, GaAs, GaN, GaP, InGaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and other suitable materials. The first substrate 100 includes any type of semiconductor substrate, such as a silicon-on-insulator (SOI) substrate. In some embodiments, the thickness T100 of the first substrate 100 is between about 700 micrometers (μm) and about 900 μm.

[0025] The second dielectric layer 210 is bonded to the first dielectric layer 110. In some embodiments, the first dielectric layer 110 and the second dielectric layer 210 include silicon oxide (SiO2), silicon nitride (SiN), silicon carbonitride (SiCN), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), polymers, etc. In some embodiments, the first dielectric layer 110 and / or the second dielectric layer 210 include a plurality of dielectric layers stacked and covering each other. The dielectric layers may include the same material or different materials. The first dielectric layer 110 and the second dielectric layer 210 may be referred to as interlayer dielectric (ILD) or intermetallic dielectric (IMD). In some embodiments, the thickness T110 of the first dielectric layer 110 and the second dielectric layer 210 is between about 3 μm and about 10 μm, respectively.

[0026] In some embodiments, the first repeating unit 10A includes a plurality of conductive plugs 112 disposed on the first substrate 100 and surrounded by a first dielectric layer 110. The number of conductive plugs 112 is not limited. In some embodiments, the conductive plugs 112 include a first group of conductive plugs 112A and a second group of conductive plugs 112B that are separated from each other. The number of conductive plugs in each group is not limited.

[0027] Figure 1B A schematic cross-sectional view of the first device 120 or the second device 220 is shown. In some embodiments, the first device 120 and the second device 220 are, respectively, or comprise three-dimensional (3D) capacitors. In some embodiments, the 3D capacitor may be a cylindrical capacitor, a crown capacitor, or a concave capacitor. In some embodiments, the first device 120 and the second device 220 are, respectively, or comprise 3D metal-insulator-metal (MIM) capacitors, and such out-of-plane dimensions can advantageously be used to increase the effective MIM area and associated capacitance density. In some embodiments, the first device 120 and the second device 220 of the present invention may each have very high capacitance density, for example, capacitance density may be greater than about 1 μF / mm². In some embodiments, the first device 120 is embedded in the mid-process (MEOL) structure of the first repeating unit 10A, and the second device 220 is embedded in the MEOL structure of the second repeating unit 20A.

[0028] like Figure 1B As shown, in some embodiments, each of the first device 120 and the second device 220 includes a bottom conductive plate 1202, a top conductive plate 1201 covering the bottom conductive plate 1202, and a plurality of 3D capacitor units 912 between the bottom conductive plate 1202 and the top conductive plate 1201. In some embodiments, the distance D1 between the bottom conductive plate 1202 and the top metal plate 1201 is in the range of about 1 μm to about 2 μm, a size significantly smaller than that of conventional active or passive elements (e.g., conventional deep trench capacitors) formed in deep trenches of a substrate.

[0029] Figure 1C An enlarged view of the 3D capacitor unit 912 is shown. The 3D capacitor unit 912 is a cylindrical capacitor, a crown-shaped capacitor, or a concave capacitor. Figure 1D As shown, in this embodiment, each 3D capacitor unit 912 is crown-shaped.

[0030] Return to reference Figure 1CThe 3D capacitor unit 912 includes a first conductive film 914 and a second conductive film 916. The first conductive film 914 and the second conductive film 916 are disposed between a bottom conductive plate 1202 and a top conductive plate 1201. In some embodiments, the first conductive film 914 includes a first portion 914A connected to the bottom conductive plate 1202 and a second portion 914B connected to the first portion 914A and extending from the bottom conductive plate 1202 to the top conductive plate 1201. In some embodiments, the second conductive film 916 is disposed adjacent to the first conductive film 914, connected to the top conductive plate 1201, and extending from the top conductive plate 1201 to the bottom conductive plate 1202. In some embodiments, the second conductive film 916 is perpendicularly intersected with the second portion 914B of the first conductive film 914. For example, as... Figure 1C The cross-sectional view shown indicates that the second conductive film 916 is adjacent to the inner and outer sides of the receiving space 904. In some embodiments, the receiving space 904 is surrounded by the first conductive film 914. In some embodiments, the second portion 914B may have a cylindrical shape.

[0031] Furthermore, the 3D capacitor unit 912 also includes a first insulating film 928 for insulating the first conductive film 914 and the second conductive film 916. In other words, the stacking of the first conductive film 914, the first insulating film 928, and the second conductive film 916 forms the MIM structure of the 3D capacitor unit 912. Figure 1C As shown, in some embodiments, a second insulating film 930 may be selectively used to fill the space between the second conductive film 916 and the top conductive plate 1201. In some embodiments, the first insulating film 928 and the second insulating film 930 each comprise a high-k dielectric material. For example, the high-k dielectric material may comprise at least one oxide of lanthanum (La), hafnium (Hf), and zirconium (Zr).

[0032] Figure 1DAn enlarged view of a first device 120 and a second device 220 showing a semiconductor structure 101A. In some embodiments, the first device 120 includes a first capacitor structure, and the second device 220 includes a second capacitor structure. In some embodiments, the first capacitor structure and the second capacitor structure are electrically connected in parallel. In some embodiments, the first device 120 and the second device 220 use the same capacitor structure. In some embodiments, the first device 120 and the second device 220 use the same capacitor structure having the same capacitance density. In some embodiments, the first device 120 and the second device 220 are electrically connected in parallel. In some embodiments, each of the first capacitor structure and the second capacitor structure of the first device 120 and the second device 220 includes a first node configured to receive a first potential and a second node configured to receive a second potential. The first potential is different from the second potential. In some embodiments, the first potential is a ground (GND) potential, and the second potential is a VDD potential or other operating potential of the first device 120 and the second device 220. In some embodiments, the first potential is a VDD potential and the second potential is a GND potential. In some embodiments, the first node of the first capacitor structure is electrically coupled to the first node of the second capacitor structure, and the second node of the first capacitor structure is electrically coupled to the second node of the second capacitor structure.

[0033] In some embodiments, the bottom conductive plate 1202 is a first node, and the top conductive plate 1201 is a second node. In other embodiments, the top conductive plate 1201 is the first node, and the bottom conductive plate 1202 is the second node. In some embodiments, the bottom conductive plate 1202 of the first device 120 is electrically coupled to the bottom conductive plate 2202 of the second device 220, and the top conductive plate 1201 of the first device 120 is electrically coupled to the top conductive plate 2201 of the second device 220, such as... Figure 1D As shown by the dashed line in the diagram. That is, the first node of the first device 120 is electrically coupled to the first node of the second device 220, and the second node of the first device 120 is electrically coupled to the second node of the second device 220.

[0034] In an embodiment where the first set of conductive plugs 112A and the second set of conductive plugs 112B are disposed on the first substrate 100, a first conductive plate 114A is disposed on the first set of conductive plugs 112A, and a second conductive plate 114B is disposed on the second set of conductive plugs 112B. In such an embodiment, the first conductive plate 114A and the second conductive plate 114B are separate from the substrate 100. The first conductive plate 114A and the second conductive plate 114B are collectively referred to as conductive plate 114.

[0035] In some embodiments, a first device 120 is disposed on and electrically connected to a first conductive plate 114A. The first conductive plate 114A contacts the first device 120 and a first set of conductive plugs 112A and is disposed between the first device 120 and the first set of conductive plugs 112A. The first conductive plate 114A is disposed between the first device 120 and the first substrate 100. The first conductive plate 114A can be used as an electrode of the first device 120. In some embodiments, the first conductive plate 114A is a second node of the first device 120.

[0036] The first interconnect structure 130 includes a plurality of conductive vias 132 and a plurality of wires 134 interconnected with each other. The wires 134 are disposed over the first device 120 and extend laterally at different layers in the first dielectric layer 110. The number of layers of wires 134 is unlimited. The conductive vias 132 extend vertically to connect the wires 134 at different layers.

[0037] In some embodiments, a conductive via 132 is disposed on the second conductive plate 114B and extends partially through the first dielectric layer 110. In some embodiments, the conductive via 132 is electrically coupled to the first device 120 via one or more wires 134. In some embodiments, another conductive via is disposed on the first conductive plate 114A and adjacent to the first device 120. In some embodiments, the wire 134 is electrically coupled to a first node of the first device 120. In some embodiments, the wire 134, the conductive via 132, and the second conductive plate 114B are electrically coupled in series to the first node of the first device 120.

[0038] The first interconnect structure 130 also includes a first metal layer 136, which is the topmost conductor of the first interconnect structure 130. The first metal layer 136 is partially surrounded by a first dielectric layer 110. The first metal layer 136 is disposed to cover and electrically couple to the first device 120. The first metal layer 136 may include a plurality of horizontally arranged metal wires having the same or different lengths.

[0039] In some embodiments, the first metal layer 136 includes a first portion 136A and a second portion 136B separated from the first portion 136A. The lengths of the first portion 136A and the second portion 136B may be the same or different. In some embodiments, the first portion 136A is electrically coupled to a first node of the first device 120. The second portion 136B is electrically coupled to a second node of the first device 120. The second portion 136B is electrically coupled to a first conductive plate 114A through wires and conductive vias in the first interconnect structure 130. The first nodes of the first capacitor structure and the second capacitor structure are respectively electrically coupled to the first portion 136A of the first metal layer 136 and the first portion 236A of the second metal layer 236, and the second nodes of the first capacitor structure and the second capacitor structure are respectively electrically coupled to the second portions 136B of the first metal layer 136 and the second portion 236B of the second metal layer 236.

[0040] The second interconnect structure 230 includes a plurality of conductive vias 232 and a plurality of wires 234 interconnected with each other. The wires 234 extend laterally at different layers in the second dielectric layer 210. The number of layers of wires 234 is unlimited. The conductive vias 232 extend vertically to connect the wires 234 at different layers.

[0041] In some embodiments, the second device 220 is configured to cover the topmost conductor 234 of the second interconnect structure 230. The topmost conductive via 232 is configured to cover such conductor 234 and partially extend through the second dielectric layer 210. In some embodiments, such conductive via 232 is electrically connected to the second device 220 via one or more conductors 234. In some embodiments, the second device 220 may include a structure similar to the first device 120. In some embodiments, the second device 220 is stacked over the first device 120 along a stacking direction. A first node of the second device 220 is adjacent to the first device 120 along the stacking direction. A second node of the second device 220 is distant from the first device along the stacking direction.

[0042] The second interconnect structure 230 also includes a second metal layer 236, which is the bottom conductive layer of the second interconnect structure 230. The second metal layer 236 is partially surrounded by the second dielectric layer 210. The second metal layer 236 may include a plurality of horizontally arranged metal lines having the same or different lengths.

[0043] In some embodiments, the second metal layer 236 includes a first portion 236A and a second portion 236B separate from the first portion 236A. The lengths of the first portion 236A and the second portion 236B may be the same or different. The first portion 236A is electrically coupled to a first node of the second device 220. The second portion 236B is electrically coupled to a second node of the second device 220. The second portion 236B is electrically coupled to the first conductive plate 214A through wires and conductive vias in the second interconnect structure 230.

[0044] In some embodiments, the second metal layer 236 of the second interconnect structure 230 is aligned and bonded to the first metal layer 136 of the first interconnect structure 130. The first metal layer 136 is in direct contact with the second metal layer 236. Each horizontally disposed metal line of the first metal layer 136 is vertically aligned with each horizontally disposed metal line of the second metal layer 236. In some embodiments, a first portion 136A of the first metal layer 136 is aligned and electrically coupled to the first portion 236A of the second metal layer 236. A second portion 136B of the first metal layer 136 is aligned and electrically coupled to the second portion 236B of the second metal layer 236. In some embodiments, the pattern of the second metal layer 236 substantially corresponds to the pattern of the first metal layer 136. In some embodiments, the pattern layout of the second metal layer 236 is a mirror image of the pattern layout of the first metal layer 136, such that when the second metal layer 236 and the first metal layer 136 are bonded face-to-face, the two pattern layouts match each other (e.g., metal to metal, dielectric to dielectric). In some embodiments, the second dielectric layer 210 is bonded to the first dielectric layer 110. In some embodiments, the linewidth of the first metal layer 136 or the second metal layer 236 is in the range of about 1 μm to about 15 μm.

[0045] refer to Figures 1A to 1D In some embodiments, the top conductive plate 1201 of the first device 120 is electrically coupled to a first portion 136A of the first metal layer 136, and the top conductive plate 2201 of the second device 220 is electrically coupled to a first portion 236A of the second metal layer 236. In some embodiments, the bottom conductive plate 1202 of the first device 120 is electrically coupled to a second portion 136B of the first metal layer 136, and the bottom conductive plate 2202 of the second device 220 is electrically coupled to a second portion 236B of the second metal layer 236.

[0046] In some embodiments, the length L1 of the interface between the first portion 136A and the first portion 236A is different from another length L2 of the interface between the second portion 136B and the second portion 236B. In some embodiments, the length L1 is in the range of about 5 μm to about 15 μm. In some embodiments, the first portion 136A and the first portion 236A are electrically coupled to first nodes of the first device 120 and the second device 220, respectively, and the first nodes of the first device 120 and the second device 220 are respectively used to receive a first potential. The first potential is higher than a second potential configured to supply power to the second nodes of the first device 120 and the second device 220. The length L1 is greater than the length L2. In some embodiments, the interface with a longer length (e.g., length L1) may have a lower contact resistance and is selected for high-potential power transmission to reduce RC delay. In some embodiments, the length of the first metal layer 136 may be different from the length of the second metal layer 236. By way of example and not limitation, the length of the first portion 136A of the first metal layer 136 is different from the length of the first portion 236A of the second metal layer 236.

[0047] In some embodiments, a third conductive plate 214A is disposed on and electrically connected to the second device 220. The third conductive plate 214A can be used as an electrode of the second device 220. In some embodiments, a fourth conductive plate 214B is disposed on and electrically connected to the topmost conductive through-hole 232. The third conductive plate 214A and the fourth conductive plate 214B are collectively referred to as conductive plate 214.

[0048] In some embodiments, a third set of conductive plugs 212A is disposed on a third conductive plate 214A, and a fourth set of conductive plugs 212B is disposed on a fourth conductive plate 214B. The number of each set of conductive plugs is not limited. The third set of conductive plugs 212A and the fourth set of conductive plugs 212B are collectively referred to as conductive plugs 212. The third conductive plate 214A contacts the second device 220 and the third set of conductive plugs 212A and is disposed between the second device 220 and the third set of conductive plugs 212A. The conductive plugs 212 and the conductive plate 214 are surrounded by a second dielectric layer 210.

[0049] In some embodiments, the conductive plugs 112 and 212, conductive plates 114 and 214, conductive vias 132 and 232, wires 134 and 234, the first metal layer 136, and the second metal layer 236 are made of the following materials: tungsten (W), copper (Cu), cobalt (Co), aluminum (Al), nickel (Ni), tantalum (Ta), titanium (Ti), molybdenum (Mo), palladium (Pd), platinum (Pt), ruthenium (Ru), iridium (Ir), silver (Ag), gold (Au), or combinations thereof. In some embodiments, some of the conductive plugs 112 and 212, conductive plates 114 and 214, conductive vias 132 and 232, wires 134 and 234, the first metal layer 136, and the second metal layer 236 are made of different conductive materials.

[0050] In some embodiments, the connection unit 25 includes a passivation layer 240 and a plurality of contact pads 250 disposed in the passivation layer 240. In some embodiments, the contact pads 250 are electrically coupled to a first metal layer 136 and a second metal layer 236. In some embodiments, the passivation layer 240 is disposed on a second dielectric layer 210 of the second repeating unit 20A. In some embodiments, the passivation layer 240 is formed of a dielectric material, such as undoped silicate glass, silicon nitride, silicon oxide, silicon oxynitride, etc. In other embodiments, the passivation layer 240 is formed of a polymer material such as epoxy resin, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), etc. In some embodiments, the passivation layer 240 contacts a portion of the second dielectric layer 210.

[0051] A third conductive plate 214A is disposed between the second device 220 and the passivation layer 240. A third set of conductive plugs 212A extends between the third conductive plate 214A and the passivation layer 240. A fourth conductive plate 214B is disposed between one of the topmost conductive through-holes 232 and the passivation layer 240. A fourth set of conductive plugs 212B extends between the fourth conductive plate 214B and the passivation layer 240.

[0052] Contact pads 250 are disposed on the conductive plugs 212 below. Contact pads 250 may be embedded in or at least partially exposed through the passivation layer 240. Contact pads 250 are connected to a third set of conductive plugs 212A and a fourth set of conductive plugs 212B, respectively. Contact pads 250 are electrically connected to the second device 220 and the second interconnect structure 230 via the conductive plugs 212 and the conductive plate 214.

[0053] In some embodiments, a plurality of connection pads 260 are respectively disposed on the underlying contact pads 250. The connection pads 260 are partially surrounded by a passivation layer 240. In some embodiments, the contact pads 250 include a first contact pad 250A and a second contact pad 250B. The first contact pad 250A is configured to receive a first potential from an external power source and is electrically coupled to a first node of the first device 120 and the second device 220. The second contact pad 250B is configured to receive a second potential from an external power source and is electrically coupled to a second node of the first device 120 and the second device 220. In some embodiments, the first potential is an operating potential, such as VDD. The second potential is lower than the first potential (e.g., the operating potential), such as GND. In some embodiments, the first device 120 and the second device 220 are electrically connected in parallel.

[0054] In some embodiments, the conductive plug 112 may not be required in the first repeating unit 10A. In some embodiments, the conductive via 132, the second conductive plate 114B, and the conductive plug 112 may not be required in the first repeating unit 10A. In some embodiments, the contact pad 250 is electrically connected to the second device 220 and the second interconnect structure 230 via the conductive plate 214. The conductive plug 212 is not required in the second repeating unit 20A. In some embodiments, the conductive via 132, the second conductive plate 114B, and the conductive plugs 112 and 212 are retained in the first repeating unit 10A and the second repeating unit 20A. In this embodiment, the first repeating unit 10A and the second repeating unit 20A are similar to each other and can be manufactured under similar process conditions to reduce overall process complexity and cost.

[0055] Figure 1E A semiconductor structure 201A is shown according to some embodiments of the present invention. Figure 1E The semiconductor structure in 201A is similar. Figure 1A For the sake of simplicity, the same components between semiconductor structure 101A and semiconductor structure 201A will not be repeated.

[0056] Semiconductor structure 201A includes a third repeating unit 30A bonded to a fourth repeating unit 40A. The third repeating unit 30A and the fourth repeating unit 40A are respectively similar... Figure 1AThe system comprises a first repeating unit 10A and a second repeating unit 20A. In some embodiments, one of the conductive vias 132 of the first repeating unit 10A is replaced by a first via 125, and one of the conductive vias 232 of the second repeating unit 20A is replaced by a second via 225. The first via 125 may be part of a first interconnect structure 130, and the second via 225 may be part of a second interconnect structure 230. In some embodiments, the first via 125 is electrically coupled to a first device 120, and the second via 225 is electrically coupled to a second device 220. In some embodiments, the first via 125 extends vertically from a first dielectric layer 110 to a first substrate 100. The first via 125 is electrically connected to the first interconnect structure 130. In some embodiments, the first via 125 extends toward and to the first substrate 100. In some embodiments, the second via 225 is vertically disposed in a second dielectric layer 210. In some embodiments, the second via 225 extends toward and contacts one of the contact pads 250. The second through hole 225 is electrically connected to the contact pad 250. The second through hole 225 is electrically connected to the second interconnect structure 230.

[0057] In some embodiments, the conductive plug 112 and the first through hole 125 may not be required in the third repeating unit 30A. In some embodiments, the conductive plug 112 and the first through hole 125 are retained in the third repeating unit 30A. In this embodiment, the third repeating unit 30A and the fourth repeating unit 40A are similar to each other and can be manufactured under similar process conditions to reduce overall process complexity and cost.

[0058] Figure 2 This illustrates some embodiments of the invention for manufacturing... Figure 1A The flowchart of method 500 for semiconductor structure 101A is shown. Method 500 includes multiple operations, and the description and illustrations are not intended to limit the order of operations. Figures 3A to 3L It is a display Figure 2 A schematic cross-sectional view of the operation sequence of method 500.

[0059] exist Figure 2 In operation 501, a first wafer 10 is provided, such as... Figure 3A As shown. The first wafer 10 includes a first substrate 100, a first dielectric layer 110 formed on the first substrate 100, and a first device 120 and a first interconnect structure 130 formed within the first dielectric layer 110. The first substrate 100 has a first surface S1 and a second surface S2 opposite to the first surface S1. The structure covering the first surface S1 can be referred to as a back-end process (BEOL) structure.

[0060] In some embodiments, a first conductive plate 114A is formed on a first set of conductive plugs 112A, and a second conductive plate 114B is formed on a second set of conductive plugs 112B. In such embodiments, the first conductive plate 114A and the second conductive plate 114B are separated from the first surface S1 of the first substrate 100. The first conductive plate 114A and the second conductive plate 114B may be collectively referred to as conductive plate 114. The conductive plate 114 may be made of the same or similar material as the conductive plugs 112. In some embodiments, a first device 120 is formed on the first conductive plate 114A and electrically connected to the first conductive plate 114A. The first conductive plate 114A may serve as an electrode of the first device 120. The first conductive plate 114A is disposed between the first device 120 and the first substrate 100.

[0061] In some embodiments, the first interconnect structure 130 includes a plurality of conductive vias 132 and a plurality of wires 134 interconnected with each other. The wires 134 extend laterally at different layers in the first dielectric layer 110, and the conductive vias 132 extend vertically to connect the wires 134 at different layers. The number of layers of wires 134 is not limited. The first interconnect structure 130 may be made of the same or similar material as the conductive plug 112. In some embodiments, one conductive via 132 is formed on the first conductive plate 114A adjacent to the first device 120, and another conductive via 132 is formed on the second conductive plate 114B. In some embodiments, the wires 134 are formed above the first device 120. In some embodiments, the first interconnect structure 130 is configured to facilitate electrical wiring between devices (e.g., capacitors) formed above the first surface S1 of the first substrate 100, thereby enabling the formation of an ideal circuit.

[0062] exist Figure 2 In operation 503, a first metal layer 136 is formed on the first device 120 of the first wafer 10, such as Figure 3B As shown. Although in Figure 3BWhile not specifically shown, the first metal layer 136 can be formed using a range of processes such as deposition, lithography, etching, and planarization. The first metal layer 136 includes a first portion 136A and a second portion 136B separate from the first portion 136A. The first portion 136A is electrically coupled to a first node 1201 of the first device 120. The second portion 136B is electrically coupled to a second node 1202 of the first device 120. The dimensions of the first portion 136A and the second portion 136B of the first metal layer 136 may be different. In some embodiments, the dimensions of the first portion 136A and the second portion 136B may be designed according to the potential requirements of the first and second nodes of the first device 120. For example, but not limited to, the first node of the first device 120 may be designed to receive an operating potential requiring lower resistance during power transmission, and the first portion 136A of the first metal layer 136 may be designed to have a larger size or a wider length to reduce contact resistance in subsequent bonding processes. For example, but not limited to, a second portion 136B of the second metal layer 236 may be designed to receive a low potential, such as GND or other potentials below the operating potential, and the second portion 136B may be designed to have a smaller size or shorter length compared to the first portion 136A. In some embodiments, the first metal layer 136 is made of aluminum or copper, but the invention is not limited thereto. The first metal layer 136 may be considered as part of the first interconnect structure 130. The top surface of the first metal layer 136 is exposed through the first dielectric layer 110 for subsequent operation. In some embodiments, the first metal layer 136 is a topmost layer of the first interconnect structure 130, and the first interconnect structure 130 is formed in a BEOL structure.

[0063] exist Figure 2 In operation 505, a second wafer 20 is provided, such as Figure 3C As shown. The second wafer 20 can be another first wafer 10 or a wafer similar to the first wafer 10. For ease of discussion, the reference numerals of the components in the first wafer 10 are used with 100 to indicate components in the second wafer 20 that are the same as those in the first wafer 10. In some embodiments, the second wafer 20 includes a second substrate 200, a second dielectric layer 210, a conductive plug 212, a conductive plate 214, a second device 220, and a second interconnect structure 230. The second dielectric layer 210 is formed on the second substrate 200. The conductive plug 212, the conductive plate 214, the second device 220, and the second interconnect structure 230 are formed within the second dielectric layer 210.

[0064] The second interconnect structure 230 includes a plurality of conductive vias 232 and a plurality of conductive wires 234. The second interconnect structure 230 includes a second metal layer 236, which is the bottommost conductive wire of the second interconnect structure 230 after the second wafer 20 is flipped. In some embodiments, the second metal layer 236 is made of aluminum or copper, but the invention is not limited thereto. The second metal layer 236 includes a first portion 236A and a second portion 236B, similar to the first metal layer 136. The first portion 236A and the second portion 236B of the second metal layer 236 are coupled to a first node 2201 and a second node 2202 of the second device 220, respectively. The size or length of the first portion 236A and the second portion 236B of the second metal layer 236 may be different. In some embodiments, the first portion 136A of the first metal layer 136 is electrically connected and directly connected to the first portion 236A of the second metal layer 236, and the second portion 136B of the first metal layer 136 is electrically connected and directly connected to the second portion 236B of the second metal layer 236.

[0065] The second wafer 20 is flipped vertically and positioned above the first wafer 10. The second metal layer 236 of the second wafer 20 is aligned with the first metal layer 136 of the first wafer 10. More specifically, the first portion 236A of the second metal layer 236 is aligned with the first portion 136A of the first metal layer 136. The second portion 236B of the second metal layer 236 is aligned with the second portion 136B of the first metal layer 136.

[0066] exist Figure 2 In operation 507, the second wafer 20 is bonded to the first wafer 10, as follows: Figure 3D As shown. In some embodiments, the second metal layer 236 is attached to the first metal layer 136, and the second dielectric layer 210 is attached to the first dielectric layer 110. For example, the front surface of the first wafer 10 is the surface close to the first metal layer 136 and away from the substrate 100. The back surface of the first wafer 10 faces the front surface. Similarly, the front surface of the second wafer 20 is the surface close to the second metal layer 236 and away from the substrate 200. The back surface of the second wafer 20 faces the front surface. The bonding of the first wafer 10 and the second wafer 20 may be referred to as face-to-face or face-to-face (F2F) wafer bonding. In some embodiments, a heating process such as annealing is used to accelerate the bonding between the first wafer 10 and the second wafer 20. However, the invention is not limited thereto.

[0067] exist Figure 2 In operation 509, the second substrate 200 of the second wafer 20 is removed, such as... Figure 3EAs shown. In some embodiments, the second substrate 200 is removed using a grinding, planarization, or etching process. In some embodiments, the second substrate 200 is removed by dry etching. The conductive plug 212 can serve as an indicator to display a stop signal for dry etching. For example, dry etching is stopped when material of the conductive plug 212 is detected during the dry etching process. That is, the conductive plug 212 serves as a grinding stop or etching stop that can improve process reliability. In such embodiments, the grinding, planarization, or etching process stops once the top surface of the conductive plug 212 is exposed. In some embodiments, the second substrate 200 is removed by wet etching using a highly selective etching solution for the silicon substrate. After the entire second substrate 200 is removed, the second dielectric layer 210 and the conductive plug 212 of the second wafer 20 are exposed. The conductive plug 212 may be partially consumed but remains on the conductive plate 214. After the second substrate 200 is removed, the conductive plate 214 remains embedded in the second dielectric layer 210.

[0068] In some embodiments, a stress-relieving film (not shown) is disposed between the second substrate 200 and the second dielectric layer 210. In some embodiments, the stress-relieving film relieves stress generated between the second substrate 200 and the second dielectric layer 210. The stress-relieving film may comprise silicon nitride or other suitable materials. In some embodiments, the stress-relieving film is formed on the second substrate 200 before the second dielectric layer 210 is deposited on the second substrate 200. In other embodiments, to minimize stress generation, the removal of the second substrate 200 employs a soft polishing or wet polishing process. In other embodiments, the second wafer 20 is annealed to a predetermined temperature to soften the second substrate 200 before polishing the second substrate 200 without adversely affecting the second device 220.

[0069] exist Figure 2 In operation 511, a passivation layer 240 is formed on the second dielectric layer 210 of the second wafer 20, such as Figure 3F As shown. The passivation layer 240 can be formed using chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable methods.

[0070] exist Figure 2 In operation 513, one or more contact pads 250 are formed on the second dielectric layer 210 of the second wafer 20, such as Figure 3GAs shown. Multiple openings exposing the top surface of the conductive plug 212 can be formed in the passivation layer 240 using lithography and etching processes. A conductive material, such as copper, is deposited into these openings using sputtering, electroplating, PVD, or other suitable methods. Excess conductive material covering the top surface of the passivation layer 240 is removed using a planarization process such as chemical mechanical polishing (CMP), thereby forming contact pads 250. In some embodiments, contact pads 250 are electrically connected to the second device 220 and the second interconnect structure 230 via the conductive plug 212 and the conductive plate 214. At this stage, semiconductor structure 101B is formed.

[0071] exist Figure 2 In operation 515, a connecting pad 260 is formed on the contact pad 250, such as Figure 3H As shown. In some embodiments, additional dielectric or polymeric material is deposited to cover contact pad 250 to thicken passivation layer 240. Multiple openings exposing the top surface of contact pad 250 can be formed in the thickened passivation layer 240 using lithography and etching processes. A conductive material, such as aluminum, is deposited into such openings using sputtering, electroplating, PVD, or other suitable methods. An etching process is used to remove some of the conductive material, thereby forming connection pad 260. Connection pad 260 is electrically connected to contact pad 250 to provide external electrical connection. At this stage, semiconductor structure 101A is formed. Semiconductor structure 101B may be further processed to form semiconductor structure 101C, such as... Figures 3I to 3L As shown.

[0072] refer to Figure 3I Two semiconductor structures 101B are provided. One semiconductor structure 101B is flipped over and positioned above the other semiconductor structure 101B. The flipped semiconductor structure 101B includes a second stack pair 16, which is substantially identical to the first stack pair 15. Contact pads 250 are partially surrounded by a passivation layer 240, and the top surface of the contact pads 250 is exposed. The corresponding contact pads 250 of the two semiconductor structures 101B are aligned with each other.

[0073] refer to Figure 3J An upper semiconductor structure 101B is attached to a lower semiconductor structure 101B. In some embodiments, the corresponding contact pads 250 of the two semiconductor structures 101B are bonded to each other. That is, the upper contact pad 250 contacts the lower contact pad 250 respectively. In some embodiments, the respective passivation layers 240 are bonded to each other. The bonding of the two semiconductor structures 101B may be referred to as back-to-back (B2B) wafer bonding. In some embodiments, a heating process such as annealing is used to accelerate the bonding between the upper contact pad 250 and the lower contact pad 250. However, the invention is not limited thereto.

[0074] refer to Figure 3KThe first substrate 100 of the upper semiconductor structure 101B (i.e., the upper first substrate 100) is removed. In some embodiments, the upper first substrate 100 is removed using a grinding, planarization, or etching process. In some embodiments, the grinding, planarization, or etching process stops once the top surface of the upper conductive plug 112 is exposed. After the upper first substrate 100 is removed, the first dielectric layer 110 and the conductive plug 112 of the upper semiconductor structure 101B are exposed. The exposed conductive plug 112 may be partially consumed but remains on the upper conductive plate 114.

[0075] refer to Figure 3L A passivation layer 270 is formed on the exposed upper first dielectric layer 110 and conductive plug 112. The passivation layer 270 may be formed of a material similar to or the same as that of the passivation layer 240. One or more contact pads 280 are formed in the passivation layer 270. A connection pad 290 is formed on each contact pad 280. The connection pad 290 is electrically connected to the contact pad 280 to provide external electrical connection. The passivation layer 270, contact pads 280, and connection pads 290 can be formed using methods similar to operations 511, 513, and 515. At this stage, a semiconductor structure 101C is formed. In some embodiments, the connection pad 290 includes a first connection pad 290A and a second connection pad 290B. Similar to semiconductor device 101A, the first connection pad 290A is electrically coupled to a first node of two first devices 120 and two second devices 220. The second connection pad 290B is electrically coupled to a second node of two first devices 120 and two second devices 220. These four devices, such as two first devices 120 and two second devices 220, are electrically connected in parallel.

[0076] Still referencing Figure 3LSemiconductor structure 101C includes a first stack pair 15 and a second stack pair 16 that stacks over the first stack pair 15. In some embodiments, the first stack pair 15 and the second stack pair 16 are stacked in a back-to-back (B2B) orientation. In some embodiments, the first repeating unit 10A and the second repeating unit 20A of the second stack pair 16 are stacked in a face-to-face orientation. In some embodiments, the first metal layer 130 and the second metal layer 230 in the first stack pair 15 and the second metal layer 230 in the second stack pair 16 are electrically coupled to contact pads 250. A connection unit 25 is inserted between the first stack pair 15 and the second stack pair 16. The contact pad 250 of the connection unit 25 is referred to as an intermediate connection pad. The intermediate connection pad is electrically coupled to a second interconnect structure 230 of the first stack pair 15 and the second stack pair 16. In some embodiments, the first device 120 and the first node of the second device 220 of the first stack pair 15 and the first node of the first device 120 and the second device 220 of the second stack pair 16 are electrically coupled together, and the first device 120 and the second node of the second device 220 of the first stack pair 15 are electrically coupled together with the second node of the first device 120 and the second device 220 of the second stack pair 16.

[0077] Figure 4 This illustrates some embodiments of the invention for manufacturing... Figure 1E The flowchart of method 600 for semiconductor structure 201A is shown. Method 600 includes multiple operations, and the description and illustrations are not intended to limit the order of operations. Figures 5A to 5I It is shown Figure 4 A schematic cross-sectional view of the operation sequence of method 600. Figure 4 Method 600 in many states is similar to Figure 2 Method 500. Therefore, for the sake of brevity, repeated or similar descriptions are omitted.

[0078] exist Figure 4 In operation 601, a third wafer 30 is provided, such as Figure 5A As shown. The third wafer 30 is similar. Figure 3A The first wafer 10 is in the middle. The third wafer 30 includes a first substrate 100, a first dielectric layer 110 formed on the first substrate 100, and a first device 120 and a first interconnect structure 130 formed in the first dielectric layer 110.

[0079] In some embodiments, the third wafer 30 includes a first via 125 extending vertically from the first dielectric layer 110 to the first substrate 100. In some embodiments, the first via 125 is electrically connected to one of the conductors 134 of the first interconnect structure 130. In some embodiments, a pad oxide (not shown) is formed between the first via 125 and the first substrate 100. The first via 125 is electrically insulated from the first substrate 100.

[0080] In some embodiments, the conductive plug 112, conductive plate 114, wire 134 and first through hole 125 are made of tungsten, copper, cobalt, aluminum, nickel, tantalum, titanium, molybdenum, palladium, platinum, ruthenium, iridium, silver, gold and other materials or combinations thereof.

[0081] The first interconnect structure 130 includes a first metal layer 136, which is the topmost conductor of the first interconnect structure 130. In some embodiments, the first metal layer 136 is made of aluminum or copper, but the invention is not limited thereto.

[0082] The first metal layer 136 may include a plurality of conductors having the same or different lengths in a layered configuration. The top surface of the conductors is exposed through the first dielectric layer 110 for subsequent operations.

[0083] exist Figure 4 In operation 603, the fourth wafer 40 is bonded to the third wafer 30, such as... Figure 5B As shown. The fourth wafer 40 may be another third wafer 30 or a wafer substantially identical to the third wafer 30. For ease of reference, elements in the fourth wafer 40 that are identical to elements in the third wafer 30 are indicated by the reference numerals of the elements in the third wafer 30 plus 100. In some embodiments, the fourth wafer 40 includes a second substrate 200, a second dielectric layer 210, a conductive plug 212, a conductive plate 214, a second device 220, a second via 225, and a second interconnect structure 230. The second dielectric layer 210 is formed on the second substrate 200. The conductive plug 212, the conductive plate 214, the second device 220, and the second interconnect structure 230 are formed within the second dielectric layer 210.

[0084] The second via 225 extends vertically from the second dielectric layer 210 to the second substrate 200. The second via 225 is electrically connected to the second interconnect structure 230. In some embodiments, a pad oxide (not shown) is formed between the second via 225 and the second substrate 200. In some embodiments, similar to the first via 125, the second via 225 is electrically insulated from the second substrate 200.

[0085] The second via 225 extends vertically from the second dielectric layer 210 to the second substrate 200. The second via 225 is electrically connected to the second interconnect structure 230. In some embodiments, a pad oxide (not shown) is formed between the second via 225 and the second substrate 200. In some embodiments, similar to the first via 125, the second via 225 is electrically insulated from the second substrate 200.

[0086] The fourth wafer 40 is flipped over and positioned to cover the third wafer 30. Before bonding, the second metal layer 236 of the fourth wafer 40 is aligned with the first metal layer 136 of the third wafer 30. The second metal layer 236 is then attached to the first metal layer 136, and the second dielectric layer 210 is attached to the first dielectric layer 110. The bonding of the third wafer 30 and the fourth wafer 40 can be referred to as F2F wafer bonding. In some embodiments, a heating process such as annealing is used to accelerate the bonding between the third wafer 30 and the fourth wafer 40. However, the invention is not limited thereto.

[0087] exist Figure 4 In operation 605, a portion of the second substrate 200 and the second through-hole 225 is removed from the fourth wafer 40, as follows: Figure 5C As shown. In some embodiments, the second substrate 200 undergoes grinding, planarization, or etching processes. In some embodiments, the grinding, planarization, or etching process stops once the top surface of the conductive plug 212 is exposed. The entire second substrate 200 is removed and a portion of the second via 225 is consumed. This exposes the second dielectric layer 210 and the conductive plug 212 of the fourth wafer 40. The conductive plug 212 may be partially consumed but remains on the conductive plate 214. After the second substrate 200 is removed, the conductive plate 214 remains embedded in the second dielectric layer 210. Figure 5C As shown, the structure between the first substrate 100 and the remaining structure of the fourth wafer 40 can be referred to as the third repeating unit 30A, and the remaining structure of the fourth wafer 40 can be referred to as the fourth repeating unit 40A. At this stage, the third repeating unit 30A and the fourth repeating unit 40A together form a first stacked pair 17. In some embodiments, the first stacked pair 17 is similar to... Figure 3E The first stack pair 15 is different in that the first stack pair 17 includes a through hole such as the first through hole 125.

[0088] exist Figure 4 In operation 607, a passivation layer 240 is formed on the second dielectric layer 210 and the remaining second via 225 of the fourth wafer 40, such as Figure 5D As shown.

[0089] exist Figure 4 In operation 609, one or more contact pads 250 are formed on the second dielectric layer 210 of the fourth wafer 40, such as Figure 5EAs shown. Multiple openings can be formed in the passivation layer 240 using lithography and etching processes to expose the top surfaces of the conductive plug 212 and the second via 225, respectively. A conductive material, such as copper, is deposited into these openings using sputtering, electroplating, PVD, or other suitable methods. Excess conductive material covering the top surface of the passivation layer 240 is removed using a planarization process such as CMP, thereby forming the contact pad 250.

[0090] In embodiments where the fourth wafer 40 does not include any conductive plugs 212, contact pads 250 are respectively disposed on the underlying conductive plate 214 and the second via 225. In some embodiments, at least one of the contact pads 250 is electrically connected to the second device 220 via the conductive plugs 212 and the conductive plate 214. In some embodiments, at least one of the contact pads 250 is electrically connected to the second interconnect structure 230 via the second via 225. At this stage, a semiconductor structure 201B is formed.

[0091] exist Figure 4 In operation 611, a connecting pad 260 is formed on the contact pad 250, such as Figure 5F As shown. In some embodiments, additional dielectric or polymeric material is deposited to cover contact pad 250 to thicken passivation layer 240. One or more openings exposing the top surface of contact pad 250 can be formed in the thickened passivation layer 240 using lithography and etching processes. A conductive material, such as aluminum, is deposited into such openings using sputtering, electroplating, PVD, or other suitable methods. An etching process is used to remove a portion of the conductive material, thereby forming connection pad 260. Connection pad 260 is electrically connected to contact pad 250 to provide external electrical connectivity. At this stage, semiconductor structure 201A is formed. In some embodiments, contact pad 250 includes a first contact pad 250A and a second contact pad 250B. Similar to semiconductor device 101A, the first contact pad 250A is electrically coupled to a first node of the first device 120 and the second device 220. The second contact pad 250B is electrically coupled to a second node of the first device 120 and the second device 220. The first device 120 and the second device 220 are electrically connected in parallel.

[0092] The semiconductor structure 201B can be further processed to form the semiconductor structure 201C, such as... Figure 5G to 5I As shown.

[0093] refer to Figure 5GTwo semiconductor structures 201B are provided. One semiconductor structure 201B is flipped over and positioned to cover the other semiconductor structure 201B. The flipped semiconductor structure 201B includes a second stack pair 18, which is substantially the same as the first stack pair 17. Contact pads 250 are partially surrounded by passivation layers 240, and the top surface of each contact pad 250 is exposed. The corresponding contact pads 250 of the two semiconductor structures 201B are aligned with each other. The upper semiconductor structure 201B is attached to the lower semiconductor structure 201B. In some embodiments, the corresponding contact pads 250 of the two semiconductor structures 201B are bonded to each other. That is, the upper contact pad 250 contacts the lower contact pad 250 respectively. In some embodiments, the respective passivation layers 240 are bonded to each other. The bonding of the two semiconductor structures 201B may be referred to as B2B wafer bonding. In some embodiments, a heating process such as annealing is used to accelerate the bonding between the upper contact pad 250 and the lower contact pad 250. However, the invention is not limited thereto.

[0094] refer to Figure 5H A portion of the first substrate 100 and the first via 125 of the upper semiconductor structure 201B (i.e., a portion of the upper first substrate 100 and the upper first via 125) is removed. In some embodiments, a grinding, planarization, or etching process is performed on the upper first substrate 100. In some embodiments, the grinding, planarization, or etching process stops once the top surface of the upper conductive plug 112 is exposed. The entire upper first substrate 100 is removed and a portion of the upper first via 125 is consumed. After the upper first substrate 100 is removed, the first dielectric layer 110 and the conductive plug 112 of the upper semiconductor structure 201B are exposed. The exposed conductive plug 112 may be partially consumed but remains on the conductive plate 114.

[0095] refer to Figure 5IA passivation layer 270 is formed on the exposed first dielectric layer 110, conductive plug 112, and upper first via 125. The passivation layer 270 may be formed of a material similar to or the same as that of the passivation layer 240. One or more contact pads 280 are formed in the passivation layer 270. Connecting pads 290 are formed on each contact pad 280. The connecting pads 290 are electrically connected to the contact pads 280 to provide external electrical connectivity. Methods similar to operations 607, 609, and 611 can be used to form the passivation layer 270, contact pads 280, and connecting pads 290. At this stage, a semiconductor structure 201C is formed. In some embodiments, the connecting pads 290 include a first connecting pad 290A and a second connecting pad 290B. Similar to the semiconductor device 101C, the first connecting pad 290A is electrically coupled to a first node of two first devices 120 and two second devices 220. The second connecting pad 290B is electrically coupled to a second node of two first devices 120 and two second devices 220. These four devices, such as two first devices 120 and two second devices 220, are electrically connected in parallel.

[0096] Still referencing Figure 5I The semiconductor structure 201C includes a first stack pair 17 and a second stack pair 18 stacked above the first stack pair 17. In some embodiments, the first stack pair 17 and the second stack pair 18 are stacked along a B2B direction. A connection unit 25 is disposed between the first stack pair 17 and the second stack pair 18. The bonding contact pad 250 of the connection unit 25 may be referred to as an intermediate connection pad. The intermediate connection pad is electrically coupled to a second interconnect structure 230 of the first stack pair 17 and a second interconnect structure 230 of the second stack pair 18.

[0097] In the semiconductor structures 101A, 101C, 201A, and 201C of the present invention, two single wafers, for example... Figure 3C The first wafer 10 and the second wafer 20 depicted Figure 5B The bonding between the third wafer 30 and the fourth wafer 40 is performed through the topmost metal layer formed in the BEOL structure (i.e., the first interconnect structure 130 and the second interconnect structure 230). No additional junction dielectric layer and additional bonding pads are required in the bonding process between the two single wafers. Therefore, process costs and complexity are reduced. Although the invention and its advantages have been described in detail, it should be understood that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, many of the processes discussed above can be implemented in different ways and replaced by other processes or combinations thereof.

[0098] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, material compositions, apparatuses, methods, and steps described in the specification. As will be readily understood by those skilled in the art from the content of this invention, existing or future processes, machines, manufactures, material compositions, apparatuses, methods, or steps perform substantially the same function or implement substantially the same function. Therefore, the appended claims are intended to include such processes, machines, manufactures, material compositions, apparatuses, methods, and steps within their scope.

[0099] Symbol Explanation

[0100] 10: First Wafer

[0101] 10A: First repeating unit

[0102] 15: First stack pair

[0103] 16: Second stack pair

[0104] 17: First stack pair

[0105] 18: Second stack pair

[0106] 20: Second wafer

[0107] 20A: Second Repeating Unit

[0108] 25: Connection Unit

[0109] 30: Third wafer

[0110] 30A: Third repeating unit

[0111] 40: Fourth wafer

[0112] 40A: Fourth repeating unit

[0113] 100: First substrate

[0114] 101A: Semiconductor Structure

[0115] 101B: Semiconductor Structure

[0116] 101C: Semiconductor Structure

[0117] 110: First dielectric layer

[0118] 112: Conductive plug

[0119] 112A: First set of conductive plugs

[0120] 112B: Second set of conductive plugs

[0121] 114: Conductive plate

[0122] 114A: First conductive plate

[0123] 114B: Second conductive plate

[0124] 120: First device

[0125] 125: First through hole

[0126] 130: First metal layer

[0127] 132: Conductive through-hole

[0128] 134: Conductor

[0129] 136: Second metal layer

[0130] 136A: Part 1

[0131] 136B: Part Two

[0132] 200: Second substrate

[0133] 201A: Semiconductor Structure

[0134] 201B: Semiconductor Structure

[0135] 201C: Semiconductor Structure

[0136] 210: Second dielectric layer

[0137] 212: Conductive plug

[0138] 212A: Third set of conductive plugs

[0139] 212B: Fourth set of conductive plugs

[0140] 214: Conductive plate

[0141] 214A: Third conductive plate

[0142] 214B: Fourth conductive plate

[0143] 220: Second device

[0144] 225: Second through hole

[0145] 230: Second interconnect structure

[0146] 232: Conductive through-hole

[0147] 234: Conductor

[0148] 236: Second metal layer

[0149] 236A: Part One

[0150] 236B: Part Two

[0151] 240: Passivation layer

[0152] 250: Contact pad

[0153] 250A: First contact pad

[0154] 250B: Second contact pad

[0155] 260: Connecting pad

[0156] 270: Passivation layer

[0157] 280: Contact pad

[0158] 290: Connecting pad

[0159] 290A: First connecting pad

[0160] 290B: Second connecting pad

[0161] 500: Methods

[0162] 501: Operation

[0163] 503: Operation

[0164] 505: Operation

[0165] 507: Operation

[0166] 509: Operation

[0167] 511: Operation

[0168] 513: Operation

[0169] 515: Operation

[0170] 600: Method

[0171] 601: Operation

[0172] 603: Operation

[0173] 605: Operation

[0174] 607: Operation

[0175] 609: Operation

[0176] 611: Operation

[0177] 904: Capacity

[0178] 912: 3D Capacitor Unit

[0179] 914: First conductive film

[0180] 914A: Part One

[0181] 914B: Part Two

[0182] 916: Second conductive film

[0183] 928: First insulating film

[0184] 930: Second insulating film

[0185] 1201: Top conductive plate

[0186] 1202: Bottom conductive plate

[0187] 2201: Top conductive plate

[0188] 2202: Bottom conductive plate

[0189] D1: Distance

[0190] L1: Length

[0191] L2: Length

[0192] S1: First surface

[0193] S2: Second surface

[0194] T100: Thickness

[0195] T110: Thickness

Claims

1. A semiconductor device comprising: A first stack pair and a connecting unit, wherein the first stack pair includes a first repeating unit and a second repeating unit. The first repeating unit includes: First dielectric layer; A first device, which is surrounded by the first dielectric layer; A first interconnect structure includes a first metal layer and is electrically coupled to the first device, the first metal layer covering the first device surrounded by the first dielectric layer. The second repeating unit includes: Second dielectric layer; The second interconnect structure includes a second metal layer bonded to the first metal layer; The second device is surrounded by the second dielectric layer and electrically coupled to the second metal layer; The connection unit includes: The contact pad is electrically coupled to the first metal layer and the second metal layer.

2. The semiconductor device of claim 1, wherein the first metal layer includes a first portion and a second portion separated from the first portion, the second metal layer includes a first portion and a second portion separated from the first portion, the first portion of the first metal layer is electrically connected to and directly connected to the first portion of the second metal layer, and the second portion of the first metal layer is electrically connected to and directly connected to the second portion of the second metal layer.

3. The semiconductor device of claim 2, wherein the first device includes a first capacitor structure, the first capacitor structure including a first node and a second node, the second device includes a second capacitor structure, the second capacitor structure including a first node and a second node, the first node of the first capacitor structure being electrically coupled to the first node of the second capacitor structure, and the second node of the first capacitor structure being electrically coupled to the second node of the second capacitor structure.

4. The semiconductor device of claim 3, wherein the first node of the first capacitor structure and the second capacitor structure are electrically coupled to the first portion of the first metal layer and the second metal layer, respectively, and the second node of the first capacitor structure and the second capacitor structure are electrically coupled to the second portion of the first metal layer and the second metal layer, respectively.

5. The semiconductor device of claim 4, wherein the contact pad comprises: The first contact pad is electrically coupled to the first node of the first capacitor structure and the second capacitor structure, and The second contact pad is electrically coupled to the second node of the first capacitor structure and the second capacitor structure.

6. The semiconductor device of claim 5, wherein the first contact pad is configured to receive a first potential, and the second contact pad is configured to receive a second potential, the second potential being different from the first potential.

7. The semiconductor device of claim 2, wherein the first portion of the first metal layer has a first length, and the second portion of the first metal layer has a second length, the second length being different from the first length.

8. The semiconductor device of claim 3, wherein the first capacitor structure and the second capacitor structure are connected in parallel.

9. The semiconductor device of claim 1, wherein the second interconnect structure further includes a second via electrically coupled to the second device, the second via extending toward and electrically coupled to the contact pad.

10. The semiconductor device of claim 9, further comprising: A substrate located below the first repeating unit and connected to the first dielectric layer, wherein the first interconnect structure further includes a first through-hole extending toward and into the substrate.

11. The semiconductor device of claim 1, further comprising a second stacked pair disposed between the first stacked pair and the contact pad, wherein the second stacked pair comprises: The third repeating unit adjacent to the first stack pair includes: Third dielectric layer; A third device, which is surrounded by the third dielectric layer; and A third interconnect structure includes a third metal layer electrically coupled to the third device; The fourth repeating unit, located away from the first stack pair, includes: Fourth dielectric layer; A fourth interconnect structure, comprising a fourth metal layer bonded to the third metal layer; and A fourth device, which is surrounded by the fourth dielectric layer and electrically coupled to the fourth metal layer, The first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are electrically coupled to the contact pad.

12. The semiconductor device of claim 11, wherein The first device includes a first capacitor structure, which includes a first node and a second node. The second device includes a second capacitor structure, which includes a first node and a second node. The third device includes a third capacitor structure, which includes a first node and a second node. The fourth device includes a fourth capacitor structure, which includes a first node and a second node. The first nodes of the first capacitor structure, the second capacitor structure, the third capacitor structure, and the fourth capacitor structure are electrically coupled together, and the second nodes of the first capacitor structure, the second capacitor structure, the third capacitor structure, and the fourth capacitor structure are electrically coupled together.

13. The semiconductor device of claim 11, wherein the connection unit further includes an intermediate connection pad formed between the first stack pair and the second stack pair, and the intermediate connection pad is electrically connected to the second metal layer of the second repeating unit and the third metal layer of the third repeating unit.

14. The semiconductor device of claim 11, wherein the first repeating unit and the second repeating unit are stacked in a face-to-face direction, the third repeating unit and the fourth repeating unit are stacked in a face-to-face direction, and the first stack pair and the second stack pair are stacked in a back-to-back direction.

15. A semiconductor device comprising: substrate; as well as N stacked pairs are stacked on top of each other on the substrate, wherein each of the N stacked pairs includes a first repeating unit and a second repeating unit, and in each of the N stacked pairs... The first repeating unit includes a first capacitor structure, which includes a first node, a second node, and a first metal layer formed in a first interconnect structure. The second repeating unit includes a second capacitor structure, which includes a first node, a second node, and a second metal layer formed in the second interconnect structure. The first node of the first capacitor structure and the second capacitor structure are electrically connected through the bonding between the first metal layer and the second metal layer, and the second node of the first capacitor structure and the second capacitor structure are electrically connected through the bonding between the first metal layer and the second metal layer. N is an integer and ≥1.

16. The semiconductor device of claim 15, further comprising a connection unit including a first contact pad and a second contact pad, wherein in the N stacked pairs, the first contact pad is electrically coupled to a first node of the first capacitor structure and the second capacitor structure, and in the N stacked pairs, the second contact pad is electrically coupled to a second node of the first capacitor structure and the second capacitor structure.

17. The semiconductor device of claim 16, wherein when N ≥ 2, the connection unit further includes an intermediate connection pad located between two adjacent stacked pairs of the N stacked pairs.

18. A method for manufacturing a semiconductor structure, the method comprising: The facility provides a first wafer including a first substrate, a first dielectric layer on the first substrate, a first device located within the first dielectric layer, and a first metal layer, the first metal layer covering the first device and partially exposed through the first dielectric layer; A second wafer comprising a second substrate, a second dielectric layer located on the second substrate, and a second device located within the second dielectric layer are provided; and a second metal layer that covers the second device and is partially exposed through the second dielectric layer; as well as The second wafer is bonded to the first wafer, wherein the second wafer is disposed to cover the first wafer, the second metal layer is bonded to the first metal layer, and the second dielectric layer is bonded to the first dielectric layer.

19. The method of claim 18, wherein before bonding the second wafer to the first wafer, the second wafer includes a plurality of first conductive plugs between the second device and the second substrate, and removing the second substrate includes at least partially exposing at least one of the plurality of first conductive plugs.

20. The method of claim 18, further comprising: Remove the second substrate until the second dielectric layer is exposed; A first passivation layer is formed on the second dielectric layer; as well as A first pad is formed, which is disposed to cover the second device and is at least partially exposed through the first passivation layer. Removing the second substrate includes grinding, planarizing, or etching the second substrate.

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