Semiconductor device
By combining regular polygonal die design with silicon material cutting channels, the low yield problem of semiconductor dies in the packaging process is solved, achieving uniform stress and high-quality packaging effect, and simplifying the cutting process.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2024-12-11
- Publication Date
- 2026-05-29
AI Technical Summary
Existing semiconductor die design and cutting methods are prone to low yield problems in packaging manufacturing processes, and existing hybrid bonding processes are uneven, resulting in poor packaging quality.
The design employs regular polygonal grains, with equilateral polygonal test key setting areas and cutting channels surrounding the outer edge of the grains. The cutting channels are made solely of silicon material without any metal structure to ensure uniform stress and cutting quality.
By using a uniform die design and cutting method, the operational quality of the packaging manufacturing process is improved, low yield problems are avoided, uniform bonding and flat surfaces of the dies are ensured in subsequent processes, and the cutting process is simplified.
Smart Images
Figure CN122121674A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a die of a regular polygon. Background Technology
[0002] In advanced semiconductor manufacturing, by progressively shrinking component sizes, the integration density of various electronic components can be continuously increased, allowing more electronic components to be integrated and placed within a specific area while occupying a relatively small package volume. Generally, the semiconductor manufacturing process begins with the production of a wafer. First, multiple regions are defined on the wafer, and on each region, various semiconductor manufacturing processes such as deposition, photolithography, etching, or planarization steps are repeatedly used to form various required circuit routes and / or active and passive components. Then, the wafer is diced into multiple dies. Next, using various packaging technologies, the dies are packaged into packages to form individual chips, which are finally electrically connected to a circuit board, such as a printed circuit board (PCB), to enable the formation of various electronic devices and the execution of various programmed processes. To meet various miniaturization requirements, the industry currently uses hybrid bonding processes (also known as metal / dielectric hybrid bonding) for die packaging. However, current die design and die cutting methods are prone to problems such as low yield in subsequent packaging processes, so further improvements are still needed. Summary of the Invention
[0003] One object of the present invention is to provide a semiconductor device comprising a regular polygonal die, or a die assembly comprising a plurality of regular polygonal dies, such that the distance from the center to the edge of each die is equal. In this way, the semiconductor device can be uniformly stressed during subsequent dicing and / or hybrid bonding processes, improving the operational quality of subsequent packaging processes and avoiding problems such as low yield.
[0004] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a die assembly, a test bond setting region, and a dicing channel. The die assembly includes a plurality of dies, each die having a regular polygonal shape. Each die has a plurality of sides, the number of which is a multiple of four and greater than four. The test bond setting region is disposed between the dies and adjacent to one of the sides of each die. The test bond setting region has an equilateral polygonal shape. The dicing channel is disposed around an outer edge of each die and an outer edge of the test bond setting region.
[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including at least one die and a dicing channel. The die has a regular polygonal shape, wherein the die includes a plurality of sides, and the number of such sides is a multiple of four and greater than four. The dicing channel is disposed around an outer edge of the die. Attached Figure Description
[0006] Figures 1 to 2 This is a schematic diagram of a semiconductor device in the first embodiment of the present invention, wherein:
[0007] Figure 1 A top view of a semiconductor device; and
[0008] Figure 2 for Figure 1 A cross-sectional view along tangent A-A';
[0009] Figures 3 to 4 This is a schematic diagram of another semiconductor device in the first embodiment of the present invention, wherein:
[0010] Figure 3 A top view of another semiconductor device; and
[0011] Figure 4 for Figure 3 A cross-sectional view along tangent B-B';
[0012] Figures 5 to 6 This is a schematic diagram of a semiconductor device in a second embodiment of the present invention, wherein:
[0013] Figure 5 A top view of a semiconductor device; and
[0014] Figure 6 This is another top view of a semiconductor device;
[0015] Figure 7 This is a top view schematic diagram of another semiconductor device in the second embodiment of the present invention.
[0016] Symbol Explanation
[0017] 10: Semiconductor devices
[0018] 20: Semiconductor devices
[0019] 30: Semiconductor devices
[0020] 40: Semiconductor devices
[0021] 100: Base
[0022] 102: Dielectric layer
[0023] 110: Grain Set
[0024] 120: Grain
[0025] 122: Side
[0026] 130: Test Key Settings Area
[0027] 132: Side
[0028] 134: Test Bond Structure
[0029] 136: Joining pad
[0030] 138: Internal Wiring Structure
[0031] 140: Cutting Track
[0032] 142: Cutting Track
[0033] 202: Dielectric layer
[0034] 204: Doped region
[0035] 234: Internal Wiring Structure
[0036] 236: Joint pad
[0037] 238: Internal Wiring Structure
[0038] 240: Protective Structure
[0039] 310: Grain Set
[0040] 320: Grain
[0041] 322: Side
[0042] 330: Test Key Settings Area
[0043] 330a: Test Key Setting Area
[0044] 332: Side
[0045] 340: Cutting Track
[0046] 342: Cutting Track
[0047] W1, W3: Width
[0048] W2, W4: Width Detailed Implementation
[0049] To enable those skilled in the art to further understand the present invention, several preferred embodiments of the present invention are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings.
[0050] Please refer to Figures 1 to 2The illustration is a schematic diagram of the semiconductor device 10 in the first embodiment of the present invention, wherein... Figure 1 This is a top view schematic diagram of semiconductor device 10. Figure 2 Then it is Figure 1 A schematic diagram of the cross-section obtained along the tangent line A-A'. First, as... Figure 1 As shown, the semiconductor device 10 includes a die set 110, a test key setting area 130, and a dicing channel 140. The die set 110 includes a plurality of dies 120 arranged in sequence. In one embodiment, the semiconductor device 10 includes, for example, a plurality of die sets 110, and each die set 110 includes four dies 120 arranged in sequence, such as... Figure 1 As shown, but not limited thereto, in other embodiments, each of the grain sets may have other numbers of grains or other arrangements, depending on the actual device requirements.
[0051] Each grain 120 has, for example, a regular polygonal shape and has a plurality of sides 122 of equal length. The number of sides 122 is a multiple of four and greater than four, such that each grain 120 presents, for example, a regular octagon or a regular dodecagon, and has eight sides 122 of equal length (e.g., ...). Figure 1 (As shown) or twelve sides, but not limited thereto. The test key setting area 130 is disposed between the dies 120 of the die set 110, and is the area jointly formed by the side edges 122 on one side of each die 120, and can simultaneously adjoin each die 120. The test key setting area 130 may, for example, have an equilateral polygon shape different from the shape of the die 120 (the regular polygon). Preferably, the test key setting area 130 may also be a regular polygon, and have a relatively smaller number of sides 132 relative to the regular polygon of the die 120. For example, in an embodiment where the die set 110 includes four dies 120, and each die 120 is a regular octagon (including eight sides 122), the test key setting area 130 is jointly formed by the side edges 122 of the four regular octagonal dies 120, thus presenting a regular quadrilateral (including four sides 132 of equal length), such as... Figure 1 As shown, but not limited thereto. That is to say, in this embodiment, the number of chips 120 included in the chip set 110 is defined as the minimum number of chips 120 required to clamp a single test key setting area 130.
[0052] The dicing grooves 140 are arranged around the outer edges of each die 120 and the outer edges of the test bond setting area 130, and preferably consist only of silicon material. That is, the dicing grooves 140 do not have any plugs, wires, conductive pads, or alignment marks or other metal structures. Figure 2As shown, this avoids problems such as surface unevenness after subsequent dicing. In one embodiment, the dicing channel 140 has a width W1, preferably between 10 micrometers (μm) and 30 micrometers, but is not limited thereto. It should be noted that, because the semiconductor device 10 of this embodiment has regular polygonal dies 120, the distance from the center (not shown) of each die 120 to each side 122 is equal, which can improve the bonding quality of the semiconductor device 10 in subsequent manufacturing processes and avoid the problem of uneven edge stress. In addition, since there is no metal structure on the dicing channel 140, the semiconductor device 10 can still maintain an overall flat surface after subsequent die dicing. In this way, each die 120 can be uniformly stressed in subsequent die-to-die or die-to-wafer hybrid bonding manufacturing processes, and maintain better operating quality in subsequent packaging manufacturing processes, thereby effectively improving problems such as low yield.
[0053] For example Figure 1 and Figure 2 As shown, the semiconductor device 10 also includes a substrate 100, and at least one test bond structure 134 and a bonding pad 136 disposed on the substrate 100. The substrate 100 may include, for example, a silicon substrate, an epitaxial silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, while the aforementioned components such as the die 120, the test bond setting area 130, and the dicing channel 140 are respectively disposed on the substrate 100. Specifically, at least one test bond structure 134 is disposed within the test bond setting area 130, and its details include the complete layout or at least a partial structure of various components to be tested, corresponding to an active (active) component or passive (passive) component such as a transistor, a capacitor, or a resistor actually formed in each die 120, or even an analog circuit. Thus, the structural health of the component to be tested in each die 120 can be synchronously simulated by detecting the test bond structure 134. In one embodiment, each grain 120 includes, for example, at least one interconnect structure disposed on the substrate 100. Figure 2 (Not shown), for example, it consists of multiple wires and multiple plug structures stacked in sequence, wherein the at least internal interconnect structure includes low-resistance metal materials such as copper (Cu), aluminum (Al), tungsten (W), or titanium (Ti), preferably copper, but not limited thereto, and the test key setting area 130 is correspondingly provided with at least one test key structure 134 located on the substrate 100, such as Figure 2As shown, the structural health of the interconnect structure is tested in subsequent simulation fabrication processes. Furthermore, in embodiments where the semiconductor device 10 includes multiple die sets 110, the test key structures 134 correspondingly disposed within the multiple test key setting areas 130 may each include different active elements, passive elements, alignment marks, wafer acceptance test pads, or analog circuits, etc.
[0054] At least one test bond structure 134 is disposed within a dielectric layer 102 of the test bond setting area 130 on the substrate 100, and can be further electrically connected to an active element, a passive element, or a circuit (not shown) disposed on or within the substrate 100 via an interconnect structure 138 disposed below. The test bond structure 134 may also include a low-resistance metal material such as copper, aluminum, tungsten, or titanium, preferably copper, but is not limited thereto. A bonding pad 136 is disposed on the at least one test bond structure 134 and electrically connected to the at least one test bond structure 134. The surface of the bonding pad 136 is exposed from the dielectric layer 102, so that the semiconductor device 10 of this embodiment can be electrically connected to other chips or semiconductor devices through the bonding pad 136 as required by actual device requirements. In one embodiment, the dicing channel 140 is formed by first etching a portion of the dielectric layer 102 between each die 120 and the test bond setting area 130 to form a trench (not shown), then performing a deposition and epitaxial fabrication process to fill the trench with silicon material of monocrystalline silicon, polycrystalline silicon, or amorphous silicon, and finally forming the dicing channel 140 consisting only of silicon material through a planarization fabrication process.
[0055] Under this configuration, the semiconductor device 10 of this embodiment can be cut from the dicing channel 140 into multiple wafers in a subsequent wafer dicing process by performing a laser dicing process or a plasma dicing process. Figure 3 and Figure 4The die 120 shown is not limited to this. In another embodiment, the die 120 can also be cut from the dicing channel 140 by a selective etching process of silicon material, such as an etching process. Overall, the semiconductor device 10 according to this embodiment provides a dicing channel 140 consisting only of silicon material without any metal structure thereon, without considering existing problems such as metal residue, surface unevenness, delamination, or peeling that may occur during subsequent cutting. Therefore, the linewidth of the dicing channel 140 can be significantly reduced, so that the width W1 of the dicing channel 140 surrounding the outer edge of each die 120 is, for example, between 10 micrometers and 30 micrometers, but not limited to this. On the other hand, the semiconductor device 10 provides regular polygonal dies 120, so that the distance from the center of each die 120 to each side 122 is equal. This allows for uniform stress when bonding to another die (not shown) or a wafer (not shown) in subsequent hybrid bonding processes, avoiding existing problems such as poor bonding quality at the edges of the die 120. Therefore, the semiconductor device 10 of this embodiment can effectively improve the operational quality of subsequent packaging processes and avoid problems such as low yield.
[0056] Please refer to Figures 3 to 4 The illustration is a schematic diagram of another semiconductor device 20 in the first embodiment of the present invention, wherein... Figure 3 This is a top view schematic diagram of semiconductor device 20. Figure 4 Then it is Figure 3 A schematic diagram of the cross-section obtained along the tangent line B-B'. First, as... Figure 2 As shown, the semiconductor device 20 includes a single die 120 and a dicing channel 240. The structure of the die 120 in the semiconductor device 20 is generally the same as that of the individual dies 120 in the semiconductor device 10, and the similarities will not be described again here. The die 120 has a regular polygonal shape, which includes a plurality of sides 122 of equal length, wherein the number of sides 122 is, for example, a multiple of four and greater than four, preferably eight, but not limited thereto. The dicing channel 142 is disposed around the outer edge of the die 120.
[0057] It should be noted that since no plugs, wires, or other metal structures are provided on the dicing track 142 surrounding the die 120, the linewidth of the dicing track 142 can be significantly reduced, resulting in a relatively small width W2 for the dicing track 142 surrounding the outer edge of the die 120, preferably between 2.5 micrometers and 12.5 micrometers, but not limited thereto. Figure 4As shown, the details of the die 120 include at least one interconnect structure 234 and a bonding pad 236 disposed on the substrate 100. The interconnect structure 234 is disposed, for example, within a dielectric layer 202 on the substrate 100, and includes the same material and structure as at least one test bond structure 134. It can be further electrically connected to a doped region 204 within the substrate 100 via another interconnect structure 238 disposed below. The bonding pad 236 is disposed on the at least one interconnect structure 234 and exposes its surface from the dielectric layer 202. Furthermore, a protective structure 240, such as a guard ring, can be additionally disposed around each die 120.
[0058] Therefore, the die 120 in the semiconductor device 20 can continue to undergo subsequent packaging processes to form a chip, and then be packaged onto a circuit board (not shown) or other secondary packaging substrate via bonding pads 236 provided on the die 120 to produce the required integrated circuit; alternatively, the die 120 can also be directly used as a chip scale package (CSP) for wafer-level packaging, which is beneficial for thin and small packaging applications. In this embodiment, since the die 120 has a regular polygonal shape, the distance from the center (not shown) of each die 120 to each side 122 is equal, so that it can be uniformly stressed in subsequent die-to-die or die-to-wafer hybrid bonding processes, thereby maintaining better operating quality in subsequent packaging processes and effectively improving problems such as low yield.
[0059] Those skilled in the art will readily understand that, to meet actual product requirements, the semiconductor device of the present invention may have other forms, and is not limited to those described in the foregoing embodiments. Other embodiments or variations of the semiconductor device of the present invention will be further described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.
[0060] Please refer to Figures 5 to 6 The illustration is a schematic diagram of the semiconductor device 30 in the second embodiment of the present invention, wherein... Figure 5 This is a top view of semiconductor device 30, and Figure 6 This is another top view of the semiconductor device 30. The structure of the semiconductor device 30 in this embodiment is generally the same as that of the semiconductor device 10 in the previous embodiment, and the similarities will not be described again here. The main difference between this embodiment and the previous embodiment is the shape of the die 320 and / or the number and arrangement of the dies 320 in the die sets 110 and 310.
[0061] In detail, such as Figure 5 As shown, the die set 110 includes four dies 320 arranged in sequence, and each die 320 is a regular dodecagon, etc., with twelve sides 322 of equal length. The test key setting area 330 is set between the dies 320 of the die set 110, including the area formed by at least two sides 322 of each die 320 of the die set 110, and presents an equilateral polygon shape different from the shape of the die 320, for example, as shown. Figure 5 The octagon shown is an equilateral octagon, but not limited to this. That is, the test key setting area 330 has eight sides 322 of equal length, but the distance from its center (not shown) to each side 322 is not all equal. However, in another embodiment, the die set 310 may also optionally include three dies 320 arranged in sequence, and the test key setting area 330a includes the area jointly formed by the side 322 of each die 320 in the die set 310, thus presenting an equilateral triangle (including three sides 322 of equal length) different from the shape of the die 320, such as... Figure 6 As shown. That is, in the embodiment where the die set 310 includes three dies 320, the die set 310 is also defined as the minimum number of dies 320 required to surround a single test key setting area 330 in different arrangements.
[0062] On the other hand, the dicing channels 340 are also arranged around the outer edges of each die 320 and the outer edges of the test bond setting areas 330 and 330a, and consist only of silicon material without any plugs, wires, or other metal structures, so that each die 320 can maintain an overall flat surface after subsequent wafer dicing. Thus, the semiconductor device 30 of this embodiment still has dies 320 that are equilateral polygons (regular dodecagons), which improves the bonding quality of the semiconductor device 30 in subsequent hybrid bonding processes and avoids the problem of uneven edge stress. Furthermore, since the dicing channels 340 do not have any metal structures, the linewidth W3 of the dicing channels 340 can be effectively reduced, for example, to between 10 micrometers and 30 micrometers, and better operating quality can be maintained in subsequent packaging processes, thereby effectively improving problems such as low yield.
[0063] In this configuration, the semiconductor device 30 can also be cut from the dicing channel 340 into multiple pieces, such as..., in a subsequent wafer dicing process, by performing a laser cutting process or a gas cutting process. Figure 7 The grain size shown is 320. Please refer to [reference needed]. Figure 7The illustration shows a top view of another semiconductor device 40 according to a second embodiment of the present invention. The semiconductor device 40 includes a single die 320 and dicing channels 342. The die 320 preferably has a regular dodecagon shape and includes twelve sides 322 of equal length, and the dicing channels 342 are arranged around the outer edge of the die 320. The dicing channels 342 do not have any plugs, wires, or other metal structures, which significantly reduces their linewidth, resulting in a relatively small width W4 around the outer edge of the die 320, preferably between 2.5 micrometers and 12.5 micrometers, but not limited thereto.
[0064] The structure of the die 320 in semiconductor device 40 is generally the same as that of each die 320 in semiconductor device 30, and the similarities will not be described again here. Therefore, semiconductor device 40 can still continue to carry out subsequent packaging manufacturing processes, and package the die 320 to a circuit board (not shown) or other secondary packaging substrate through a bonding pad (not shown) provided on the die 320 to produce the required integrated circuit.
[0065] The semiconductor device of the present invention comprises a dicing channel consisting only of silicon material without any metal structures, thus eliminating existing problems such as metal residue and surface unevenness that may occur during subsequent die cutting. This significantly reduces the linewidth of the dicing channel and simplifies subsequent die cutting processes. Furthermore, the semiconductor device comprises a regular polygonal die or a die set consisting of multiple regular polygonal dies, ensuring that the distance from the center to the edge of each die is equal. This allows the die to be uniformly stressed during subsequent cutting and / or hybrid bonding processes, improving the operational quality of subsequent packaging processes and avoiding problems such as low yield.
[0066] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.
Claims
1. A semiconductor device, comprising: A grain set includes multiple grains, each grain having a regular polygonal shape, wherein each grain has multiple sides, and the number of such sides is a multiple of four and greater than four. A test key setting area is disposed between the dies in the die set and adjacent to at least one of the side edges of each die; the test key setting area has an equilateral polygon shape; and The cutting channels are arranged around the outer edge of each grain and the outer edge of the test bond setting area.
2. The semiconductor device as claimed in claim 1, wherein, The test bond setting area has multiple sides, and the number of these sides of the test bond setting area is less than the number of these sides of each grain.
3. The semiconductor device as claimed in claim 2, wherein, The number of those sides of each grain is eight.
4. The semiconductor device as claimed in claim 2, wherein, The number of the sides of each grain is twelve.
5. The semiconductor device of claim 3, wherein, The number of these sides of the test key setting area is four.
6. The semiconductor device of claim 4, wherein, The number of these sides of the test key setting area is eight.
7. The semiconductor device of claim 6, wherein, The number of grains in this grain set is four.
8. The semiconductor device of claim 4, wherein, The number of these sides of the test key setting area is three.
9. The semiconductor device of claim 8, wherein, The number of grains in this grain set is three.
10. The semiconductor device of claim 1, wherein, The cut track contains only silicon material.
11. The semiconductor device of claim 1, wherein, The width of the cut is between 10 micrometers and 30 micrometers.
12. The semiconductor device of claim 1, further comprising: At least one test key structure is set within the test key setting area.
13. The semiconductor device of claim 12, further comprising: The substrate, the test key setting area and the cutting channel are respectively set on the substrate; At least one interconnect structure is disposed on the substrate and located within each of the grains, the at least one interconnect structure including a structure identical to the at least one test bond structure; and A bonding pad is disposed on the at least one test key structure.
14. A semiconductor device, comprising: The grain has a regular polygonal shape, wherein the grain includes a plurality of sides, and the number of such sides is a multiple of four and greater than four; as well as Cutting channels are arranged around the outer edge of the grain.
15. The semiconductor device of claim 14, wherein, The number of those sides of the grain is eight.
16. The semiconductor device of claim 14, wherein, The number of those sides of the grain is twelve.
17. The semiconductor device of claim 14, wherein, The cut track contains only silicon material.
18. The semiconductor device of claim 17, wherein, The width of the cut is between 2.5 micrometers and 12.5 micrometers.
19. The semiconductor device of claim 18, wherein the die further comprises: Base; as well as At least one interconnect structure is disposed on the substrate.