Power semiconductor module
By setting up a coreless current sensing module within the packaging frame, with the current sensing chip placed inside the busbar via and electrically connected to the pins, the problems of large size and low density of power semiconductor modules are solved, achieving higher power density and lower cost.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHUZHOU CRRC TIMES SEMICON CO LTD
- Filing Date
- 2026-01-15
- Publication Date
- 2026-05-29
AI Technical Summary
How to reduce the size of power semiconductor modules and increase power density to meet the needs of industries such as new energy vehicles.
A power semiconductor chip is packaged using a packaging frame, and a coreless current sensing module is set up inside the packaging frame. The current sensing chip is placed inside the busbar through the through-hole of the packaging frame and electrically connected to the pin to realize the current acquisition function, replacing the sensor module of the downstream electronic control component, improving the current acquisition accuracy and reducing the module size.
It achieves higher power density and lower cost, while improving current acquisition accuracy and reducing the size of power semiconductor modules.
Smart Images
Figure CN122121689A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductors, and more particularly to a power semiconductor module. Background Technology
[0002] Power semiconductor modules are a key component of power electronic systems and are widely used in industries such as new energy vehicles, new energy power generation, and rail transportation. With the booming development of industries like new energy vehicles, the demand for power semiconductor modules is increasing daily, and increasingly stringent requirements are being placed on their size and power density. Therefore, how to reduce the size of power semiconductor modules and increase their power density is a crucial problem that the industry urgently needs to solve. Summary of the Invention
[0003] The purpose of this disclosure is to provide at least one power semiconductor module that can at least solve the problem of how to reduce the size of the power semiconductor module and increase the power density, and can at least achieve the effect of reducing the size of the power semiconductor module and increasing the power density.
[0004] In a first aspect, this disclosure provides a power semiconductor module, including: a substrate, a power semiconductor chip, a packaging frame, a first busbar, a coreless current sensing module, and a first pin; The power semiconductor chip is disposed on the first surface of the substrate; The packaging frame is used to encapsulate the power semiconductor chip; The first end of the first busbar is encapsulated within the encapsulation frame, and the second end of the first busbar extends out of the encapsulation frame. The portion of the first busbar encapsulated within the encapsulation frame has a first through hole, and the encapsulation frame has a second through hole communicating with the first through hole. The coreless current sensing module includes a circuit board on which a current sensing chip is integrated. The current sensing chip is placed in the first through hole through the second through hole. The first end of the first pin is encapsulated within the encapsulation frame and electrically connected to the current sensing chip, while the second end of the first pin extends outside the encapsulation frame.
[0005] Optionally, the outline of the first via is set around the current sensing chip.
[0006] Optionally, the shape of the outline of the first via is consistent with the shape of the outline of the surrounding current sensing chip.
[0007] Optionally, the first busbar has a sheet-like structure, and the first through hole penetrates the first busbar along the thickness direction of the first busbar.
[0008] Optionally, the surface of the encapsulation frame is provided with grooves; The bottom of the groove is provided with the second through hole; The circuit board is embedded in the groove, so that the current sensing chip is placed in the first through hole through the second through hole.
[0009] Optionally, it also includes: a second motherboard and a third motherboard; Wherein, the first end of the second busbar is encapsulated within the encapsulation frame, and the second end of the second busbar extends out of the encapsulation frame; The first end of the third busbar is encapsulated within the encapsulation frame, and the second end of the third busbar extends out of the encapsulation frame; The second busbar and the third busbar have a sheet-like structure; The third busbar has the opposite polarity to the second busbar; The portion of the second busbar away from the first end of the second busbar and the portion of the third busbar away from the first end of the third busbar are stacked together along the thickness direction of the liner.
[0010] Optionally, the extension directions of the first and second ends of the second busbar and the extension directions of the first and second ends of the third busbar are both the first direction; The thickness direction of both the second busbar and the first busbar is the second direction; The second busbar and the third busbar have equal lengths along the third direction; The third direction is perpendicular to the first direction and the second direction.
[0011] Optionally, the edge of the second end of the second busbar is provided with a first notch for stress relief; the edge of the second end of the third busbar is provided with a second notch for stress relief.
[0012] Optionally, the first notch is a strip-shaped notch extending parallel to the extension direction of the first and second ends of the second busbar; the second notch is a strip-shaped notch extending parallel to the extension direction of the first and second ends of the third busbar.
[0013] Optionally, the first notch is located at the middle position of the second end of the second busbar; the second notch is located at the middle position of the second end of the third busbar.
[0014] Optionally, it also includes: a second motherboard and a third motherboard; The first end of the second busbar is encapsulated within the encapsulation frame, and the second end of the second busbar extends out of the encapsulation frame; The first end of the third busbar is encapsulated within the encapsulation frame, and the second end of the third busbar extends out of the encapsulation frame; The third busbar has the opposite polarity to the second busbar; The second busbar and the third busbar have no overlapping portion along the thickness direction of the liner.
[0015] Optionally, the first busbar is an AC busbar, and the second and third busbars are DC busbars; The power semiconductor module includes a three-phase full-bridge circuit for AC / DC conversion, and the three-phase full-bridge circuit includes the power semiconductor chip; The three phases of the AC side of the three-phase full-bridge circuit are respectively connected to one of the first busbars; The DC side of the three-phase full-bridge circuit shares a common set of DC busbars, which includes the second busbar and the third busbar.
[0016] Optionally, the liner has a second surface opposite to the first surface; The power semiconductor module further includes: a substrate; the substrate is located on the second surface of the liner, and a heat dissipation structure is provided on the surface of the substrate facing away from the liner.
[0017] Optionally, it also includes: a second pin; the second pin is located on the substrate, a first end of the second pin is encapsulated within the encapsulation frame, and a second end of the second pin extends outside the encapsulation frame.
[0018] The advantages of this disclosure compared to the prior art are: The power semiconductor module disclosed herein includes a power semiconductor chip disposed on a substrate, which is packaged in a packaging frame. The first end of a first busbar is packaged within the packaging frame. It also includes a coreless current sensing module, which includes a circuit board integrating a current sensing chip. The current sensing chip is placed in the first through-hole of the first busbar through a second through-hole in the packaging frame and electrically connected to the first end of a first pin packaged within the packaging frame, so that it extends out of the packaging frame through the first pin, thereby realizing the current acquisition function of the power semiconductor module. On the one hand, this can replace the solution of assembling a sensor module separately for downstream electronic control components, thereby improving efficiency and reducing the size of the electronic control components, thus achieving higher power density and lower cost. On the other hand, placing the current sensing chip in the first through-hole of the first busbar not only improves the accuracy of current acquisition but also reduces the size of the power semiconductor module, increasing its power density. Attached Figure Description
[0019] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, and these illustrative descriptions do not constitute a limitation on the embodiments.
[0020] Figure 1 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 1 ; Figure 2 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 2 ; Figure 3 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 3 ; Figure 4 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 4 ; Figure 5 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 5 ; Figure 6 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 6 ; Figure 7 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 7 ; Figure 8 This is a schematic diagram of the structure of a power semiconductor module provided in one embodiment of the present disclosure. Figure 8 . Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the various embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this disclosure. The various embodiments can be combined with and referenced by each other without contradiction.
[0022] This embodiment provides a power semiconductor module, such as Figures 1 to 8 It includes: a substrate 110, a power semiconductor chip 210, a package frame 150, a first busbar 120, a coreless current sensing module, and a first pin 140.
[0023] The power semiconductor chip 210 is disposed on the first surface of the substrate 110.
[0024] The packaging frame 150 is used to package the power semiconductor chip 210.
[0025] The first end of the first busbar 120 is encapsulated within the encapsulation frame 150, and the second end of the first busbar 120 extends out of the encapsulation frame 150. The portion of the first busbar 120 encapsulated within the encapsulation frame 150 has a first through hole 121, and the encapsulation frame 150 is provided with a second through hole 151 that communicates with the first through hole 121.
[0026] The coreless current sensing module includes a printed circuit board (PCB) 130, on which a current sensing chip 131 is integrated. The current sensing chip 131 is placed in a first through hole 121 through a second through hole 151.
[0027] The first end of the first pin 140 is encapsulated within the package frame 150 and electrically connected to the current sensing chip 131, while the second end of the first pin 140 extends out of the package frame 150.
[0028] The power semiconductor module in this embodiment includes a power semiconductor chip disposed on a substrate and packaged by a packaging frame. The first end of the first busbar is packaged within the packaging frame. It also includes a coreless current sensing module, which includes a circuit board 130 integrating a current sensing chip 131. The current sensing chip 131 is placed in the first through-hole 121 of the first busbar 120 through the second through-hole 151 of the packaging frame 150 and electrically connected to the first end of the first pin 140 packaged within the packaging frame 150, so that it can be led out of the packaging frame 150 through the first pin 140 to realize the current acquisition function of the power semiconductor module. On the one hand, it can replace the solution of assembling the sensor module separately for downstream electronic control components to improve efficiency and reduce the size of the electronic control components, thereby achieving higher power density and lower cost. On the other hand, placing the current sensing chip 131 in the first through-hole 121 of the first busbar 120 not only improves the accuracy of current acquisition but also reduces the size of the power semiconductor module and increases the power density of the power semiconductor module.
[0029] The number of first busbars 120 can be one or more. The number of current sensing chips 131 integrated in the circuit board 130 is the same as the number of first busbars 120. Each current sensing chip 131 corresponds one-to-one with a first busbar 120. The current sensing chip 131 is used to collect the current of the corresponding first busbar 120. Figure 1 The diagram shows the first mother row of three rows, numbered 120.
[0030] In one exemplary embodiment, such as Figure 5As shown, the first busbar 120 has a sheet-like structure, and the first through hole 121 penetrates the first busbar 120 along its thickness direction. The first busbar 120 has a sheet-like structure and a sufficient flat surface to set the first through hole 121, so that the current sensing chip 131 passes through the first through hole 121 and is placed inside the first through hole 121.
[0031] In one exemplary embodiment, the outline of the first via 121 is arranged around the current sensing chip 131. In this way, the area around the current sensing chip 131 can be very close to the first busbar 120, improving the accuracy of current acquisition.
[0032] In some embodiments, the shape of the outline of the first via 121 is consistent with the shape of the outline of the surrounding current sensing chip 131. For example, the shape of the outline of the side of the current sensing chip 131 surrounded by the first via 121 is rectangular. Then, the shape of the outline of the first via 121 is also rectangular. By setting the shape of the outline of the first via 121 to be consistent with the shape of the outline of the surrounding current sensing chip 131, the distance between the current sensing chip 131 and the first busbar 120 is uniformly set, thereby further improving the accuracy of current acquisition.
[0033] In some embodiments, such as Figure 6 and Figure 7 As shown, the surface of the packaging frame 150 is provided with a groove 152; the bottom of the groove 152 is provided with a second through hole 151; the circuit board 130 is embedded in the groove 152, so that the current sensing chip 131 is placed in the first through hole 121 through the second through hole 151. Figure 6 and Figure 7 for Figure 2 A schematic diagram of the partial structure within the dashed box. Figure 6 To set the coreless current sensing module to its previous state. Figure 7 This describes the state after setting up the coreless current sensing module.
[0034] The number of second through holes 151 is the same as the number of first through holes 121. The second through holes 151 correspond one-to-one with the first through holes 121.
[0035] For example, the first busbar 120 is located on the side of the package frame 150. The current sensing chip 131 is fixed to the side of the package frame 150 by soldering.
[0036] By creating a recess 152 in the packaging frame 150, the circuit board 130 with integrated current sensing chip 131 is embedded in the recess 152 of the packaging frame 150, so that the current sensing chip 131 faces the recess 152 and is placed in the first through hole 121 of the first busbar 120 through the second through hole 151 at the bottom of the recess 152, which further reduces the volume of the power semiconductor module and improves the power density.
[0037] In addition, a cover plate 132 is provided at the top of the groove, which is used to encapsulate the circuit board in the groove 152.
[0038] The first end of the first pin 140 is encapsulated within the package frame 150, which makes it more stable.
[0039] There are multiple first pins 140. The multiple first pins 140 include pins for current signal acquisition and pins for connecting to a power supply.
[0040] The plurality of first pins 140 includes at least one set of first pins 140, the second end of each set of first pins 140 extending outside the package frame 150 around the recess 152 of the package frame 150. In this way, the first pins 140 can be centrally arranged next to the circuit board 130, further reducing the size of the power semiconductor module and increasing the power density.
[0041] In some embodiments, such as Figure 1 , Figure 2 and Figure 3 As shown, the power semiconductor module also includes a second pin 160, which is located on the substrate 110. The first end of the second pin 160 is encapsulated within the package frame 150, and the second end of the second pin 160 extends outside the package frame 150. The second pin 160 is a signal terminal of the power semiconductor module. The second pin 160 can be a solderless press-fit pin or a common solderable pin for prototyping.
[0042] Signal transmission between the power semiconductor module and external circuits can be achieved through the second pin 160.
[0043] The second pin 160 and the first pin 140 can be electrically connected to the same external circuit.
[0044] For example, the power semiconductor chip 210 includes fast recovery diodes (FRDs) and insulated gate bipolar transistors (IGBTs) made of materials such as silicon, silicon carbide (SiC), and gallium nitride (GaN), or includes metal-oxide-semiconductor field-effect transistors (MOSFETs), or includes Schottky barrier diodes (SBDs) and IGBTs, or includes other power semiconductor chips.
[0045] In an exemplary embodiment, the substrate 110 has a second surface opposite to the first surface. The power semiconductor module further includes a substrate 190, which is located on the second surface of the substrate 110. A heat dissipation structure 191 is disposed on the surface of the substrate 190 facing away from the substrate 110. The substrate 190 with the heat dissipation structure 191 mainly serves as a mechanical support, provides a mounting interface, and plays an important role in the overall heat dissipation of the power semiconductor module. The substrate 190 is made of a high thermal conductivity material, such as bare copper, or copper with nickel, silver, or other plating layers. For example, the heat dissipation structure 191 includes one or a combination of at least two of the following: pin fins, tracks, and fins. The shape of the pin fins can be cylindrical, elliptical, prismatic, or square. The arrangement of the heat dissipation structures 191 can be a uniform array or a non-uniform array. The length of the heat dissipation structure 191 (e.g., the length of the pin fins) is less than the depth of the heat sink, and can be 5-6 mm.
[0046] The liner 110 and the substrate 190 can be welded, sintered, or transient liquid phase diffusion welded.
[0047] For example, the power semiconductor chip 210, the substrate 110, and the base plate 190 are arranged in a stacked structure. The power semiconductor chip 210 and the substrate 110 are interconnected through a chip interconnect layer, which is a chip solder layer. The substrate 110 and the base plate 190 are interconnected through a system interconnect layer, which is a system solder layer 114. The heat from the power semiconductor chip 210 is transferred to the coolant through the power semiconductor chip 210, the chip solder layer, the substrate 110, the system solder layer 114, and the base plate 190.
[0048] For example, power semiconductor chips 210 and power semiconductor chips 210, and power semiconductor chips 210 and substrate 110, can be interconnected by copper wires, aluminum wires, copper strips or aluminum strips.
[0049] For example, the interconnect between the power semiconductor chip 210 and the substrate 110 can be achieved using tin-based solder, or processes such as silver sintering or copper sintering.
[0050] For example, power semiconductor chips 210 and power semiconductor chips 210 can be interconnected via bonding wires 220.
[0051] The circuit layout surface of the substrate 190 near the substrate 110 may be provided with bosses for maintaining the uniformity of solder thickness, and the thickness of the bosses is 0.05~0.3mm.
[0052] The first and second surfaces of the substrate 110 are provided with a front copper cladding layer 111 and a back copper cladding layer 112 on the upper and lower surfaces for circuit interconnection. It can be designed in different shapes according to different circuit needs, and the surface can be bare copper, gold plated, nickel, silver or other plating layers.
[0053] For example, the liner 110 is fabricated using processes such as Direct Bonded Copper (DBC) or Active Metal Brazing (AMB). Figure 3 As shown, in the backing plate 110, a ceramic insulating layer 113 is disposed between the front copper clad layer 111 and the back copper clad layer 112. The ceramic material of the ceramic insulating layer 113 includes alumina (Al2O3), and the ceramic insulating layer may be doped with oxides such as zirconium dioxide (ZrO2) to enhance the thermal conductivity or structural strength of the ceramic insulating layer. Alternatively, the ceramic insulating layer may include ceramic materials such as silicon dioxide (Si3N4), aluminum nitride (AlN), or other insulating materials.
[0054] The power semiconductor module in this embodiment is a frame-structured packaged power semiconductor module. The packaging frame 150 of the power semiconductor module can be a plastic frame. For example, the material of the plastic frame is a polymer material, which provides insulation and sealing protection for the power semiconductor chip 210, supports the circuit mounting interface, and has no impact on the module's heat dissipation. It can also be any other material that meets the requirements for pressure and moisture resistance.
[0055] The power semiconductor module also includes silicone gel. Silicone gel enables sealing and protection.
[0056] The first end of the first busbar 120 is built into the encapsulation frame 150 and is integrated into a single frame through injection molding.
[0057] The first busbar 120 has multiple sub-pins at its first end. These sub-pins are electrically connected to the power semiconductor chip via a substrate 110. The connection between the sub-pins of the first busbar 120 and the substrate 110 is achieved by soldering or ultrasonic welding. See also... Figure 1 , Figure 2 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The second end of the first busbar 120 is provided with a third through hole 122, through which it is connected to an external circuit. The connection between the second end of the first busbar 120 and the external circuit can be achieved by screw fastening or by laser welding.
[0058] The second end of the first busbar 120 is parallel to the liner 110. The first end of the first busbar 120 is designed with a bent structure, and the first end of the first busbar 120 is connected to the liner 110 through the bent part. The second end is led out from the side of the encapsulation frame 150 to realize the external interface.
[0059] In some embodiments, the power semiconductor module, see Figure 1 , Figure 2 and Figure 3 It also includes a second busbar 170 and a third busbar 180. The first end of the second busbar 170 is encapsulated within the encapsulation frame 150, and the second end of the second busbar 170 extends outside the encapsulation frame 150. The first end of the third busbar 180 is encapsulated within the encapsulation frame 150, and the second end of the third busbar 180 extends outside the encapsulation frame 150. The second busbar 170 and the third busbar 180 have a sheet-like structure. The polarity of the third busbar 180 is opposite to that of the second busbar 170. The portions of the second busbar 170 and the third busbar 180 located away from their first ends are stacked along the thickness direction of the liner 110.
[0060] The first ends of the second busbar 170 and the third busbar 180 each have multiple sub-pins. The first ends of the second busbar 170 and the third busbar 180 are connected to the substrate 110 through the sub-pins. Figure 2 The diagram illustrates the first end of the third busbar 180 with 5 sub-pins as an example, and the first end of the second busbar 170 with 6 sub-pins as an example. The 6 sub-pins at the first end of the second busbar 170 are divided into two groups of 3 sub-pins each. The 5 sub-pins at the first end of the third busbar 180 are located between the two groups of sub-pins of the second busbar 170.
[0061] The second ends of the second busbar 170 and the third busbar 180 are parallel to the liner 110, and the first ends have bends. The first ends of the second busbar 170 and the third busbar 180 are connected to the liner 110 through the bends.
[0062] Among them, one of the second busbar 170 and the third busbar 180 is the positive electrode, and the other is the negative electrode.
[0063] For example, the number of the second mother row 170 and the third mother row 180 is 1.
[0064] In this embodiment, the second busbar 170 and the third busbar 180 with opposite polarities are sheet-like structures. The portion of the second busbar 170 away from the first end of the second busbar 170 and the portion of the third busbar 180 away from the first end of the third busbar 180 are stacked along the thickness direction of the liner 110, thereby forming a large-area busbar stack structure. This allows the magnetic fields of the second busbar 170 and the third busbar 180 with opposite polarities to cancel each other out, reducing parasitic parameters, i.e., reducing inductance, thereby improving the outflow performance of the power semiconductor module.
[0065] In some embodiments, the extending directions of the first and second ends of the second busbar 170 and the extending directions of the first and second ends of the third busbar 180 are both first directions. The thickness direction of both the second busbar 170 and the first busbar 120 is the second direction; The second busbar 170 and the third busbar 180 have equal lengths along the third direction; The third direction is perpendicular to the first and second directions.
[0066] In this embodiment, by setting the lengths of the second busbar 170 and the third busbar 180 along the third direction to be equal, the stacking lengths of the second busbar 170 and the third busbar 180 in the third direction can be made consistent, resulting in better magnetic field cancellation effect, further reducing inductance and improving the outflow performance of the power semiconductor module.
[0067] In some embodiments, such as Figure 1 and Figure 2 As shown, the edge of the second end of the second busbar 170 is provided with a first notch 171 for stress relief; the edge of the second end of the third busbar 180 is provided with a second notch 181 for stress relief.
[0068] The second busbar 170 and the third busbar 180 are sheet-like structures with a large area. By setting a first notch 171 at the edge of the second end of the second busbar 170 and a second notch 181 at the edge of the second end of the third busbar 180, stress can be effectively released and damage can be avoided.
[0069] In some embodiments, the first notch 171 is a strip-shaped notch extending parallel to the first and second ends of the second busbar 170; the second notch 181 is a strip-shaped notch extending parallel to the first and second ends of the third busbar 180.
[0070] The first notch 171 is located at least in the portion of the second busbar 170 that extends beyond the encapsulation frame 150.
[0071] The second notch 181 is located at least in the portion of the third busbar 180 that extends beyond the encapsulation frame 150.
[0072] By setting the first notch 171 as a strip-shaped notch parallel to the extension direction of the first and second ends of the second busbar 170, and setting the second notch 181 as a strip-shaped notch parallel to the extension direction of the first and second ends of the third busbar 180, stress can be fully released, thus improving the stress release effect.
[0073] In some embodiments, the first notch 171 is located at the middle position of the second end of the second busbar 170; the second notch 181 is located at the middle position of the second end of the third busbar 180.
[0074] Thus, the first notch 171 divides the second end of the second busbar 170 extending outside the packaging frame 150 into two equal parts, and the second notch 181 divides the second end of the third busbar 180 extending outside the packaging frame 150 into two equal parts, which can release stress evenly.
[0075] In some embodiments, such as Figure 8 As shown, the power semiconductor module further includes a second busbar 170 and a third busbar 180. The first end of the second busbar 170 is encapsulated within the package frame 150, and the second end of the second busbar 170 extends outside the package frame 150. The first end of the third busbar 180 is encapsulated within the package frame 150, and the second end of the third busbar 180 extends outside the package frame 150. The polarity of the third busbar 180 is opposite to that of the second busbar 170. The second busbar 170 and the third busbar 180 have no overlapping portion along the thickness direction of the substrate 110.
[0076] The first ends of the second busbar 170 and the third busbar 180 each have multiple sub-pins. The first ends of the second busbar 170 and the third busbar 180 are connected to the substrate 110 through the sub-pins.
[0077] The second ends of the second busbar 170 and the third busbar 180 are parallel to the liner 110, and the first ends have bends. The first ends of the second busbar 170 and the third busbar 180 are connected to the liner 110 through the bends.
[0078] One of the second busbar 170 and the third busbar 180 is the positive terminal, and the other is the negative terminal.
[0079] The second busbar 170 and the third busbar 180 can be set on the same floor, or they can be set on different floors.
[0080] In this embodiment, the second busbar 170 and the third busbar 180 form a non-stacked direct-out structure, each extending independently and directly out of the encapsulation frame 150, allowing for flexible configuration.
[0081] In some embodiments, the first busbar 120 is an AC busbar, and the second busbar 170 and the third busbar 180 are DC buses. The power semiconductor module includes a three-phase full-bridge circuit for AC-DC conversion, the three-phase full-bridge circuit including the power semiconductor chip. Each of the three phases on the AC side of the three-phase full-bridge circuit is connected to a corresponding first busbar 120. The DC side of the three-phase full-bridge circuit shares a set of DC buses, including the second busbar 170 and the third busbar 180.
[0082] The three-phase full-bridge circuit is connected to the external circuit through the second pin 160.
[0083] In one set of DC busbars, the number of the second busbar 170 and the third busbar 180 can be set according to actual needs. For example, the second busbar 170 is the positive terminal and the number is 2. The third busbar 180 is the negative terminal and the number is 1.
[0084] The number of first busbars 120 is 3, and a current sensing chip 131 is set in the first through hole 121 of each first busbar 120.
[0085] The power semiconductor module in this embodiment includes a three-phase full-bridge circuit, with a common DC bus on the DC side, which simplifies the structure and realizes a high-power density module package with a low-power packaging frame structure suitable for automotive-grade applications with a three-phase full-bridge circuit.
[0086] Correspondingly, the circuit board 130 has an integrated three-phase current sensing chip 131 structure, and the circuit board 130 is integrated in the package frame 150.
[0087] The external interfaces of the second busbar 170 and the third busbar 180 are connected to the external circuit using screws and laser welding.
[0088] The substrate 110 in the power semiconductor module is a single substrate, employing a single-substrate three-phase full-bridge circuit layout. The chip layout can be such that the lower-side chips are placed close to the DC bus, and the upper-side chips are placed close to the AC bus, see [reference needed]. Figure 2 The power semiconductor module shown has three lower transistors on top and three upper transistors on the bottom, with the dividing line between the upper and lower transistors perpendicular to the connection between the DC and AC busbars. Alternatively, the dividing line between the upper and lower transistors can be along the connection between the AC and DC busbars. Based on a single-substrate three-phase full-bridge circuit layout, different chip schemes can be flexibly configured according to different power level requirements, achieving module miniaturization and improving power density.
[0089] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the present disclosure.
Claims
1. A power semiconductor module, characterized in that, include: The components include: a substrate, a power semiconductor chip, a packaging frame, a first busbar, a coreless current sensing module, and a first pin. The power semiconductor chip is disposed on the first surface of the substrate; The packaging frame is used to encapsulate the power semiconductor chip; The first end of the first busbar is encapsulated within the encapsulation frame, and the second end of the first busbar extends out of the encapsulation frame. The portion of the first busbar encapsulated within the encapsulation frame has a first through hole, and the encapsulation frame has a second through hole communicating with the first through hole. The coreless current sensing module includes a circuit board on which a current sensing chip is integrated. The current sensing chip is placed in the first through hole through the second through hole. The first end of the first pin is encapsulated within the encapsulation frame and electrically connected to the current sensing chip, while the second end of the first pin extends outside the encapsulation frame.
2. The power semiconductor module according to claim 1, characterized in that, The outline of the first through hole is set around the current sensing chip.
3. The power semiconductor module according to claim 2, characterized in that, The shape of the outline of the first via is consistent with the shape of the outline of the surrounding current sensing chip.
4. The power semiconductor module according to claim 1, characterized in that, The first busbar has a sheet-like structure, and the first through hole penetrates the first busbar along the thickness direction of the first busbar.
5. The power semiconductor module according to claim 1, characterized in that, The surface of the packaging frame is provided with grooves; The bottom of the groove is provided with the second through hole; The circuit board is embedded in the groove, so that the current sensing chip is placed in the first through hole through the second through hole.
6. The power semiconductor module according to claim 1, characterized in that, Also includes: Second and third motherboards; Wherein, the first end of the second busbar is encapsulated within the encapsulation frame, and the second end of the second busbar extends out of the encapsulation frame; The first end of the third busbar is encapsulated within the encapsulation frame, and the second end of the third busbar extends out of the encapsulation frame; The second busbar and the third busbar have a sheet-like structure; The third busbar has the opposite polarity to the second busbar; The portion of the second busbar away from the first end of the second busbar and the portion of the third busbar away from the first end of the third busbar are stacked together along the thickness direction of the liner.
7. The power semiconductor module according to claim 6, characterized in that, The extension directions of the first and second ends of the second busbar and the extension directions of the first and second ends of the third busbar are both the first direction; The thickness direction of both the second busbar and the first busbar is the second direction; The second busbar and the third busbar have equal lengths along the third direction; The third direction is perpendicular to the first direction and the second direction.
8. The power semiconductor module according to claim 6 or 7, characterized in that, The edge of the second end of the second busbar is provided with a first notch for stress relief; the edge of the second end of the third busbar is provided with a second notch for stress relief.
9. The power semiconductor module according to claim 8, characterized in that, The first notch is a strip-shaped notch extending parallel to the first and second ends of the second busbar; the second notch is a strip-shaped notch extending parallel to the first and second ends of the third busbar.
10. The power semiconductor module according to claim 9, characterized in that, The first gap is located at the middle position of the second end of the second busbar; the second gap is located at the middle position of the second end of the third busbar.
11. The power semiconductor module according to claim 1, characterized in that, Also includes: Second and third motherboards; The first end of the second busbar is encapsulated within the encapsulation frame, and the second end of the second busbar extends out of the encapsulation frame; The first end of the third busbar is encapsulated within the encapsulation frame, and the second end of the third busbar extends out of the encapsulation frame; The third busbar has the opposite polarity to the second busbar; The second busbar and the third busbar have no overlapping portion along the thickness direction of the liner.
12. The power semiconductor module according to claim 6 or 11, characterized in that, The first busbar is an AC busbar, and the second and third busbars are DC busbars; The power semiconductor module includes a three-phase full-bridge circuit for AC / DC conversion, and the three-phase full-bridge circuit includes the power semiconductor chip. The three phases of the AC side of the three-phase full-bridge circuit are respectively connected to one of the first busbars; The DC side of the three-phase full-bridge circuit shares a common set of DC busbars, which includes the second busbar and the third busbar.
13. The power semiconductor module according to claim 1, characterized in that, The liner has a second surface opposite to the first surface; The power semiconductor module further includes: a substrate; the substrate is located on the second surface of the liner, and a heat dissipation structure is provided on the surface of the substrate facing away from the liner.
14. The power semiconductor module according to claim 1, characterized in that, Also includes: Second pin; The second pin is located on the substrate, the first end of the second pin is encapsulated within the encapsulation frame, and the second end of the second pin extends outside the encapsulation frame.