Method and apparatus for controlling transmit power level as a function of preamble bit length

Abstract

In one example, a method of a transceiver includes receiving a first communication signal including a first message, detecting a signal strength of the first communication signal, generating a preamble having a preamble bit length adjusted based at least in part on the detected signal strength of the first communication signal, and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.

Description

Priority Statement

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 594,916, filed October 31, 2023, entitled “Apparatus and Method for Controlling Transmit Power Level According to Preamble Length,” filed under 35 USC § 119(e), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to transceivers, and more specifically to methods and apparatus for controlling the transmit power level of a transceiver based on the preamble bit length of a message preamble. Background Technology

[0003] In a transceiver, reducing the power of the signals is desirable, as long as it does not adversely affect the delivery of the message carried by the transmitted signals. In one or more examples, the transceiver may be a battery-powered wireless transceiver for use in a wireless personal area network. Attached Figure Description

[0004] Although this disclosure concludes with claims that particularly point out and clearly claim protection for particular embodiments, the various advantages of the examples within the scope of this disclosure will be more readily apparent from the following description when read in conjunction with the accompanying drawings, in which:

[0005] Figure 1 It is a depiction of a communication system comprising a transceiver of a first communication device and a transceiver of a second communication device, based on one or more examples;

[0006] Figure 2 depicts the scene in Figure 1 The preamble of the message transmitted between transceivers;

[0007] Figures 3A, 3B and 3C depict a preamble with a variable preamble bit length for transmit power level control, according to one or more examples.

[0008] Figure 4A It is a message flow diagram of a message flow that wirelessly communicates between transceivers for sending power level control messages, based on one or more examples.

[0009] Figure 4B It is a message flow diagram of a message flow that wirelessly communicates between transceivers for sending power level control messages, based on one or more examples.

[0010] Figure 5A This is a flowchart of a method for a first transceiver, based on one or more examples, to control the transmit power level of a second transceiver according to the preamble bit length of the preamble;

[0011] Figure 5B This is a flowchart of a more detailed method for a first transceiver, based on one or more examples, to control the transmit power level of a second transceiver according to the preamble bit length of the preamble;

[0012] Figure 6A This is a flowchart of a method for a second transceiver, based on one or more examples, to control the transmit power level according to the preamble bit length of the preamble received from the first transceiver;

[0013] Figure 6B This is a flowchart of a more detailed method for a second transceiver, based on one or more examples, to control the transmit power level according to the preamble bit length of the preamble received from the first transceiver;

[0014] Figure 7 It is a block diagram of a communication device including a transceiver PHY, based on one or more examples;

[0015] Figure 8 It is a schematic block diagram of electronic circuitry in one or more examples of a transceiver (e.g., a transceiver PHY) for controlling the transmit power level based on the preamble bit length;

[0016] Figure 9 This is based on one or more examples for controlling the transmit power level according to the preamble bit length. Figure 8 A schematic block diagram of the preamble sequence generator circuit of the electronic circuit;

[0017] Figure 10 It is a schematic block diagram of electronic circuitry in one or more examples of a transceiver (e.g., a transceiver PHY) for controlling the transmit power level based on the preamble bit length;

[0018] Figure 11 It is a schematic block diagram of electronic circuitry in a transceiver according to one or more examples for controlling the transmit power level based on the preamble bit length;

[0019] Figure 12 It is a schematic block diagram of electronic circuitry in a transceiver according to one or more examples for controlling the transmit power level based on the preamble bit length;

[0020] Figure 13 It is a flowchart of a method for controlling the transmit power level based on the preamble bit length using one or more examples;

[0021] Figure 14 It is the protocol stack associated with the IEEE 802.15.4 standard for Low-Rate Wireless Personal Area Networks (LR-WPAN); and

[0022] Figure 15 It is a block diagram of a circuit that can be used in some examples to implement the various functions, operations, actions, processes and / or methods disclosed herein. Detailed Implementation

[0023] In the following detailed description, reference is made to the accompanying drawings, which form part of this disclosure, and specific examples in which this disclosure may be practiced are shown by way of example. These examples are described in sufficient detail to enable those skilled in the art to practice this disclosure. However, other examples enabled herein may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of this disclosure.

[0024] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of this disclosure. In some cases, for the reader's convenience, similar structures or components in the various figures may retain the same or similar designations; however, similarity in designations does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other property.

[0025] The following description may include examples to help enable those skilled in the art to practice the disclosed examples. The use of the terms “exemplary,” “for example,” and “e.g.” indicates that the related description is illustrative, and while the scope of this disclosure is intended to cover examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of this disclosure to the specified parts, steps, features, functions, etc.

[0026] It should be readily understood that the components of the examples, as generally described herein and illustrated in the accompanying drawings, can be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of this disclosure, but rather to represent various examples only. While various aspects of these examples are presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0027] Furthermore, the specific embodiments shown and described are merely examples and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Components, circuits, and functions may be shown in block diagram form so as not to obscure this disclosure with unnecessary detail. Rather, the specific embodiments shown and described are merely exemplary and should not be construed as the only way to implement this disclosure unless otherwise indicated herein. Additionally, block definitions and logical partitioning between blocks are examples of specific embodiments. It will be apparent to those skilled in the art that this disclosure can be practiced with many other partitioning solutions. In most cases, details regarding timing considerations, etc., have been omitted, as such details are not necessary for obtaining a full understanding of this disclosure and are within the capabilities of those skilled in the art.

[0028] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For clarity of presentation and description, some figures may illustrate a signal as a single signal. It should be understood by those skilled in the art that a signal may represent a signal bus, wherein the bus may have multiple bit widths, and this disclosure can be implemented on any number of data signals, including a single data signal.

[0029] The various exemplary logic blocks, modules, and circuits described in conjunction with the examples disclosed herein can be implemented or carried out using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (which may also be referred to herein as a host processor or simply host) can be a microprocessor, but in alternative embodiments, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. When a general-purpose computer including a processor is used to execute computational instructions (e.g., software code) related to the examples of this disclosure, the general-purpose computer is considered a special-purpose computer.

[0030] Examples can be described based on processes depicted as flowcharts, schematic diagrams, structural diagrams, or block diagrams. While a flowchart may describe operable actions as a continuous process, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. Furthermore, the order of actions can be rearranged. Processes in this document may correspond to methods, threads, functions, procedures, subroutines, subroutines, other structures, or combinations thereof. Furthermore, the methods disclosed herein can be implemented in hardware, software, or both. If implemented in software, functions may be stored or transmitted as one or more instructions or code onto a computer-readable medium. Computer-readable media includes both computer storage media and communication media, which includes any medium that facilitates the transfer of a computer program from one location to another.

[0031] Any reference to elements in this document using names such as “first”, “second”, etc., does not limit the number or order of those elements unless such limitation is explicitly stated. Rather, these names may be used herein as a convenient way to distinguish between two or more elements or instances of elements. Thus, referring to a first element and a second element does not imply that only two elements can be used there, or that the first element must somehow precede the second element. Furthermore, unless otherwise specified, a group of elements may include one or more elements.

[0032] As used herein, the term “substantially” means, and includes, the degree to which a given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances, as would be understood by one of ordinary skill in the art. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied at least 90%, at least 95%, or even at least 99%.

[0033] Wireless output power is characterized by the inverse square law of distance: when the distance between wireless transceivers doubles, four (4) times the output power should be used for transmission. In some wireless systems, a wireless transceiver operates at (e.g., always) maximum power output regardless of the distance of the other wireless transceiver. That is, some existing solutions utilize a constant maximum output power for transmission, which can be inefficient or wasteful in some cases. However, power savings can be achieved if feedback is available. To illustrate this by example, if a wireless transceiver has a maximum range of twenty (20) meters and another wireless transceiver is known to be only ten (10) meters away, the transceiver may only need to transmit at one-quarter (¼) of its output power. This reduction would result in significant power savings and is particularly valuable for embedded devices powered by one or more batteries.

[0034] Figure 1This is a depiction of a communication system 100 including a transceiver 102 of a first communication device and a transceiver 104 of a second communication device, according to one or more examples. Each transceiver in transceivers 102 and 104 includes at least a transmitter portion and a receiver portion. In one or more examples, each transceiver in transceivers 102 and 104 is or includes a transceiver PHY, which will be discussed later. Figure 7 A portion of the communication equipment shown and described.

[0035] In one or more examples, transceiver 102 and transceiver 104 communicate with each other via wireless communication signals. Here, transceiver 102 may be or include a wireless transceiver including an antenna 106 for transmitting wireless communication signals received at transceiver 104, and transceiver 104 may be or include a wireless transceiver including an antenna 108 for transmitting wireless communication signals received at transceiver 102.

[0036] In one or more examples, transceiver 102 and transceiver 104 communicate with each other according to a predetermined communication protocol. The predetermined communication protocol may be part of a communication standard (e.g., an industry-adopted communication standard). In one or more examples, transceiver 102 and transceiver 104 communicate with each other according to a Wireless Personal Area Network (WPAN) standard (such as the Low Rate (LR) WPAN (LR-WPAN) standard or the Institute of Electrical and Electronics Engineers (IEEE) 802.15.4).

[0037] In one or more alternative examples, transceiver 102 and transceiver 104 are configured according to different communication standards, such as Bluetooth or Bluetooth Low Energy (BLE) standards (e.g., Bluetooth). ® They communicate with each other using core specifications, sub-GHz standards (e.g., IEEE 802.15.4g), Wi-Fi standards (e.g., IEEE 802.11), etc. Bluetooth ® It is a registered trademark of Bluetooth Special Interest Group (SIG), Inc. (Kirkland, Washington, USA).

[0038] like Figure 1As depicted, transceiver 102 can transmit a wireless communication signal, including message 110, to transceiver 104. In one or more examples, message 110 includes a PHY Protocol Data Unit (PPDU) 105 associated with a communication standard (e.g., the IEEE 802.15.4 standard). In one or more examples, message 110 has a message format that includes a synchronization header (SHR) 107 with a preamble 112 and a start frame delimiter (SFD) 114, a payload 116 (e.g., a PHY payload), and a cyclic redundancy check (CRC) 118. The SHR 107, including the preamble 112, is used at least for timing synchronization between transceivers 102 and 104. The SFD 114 is used to indicate the end of the preamble 112 and the beginning of the payload 116. The CRC 118 is used to ensure the integrity of the payload 116.

[0039] The corresponding transceivers in transceivers 102 and 104 include state machines. When a wireless communication signal including message 110 is transmitted from transceiver 102 to transceiver 104, the preamble 112 of SHR 107 places the receiver section of transceiver 104 into a predetermined state. Upon receiving SFD 114, the receiver section is enabled to receive and store the PHY content from payload 116. Upon receiving CRC 118, the receiver section checks the integrity of the PHY content. The received signal strength of the wireless communication signal is evaluated via an analog-to-digital converter (ADC). In one or more example environments where the receiver section has a receiver sensitivity of -90 dBm: if the received signal is -80 dBm, the signal strength is sufficient; if the received signal is -75 dBm or greater, the signal is too strong (e.g., the battery power of transceiver 102 is wasted); if the received signal is -85 dBm or less, the signal is too weak (e.g., data is not being adequately received at transceiver 104).

[0040] According to one or more examples, transceivers 102 and 104 may use the preamble bit length of the preamble 112 of message 110 to control or adjust the transmission power level. According to one or more examples, a respective transceiver in transceivers 102 and 104 commands another transceiver to adjust its transmission power level according to the preamble bit length of the preamble. In one or more examples, a transceiver detects the preamble bit length of the preamble of a message received from another transceiver and adjusts the transmission power level of the communication signal used to transmit to the other transceiver based on that preamble length. In one or more other examples, a transceiver detects the signal strength of a first communication signal from another transceiver and, in response, transmits a second communication signal to the other transceiver having a preamble with a preamble bit length adjusted based on the detected signal strength. Here, the preamble with the preamble bit length is used to adjust the transmission power level for transmission at the other transceiver.

[0041] Figure 2 depicts the scene in Figure 1 The preamble 112 is used to communicate message 110 between transceivers 102 and 104. The preamble 112 may include a pre-defined sequence or pattern of binary values ​​(e.g., +1 or -1). The preamble 112, including the pre-defined sequence, has a preamble bit length defined by the number of pre-defined bits, where corresponding bits have the same duration. In Figure 2, the preamble 112 is indicated as having a preamble bit length of X bits. The preamble 202 with a bit length of X bits may be a preamble commonly or universally used in communication (e.g., in a particular wireless communication system), a preamble with a minimum preamble bit length for communication, and / or a preamble specified or indicated in the technical specifications of a communication standard used for communication.

[0042] In a specific, non-limiting example of Figure 2, preamble 112 has a preamble bit length of sixteen (16) bits (i.e., X = 16 bits), compatible with the communication standard associated with IEEE 802.15.4. Here, the pre-signal sequence or pattern is a 16-bit sequence of alternating +1 and -1 binary values. In one or more other examples, the preamble bit length of preamble 112 may be thirty-two (32) bits (i.e., X = 32 bits).

[0043] Figures 3A, 3B, and 3C depict a preamble 302 with a variable preamble bit length for transmit power level control, according to one or more examples. In one or more examples, the preamble 302 of Figures 3A, 3B, and 3C is compatible with the communication standard (i.e., IEEE 802.15.4) associated with the preamble 112 of Figure 2. In one or more examples, the corresponding preambles in the preamble 302 of Figures 3A, 3B, and 3C have the same preamble sequence or pattern (e.g., alternating +1 and -1 binary values) but have different corresponding bit lengths.

[0044] In one or more examples, the preamble 302 of Figure 3A has a preamble bit length of A bits, the preamble 302 of Figure 3B has a preamble bit length of (AZ) bits, and the preamble 302 of Figure 3C has a preamble bit length of (A+Z) bits. Here, A and Z are predetermined positive integer constants, where A>Z. In one or more other examples, A bits = (X+Y) bits, where X is a predetermined preamble bit length of the preamble specified in the communication standard (e.g., IEEE 802.15.4) to which the transceiver is compatible, X and Y are predetermined positive integer constants, and Y>Z.

[0045] In one or more examples, when transmitting from the first transceiver, the preamble 302 of FIG3A with a preamble bit length of A bits is used to control the second transceiver to maintain its current transmit power level. When receiving at the second transceiver, the preamble 302 of FIG3A with a preamble bit length of A bits causes the current transmit power level of the second transceiver to be maintained (i.e., the current transmit power level does not change).

[0046] In one or more examples, when transmitting from the first transceiver, the preamble 302 of FIG. 3B, with a preamble bit length of (AZ) bits, is used to control the second transceiver to reduce its current transmit power level. When receiving at the second transceiver, the preamble 302 of FIG. 3B, with a preamble bit length of (AZ) bits, causes the second transceiver's current transmit power level to decrease. In one or more examples, the preamble 302 of FIG. 3B, with a preamble bit length of (AZ) bits, causes the transmit power level to decrease by a predetermined adjustment amount, so that the transmit power level decreases incrementally.

[0047] In one or more examples, when transmitting from the first transceiver, the preamble 302 of FIG. 3C, having a preamble bit length of (A+Z) bits, is used to control the second transceiver to increase its current transmit power level. When receiving at the second transceiver, the preamble 302 of FIG. 3C, having a preamble bit length of (A+Z) bits, causes the second transceiver's current transmit power level to increase. In one or more examples, the preamble 302 of FIG. 3C, having a preamble bit length of (A+Z) bits, causes the transmit power level to increase by a predetermined adjustment amount, so that the transmit power level increases incrementally.

[0048] In a specific, non-limiting example, for a communication standard associated with IEEE 802.11, X = 16 bits (e.g., preamble 112 in Figure 2). Even more specifically, Y = 8 bits and Z = 4 bits. When X = 16 bits, Y = 8 bits, and Z = 4 bits, the preamble bit length of A = (16 + 8) bits = 24 bits (Figure 3A); the preamble bit length of (AZ) bits = (24 - 4) bits = 20 bits (Figure 3B); and the preamble bit length of (A + Z) bits = (24 + 4) bits = 28 bits (Figure 3C).

[0049] In one or more alternative examples, X = 32 bits, Y = 8 bits, and Z = 4 bits. When X = 32 bits, Y = 8 bits, and Z = 4 bits, the preamble length of A = (32 + 8) bits = 40 bits; the preamble length of (AZ) bits = (32 - 4) bits = 28 bits; and the preamble length of (A + Z) bits = (32 + 4) bits = 36 bits.

[0050] In one or more examples, the value of Y is chosen to be greater than the tolerance for the missing preamble bits (e.g., T bits) for valid preamble detection. The receiver PHY may not receive every single preamble bit when it detects the preamble through the receiver portion of the transceiver. Instead, the receiver PHY may be adapted to tolerate a certain number of missing preamble bits while still considering the preamble valid and / or detected. In one or more examples, for X=16 bits, the tolerance for the missing preamble bits for a validly detected preamble is T=1; therefore, Y may be chosen as any positive integer greater than or equal to two (2). In one or more other examples, for X=16 bits, the tolerance for the missing preamble bits for a validly detected preamble is T=3; therefore, Y may be chosen as any positive integer greater than or equal to four (4). On the other hand, in one or more alternative examples, the receiver tolerance is zero (i.e., T=0), where Y may be chosen as any positive integer (i.e., Y>0).

[0051] In one or more other examples, any suitable number of bits may be used for the preamble bit length and / or the values ​​of X, Y, A, and Z. In one or more other examples, different preamble bit lengths may be used to provide different corresponding transmit power level control (e.g., a (AZ) bit preamble bit length may be used to command an increase in the transmit power level, and a (A+Z) bit preamble bit length may be used to command a decrease in the transmit power level). In one or more other examples, the preamble bit length may be used to provide control different from transmit power level control (e.g., PHY-level control) (e.g., a variable preamble bit length may be used to provide signal frequency control; for example, to maintain, increase, or decrease the transmit signal frequency or the receive signal frequency).

[0052] In one or more alternative examples, an X-bit preamble length is used to maintain the current transmit power level, a (X+J)-bit preamble length is used to increase the current transmit power level, and a (X+K)-bit third preamble length is used to decrease the current transmit power level. Here, X is a predetermined preamble length specified in the communication standard (e.g., IEEE 802.15.4) compatible with the transceiver, X, J, and K are predetermined positive integer constants, and J ≠ K. Here, in one or more examples compatible with IEEE 802.15.4, X = 16 bits, J = 8 bits, and K = 16 bits (i.e., the bit length matching the corresponding bit lengths associated with preamble 112 of FIG. 2, preamble 302 of FIG. 3A, and preamble 302 of FIG. 3C). In one or more alternative examples, X = 32 bits, J = 8 bits, and K = 16 bits.

[0053] Figure 4A This is a message flow diagram of message flow 400A, wirelessly communicated between transceiver 102 and transceiver 104 according to one or more examples, for transmitting power level control. According to one or more examples, message flow 400A indicates processing for transmitting power level control based on the preamble bit length. In one or more examples, the action of message flow 400A is implemented in the transceiver PHY (e.g., in PHY circuitry) for end-to-end PHY-level control of the transmit power level.

[0054] In message flow 400A, at action 402, transceiver 102 sends a first communication signal including a first message (e.g., message 110) to transceiver 104. Transceiver 104 receives the first communication signal including the first message from transceiver 102. At action 404, transceiver 104 detects the signal strength of the first communication signal. At action 406, transceiver 104 generates a preamble with a preamble bit length. When generating the preamble at action 406, transceiver 104 adjusts the preamble bit length of the preamble based on the detected signal strength of the first communication signal. At action 408, transceiver 104 sends a second communication signal including a second message to transceiver 102. The second message includes a preamble with a preamble bit length adjusted based on the detected signal strength of the first communication signal. In one or more examples, when transceiver 102 sends an initial communication signal to transceiver 104 (e.g., a first communication signal including a first message at action 402), transceiver 102 sends the initial communication signal at the maximum output power of transceiver 102.

[0055] In one or more examples, at action 404, a signal strength that is too high is detected at transceiver 104, and in response, at action 406, the preamble bit length of the preamble is adjusted to a first preamble bit length. In one or more examples, the first preamble bit length is used to command transceiver 102 to reduce its transmit power level. In one or more other examples, at action 404, a signal strength that is too low is detected at transceiver 104, and in response, at action 406, the preamble bit length of the preamble is adjusted to a second preamble bit length. In one or more other examples, the second preamble bit length is used to command transceiver 102 to increase its transmit power level.

[0056] In action 408, transceiver 102 receives a second communication signal including a second message from transceiver 104. Transceiver 102 uses the preamble of the second message to perform synchronization. In action 410, transceiver 102 detects the preamble bit length of the second message's preamble. In action 412, transceiver 102 adjusts the transmit power level used for transmission based on the preamble bit length. In action 414, transceiver 102 transmits a third communication signal including a third message to transceiver 104 at the adjusted transmit power level.

[0057] In one or more examples, at action 410, the preamble bit length of the preamble is detected to be a first preamble bit length, and in response, the transmit power level is increased at action 412. In one or more other examples, at action 410, the preamble bit length of the preamble is detected to be a second preamble bit length, and in response, the transmit power level is decreased at action 412.

[0058] In action 414, transceiver 104 receives a third communication signal including a third message from transceiver 102. In action 416, transceiver 104 detects the signal strength of the third communication signal. In action 418, transceiver 104 generates a preamble with a preamble bit length. When generating the preamble in action 418, transceiver 104 adjusts the preamble bit length of the preamble based on the detected signal strength of the third communication signal. In action 420, transceiver 104 transmits a fourth communication signal including a fourth message to transceiver 102. The fourth message includes a preamble with a preamble bit length adjusted based on the detected signal strength of the third communication signal.

[0059] In one or more examples, at action 416, a signal strength at transceiver 104 is detected to be sufficient (e.g., within a target threshold range), and in response, at action 418, the preamble bit length is adjusted to a third preamble bit length. In one or more examples, the third preamble bit length is used to command transceiver 102 to maintain its (current) transmit power level.

[0060] In action 420, transceiver 102 receives a fourth communication signal including a fourth message from transceiver 104. Transceiver 102 uses the preamble of the fourth message to perform synchronization. In action 422, transceiver 102 detects the preamble bit length of the fourth message. In action 424, transceiver 102 adjusts the transmit power level for transmission in response to the detected preamble bit length. In action 426, transceiver 102 transmits a fifth communication signal including a fifth message to transceiver 104 at the adjusted transmit power level.

[0061] In one or more alternative examples, at action 422, the preamble bit length of the preamble is detected to be the third preamble bit length, and in response, the transmit power level is maintained at action 424. The fifth communication signal from transceiver 102 to transceiver 104 may have sufficient or optimal signal strength, such that no further adjustments are required (e.g., for at least a certain period of time thereafter).

[0062] According to one or more examples, the corresponding transceivers in transceivers 102 and 104 can be adapted at each end with the same or similar adjustment capabilities, such as regarding Figure 4B As described.

[0063] Figure 4B This is a message flow diagram of message flow 400B, wirelessly communicated between transceiver 102 and transceiver 104 according to one or more examples, for transmitting power level control. According to one or more examples, message flow 400B indicates processing for transmitting power level control based on the preamble bit length. In one or more examples, the action of message flow 400B is implemented in the transceiver PHY (e.g., in PHY circuitry) for end-to-end PHY-level control of the transmit power level. Figure 4B In one or more examples, the corresponding transceivers in transceivers 102 and 104 are adapted with the same or similar adjustment capabilities at each end.

[0064] In message stream 400B, at action 450, transceiver 102 sends a first communication signal including a first message (e.g., message 110) to transceiver 104. The first message includes a preamble with a preamble bit length. Transceiver 104 receives the first communication signal including the first message from transceiver 102. Transceiver 104 uses the preamble of the first message to perform synchronization. At action 452, transceiver 102 detects the preamble bit length of the preamble of the first message. At action 454, transceiver 102 adjusts the transmit power level used for transmission based on the detected preamble bit length. In one or more examples, when transceiver 102 sends the initial communication signal (e.g., the first communication signal including the first message at action 450) to transceiver 104, transceiver 102 transmits the initial communication signal at its maximum output power.

[0065] At action 456, transceiver 104 further detects the signal strength of the first communication signal. At action 458, transceiver 104 generates a preamble with a preamble bit length. When generating the preamble at action 456, transceiver 104 adjusts the preamble bit length based on the detected signal strength. At action 460, transceiver 104 transmits a second communication signal including a second message to transceiver 102 at the adjusted transmit power level. The second message includes a preamble with a preamble bit length adjusted based on the detected signal strength.

[0066] In one or more examples, a preamble bit length of the first preamble bit length is detected at action 452, and in response, the transmit power level is reduced at action 454. In one or more other examples, a preamble bit length of the second preamble bit length is detected at action 452, and in response, the transmit power level is increased at action 454.

[0067] In one or more examples, at action 456, a signal strength that is too high at transceiver 104 is detected, and in response, at action 458, the preamble bit length is adjusted to a first preamble bit length. In one or more examples, the first preamble bit length is used to command transceiver 102 to reduce its transmit power level. In one or more other examples, at action 456, a signal strength that is too low at transceiver 104 is detected, and in response, at action 458, the preamble bit length is adjusted to a second preamble bit length. In one or more examples, the second preamble bit length is used to command transceiver 102 to increase its transmit power level.

[0068] At action 460, transceiver 102 receives a second communication signal including a second message from transceiver 104. Transceiver 102 uses the preamble of the second message to perform synchronization. At action 462, transceiver 102 detects the preamble bit length of the preamble of the second message. At action 464, transceiver 102 adjusts the transmit power level for transmission based on the detected preamble bit length. At action 466, transceiver 102 detects the signal strength of the second communication signal. At action 468, transceiver 102 generates a preamble with a preamble bit length. When generating the preamble at action 468, the preamble bit length of the preamble is adjusted based on the detected signal strength. At action 470, transceiver 102 transmits a third communication signal including a third message to transceiver 104 at the adjusted power level. The third message includes a preamble with a preamble bit length adjusted based on the detected signal strength.

[0069] In one or more examples, at action 462, the preamble bit length of the preamble is detected to be a first preamble bit length, and in response, the transmit power level is reduced at action 464. In one or more other examples, at action 462, the preamble bit length of the preamble is detected to be a second preamble bit length, and therefore the transmit power level is increased at action 464.

[0070] In one or more examples, at action 466, a signal strength (e.g., still) too high is detected at transceiver 102, and in response, the preamble bit length is adjusted to a first preamble bit length at action 468. In one or more examples, the first preamble bit length is used to command transceiver 104 to reduce its transmit power level. In one or more other examples, at action 466, a signal strength (e.g., still) too low is detected at transceiver 102, and in response, the preamble bit length is adjusted to a second preamble bit length at action 468. In one or more examples, the second preamble bit length is used to command transceiver 104 to reduce its transmit power level.

[0071] From action 470, transceiver 104 receives a third communication signal including a third message from transceiver 102. Transceiver 104 uses the preamble of the third message to perform synchronization. At action 472, transceiver 104 detects the preamble bit length of the message's preamble. At action 474, transceiver 104 adjusts the transmit power level used for transmission based on the detected preamble bit length. At action 476, transceiver 104 also detects the signal strength of the communication signal. At action 478, transceiver 104 generates a preamble with a preamble bit length. When generating the preamble at action 478, transceiver 104 adjusts the preamble bit length of the preamble based on the detected signal strength of the third communication signal. At action 480, transceiver 104 transmits a fourth communication signal including a fourth message to transceiver 102. The fourth message includes a preamble with a preamble bit length adjusted based on the detected signal strength of the third communication signal.

[0072] In one or more alternative examples, at action 472, the preamble bit length of the preamble is detected to be the third preamble bit length, and in response, the transmit power level is maintained at action 474. In one or more examples, at action 476, a signal strength at transceiver 104 is detected to be sufficient (e.g., within a target threshold range), and in response, the preamble bit length of the preamble is adjusted to the third preamble bit length at action 478. In one or more examples, the third preamble bit length is used to command transceiver 102 to maintain its (current) transmit power level.

[0073] From action 480, transceiver 102 receives a fourth communication signal, including a fourth message, from transceiver 104. Transceiver 102 uses the preamble of the fourth message to perform synchronization. At action 482, transceiver 102 detects the preamble bit length of the fourth message preamble. Then, the actions of transceiver 102 and transceiver 104 can be repeated and / or continued in the same or similar manner as described above.

[0074] Figure 5A This is a flowchart of method 500A, which describes a method for controlling the transmit power level of a second transceiver based on the preamble bit length of a preamble, according to one or more examples. Method 500A can be implemented by a transceiver (e.g., ...). Figure 1 The transceiver 102 and / or transceiver 104 are used to perform this action. In one or more examples, the action of method 500B is implemented in the transceiver PHY (e.g., in the PHY circuitry) for PHY-level control of the transmit power level. In one or more examples, transceiver 102 operates to perform this action. Figure 5A Method 500A is used for communicating with transceiver 104 and for controlling the transmit power level of transceiver 104, which operates to perform... Figure 6AMethod 600A (e.g., reference) Figure 4A (Message stream 400A). In one or more specific examples, the corresponding transceivers in transceiver 102 and transceiver 104 operate to perform... Figure 5A Method 500A and Figure 6A Method 600A is used for both communication with another transceiver and for transmitting power level control of the other transceiver (e.g., reference). Figure 4B Message stream 400B).

[0075] exist Figure 5A In method 500A, at action 502, a first communication signal including a first message is received. At action 504, the signal strength of the first communication signal is detected. At action 506, a preamble having a preamble bit length is generated. When generating the preamble at action 506, the preamble bit length is adjusted at least partially based on the detected signal strength of the first communication signal. At action 506, a second communication signal including a second message is transmitted. When transmission is performed at action 508, the second message includes a preamble having a preamble bit length adjusted based on the detected signal strength.

[0076] In one or more examples, when another transceiver sends an initial communication signal for receiving (e.g., a first communication signal including a first message at action 502) to the transceiver, the other transceiver transmits the initial communication signal at maximum output power. That is, transceivers may (e.g., always or periodically) initiate the transmission of messages to another transceiver at maximum output power (e.g., and if beneficial, are subsequently controlled to reduce their respective transmission power).

[0077] As Figure 5A An example of action 506 is to compare the detected signal strength with one or more thresholds and adjust the preamble bit length of the preamble based on the comparison result. As a particular non-limiting example, a preamble with a first preamble bit length is generated based at least in part on the comparison result indicating that the detected signal strength is greater than a threshold; and a preamble with a second preamble bit length is generated based at least in part on the comparison result indicating that the detected signal strength is less than a threshold.

[0078] In one or more examples, a preamble with a preamble bit length is an instruction for another transceiver to adjust the transmit power level used for transmission based on the preamble bit length. For example, at another transceiver, a second communication signal including a second message with a preamble is received, and the transmit power level used for transmission is adjusted at the other transceiver at least in part based on the preamble bit length of the preamble. The preamble is also used for synchronization at the other transceiver.

[0079] In one or more examples, used to perform Figure 5A The method of the 500A transceiver is additionally implemented Figure 6A Method 600A, which will be discussed later below, describes an approach whereby the transceiver detects the preamble bit length of the preamble bit of the first message of the first communication signal; and the transceiver adjusts the transmit power level for transmitting the second communication signal based at least in part on the preamble bit length of the first message. For example, the transmit power level for transmitting the second communication signal is reduced based at least in part on the preamble bit length including a first preamble bit length; the transmit power level for transmitting the second communication signal is maintained (e.g., the transmit power level is not changed) based at least in part on the preamble bit length including a second preamble bit length; and the transmit power level for transmitting the second communication signal is increased based at least in part on the preamble bit length including a third preamble bit length.

[0080] In one or more examples, a predetermined adjustment amount is used for a corresponding incremental adjustment associated with the received preamble. In one or more other examples, only two (e.g., coarse) adjustment settings associated with the corresponding smaller and larger preamble bit lengths are used for control (e.g., setting the transmit power level to a lower setting or setting the transmit power level to a higher setting).

[0081] Figure 5B This is a flowchart of a more detailed method 500B for a first transceiver to control the transmit power level of a second transceiver based on the preamble bit length of the preamble, according to one or more examples. Figure 5B Method 500B and Figure 5A Method 500A is essentially the same, except that actions 502, 504, and 508 of method 500B are the same as those in method 500A, and action 506 of method 500A is represented as one of actions 506a, 506b, and 506c of method 500B. In one or more examples, transceiver 102 ( Figure 1 ) operation to perform Figure 5B Method 500B, for use with transceiver 104 ( Figure 1 ) to communicate and to control the transmit power level of transceiver 104, transceiver 104 operates to perform Figure 6B Method 600B (for example, refer to Figure 4A (Message stream 400A). In one or more specific examples, the corresponding transceivers in transceiver 102 and transceiver 104 operate to perform... Figure 5B Method 500B and Figure 6B Method 600B is used for both to communicate with each other and to control each other's transmit power levels (e.g., reference). Figure 4B Message stream 400B).

[0082] exist Figure 5B In method 500B, at action 505, the detected signal strength of the first communication signal is compared with one or more thresholds. Based at least in part on the result of the comparison at action 505, the preamble bit length of the preamble is adjusted (e.g., according to one of actions 506a, 506b, and 506c). More specifically, at action 506a, if the result of the comparison at action 505 indicates that the detected signal strength is greater than a target threshold range (e.g., the signal strength is too high), a preamble bit length including a first preamble bit length is generated. At action 506b, if the result of the comparison at action 505 indicates that the detected signal strength is within the target threshold range (e.g., sufficient or good signal strength), a preamble bit length including a second preamble bit length is generated. At action 506c, if the result of the comparison at action 505 indicates that the detected signal strength is less than the target threshold range (e.g., the signal strength is too low), a preamble bit length including a third preamble bit length is generated. When transmission is performed at action 508, the second message of the second communication signal includes a preamble with a preamble bit length adjusted based on the detected signal strength (e.g., according to one of actions 506a, 506b, and 506c).

[0083] In one or more examples, preambles with a first preamble length, a second preamble length, and a third preamble length are generated as having the same pattern or sequence (e.g., an alternating sequence of +1 and -1 values).

[0084] In one or more examples of method 500B, the second preamble bit length of the preamble of action 506b is A bits (e.g., preamble 302 of FIG. 3A), the first preamble bit length of the preamble of action 506a is one of (AZ) bits or (A+Z) bits (e.g., (AZ) bits and / or preamble 302 of FIG. 3B), and the third preamble bit length of the preamble of action 506c is the other of (AZ) bits or (A+Z) bits (e.g., (A+Z) bits and / or preamble 302 of FIG. 3C) (where A and Z are predetermined positive integer constants and A>Z). Here, in one or more specific examples, A bits = (X+Y) bits, where X is a predetermined preamble bit length of the preamble specified in the communication standard compatible with the transceiver, and Y>Z (where X and Y are predetermined positive integer constants).

[0085] In one or more alternative examples of method 500B, the second preamble bit length is X bits, the first preamble bit length is (X+J) bits, and the third preamble bit length is (X+K) bits, where X is a predetermined preamble bit length of the preamble specified in the communication standard compatible with the transceiver, and J≠K (where X, J, and K are predetermined positive integer constants).

[0086] Figure 6A This is a flowchart of method 600A, which describes a second transceiver controlling a transmit power level based on the preamble bit length of a preamble received from a first transceiver, according to one or more examples. Method 600A can be implemented in the transceiver of a communication device (e.g., ...). Figure 1 The method 600A is implemented in transceiver 102 and / or transceiver 104. In one or more examples, the operation of method 600A is implemented in the transceiver PHY (e.g., in the PHY circuitry) for PHY-level control of the transmit power level. In one or more examples, transceiver 102 operates to perform... Figure 6A Method 600A is used for communicating with transceiver 104 and for controlling the transmit power level of transceiver 104, which operates to perform... Figure 5A Method 500A (e.g., reference) Figure 4A (Message stream 400A). In one or more specific examples, the corresponding transceivers in transceiver 102 and transceiver 104 operate to perform... Figure 5A Method 500A and Figure 6A Method 600A for both to communicate with each other and to control each other's transmit power levels (e.g., reference). Figure 4B Message stream 400B).

[0087] exist Figure 6A In method 600A, at action 602, a first communication signal including a first message is received. Synchronization is performed using the preamble of the first message. At action 604, the preamble bit length of the first message's preamble is detected. At action 606, the gain of the transceiver's transmitter amplifier is adjusted, at least partially based on the preamble bit length of the preamble. At action 608, a second communication signal including a second message is amplified using the transmitter amplifier with the adjusted gain. At action 610, the amplified second communication signal including the second message is transmitted.

[0088] As Figure 6A An example of action 606 is to reduce the gain of the transmitter amplifier based at least in part on the preamble bit length, including a first preamble bit length; and to increase the gain of the transmitter amplifier based at least in part on the preamble bit length, including a second preamble bit length.

[0089] In one or more examples, detecting the preamble bit length of the preamble at action 604 includes maintaining a count of the received bits of the preamble until the total count of the received bits of the preamble is reached. Here, in one or more examples, adjusting the gain of the transmitter amplifier at action 606 includes adjusting the gain of the transmitter amplifier at least in part based on the total count of the received bits of the preamble. In one or more particular examples, adjusting the gain of the transmitter amplifier at action 606 includes incrementing or decrementing a gain control count used for adjusting the gain at least in part based on the total count of the received bits of the preamble. In one or more additional examples, the adjustment at action 606, the amplification at action 608, and the transmission at action 610 are repeated (e.g., periodically) at least in part based on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble.

[0090] In one or more examples, used to perform Figure 6A The transceiver of method 600A is used to additionally perform Figure 5A Method 500A, which was discussed earlier above, involves detecting the signal strength of a first communication signal in one or more examples; generating a preamble with a preamble bit length, wherein the preamble bit length is adjusted at least partially based on the detected signal strength; and transmitting an amplified second communication signal at action 610 including a second message with a preamble having the preamble bit length. In one or more examples, the detected signal strength is compared to one or more thresholds, and the preamble bit length of the preamble is adjusted based on the result of the comparison. As a particular non-limiting example, a preamble with a first preamble bit length is generated, at least partially based on the result of the comparison indicating that the detected signal strength is greater than a threshold; and a preamble with a second preamble bit length is generated, at least partially based on the result of the comparison indicating that the detected signal strength is less than a threshold. In one or more examples, the preamble with the preamble bit length is an instruction for another transceiver to adjust the transmit power level used for transmission according to the preamble bit length. For example, at another transceiver, a second communication signal including a second message with a preamble is received, and the transmit power level for transmission is adjusted at the other transceiver at least in part based on the preamble bit length of the preamble.

[0091] In one or more examples, a predetermined adjustment amount is used for a corresponding incremental adjustment associated with the received preamble. In one or more other examples, only two (e.g., coarse) adjustment settings associated with the corresponding smaller and larger preamble bit lengths are used for control (e.g., setting the transmit power level to a lower setting or setting the transmit power level to a higher setting).

[0092] Figure 6BThis is a flowchart of a more detailed method 600B for a second transceiver, based on one or more examples, to control the transmit power level according to the preamble bit length of the preamble received from the first transceiver. Method 600B can be implemented in the transceiver of a communication device (e.g., ...). Figure 1 Implemented in transceiver 102 and / or transceiver 104). In one or more examples, transceiver 102 ( Figure 1 ) operation to perform Figure 6B Method 600B, for use with transceiver 104 ( Figure 1 ) to communicate and to control the transmit power level of transceiver 104, transceiver 104 operates to perform Figure 5B Method 500B (for example, refer to Figure 4A (Message stream 400A). In one or more specific examples, the corresponding transceivers in transceiver 102 and transceiver 104 operate to perform... Figure 5A Method 500A and Figure 6A Method 600A for both to communicate with each other and to control each other's transmit power levels (e.g., reference). Figure 4B Message stream 400B).

[0093] Figure 6B Method 600B and Figure 6A Method 600B is essentially the same as Method 600A, wherein actions 602, 604, 608 and 610 of Method 600B are the same as those in Method 600A, and action 606 of Method 600A is represented as one of actions 606a, 606b and 606c of Method 600B.

[0094] exist Figure 6B In method 600B, at action 604, the preamble bit length of the preamble is detected. At least in part based on the preamble bit length at action 604 including a first preamble bit length, at action 606a, the gain of the transmitter amplifier used to transmit the second communication signal is reduced. At least in part based on the preamble bit length at action 604 including a second preamble bit length, at action 606b, the gain of the transmitter amplifier used to transmit the second communication signal is maintained (e.g., the gain is not changed). At least in part based on the preamble bit length at action 604 including a third preamble bit length, at action 606c, the gain of the transmitter amplifier used to transmit the second communication signal is increased. At action 610, the amplified second communication signal including the second message is transmitted.

[0095] In one or more examples, preambles with a first preamble length, a second preamble length, and a third preamble length are generated as having the same pattern or sequence (e.g., an alternating sequence of +1 and -1 values).

[0096] In one or more examples of method 600B, the second preamble bit length of the preamble of action 606b is A bits (e.g., preamble 302 of FIG. 3A), the first preamble bit length of the preamble of action 606a is one of (AZ) bits or (A+Z) bits (e.g., (AZ) bits and / or preamble 302 of FIG. 3B), and the third preamble bit length of the preamble of action 606c is the other of (AZ) bits or (A+Z) bits (e.g., (A+Z) bits and / or preamble 302 of FIG. 3C) (where A and Z are predetermined positive integer constants and A>Z). Here, in one or more specific examples, A bits = (X+Y) bits, where X is a predetermined preamble bit length of the preamble specified in the communication standard to which the transceiver is compatible, and Y>Z (where X and Y are predetermined positive integer constants).

[0097] In one or more alternative examples of method 600B, the second preamble bit length is X bits, the first preamble bit length is (X+J) bits, and the third preamble bit length is (X+K) bits, where X is a predetermined preamble bit length of the preamble specified in the communication standard to which the transceiver is compatible, X, J, and K are predetermined positive integer constants, and J≠K.

[0098] Figure 7 This is a block diagram of a communication device 700 including a transceiver PHY 704, based on one or more examples. In one or more examples, Figure 7 The architecture of the communication device 700 can be included in... Figure 1 The first communication device including transceiver 102 and including Figure 1 The corresponding communication device in the second communication device of transceiver 104.

[0099] Figure 7 The communication device 700 includes application layer processing circuitry 702, a transceiver PHY 704, and an analog front-end (AFE) 706. Application layer processing circuitry 702 includes an application receive processing module 710 and an application transmit processing module 712. Application layer processing circuitry 702 can be implemented using one or more processors (such as one or more microcontrollers, microprocessors, etc.) for processing. Transceiver PHY 704 includes receiver PHY 714, transmitter PHY 716, and control circuitry 718 operatively coupled to receiver PHY 714 and transmitter PHY 716. AFE 720 includes receiver AFE circuitry 720 and transmitter AFE circuitry 722.

[0100] For receiving processing, the wireless communication signal is received and processed at the receiver AFE circuit 720, and routed to the receiver PHY 714 for processing. The data signal is then passed to the application receiving processing module 710 for processing. For transmitting processing, the data signal from the application transmitting processing module 712 is passed to the transmitter PHY 716 for processing, and routed to the transmitter AFE circuit 722 for transmitting the wireless communication signal for processing.

[0101] In one or more examples, the transceiver PHY 704 includes Figure 8 , Figure 9 , Figure 10 , Figure 11 and Figure 12 This refers to any electronic circuit or combination thereof, which is discussed in detail below. As one or more examples, 718 may or may not have control circuitry. Figure 7 The receiver PHY 714 may include Figure 8 and / or Figure 9 The electronic circuitry; and / or having or not having control circuitry 718. Figure 7 The transmitter PHY 716 may include Figure 10 , Figure 11 or Figure 12 Electronic circuits.

[0102] Figure 8 This is a schematic block diagram of electronic circuitry 800 in one or more example transceivers (e.g., transceiver PHY) for controlling the transmit power level based on the preamble bit length. In one or more examples, electronic circuitry 800 implements... Figure 5A Method 500A or Figure 5B Method 500B.

[0103] Electronic circuit 800 includes a received signal strength indicator circuit 802, an analog-to-digital converter (ADC) 804, a comparator circuit 806, and a preamble sequence generator circuit 808. The received signal strength indicator circuit 802 detects the signal strength of a first communication signal that includes a first message. In one or more examples, the received signal strength indicator circuit 802 generates a received signal strength indicator (RSSI) of the first communication signal at output 810. The received signal strength indicator at output 810 is provided as an analog signal to the input of the ADC 804. The ADC 804 converts the analog value of the detected signal strength into a binary signal value provided at output 812 and provides these binary signal values ​​to the input of the comparator circuit 806.

[0104] Comparator circuit 806 compares the detected signal strength (e.g., binary signal value) of the first communication signal with one or more thresholds at input 816. One or more outputs 814 of comparator circuit 806 are coupled to preamble sequence generator circuit 808. Preamble sequence generator circuit 808 generates a preamble at output 818. Preamble sequence generator circuit 808 adjusts the preamble bit length of the preamble based at least in part on one or more outputs 814 of comparator circuit 806. In one or more examples, the preamble may be considered a variable bit length preamble that is adjusted according to the detected signal strength or RSSI. The preamble is included in a second message carried by a second communication signal for transmission.

[0105] In one or more examples, the preamble sequence generator circuit 808 generates a preamble with a first preamble bit length based at least in part on one or more outputs 814 of the comparator circuit 806 indicating that the detected signal strength is greater than a threshold, and generates a preamble with a second preamble bit length based at least in part on one or more outputs 814 of the comparator circuit 806 indicating that the detected signal strength is less than a threshold.

[0106] In one or more specific examples, the preamble sequence generator circuit 808 generates a preamble with a first preamble bit length based at least in part on one or more outputs 814 of the comparator circuit 806 indicating that the detected signal strength is greater than a target threshold range (e.g., the signal strength is too high), generates a preamble with a second preamble bit length based at least in part on one or more outputs 814 of the comparator circuit 806 indicating that the detected signal strength is within the target threshold range (e.g., sufficient or good signal strength), and generates a preamble with a third preamble bit length based at least in part on one or more outputs 814 of the comparator circuit 806 indicating that the detected signal strength is less than the target threshold range (e.g., the signal strength is too low).

[0107] In one or more examples, the second preamble bit length is A bits (e.g., preamble 302 in FIG3A), the first preamble bit length is one of (AZ) bits or (A+Z) bits (e.g., (AZ) bits and / or preamble 304 in FIG3B), and the third preamble bit length is the other of (AZ) bits or (A+Z) bits (e.g., (A+Z) bits and / or preamble 306 in FIG3C). Here, in one or more specific examples, A bits = (X+Y) bits, where X is a predetermined preamble bit length specified in the communication standard to which the transceiver is compatible, and Y > Z (where X and Y are predetermined positive integer constants).

[0108] In one or more alternative examples, the second preamble bit length is X bits, the first preamble bit length is (X+J) bits, and the third preamble bit length is (X+K) bits, where X is a predetermined preamble bit length specified in the communication standard to which the transceiver is compatible, and J≠K (where X, J, and K are predetermined positive integer constants).

[0109] refer to Figure 9 As one or more examples, the preamble sequence generator circuit 808 may include a switching circuit 902 and multiple preamble sequence generator circuit sections 904, 906, and 908. Relevant preamble sequence generator circuit sections 904, 906, and 908 may be selectively enabled to generate preamble sequences with different preamble bit lengths. As an example, preamble sequence generator circuit section 904 may generate a preamble with a first preamble bit length (e.g., (AZ) bits), preamble sequence generator circuit section 906 may generate a preamble with a second preamble bit length (e.g., A bits), and preamble sequence generator circuit section 908 may generate a preamble with a third preamble bit length (e.g., (A+Z) bits). In one or more examples, switching circuit 902 can switchably enable or activate a corresponding preamble sequence generator circuit section in preamble sequence generator circuit sections 904, 906 and 908 based on one or more outputs 814 of comparator circuit 806 to generate a preamble with a desired preamble length.

[0110] As another example, preamble sequence generator circuit section 904 can generate a preamble with a first preamble bit length (e.g., (AZ) bits), preamble sequence generator circuit section 906 can continue to generate a preamble with a second preamble bit length (e.g., A bits), and preamble sequence generator circuit section 908 can further continue to generate a preamble with a third preamble bit length (e.g., (A+Z) bits). Here, in one or more examples, switching circuit 902 can switchably enable or activate the respective preamble sequence generator circuit sections 904, 906, and 908 based on one or more outputs 814 of comparator circuit 806 to generate a preamble with a desired preamble length.

[0111] Figure 10 This is a schematic block diagram of electronic circuitry 1000 in one or more examples of a transceiver (e.g., a transceiver PHY) for controlling the transmit power level based on the preamble bit length. In one or more examples, electronic circuitry 1000 implements... Figure 6A Method 600A or Figure 6BMethod 600B. In one or more examples, when the initial communication signal is transmitted from the transceiver, the gain of the transmitter amplifier 1012 is set to the maximum output power.

[0112] The electronic circuit 1000 includes a preamble bit length detector circuit 1002, a gain adjustment circuit 1004, and a transmitter amplifier 1012. Figure 10 In one or more examples, the preamble bit length detector circuit 1002 includes a counter circuit 1006 and a register 1008, and the gain adjustment circuit includes a gain control circuit 1010. Generally, the preamble bit length detector circuit 1002 is used to detect the preamble bit length of the preamble of the first message of the first communication signal. The gain adjustment circuit 1004 is used to adjust the gain of the transmitter amplifier 1012 based at least in part on the detected preamble bit length. The transmitter amplifier 1012 is used to amplify the second communication signal, including the second message, using the adjusted gain for transmission.

[0113] More specifically, the counter circuit 1006 of the preamble bit length detector circuit 1002 maintains a count of the received bits of the preamble until the total count of the received bits of the preamble is reached. For example, input 1014 of the counter circuit 1006 may receive a preamble bit detection signal for a corresponding preamble bit in the detected preamble bits of the preamble sequence, thereby incrementing or decrementing the count provided at output 1016 of the counter circuit 1006. When the total count of the received bits of the preamble is reached at the counter circuit 1006 (e.g., indicated by SFD detection and / or others), the total count of the preamble from the counter circuit 1006 (via a load signal at register 1008) is loaded into register 1008. The total count is provided as a gain control count at output 1018 of register 1008. The gain control circuit 1010 converts the gain control count from register 1008 into an analog or digital binary signal value representing the (adjusted) gain at one or more outputs 1020. Transmitter amplifier 1012 uses the adjusted gain to amplify the transmit signal at input 1022 to generate the amplified transmit signal at output 1024.

[0114] In one or more examples, the gain of transmitter amplifier 1012 may be repeatedly adjusted (e.g., periodically) in the same or similar manner as described, based on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble, wherein after the corresponding preamble detection, counter circuit 1006 is reset (via a reset signal at counter circuit 1006), and register 1008 is loaded with a new total value for the corresponding newly received preamble.

[0115] Figure 11This is a schematic block diagram of electronic circuitry 1100 in one or more examples of a transceiver (e.g., a transceiver PHY) for controlling the transmit power level based on the preamble bit length. In one or more examples, electronic circuitry 1100 implements... Figure 6A Method 600A or Figure 6B Method 600B.

[0116] Figure 11 Electronic circuit 1100 and Figure 10 The electronic circuits 1000 are essentially the same, wherein the same or similar parts or components that operate in the same or similar manner are kept with the same numbering in the drawings. Figure 11 In this circuit, the gain adjustment circuit 1004 also includes a counter circuit 1009 and a gain control circuit 1010. Figure 11 In this circuit, the counter circuit 1009 of the gain adjustment circuit 1004 maintains a separate gain control count (i.e., separate from the total count from the counter circuit 1006 and / or the register 1008) at one or more outputs 1011. The counter circuit 1009 increments or decrements the gain control count at one or more outputs 1011 based at least in part on the total count of the received preamble bits from the counter circuit 1006 and / or the register 1008. The gain control count at one or more outputs 1011 of the counter circuit 1009 is provided to the gain control circuit 1010 for adjusting the gain of the transmitter amplifier 1012. The gain control count at the counter circuit 1009 can be maintained, incremented, or decremented from preamble to preamble (e.g., the counter circuit 1009 does not reset from preamble to preamble).

[0117] In one or more examples, when an initial communication signal is to be sent from one transceiver to another, the counter circuit 1009 and / or the register 1008 may be initialized or loaded with a gain control count, which includes a maximum gain control count corresponding to the maximum gain (i.e., for maximum output power) to be provided from the gain control circuit 1010 to the transmitter amplifier 1012.

[0118] In one or more alternative examples, counter circuit 1006 provides an increment signal output at output 1016 for asserting an increment signal (e.g., a binary signal value where 1 = increment) and a decrement signal output at output 1016 for asserting a decrement signal (e.g., using another binary signal value where 1 = decrement), instead of providing the entire total count of the received preamble bits. The assert signal is not invoked to maintain the current gain control count. When the total count of the received bits of the preamble is reached (e.g., indicated by SFD detection and / or others), one of the binary signal values ​​(e.g., the increment or decrement signal) is loaded into register 1008 (via a load signal at register 1008), thereafter which the binary signal value is provided at output 1018 of register 1008 for adjusting counter circuit 1009. For example, the increment and decrement signal outputs may be derived from a limited selection of output 1016 from counter circuit 1006 (e.g., a selected output associated only with the leftmost or higher-order bit of the total count).

[0119] In one or more examples, the gain of transmitter amplifier 1012 may be repeatedly adjusted (e.g., periodically) in the same or similar manner as described, based on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble, wherein after the corresponding preamble detection, counter circuit 1006 is reset (via a reset signal at counter circuit 1006), and register 1008 is loaded with a new total value (or increment / decrement signal) for the corresponding newly received preamble. Here, the gain control count at counter circuit 1009 may be maintained, incremented, or decremented from preamble to preamble (e.g., counter circuit 1009 is not reset from preamble to preamble).

[0120] Figure 12 This is a schematic block diagram of electronic circuitry 1200 in one or more example transceivers (e.g., transceiver PHY) for controlling the transmit power level based on the preamble bit length. Figure 12 In one or more examples, electronic circuit 1200 implements Figure 6B Method 600B.

[0121] Figure 12 Electronic circuit 1200 and Figure 10 Electronic circuits 1000 and / or Figure 11 The electronic circuits 1100 are essentially the same, wherein the same or similar parts or elements that operate in the same or similar manner are kept with the same numbering in the drawings. Figure 12In the middle, the electronic circuit 1200 includes: a preamble length detector circuit 1202, which includes a counter circuit 1006, a register 1008 and a subtractor circuit 1210; and a gain adjustment circuit 1204, which includes an adder circuit 1212, a register 1214 and a gain control circuit 1010.

[0122] In the preamble bit length detector circuit 1202, the total count of preamble bits is provided to the subtractor circuit 1210 at output 1018 of register 1008. The total count can be one of the preamble length (AZ), preamble length A, or preamble length (A+Z) (e.g., Figures 3A, 3B, and 3C). The subtractor circuit 1210 subtracts the value “A” from the total count and provides the result at output 1226. The result at output 1226 is an adjustment value equal to one of -Z, 0, or +Z (e.g., where a negative -Z can be indicated at one of the outputs). In the gain adjustment circuit 1204, the adder circuit 1212 receives the adjustment value and adds it to the current gain control count (provided from output 1018 of register 1214), and the result is provided at output 1228. When the result from the adder circuit 1212 is ready, the result is loaded into register 1214 (via a load signal at register 1214). The result provided at output 1018 of register 1214 is a new adjusted gain control count for the gain control circuit 1010 used to adjust the gain of transmitter amplifier 1012.

[0123] In one or more examples, when an initial communication signal is to be sent from one transceiver to another, the adder circuit 1212 and / or register 1214 may be initialized or loaded with a gain control count, which includes a maximum gain control count corresponding to the maximum gain to be provided from the gain control circuit 1010 to the transmitter amplifier 1012.

[0124] In one or more examples, the gain of transmitter amplifier 1012 may be repeatedly adjusted (e.g., periodically) in the same or similar manner as described, based on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble, wherein after the corresponding preamble detection, counter circuit 1006 is reset (via a reset signal at counter circuit 1006), register 1008 is loaded with a new total value (or increment / decrement signal) for the corresponding newly received preamble, and adder circuit 1212 and register 1214 are used to adjust and maintain the gain control count. Here, from preamble to preamble, the gain control count at adder circuit 1212 / register 1214 may be maintained, incremented, or decremented.

[0125] Figure 13This is a flowchart of method 1300, which uses one or more counter circuits to control the transmit power level based on the preamble bit length, according to one or more examples. Method 1300 can be implemented in the transceiver of a communication device (e.g., Figure 1 The operation of method 1300 is implemented in transceiver 102 and / or transceiver 104. In one or more examples, the operation of method 1300 is implemented in the transceiver PHY (e.g., in the PHY circuitry) for PHY-level control of the transmit power level. In one or more examples, the operation of method 1300 may be implemented in the electronic circuitry of the transceiver PHY (such as...). Figure 11 Electronic circuit 1100 or Figure 12 It is implemented in the electronic circuit 1200.

[0126] exist Figure 13 In method 1300, at action 1302, a count associated with the preamble bit length of the preamble is maintained. At action 1304, a gain control count is incremented or decremented (e.g., maintained) at least partially based on the total count associated with the preamble bit length. At action 1306, the gain of the transmitter amplifier is adjusted at least partially based on the gain control count. The transmitter amplifier can use the adjusted gain to amplify the communication signal to generate an amplified communication signal for transmission. In one or more examples, the gain of the transmitter amplifier can be repeatedly adjusted (e.g., periodically) in the same or similar manner (e.g., repeating actions 1302, 1304, and 1306) based on the corresponding preamble bit length in the subsequently detected preamble bit length of a subsequently received preamble (e.g., for the next preamble received at action 1308). In one or more examples, a predetermined adjustment amount is used for the corresponding incrementing adjustment associated with the received preamble.

[0127] Figure 14 This is the protocol stack 1400 associated with the IEEE 802.15.4 standard for Low Rate Wireless Personal Area Networks (LR-WPANs). The protocol stack 1400 associated with the IEEE 802.15.4 standard includes layer 3 and above 1402, a Logical Link Control (LLC) sublayer 1404, a Service Specific Convergence Sublayer (SSCS) 1406, a Media Access Control (MAC) layer 1408 (or layer 2), and a Physical (PHY) layer 1410 (or layer 1). In IEEE 802.15.4, the preamble preposition sequence is a 16-bit sequence of alternating +1 and -1 values, and variations of this preamble bit length for transmit power level control are described herein (e.g., Figures 3B, 3C, and 3D). In one or more examples, methods and apparatuses including electronic circuitry (e.g., Figure 5A Method 500A Figure 5B Method 500B Figure 6AMethod 600A Figure 6B Method 600B and / or Figure 13 Method 1300, and Figure 8 Electronic circuit 800, Figure 10 Electronic circuit 1000, Figure 11 Electronic circuit 1100 and / or Figure 12 The electronic circuitry 1200 is implemented in the PHY layer 1410 of the IEEE 802.15.4 protocol stack 1400. In one or more alternative examples, variations in the preamble length for transmit power level control can be applied for other communication standards such as Bluetooth, Wi-Fi, and sub-GHz.

[0128] Figure 15 This is a block diagram of circuitry 1500, which in some examples can be used to implement the various functions, operations, actions, processes, and / or methods disclosed herein. Circuitry 1500 includes one or more processors 1504 (sometimes referred to herein as "processor 1504") operatively coupled to one or more data storage devices (sometimes referred to herein as "storage device 1506"). Storage device 1506 includes machine-executable code 1508 stored thereon, and processor 1504 includes logic circuitry 1510. Machine-executable code 1508 includes information describing functional elements that can be implemented (e.g., executed by) logic circuitry 1510. Logic circuitry 1510 is adapted to implement (e.g., execute) the functional elements described by machine-executable code 1508. When executing the functional elements described by machine-executable code 1508, circuitry 1500 should be considered as dedicated hardware for executing the functional elements disclosed herein. In some examples, processor 1504 may execute the functional elements described by machine-executable code 1508 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel process flows.

[0129] When implemented by the logic circuitry 1510 of processor 1504, machine-executable code 1508 adapts processor 1504 to perform the operations of the examples disclosed herein. For example, machine-executable code 1508 can be used to adapt processor 1504 to perform the methods or processes described herein (e.g., with...). Figure 7 The methods or processes associated with the application receiving processing module 710 and the application transmitting processing module 712, and / or with Figure 14 At least part or all of the methods or processes associated with layer 3 and above 1402.

[0130] Processor 1504 may include a general-purpose processor, special-purpose processor, central processing unit (CPU), microcontroller, programmable logic controller (PLC), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware unit, other programmable device, or any combination thereof, designed to perform the functions disclosed herein. A general-purpose computer including a processor is considered a special-purpose computer when it executes functional elements corresponding to the machine-executable code 1508 (e.g., software code, firmware code, hardware description) associated with the examples of this disclosure. It should be noted that the general-purpose processor (also referred to herein as a host processor or simply host) may be a microprocessor, but in alternative embodiments, processor 1504 may include any conventional processor, controller, microcontroller, or state machine. Processor 1504 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0131] In some examples, storage device 1506 includes volatile data storage devices (e.g., random access memory (RAM)) and non-volatile data storage devices (e.g., flash memory, hard disk drive, solid-state drive, erasable programmable read-only memory (EPROM), etc.). In some examples, processor 1504 and storage device 1506 may be implemented in a single device (e.g., semiconductor device product, system-on-a-chip (SoC), etc.). In some examples, processor 1504 and storage device 1506 may be implemented in a separate device.

[0132] In some examples, the machine-executable code 1508 may include computer-readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer-readable instructions may be stored on storage device 1506, directly accessed by processor 1504, and executed by processor 1504 using at least logic circuitry 1510. Also by way of non-limiting example, the computer-readable instructions may be stored on storage device 1506, passed to a memory device (not shown) for execution, and executed by processor 1504 using at least logic circuitry 1510. Thus, in some examples, logic circuitry 1510 includes logic circuitry 1510 that can be configured electrically.

[0133] In some examples, machine-executable code 1508 may describe hardware (e.g., circuitry) to be implemented in logic circuitry 1510 to perform functional elements. This hardware can be described from any of a range of abstraction levels, from low-level transistor layout to high-level description languages. At high-level abstraction, hardware description languages ​​(HDLs), such as the IEEE standard hardware description language (HDL), can be used. VERILOG can be used by way of non-limiting example. ™ SYSTEMVERILOG ™ Or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL) ™ ).

[0134] HDL descriptions can be converted into descriptions at any of a variety of other levels of abstraction as needed. As a non-limiting example, a high-level description can be converted into a logic-level description such as Register Pass Language (RTL), Gate-level (GL) description, Placement-level description, or Mask-level description. As a non-limiting example, micro-operations to be performed by the hardware logic circuitry of logic circuitry 1510 (e.g., gates, flip-flops, registers, but not limited thereto) can be described in RTL and then converted into a GL description by a synthesis tool. The GL description can then be converted into a placement-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, discrete gate or transistor logic unit, discrete hardware unit, or a combination thereof of the programmable logic device. Therefore, in some examples, machine-executable code 1508 may include HDL, RTL, GL descriptions, Mask-level descriptions, other hardware descriptions, or any combination thereof.

[0135] In an example where machine-executable code 1508 includes a hardware description (at any level of abstraction), a system (not shown, but including storage device 1506) can be used to implement the hardware description described by machine-executable code 1508. By way of non-limiting example, processor 1504 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1510 may be electrically controlled to implement the circuitry corresponding to the hardware description as logic circuitry 1510. Also by way of non-limiting example, logic circuitry 1510 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage device 1506) according to the hardware description of machine-executable code 1508.

[0136] Regardless of whether the machine-executable code 1508 includes computer-readable instructions or a hardware description, the logic circuit 1510 is adapted to execute the functional elements described by the machine-executable code 1508 when implementing the functional elements of the machine-executable code 1508. It should be noted that although the hardware description may not directly describe the functional elements, it indirectly describes the functional elements that the hardware elements described by the hardware description can execute.

[0137] As used in this disclosure, the terms "module" or "component" can refer to a specific hardware implementation for performing the actions of a module or component and / or a software object or software routine that can be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, processing device, etc.). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes that execute on a computing system (e.g., as separate threads). While some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and conceivable.

[0138] As used in this disclosure, the term "combination" referring to multiple elements can include a combination of all elements or any one of various different sub-combinations of certain elements. For example, the phrase "A, B, C, D or combinations thereof" can refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any sub-combination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0139] Terms used in this disclosure, and especially in the appended claims (e.g., the body of the appended claims), are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, the term “comprising” should be interpreted as “including but not limited to”, etc.).

[0140] Furthermore, if a specific number of introduced claim statements are anticipated, such an intent will be explicitly stated in the claims, and without such statements, no such intent exists. For example, as an aid to understanding, the appended claims may contain the use of the introductory phrases “at least one” and “one or more” to introduce claim statements. However, the use of such phrases should not be construed as implying that a claim statement introduced by the indefinite article “a” or “an” limits any particular claim containing such an introduced claim statement to an example containing only one such statement, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an” (e.g., “a” and / or “an” can be interpreted as referring to “at least one” or “one or more”); the same applies to the use of definite articles to introduce claim statements.

[0141] Furthermore, even when a specific number of the introduced claims are explicitly stated, those skilled in the art will recognize that such statements should be interpreted as meaning at least the number stated (e.g., the unmodified statement "two statements" means at least two statements, or two or more statements, in the absence of other modifying elements). Moreover, in those instances where conventional expressions such as "at least one of A, B, and C" or "one or more of A, B, and C" are used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, etc.

[0142] Any separate word or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to include the possibility of including one term, any one of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibility of including "A" or "B" or "A and B".

[0143] The following is a non-exhaustive and non-limiting list of embodiments. Not every embodiment listed below is explicitly and individually indicated to be combinable with all other embodiments listed below and discussed above. However, it is intended that these embodiments be combinable with all other embodiments unless it would be obvious to those skilled in the art that these embodiments are not combinable.

[0144] Example 1: A method comprising: at a transceiver, receiving a first communication signal including a first message; detecting the signal strength of the first communication signal; generating a preamble having a preamble bit length adjusted at least in part based on the detected signal strength of the first communication signal; and transmitting a second communication signal including a second message, the second message including the preamble having the preamble bit length.

[0145] Example 2: According to the method of Example 1, the method includes: at the transceiver, comparing the detected signal strength with one or more thresholds, wherein the preamble bit length of the preamble is adjusted at least in part based on the result of the comparison.

[0146] Example 3: The method according to any one of Examples 1 and 2, the method comprising: at the transceiver, generating a preamble having a preamble bit length including a first preamble bit length based at least in part on the result of the comparison indicating that the detected signal strength is greater than a threshold; and generating a preamble having a preamble bit length including a second preamble bit length based at least in part on the result of the comparison indicating that the detected signal strength is less than the threshold.

[0147] Example 4: A method according to any one of Examples 1 to 3, the method comprising: at the transceiver, generating a preamble having a preamble bit length including a first preamble bit length, at least partially based on the result of the comparison indicating that the detected signal strength is greater than a target threshold range, the target threshold range being defined by the one or more thresholds; generating a preamble having a preamble bit length including a second preamble bit length, at least partially based on the result of the comparison indicating that the detected signal strength is within the target threshold range; and generating a preamble having a preamble bit length including a third preamble bit length, at least partially based on the result of the comparison indicating that the detected signal strength is less than the target threshold range.

[0148] Example 5: The method according to any one of Examples 1 to 4, wherein: the length of the second preamble bit is A bits, the length of the first preamble bit is one of (AZ) bits or (A+Z) bits, the length of the third preamble bit is the other of (AZ) bits or (A+Z) bits, and wherein A and Z are predetermined positive integer constants, and A>Z.

[0149] Example 6: The method according to any one of Examples 1 to 5, wherein: A bits = (X+Y) bits, and wherein X and Y are predetermined positive integer constants, X is a predetermined preamble bit length of the preamble specified in the communication standard compatible with the transceiver, and Y>Z.

[0150] Example 7: The method according to any one of Examples 1 to 6, wherein: the second preamble bit length is X bits, the first preamble bit length is (X+J) bits, the third preamble bit length is (X+K) bits, and wherein X, J and K are predetermined positive integer constants, X is a predetermined preamble bit length of the preamble specified in the communication standard compatible with the transceiver, and J≠K.

[0151] Example 8: The method according to any one of Examples 1 to 7, the method comprising: at the transceiver, detecting the preamble bit length of the preamble bit of the first message of the first communication signal; and adjusting the transmission power level for transmitting the second communication signal based at least in part on the preamble bit length of the first message.

[0152] Example 9: A method according to any one of Examples 1 to 8, the method comprising: at the transceiver, detecting the preamble bit length of the preamble bit of the first message of the first communication signal; reducing the transmission power level for transmitting the second communication signal based at least in part on the preamble bit length including a first preamble bit length; maintaining the transmission power level for transmitting the second communication signal based at least in part on the preamble bit length including a second preamble bit length; and increasing the transmission power level for transmitting the second communication signal based at least in part on the preamble bit length including a third preamble bit length.

[0153] Example 10: The method according to any one of Examples 1 to 9, wherein the preamble having the preamble bit length includes instructions to another transceiver to adjust the transmit power level for transmission according to the preamble bit length.

[0154] Example 11: An apparatus comprising: a transceiver, the transceiver including: a received signal strength indicator circuit for detecting the signal strength of a first communication signal including a first message; a comparator circuit for comparing the detected signal strength of the first communication signal with one or more thresholds; and a preamble sequence generator circuit for generating a preamble for a second message of a second communication signal for transmission, the preamble sequence generator circuit being configured to adjust the preamble bit length of the preamble based at least in part on one or more outputs of the comparator circuit.

[0155] Example 12: The apparatus according to Example 11, wherein: the preamble sequence generator circuit is configured to: generate a preamble having a preamble bit length including a first preamble bit length based at least in part on the one or more outputs of the comparator circuit indicating that the detected signal strength is greater than a threshold; and generate a preamble having a preamble bit length including a second preamble bit length based at least in part on the one or more outputs of the comparator circuit indicating that the detected signal strength is less than the threshold.

[0156] Example 13: An apparatus according to any one of Examples 11 and 12, wherein: the preamble sequence generator circuit is configured to: generate a preamble having a preamble bit length including a first preamble bit length, based at least in part on the one or more outputs of the comparator circuit indicating that the detected signal strength is greater than a target threshold range, the target threshold range being defined by the one or more thresholds; generate a preamble having a preamble bit length including a second preamble bit length, based at least in part on the one or more outputs of the comparator circuit indicating that the detected signal strength is within the target threshold range; and generate a preamble having a preamble bit length including a third preamble bit length, based at least in part on the one or more outputs of the comparator circuit indicating that the detected signal strength is less than the target threshold range.

[0157] Example 14: The apparatus according to any one of Examples 11 to 13, wherein: the length of the second preamble bit is A bits, the length of the first preamble bit is one of (AZ) bits or (A+Z) bits, the length of the third preamble bit is the other of (AZ) bits or (A+Z) bits, and wherein A and Z are predetermined positive integer constants, wherein A>Z.

[0158] Example 15: An apparatus according to any one of Examples 11 to 14, wherein the transceiver includes a transceiver PHY, the transceiver PHY including the received signal strength indicator circuit, the comparator circuit and the preamble sequence generator circuit, the apparatus including: an analog-to-digital converter, the analog-to-digital converter being used to convert an analog value of the detected signal strength into a digital value, the analog-to-digital converter being used to provide the digital value of the detected signal strength to the input of the comparator circuit.

[0159] Example 16: An apparatus according to any one of Examples 11 to 15, wherein: the transceiver includes: a preamble bit length detector circuit for detecting the preamble bit length of the preamble of the first message of the first communication signal; a transmitter amplifier; a gain adjustment circuit for adjusting the gain of the transmitter amplifier at least in part based on the detected preamble bit length; and the transmitter amplifier for amplifying a second communication signal including a second message for transmission with the adjusted gain.

[0160] Example 17: An apparatus according to any one of Examples 11 to 16, wherein: the gain adjustment circuit is used to reduce the gain of the transmitter amplifier based at least in part on the preamble bit length including a first preamble bit length, and the gain adjustment circuit is used to increase the gain of the transmitter amplifier based at least in part on the preamble bit length including a second preamble bit length.

[0161] Example 18: An apparatus according to any one of Examples 11 to 17, wherein: the preamble bit length detector circuit includes a first counter circuit for maintaining a count of the received bits of the preamble to reach a total count of the received bits of the preamble, and the gain adjustment circuit includes a second counter circuit for maintaining a gain control count for adjusting the gain of the transmitter amplifier, the second counter circuit for incrementing or decrementing the gain control count at least in part based on the total count of the received bits of the preamble from the first counter circuit.

[0162] Example 19: A method comprising: receiving, at a transceiver, a first communication signal including a first message; detecting a preamble bit length of a preamble bit of the first message; adjusting the gain of a transmitter amplifier of the transceiver at least in part based on the preamble bit length of the preamble bit; amplifying the second communication signal including a second message with the transmitter amplifier having the adjusted gain; and transmitting the amplified second communication signal including the second message.

[0163] Example 20: According to the method of Example 19, the method includes: at the transceiver, at least in part based on the preamble bit length including a first preamble bit length, reducing the gain of the transmitter amplifier for transmitting the amplified second communication signal; and at least in part based on the preamble bit length including a second preamble bit length, increasing the gain of the transmitter amplifier for transmitting the amplified second communication signal.

[0164] Example 21: The method according to any one of Examples 19 and 20, the method comprising: at the transceiver, reducing the gain of the transmitter amplifier for transmitting the amplified second communication signal based at least in part on the preamble bit length including a first preamble bit length; maintaining the gain of the transmitter amplifier for transmitting the amplified second communication signal based at least in part on the preamble bit length including a second preamble bit length; and increasing the gain of the transmitter amplifier for transmitting the amplified second communication signal based at least in part on the preamble bit length including a third preamble bit length.

[0165] Example 22: The method according to any one of Examples 19 to 21, wherein: the length of the second preamble bit is A bits, the length of the first preamble bit is one of (AZ) bits or (A+Z) bits, the length of the third preamble bit is the other of (AZ) bits or (A+Z) bits, and wherein A and Z are predetermined positive integer constants, wherein A>Z.

[0166] Example 23: The method according to any one of Examples 19 to 22, wherein: detecting the preamble bit length of the preamble includes maintaining a count of the received bits of the preamble to reach a total count of the received bits of the preamble, and adjusting the gain of the transmitter amplifier includes adjusting the gain of the transmitter amplifier at least in part based on the total count of the received bits of the preamble.

[0167] Example 24: The method according to any one of Examples 19 to 23, wherein: detecting the preamble bit length of the preamble includes maintaining a count of the received bits of the preamble to reach a total count of the received bits of the preamble; adjusting the gain of the transmitter amplifier includes incrementing or decrementing a gain control count for adjusting the gain based at least in part on the total count of the received bits of the preamble; and repeating the adjustment, the amplification, and the transmission based at least in part on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble.

[0168] Example 25: The method according to any one of Examples 19 to 24, the method comprising: at the transceiver, detecting the signal strength of the first communication signal; and generating a preamble having a preamble bit length adjusted at least partially based on the detected signal strength, wherein transmitting the amplified second communication signal comprises transmitting the amplified second communication signal including the second message, the second message carrying the preamble having the preamble bit length.

[0169] Example 26: The method according to any one of Examples 19 to 25, the method comprising: at the transceiver, comparing the detected signal strength with one or more thresholds, wherein the preamble bit length of the preamble of the second message is adjusted at least in part based on the result of the comparison.

[0170] Example 27: A method according to any one of Examples 19 to 26, the method comprising: at the transceiver, generating a preamble having a preamble bit length including a first preamble bit length, at least partially based on the result of the comparison indicating that the detected signal strength is greater than a target threshold range, the target threshold range being defined by the one or more thresholds; generating a preamble having a preamble bit length including a second preamble bit length, at least partially based on the result of the comparison indicating that the detected signal strength is within the target threshold range; and generating a preamble having a preamble bit length including a third preamble bit length, at least partially based on the result of the comparison indicating that the detected signal strength is less than the target threshold range.

[0171] Example 28: The method according to any one of Examples 19 to 27, wherein the preamble in the second message having the preamble bit length includes an instruction to another transceiver to adjust the transmit power level for transmission according to the preamble bit length.

[0172] Example 29: The method according to any one of Examples 19 to 28, the method comprising: receiving, at another transceiver, a second communication signal including a second message having the preamble; and adjusting a transmit power level for transmission based at least in part on the preamble bit length of the preamble.

[0173] Example 30: An apparatus comprising: a transceiver, the transceiver including: a preamble bit length detector circuit for detecting the preamble bit length of a first message of a first communication signal; a transmitter amplifier; a gain adjustment circuit for adjusting the gain of the transmitter amplifier at least partially based on the detected preamble bit length; and the transmitter amplifier for using the adjusted gain to amplify a second communication signal including a second message for transmission.

[0174] Example 31: The apparatus according to Example 30, wherein the transceiver includes a transceiver PHY, the transceiver PHY includes the preamble bit length detector circuit, the transmitter amplifier and the gain adjustment circuit, and the preamble bit length detector circuit includes a counter circuit for maintaining the count of the received bits of the preamble.

[0175] Example 32: An apparatus according to any one of Examples 30 and 31, wherein: the preamble bit length detector circuit includes a first counter circuit for maintaining a count of received bits of the preamble to reach a total count of received bits of the preamble; the gain adjustment circuit includes a second counter circuit for maintaining a gain control count for adjusting the gain of the transmitter amplifier; the second counter circuit is configured to increment or decrement the gain control count at least in part based on the total count of received bits of the preamble from the first counter circuit; wherein the gain adjustment circuit is configured to repeat the adjustment of the gain at least in part based on a corresponding preamble bit length in a subsequently detected preamble bit length of a subsequently received preamble.

[0176] Example 33: An apparatus according to any one of Examples 30 to 32, wherein: the gain adjustment circuit is configured to: reduce the gain of the transmitter amplifier based at least in part on the preamble bit length including a first preamble bit length; and increase the gain of the transmitter amplifier based at least in part on the preamble bit length including a second preamble bit length.

[0177] Example 34: An apparatus according to any one of Examples 30 to 33, wherein: the gain adjustment circuit is configured to: reduce the gain of the transmitter amplifier at least partially based on the preamble bit length including a first preamble bit length; maintain the gain of the transmitter amplifier at least partially based on the preamble bit length including a second preamble bit length; and increase the gain of the transmitter amplifier at least partially based on the preamble bit length including a third preamble bit length.

[0178] Example 35: The apparatus according to any one of Examples 30 to 34, wherein: the second preamble bit length is A bits, the first preamble bit length is one of (AZ) bits or (A+Z) bits, the third preamble bit length is the other of (AZ) bits or (A+Z) bits, and wherein A and Z are predetermined positive integer constants, wherein A>Z.

[0179] Example 36: An apparatus according to any one of Examples 30 to 35, wherein: the transceiver comprises: a received signal strength detector for detecting the signal strength of the first communication signal; a comparator circuit for comparing the detected signal strength of the first communication signal with one or more thresholds; and a preamble sequence generator circuit for generating a preamble for the second message, the preamble sequence generator circuit being configured to adjust the preamble bit length of the preamble based at least in part on one or more outputs of the comparator circuit.

[0180] While this disclosure describes certain illustrative examples, those skilled in the art will recognize and understand that this disclosure is not limited thereto. Rather, many additions, deletions, and modifications may be made to the illustrative and described embodiments without departing from the scope of the invention as claimed below and its legal equivalents. Furthermore, features from one embodiment may be combined with features from another embodiment while still being included within the scope of the invention as contemplated by the inventors.

Claims

1. A method, the method comprising: At the transceiver Receive a first communication signal including a first message; Detect the signal strength of the first communication signal; Generate a preamble having a preamble bit length adjusted at least in part based on the detected signal strength of the first communication signal; as well as A second communication signal is sent, comprising a second message, the second message including the preamble having the preamble bit length.

2. The method according to claim 1, wherein the method comprises: At the transceiver, The detected signal strength is compared with one or more thresholds. The preamble bit length of the preamble is adjusted at least in part based on the result of the comparison.

3. The method according to claim 2, wherein the method comprises: At the transceiver, Based at least in part on the result of the comparison indicating that the detected signal strength is greater than a threshold, a preamble is generated having a preamble bit length including a first preamble bit length; as well as Based at least in part on the result of the comparison indicating that the detected signal strength is less than the threshold, a preamble is generated having a preamble bit length including a second preamble bit length.

4. The method according to claim 2, wherein the method comprises: At the transceiver, Based at least in part on the result of the comparison indicating that the detected signal strength is greater than a target threshold range, a preamble is generated having a preamble bit length including a first preamble bit length, the target threshold range being defined by the one or more thresholds; Based at least in part on the result of the comparison indicating that the detected signal strength is within the target threshold range, a preamble with a preamble bit length including a second preamble bit length is generated; as well as Based at least in part on the result of the comparison indicating that the detected signal strength is less than the target threshold range, a preamble with a preamble bit length including a third preamble bit length is generated.

5. The method according to claim 4, wherein: The second preamble bit length is A bits. The length of the first preamble bit is either (AZ) bits or (A+Z) bits. The length of the third preamble bit is either (AZ) bits or (A+Z) bits, and Where A and Z are predetermined positive integer constants, and A > Z.

6. The method according to claim 5, wherein: A position = (X + Y) positions, and Where X and Y are predetermined positive integer constants, X is the predetermined preamble bit length of the preamble specified in the communication standard compatible with the transceiver, and Y>Z.

7. The method according to claim 4, wherein: The second preamble bit length is X bits. The length of the first preamble bit is (X+J) bits. The length of the third preamble bit is (X+K) bits, and Where X, J, and K are predetermined positive integer constants, X is the predetermined preamble bit length of the preamble specified in the communication standard compatible with the transceiver, and J≠K.

8. The method according to claim 1, wherein the method comprises: At the transceiver, Detect the length of the preamble bits of the first message of the first communication signal; as well as The transmission power level for transmitting the second communication signal is adjusted at least in part based on the preamble bit length of the first message.

9. The method according to claim 8, wherein the method comprises: At the transceiver, Detect the length of the preamble bits of the first message of the first communication signal; The transmit power level used to transmit the second communication signal is reduced, at least in part based on the preamble bit length, including the first preamble bit length. The transmit power level for transmitting the second communication signal is maintained at least in part based on the preamble bit length, including a second preamble bit length; and The transmit power level for transmitting the second communication signal is increased, at least in part based on the preamble bit length, including a third preamble bit length.

10. The method of claim 1, wherein the preamble having the preamble bit length includes instructions to another transceiver to adjust the transmit power level for transmission according to the preamble bit length.

11. An apparatus comprising: Transceiver, the transceiver comprising: A received signal strength indicator circuit is used to detect the signal strength of a first communication signal including a first message; A comparator circuit is used to compare the detected signal strength of the first communication signal with one or more thresholds; and A preamble sequence generator circuit is used to generate a preamble for a second message of a second communication signal for transmission, and the preamble sequence generator circuit is used to adjust the preamble bit length of the preamble based at least in part on one or more outputs of the comparator circuit.

12. The apparatus according to claim 11, wherein: The preamble sequence generator circuit is used for: The preamble is generated, at least in part, based on the indication from one or more outputs of the comparator circuit that the detected signal strength is greater than a threshold; and The preamble is generated at least in part based on the indication from one or more outputs of the comparator circuit that the detected signal strength is less than the threshold. The preamble has a preamble bit length including a second preamble bit length.

13. The apparatus according to claim 11, wherein: The preamble sequence generator circuit is used for: The preamble is generated at least in part based on the one or more outputs of the comparator circuit indicating that the detected signal strength is greater than a target threshold range, having a preamble bit length including a first preamble bit length, the target threshold range being defined by the one or more thresholds; The preamble is generated with a preamble bit length including a second preamble bit length, based at least in part on the indication of the detected signal strength by one or more outputs of the comparator circuit within the target threshold range. as well as The preamble is generated with a preamble bit length including a third preamble bit length, based at least in part on the indication from one or more outputs of the comparator circuit that the detected signal strength is less than the target threshold range.

14. The apparatus according to claim 13, wherein: The second preamble bit length is A bits. The length of the first preamble bit is either (AZ) bits or (A+Z) bits. The length of the third preamble bit is either (AZ) bits or (A+Z) bits, and Where A and Z are predetermined positive integer constants, where A > Z.

15. The apparatus of claim 11, wherein the transceiver comprises a transceiver PHY, the transceiver PHY comprising the received signal strength indicator circuit, the comparator circuit, and the preamble sequence generator circuit, the apparatus comprising: An analog-to-digital converter (ADC) is used to convert an analog value of the detected signal strength into a digital value, and the ADC is used to provide the digital value of the detected signal strength to the input of the comparator circuit.

16. The apparatus according to claim 11, wherein: The transceiver includes: A preamble bit length detector circuit is used to detect the preamble bit length of the first message of the first communication signal; Transmitter amplifier; A gain adjustment circuit, the gain adjustment circuit being used to adjust the gain of the transmitter amplifier at least in part based on the detected preamble bit length; and The transmitter amplifier is used to amplify a second communication signal, including the second message, with an adjusted gain for transmission.

17. The apparatus according to claim 16, wherein: The gain adjustment circuit is used to reduce the gain of the transmitter amplifier based at least in part on the preamble bit length, including a first preamble bit length, and the gain adjustment circuit is used to increase the gain of the transmitter amplifier based at least in part on the preamble bit length, including a second preamble bit length.

18. The apparatus according to claim 16, wherein: The preamble bit length detector circuit includes a first counter circuit, which is used to maintain the count of the received bits of the preamble to reach the total count of the received bits of the preamble. The gain adjustment circuit includes a second counter circuit for maintaining a gain control count for adjusting the gain of the transmitter amplifier, the second counter circuit for incrementing or decrementing the gain control count based at least in part on the total count of the received bits of the preamble from the first counter circuit.

19. A method comprising: At the transceiver Receive a first communication signal including a first message; Detect the length of the preamble bits of the preamble of the first message; The gain of the transceiver's transmitter amplifier is adjusted at least in part based on the length of the preamble bit of the preamble; The second communication signal, including the second message, is amplified using the transmitter amplifier with the adjusted gain; and Send an amplified second communication signal that includes the second message.

20. The method of claim 19, wherein the method comprises: At the transceiver, At least in part based on the preamble bit length including the first preamble bit length, the gain of the transmitter amplifier used to transmit the amplified second communication signal is reduced; and The gain of the transmitter amplifier for transmitting the amplified second communication signal is increased, at least in part based on the preamble bit length, including the second preamble bit length.

21. The method of claim 19, wherein the method comprises: At the transceiver, At least in part based on the preamble bit length, including the first preamble bit length, the gain of the transmitter amplifier used to transmit the amplified second communication signal is reduced; The gain of the transmitter amplifier for transmitting the amplified second communication signal is maintained at least in part based on the preamble bit length, including the second preamble bit length; and The gain of the transmitter amplifier for transmitting the amplified second communication signal is increased, at least in part based on the preamble bit length, including the third preamble bit length.

22. The method of claim 21, wherein: The second preamble bit length is A bits. The length of the first preamble bit is either (AZ) bits or (A+Z) bits. The length of the third preamble bit is either (AZ) bits or (A+Z) bits, and Where A and Z are predetermined positive integer constants, where A > Z.

23. The method according to claim 19, wherein: Detecting the preamble bit length includes maintaining a count of the received bits of the preamble to reach a total count of the received bits of the preamble, and Adjusting the gain of the transmitter amplifier includes adjusting the gain of the transmitter amplifier based at least in part on the total count of the received bits of the preamble.

24. The method of claim 19, wherein: Detecting the preamble bit length of the preamble includes maintaining a count of the received bits of the preamble to reach a total count of the received bits of the preamble. Adjusting the gain of the transmitter amplifier includes incrementing or decrementing a gain control count for adjusting the gain, at least in part based on the total count of the received bits of the preamble. The adjustment, the amplification, and the transmission are repeated at least in part based on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble.

25. The method according to claim 19, wherein the method comprises: At the transceiver, Detect the signal strength of the first communication signal; as well as Generate a preamble with a preamble bit length adjusted at least in part based on the detected signal strength. Sending the amplified second communication signal includes sending the amplified second communication signal including the second message, wherein the second message carries the preamble having the preamble bit length.

26. The method of claim 25, wherein the method comprises: At the transceiver, The detected signal strength is compared with one or more thresholds. The length of the preamble bit in the second message is adjusted at least in part based on the result of the comparison.

27. The method of claim 26, wherein the method comprises: At the transceiver, Based at least in part on the result of the comparison indicating that the detected signal strength is greater than a target threshold range, a preamble is generated having a preamble bit length including a first preamble bit length, the target threshold range being defined by the one or more thresholds; Based at least in part on the result of the comparison indicating that the detected signal strength is within the target threshold range, a preamble with a preamble bit length including a second preamble bit length is generated; as well as Based at least in part on the result of the comparison indicating that the detected signal strength is less than the target threshold range, a preamble with a preamble bit length including a third preamble bit length is generated.

28. The method of claim 25, wherein the preamble having the preamble bit length in the second message includes an instruction to another transceiver to adjust the transmit power level for transmission according to the preamble bit length.

29. The method of claim 25, wherein the method comprises: At another transceiver, Receive the second communication signal including the second message having the preamble; as well as The transmit power level used for transmission is adjusted at least in part based on the length of the preamble bits of the preamble.

30. An apparatus comprising: Transceiver, the transceiver comprising: A preamble bit length detector circuit is used to detect the preamble bit length of the preamble bit of the first message of the first communication signal. Transmitter amplifier; A gain adjustment circuit, the gain adjustment circuit being used to adjust the gain of the transmitter amplifier at least in part based on the detected preamble bit length; and A transmitter amplifier is used to amplify a second communication signal, including a second message, using an adjusted gain for transmission.

31. The apparatus of claim 30, wherein the transceiver includes a transceiver PHY, the transceiver PHY including the preamble bit length detector circuit, the transmitter amplifier and the gain adjustment circuit, and the preamble bit length detector circuit including a counter circuit for maintaining a count of the received bits of the preamble.

32. The apparatus according to claim 30, wherein: The preamble bit length detector circuit includes a first counter circuit, which is used to maintain the count of the received bits of the preamble to reach the total count of the received bits of the preamble. The gain adjustment circuit includes a second counter circuit for maintaining a gain control count for adjusting the gain of the transmitter amplifier. The second counter circuit is used to increment or decrement the gain control count based at least in part on the total count of the received bits of the preamble from the first counter circuit. The gain adjustment circuit is used to repeat the adjustment of the gain at least in part based on the corresponding preamble bit length in the subsequently detected preamble bit length of the subsequently received preamble.

33. The apparatus according to claim 30, wherein: The gain adjustment circuit is used for: The gain of the transmitter amplifier is reduced at least in part based on the preamble bit length, including the first preamble bit length; and The gain of the transmitter amplifier is increased at least in part based on the preamble bit length, including the second preamble bit length.

34. The apparatus according to claim 30, wherein: The gain adjustment circuit is used for: The gain of the transmitter amplifier is reduced at least in part based on the preamble bit length, including the first preamble bit length. The gain of the transmitter amplifier is maintained at least in part based on the preamble bit length, including the second preamble bit length; and The gain of the transmitter amplifier is increased at least in part based on the preamble bit length, including a third preamble bit length.

35. The apparatus according to claim 34, wherein: The second preamble bit length is A bits. The length of the first preamble bit is either (AZ) bits or (A+Z) bits. The length of the third preamble bit is either (AZ) bits or (A+Z) bits, and Where A and Z are predetermined positive integer constants, where A > Z.

36. The apparatus according to claim 30, wherein: The transceiver includes: A received signal strength detector, wherein the received signal strength detector is used to detect the signal strength of the first communication signal; A comparator circuit is used to compare the detected signal strength of the first communication signal with one or more thresholds; and A preamble sequence generator circuit is used to generate a preamble for the second message, and the preamble sequence generator circuit is used to adjust the preamble bit length of the preamble based at least in part on one or more outputs of the comparator circuit.

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