Electronic device for testing semiconductor devices and testing method

Abstract

This invention provides an electronic device and a testing method for testing semiconductor devices. The semiconductor device includes a first metal layer, a second metal layer, a first via element, and a first ground via element. The first via element is coupled between the first metal layer and the second metal layer. The first ground via element is coupled to ground and disposed adjacent to the first via element. The electronic device includes a detector and a processor. The detector detects a first floating region associated with the first metal layer, a first distance between the first via element and the first ground via element, and a first contact region between the second metal layer and the first via element. The processor is coupled to the detector. The processor performs a first layout verification process on the second metal layer based on the first floating region, the first distance, the first contact region, and a first layout criterion.

Description

Technical Field

[0001] This invention generally relates to an electronic device, and more specifically, to an electronic device for reducing the probability of failure of an integrated circuit (IC). Background Technology

[0002] Antenna effect, more formally known as plasma-induced gate oxide damage, is an effect that can lead to yield and reliability problems during the fabrication of metal-oxide-semiconductor (MOS) integrated circuits. Therefore, a novel solution is needed to address the problems in existing technologies. Summary of the Invention

[0003] In one exemplary embodiment, the present invention relates to an electronic device for testing a semiconductor device. The semiconductor device includes a first metal layer, a second metal layer, a first via element, and a first ground via element. The first via element is coupled between the first metal layer and the second metal layer. The first ground via element is coupled to ground and disposed adjacent to the first via element. The electronic device includes a detector and a processor. The detector is used to detect a first floating region associated with the first metal layer, a first distance between the first via element and the first ground via element, and a first contact region between the second metal layer and the first via element. The processor is coupled to the detector. The processor performs a first layout verification process on the second metal layer based on the first floating region, the first distance, the first contact region, and a first layout criterion.

[0004] In some embodiments, the processor performs the first layout verification process to compare a first antenna integrity parameter with the first layout criterion. The first antenna integrity parameter is calculated by the processor using the following formula:

[0005]

[0006] Where “T1” represents the integrity parameter of the first antenna, “A1” represents the first floating area, “C1” represents the first contact area, “R1” represents the first distance, and “N” represents the first positive number.

[0007] In some embodiments, if the first antenna integrity parameter is less than or equal to the first layout criterion, the processor determines that the first layout verification process has passed. If the first antenna integrity parameter is greater than the first layout criterion, the processor determines that the first layout verification process has failed.

[0008] In some embodiments, the first positive number is equal to 1 or 2.

[0009] In some embodiments, the semiconductor device further includes a third metal layer, a second via element, and a second ground via element. The second via element is coupled between the second metal layer and the third metal layer. The second ground via element is coupled to ground and is disposed adjacent to the second via element. The detector further detects a second floating region associated with the second metal layer, a second distance between the second via element and the second ground via element, and a second contact region between the third metal layer and the second via element. The processor further performs a second layout verification process on the third metal layer based on the first floating region, the second floating region, the second distance, the second contact region, and a second layout criterion.

[0010] In some embodiments, the processor performs the second layout verification process to compare the second antenna integrity parameter with the second layout criterion. The second antenna integrity parameter is calculated by the processor using the following formula:

[0011]

[0012] Where “T2” represents the second antenna integrity parameter, “A1” represents the first floating area, “A2” represents the second floating area, “C2” represents the second contact area, “R2” represents the second distance, and “M” represents the second positive number.

[0013] In some embodiments, if the second antenna integrity parameter is less than or equal to the second layout criterion, the processor determines that the second layout verification process has passed. If the second antenna integrity parameter is greater than the second layout criterion, the processor determines that the second layout verification process has failed.

[0014] In some embodiments, the second positive number is equal to 1 or 2.

[0015] In another exemplary embodiment, the present invention relates to a testing method comprising the following steps: providing a first metal layer, a second metal layer, a first conductive via element, and a first ground via element, wherein the first conductive via element is coupled between the first metal layer and the second metal layer, and wherein the first ground via element is coupled to ground voltage and disposed next to the first conductive via element; detecting a first floating region associated with the first metal layer; detecting a first distance between the first conductive via element and the first ground via element; detecting a first contact region between the second metal layer and the first conductive via element; and performing a first layout verification process on the second metal layer according to the first floating region, the first distance, the first contact region, and a first layout criterion. Attached Figure Description

[0016] The invention can be more fully understood by reading the following detailed description and examples, in conjunction with the accompanying drawings, in which:

[0017] Figure 1A This is a top view of a semiconductor device and electronic apparatus according to embodiments of the present invention;

[0018] Figure 1B This is a side view of a semiconductor device according to an embodiment of the present invention;

[0019] Figure 2A This is a top view of a semiconductor device and electronic apparatus according to embodiments of the present invention;

[0020] Figure 2B This is a side view of a semiconductor device according to an embodiment of the present invention;

[0021] Figure 3 This is a top view of a semiconductor device according to an embodiment of the present invention; and

[0022] Figure 4 This is a flowchart of a testing method according to an embodiment of the present invention. Detailed Implementation

[0023] To illustrate the purpose, features, and advantages of the present invention, embodiments and illustrations of the present invention are shown in detail below.

[0024] Throughout the specification and claims, certain terms are used to refer to specific components. Those skilled in the art will understand that manufacturers may use different names to refer to a component. This document is not intended to distinguish between components with different names but identical functions. In the following description and claims, the terms "comprising" and "including" are used in an open-ended manner and should therefore be interpreted as "including, but not limited to...". The term "substantially" indicates that the value is within an acceptable tolerance range. Those skilled in the art can solve the technical problem and achieve the intended technical performance within the predetermined tolerance range. Furthermore, the term "coupled" means that it can be an indirect or direct electrical connection. Therefore, if one device is coupled to another device, the connection can be a direct electrical connection or an indirect electrical connection via other devices and connections.

[0025] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. To simplify this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For instance, the formation of a first feature on or above a second feature in the following description may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and does not, in itself, determine the relationship between the various embodiments and / or configurations discussed.

[0026] In addition, spatial relative terms such as “below,” “under,” “lower,” “above,” “above,” etc., may be used here to describe the relationship between one element or feature and another, as shown in the figure. Spatial relative terms are intended to cover different orientations of the device in use or operation, other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used here may be interpreted accordingly.

[0027] Figure 1A This is a top view of a semiconductor device 100 and an electronic device 101 according to an embodiment of the present invention. Figure 1B This is a side view of a semiconductor device 100 according to an embodiment of the present invention. Please also refer to... Figure 1A and Figure 1B .exist Figure 1A and Figure 1B In the embodiments described, the semiconductor device 100 includes a first metal layer 110, a second metal layer 120, a first via element 130, and a first ground via element 140. It should be understood that the semiconductor device 100 may also include other components, such as a silicon substrate, a P-doped layer, and an N-doped layer, although they are not present in the substrate. Figure 1A and Figure 1B It is displayed in the middle.

[0028] The shape and type of the first metal layer 110 and the second metal layer 120 are not limited in this invention. For example, the first metal layer 110 and the second metal layer 120 may be located on two different planes, which may be substantially parallel to each other. In some embodiments, the first metal layer 110 and the second metal layer 120 may be two vertically adjacent metal layers in a multi-metal layer structure, such as a back metallization structure in a semiconductor chip. In other words, there may be an additional metal layer disposed below and coupled to the first metal layer 110. In embodiments where the semiconductor device 100 is a semiconductor chip, the first metal layer 110 and / or the second metal layer 120 may have a minimum metal spacing of less than or equal to 80 nm (e.g., metal layer M1 or M2). In some embodiments, the first metal layer 110 and / or the second metal layer 120 may have a minimum metal spacing of greater than 80 nm, for example, a top metal layer away from the substrate body of the semiconductor device 100.

[0029] A first conductive via element 130 is coupled between a first metal layer 110 and a second metal layer 120. A first ground via element 140 is coupled to ground voltage VSS and is disposed adjacent to the first conductive via element 130. For example, the first ground via element 140 can be grounded through a metal layer and via stacked below, extending to the active region (or OD region) of the underlying substrate body. In some embodiments, the first conductive via element 130 and the first ground via element 140 are located on the same layer. It should be noted that the terms “adjacent” or “close” throughout the disclosure mean that the distance (spacing) between two corresponding elements is less than a predetermined distance (e.g., 10 mm or less), but generally does not mean that the two corresponding elements are in direct contact (i.e., the aforementioned distance / spacing between them is reduced to 0). Figure 1A and Figure 1B In the illustrated embodiment, the first metal layer 110, the second metal layer 120, and the first through-hole element 130 are electrically floating, wherein at the level of the through-hole element 130, the first ground through-hole element 140 is considered as the most recent discharge point associated with the through-hole element 130.

[0030] Electronic device 101 is used to test semiconductor device 100. For example, electronic device 101 can be implemented by hardware circuitry, software programs, or a combination thereof. Specifically, electronic device 101 includes detector 150 and processor 160. Detector 150 can detect a first floating region A1 associated with the first metal layer 110, a first distance R1 between the first via element 130 and the first ground via element 140, and a first contact region C1 between the second metal layer 120 and the first via element 130. In embodiments where the first metal layer 110 is not the bottommost metal layer (i.e., there are additional metal layers stacked below the first metal layer 110), the first floating region A1 can be defined as the cumulative floating region of the first metal layer 110 and any electrically floating metal layers stacked below it (if present). The first distance R1 can be as follows: Figure 1B The center-to-center distance between the first via element 130 and the second via element 140 is shown. In some other embodiments, the first distance R1 may be determined as the edge-to-edge or closest distance between the first via element 130 and the second via element 140. The first contact area C1 may be equivalent to the top area of ​​the first via element 130, rather than the bottom area of ​​the first via element 130. The processor 160 is coupled to the detector 150. The processor 160 may perform a first layout verification process on the second metal layer 120 based on the first floating area A1, the first distance R1, the first contact area C1, and the first layout criteria. For example, the first layout criteria may be a predetermined value stored in the processor 160.

[0031] In some embodiments, the processor 160 may perform a first layout verification process to compare a first antenna integrity parameter with a first layout criterion. For example, the first antenna integrity parameter may be calculated by the processor using formula (1):

[0032] ……………………………………………………………(1)

[0033] Where “T1” represents the integrity parameter of the first antenna, “A1” represents the first floating area, “C1” represents the first contact area, “R1” represents the first distance, and “N” represents a first positive number.

[0034] In some embodiments, if the first antenna integrity parameter is less than or equal to the first layout criterion, the processor 160 determines that the first layout verification process has passed. In an alternative embodiment, if the first antenna integrity parameter is greater than the first layout criterion, the processor 160 determines that the first layout verification process has failed. In this case, the risk of integrated circuit failure due to antenna effects caused by accumulated charge during manufacturing may be high and unacceptable.

[0035] In some embodiments, the first positive number (N) can be a positive integer, such as 1 or 2. For example, if the first positive number is set to 1, the first layout criterion can be selected from 80,000 to 1,200,000; if the first positive number is set to 2, the first layout criterion can be selected from 20,000 to 400,000, but is not limited thereto.

[0036] In some embodiments, the first layout criterion can be adjusted according to Table I, as follows:

[0037] Table I

[0038]

[0039] By incorporating a first distance R1 during the initial layout verification process, this design provides a more comprehensive three-dimensional (3D) inspection method for integrated circuit design. Actual measurements show that the electronic device 101 of this invention can significantly reduce the probability of integrated circuit failure or damage due to non-ideal antenna effects of the semiconductor device 100. Therefore, the performance of the semiconductor device 100 can be effectively improved.

[0040] The following embodiments will describe different configurations and detailed structural features of the semiconductor device 100 and the electronic device 101. It should be understood that these figures and descriptions are merely examples and not intended to limit the invention.

[0041] Figure 2A This is a top view of the semiconductor device 200 and electronic device 201 according to an embodiment of the present invention. Figure 2B This is a side view of a semiconductor device 200 according to an embodiment of the present invention. Please also refer to... Figure 2A and Figure 2B . Figure 2A and Figure 2B They are similar to Figure 1A and Figure 1B .exist Figure 2A and Figure 2B In one embodiment, the electronic device 201 for testing the semiconductor device 200 includes a detector 250 and a processor 260. In addition to the first metal layer 110, second metal layer 120, first via element 130, and first ground via element 140 described above, the semiconductor device 200 also includes a third metal layer 270, a second via element 280, and a second ground via element 290 disposed above the second metal layer 120. For example, the first metal layer 110, second metal layer 120, and third metal layer 270 may be located on three different planes, which may be substantially parallel.

[0042] The second via element 280 is coupled between the second metal layer 120 and the third metal layer 270, such that the first metal layer 110, the first via element 130, the second metal layer 120, the second via element 280, and the third metal layer 270 are electrically floating. The second ground via element 290 is also coupled to the first ground via element 140 and is disposed adjacent to the second via element 280. In some embodiments, the second via element 280 and the second ground via element 290 are located on the same layer, wherein the second ground via element 290 is considered the nearest discharge point associated with the second via element 280. The detector 250 can detect a first floating region A1 associated with the first metal layer 110, a second floating region A2 associated with the second metal layer 120, a second distance R2 between the second via element 280 and the second ground via element 290, and a second contact region C2 between the third metal layer 270 and the second via element 280. For example, the second contact area C2 may be equivalent to the top area of ​​the second via element 280, rather than the bottom area of ​​the second via element 280. The processor 260 may further perform a second layout verification process on the third metal layer 270 based on the first floating area A1, the second floating area A2, the second distance R2, the second contact area C2, and the second layout criterion. For example, the second layout criterion may be another predetermined value stored in the processor 260.

[0043] In some embodiments, processor 260 may perform a second layout verification process to compare the second antenna integrity parameter with a second layout criterion. For example, the second antenna integrity parameter may be calculated by processor 260 using formula (2):

[0044] ……………………………………………………(2)

[0045] Where “T2” represents the second antenna integrity parameter, “A1” represents the first floating region, “A2” represents the second floating region, “C2” represents the second contact region, “R2” represents the second distance, and “M” represents a second positive number. In formula (2), A1+A2 represents the total cumulative floating region associated with the first metal layer 110 and the second metal layer 120. Similar to the previously described embodiment, when the first metal layer 110 is not the bottommost metal layer (i.e., there are additional metal layers stacked below the first metal layer 110), the first floating region A1 can be defined as the cumulative floating region of the first metal layer 110 and the metal layers stacked and coupled below it (if present). In such an embodiment, A1+A2 in formula (2) can be regarded as the total cumulative floating region associated with the first metal layer 110, the second metal layer 120, and the metal layers stacked and coupled below them.

[0046] In some embodiments, if the second antenna integrity parameter is less than or equal to the second layout criterion, the processor 260 will determine that the second layout verification process has passed. In an alternative embodiment, if the second antenna integrity parameter is greater than the second layout criterion, the processor 260 will determine that the second layout verification process has failed.

[0047] In some embodiments, the second positive number (M) can be a positive integer, such as 1 or 2. For example, if the second positive number is set to 1, the second layout criterion can be selected from 80,000 to 1,200,000; if the second positive number is set to 2, the second layout criterion can be selected from 20,000 to 400,000, but is not limited thereto. According to actual measurements, the performance of the semiconductor device 200 can be further improved due to the simultaneous application of the first layout verification process and the second layout verification process. Figure 2A and 2B Other features of the semiconductor device 200 and electronic device 201 in the process are similar to Figure 1A and Figure 1B The semiconductor device 100 and electronic device 101 in the embodiments have similar features. Therefore, the two embodiments can achieve similar performance levels.

[0048] In some embodiments, the second layout criteria may be adjusted according to the following Table II:

[0049] Table II

[0050]

[0051] Figure 3 This is a top view of a semiconductor device 300 according to an embodiment of the present invention. Figure 3 and Figure 2A and Figure 2B Similar. Figure 3 In this embodiment, the semiconductor device 300 includes a first metal layer 110, a second metal layer 120, a first via element 130, a first ground via element 140, a third metal layer 270, a second via element 280, and a second ground via element 290. Their arrangement has been described in the previous embodiments. The first metal layer 110 has a first floating region A1. The second metal layer 120 has a second floating region A2. A first distance R1 is defined between the first via element 130 and the first ground via element 140. A second distance R2 is defined between the second via element 280 and the second ground via element 290. A first contact region C1 is defined between the second metal layer 120 and the first via element 130. A second contact region C2 is defined between the third metal layer 270 and the second via element 280.

[0052] The second metal layer 120 can pass the first layout verification process. The first layout verification process is performed based on the first floating region A1, the first distance R1, the first contact region C1, and the first layout criterion. For example, the first layout verification process can be performed to compare the first antenna integrity parameters with the first layout criterion, and the first antenna integrity parameters can be calculated using the above equation (1).

[0053] The third metal layer 270 can pass the second layout verification process. The second layout verification process is performed based on the first floating region A1, the second floating region A2, the second distance R2, the second contact region C2, and the second layout criterion. For example, the second layout verification process can be performed to compare the second antenna integrity parameter with the second layout criterion, and the second antenna integrity parameter can be calculated using the above equation (2).

[0054] It should be noted that since both the first and second layout verification processes have passed, the probability of IC failure caused by the non-ideal antenna effect of the semiconductor device 300 of the present invention is very low. Figure 3 Other features of the semiconductor device 300 in Figure 2A and Figure 2B The semiconductor device 200 in both embodiments has similar characteristics. Therefore, the two embodiments can achieve similar performance levels. As mentioned earlier, in some other embodiments, the semiconductor device 300 includes more metal layers and more via elements, and they are arranged and verified in a similar manner.

[0055] Figure 4 This is a flowchart of a test method according to an embodiment of the present invention. The test method includes the following steps. First, in step S410, a first metal layer, a second metal layer, a first conductive via element, and a first ground via element are provided. The first conductive via element is coupled between the first metal layer and the second metal layer. The first ground via element is coupled to ground voltage and is disposed next to the first conductive via element. In step S420, a first floating region associated with the first metal layer is detected. In step S430, a first distance between the first conductive via element and the first ground via element is detected. In step S440, a first contact region between the second metal layer and the first conductive via element is detected. Finally, in step S450, a first layout verification process is performed on the second metal layer according to the first floating region, the first distance, the first contact region, and the first layout criteria. It should be noted that the above steps do not need to be performed in sequence, and Figure 1A , Figure 1B , Figure 2A , Figure 2B and Figure 3 Each feature of the embodiments can be applied to Figure 4 The testing method.

[0056] This invention presents a novel electronic device, a novel semiconductor device, and a testing method thereof. Compared with conventional designs, this invention has at least the advantage of effectively suppressing non-ideal antenna effects, and is therefore suitable for application in various devices.

[0057] Note that the above component parameters are not limitations of this invention. Designers can fine-tune these settings or values ​​according to different requirements. It should be understood that the electronic devices, semiconductor devices, and testing methods of this invention are not limited to... Figures 1A to 4 The configuration. This invention may include only... Figures 1A to 4 Any one or more features of any one or more embodiments thereof. In other words, not all features shown in the figures should be implemented in the electronic device, semiconductor device, and test method of the present invention.

[0058] The methods of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e., executable instructions) embodied in a tangible medium, such as a floppy disk, CD-ROM, hard disk, or any other machine-readable storage medium, wherein, when the program code is loaded and executed by a machine such as a computer, the machine thus becomes an apparatus for implementing these methods. The methods may also be embodied in the form of program code and transmitted via some transmission medium, such as wires or cables, via optical fibers, or via any other form of transmission, wherein, when the program code is received and loaded and executed by a machine such as a computer, the machine becomes an apparatus for implementing the disclosed methods. When implemented on a general-purpose processor, the program code is combined with the processor to provide a unique apparatus that resembles the operation of applying specific logic circuitry.

[0059] The use of ordinal numbers such as "first," "second," and "third" to modify claim elements does not indicate the priority, order, or chronological order of one claim element relative to another. Rather, it serves merely as a label to distinguish one claim element with a certain name from another element with the same name (but ordinal numbers are used to distinguish claim elements).

[0060] While the invention has been described by way of examples and preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as would be understood by those skilled in the art). Therefore, the scope of the claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. An electronic device for testing a semiconductor device, the semiconductor device comprising a first metal layer, a second metal layer, a first via element, and a first ground via element, the first via element being coupled between the first metal layer and the second metal layer, the first ground via element being coupled to ground voltage and disposed adjacent to the first via element, the electronic device comprising: A detector is used to detect a first floating region associated with the first metal layer, a first distance between the first conductive via element and the first ground via element, and a first contact area between the second metal layer and the first conductive via element; as well as A processor, coupled to the detector, performs a first layout verification process on the second metal layer based on the first floating region, the first distance, the first contact region, and the first layout criteria.

2. The electronic device of claim 1, wherein the processor performs the first layout verification process to compare the first antenna integrity parameter with the first layout criterion, and the first antenna integrity parameter is calculated by the processor using the following formula: Where "T1" represents the integrity parameter of the first antenna, "A1" represents the first floating area, "C1" represents the first contact area, "R1" represents the first distance, and "N" represents the first positive number.

3. The electronic device of claim 2, wherein if the first antenna integrity parameter is less than or equal to the first layout criterion, the processor determines that the first layout verification process has passed; if the first antenna integrity parameter is greater than the first layout criterion, the processor determines that the first layout verification process has failed.

4. The electronic device of claim 2, wherein the first positive number is equal to 1 or 2.

5. The electronic device of claim 1, wherein the semiconductor device further comprises a third metal layer, a second via element and a second ground via element, the second via element being coupled between the second metal layer and the third metal layer, the second ground via element being coupled to the ground voltage and disposed next to the second via element, the detector further detecting a second floating region associated with the second metal layer, a second distance between the second via element and the second ground via element, and a second contact region between the third metal layer and the second via element, and the processor further performing a second layout verification process on the third metal layer according to the first floating region, the second floating region, the second distance and the second layout criteria.

6. The electronic device of claim 5, wherein the processor performs the second layout verification process to compare the second antenna integrity parameter with the second layout criterion, and the second antenna integrity parameter is calculated by the processor using the following formula: Where "T2" represents the second antenna integrity parameter, "A1" represents the first floating area, "A2" represents the second floating area, "C2" represents the second contact area, "R2" represents the second distance, and "M" represents the second positive number.

7. The electronic device of claim 6, wherein if the second antenna integrity parameter is less than or equal to the second layout criterion, the processor determines that the second layout verification process has passed; if the second antenna integrity parameter is greater than the second layout criterion, the processor determines that the second layout verification process has failed.

8. The electronic device of claim 6, wherein the second positive number is equal to 1 or 2.

9. A testing method, comprising the following steps: A first metal layer, a second metal layer, a first conductive via element, and a first ground via element are provided, wherein the first conductive via element is coupled between the first metal layer and the second metal layer, and wherein the first ground via element is coupled to ground voltage and disposed next to the first conductive via element; Detect the first floating region associated with the first metal layer; Detect the first distance between the first conductive via element and the first grounding via element; Detect the first contact area between the second metal layer and the first through-hole element; as well as A first layout verification process is performed on the second metal layer based on the first floating area, the first distance, the first contact area, and the first layout criteria.

10. The testing method of claim 9, wherein the first layout verification process includes: The first antenna integrity parameter is compared with the first layout standard, wherein the first antenna integrity parameter is calculated using the following equation: Where "T1" represents the integrity parameter of the first antenna, "A1" represents the first floating area, "C1" represents the first contact area, "R1" represents the first distance, and "N" represents a first positive number.

11. The test method as described in claim 10, further comprising: If the first antenna integrity parameter is less than or equal to the first layout standard, the first layout verification process is deemed to have passed; if the first antenna integrity parameter is greater than the first layout standard, the first layout verification process is deemed to have failed.

12. The test method of claim 10, wherein the first positive number is equal to 1 or 2.

13. The test method as described in claim 9, further comprising: A third metal layer, a second conductive via element, and a second ground via element are provided, wherein the second conductive via element is coupled between the second metal layer and the third metal layer, and wherein the second ground via element is coupled to the ground voltage and is disposed near the second conductive via element; Detect the second floating region associated with the second metal layer; Detect the second distance between the second conductive via element and the second grounding via element; Detect the second contact area between the third metal layer and the second conductive via element; A second layout verification process is performed on the third metal layer based on the first floating area, the second floating area, the second distance, the second contact area, and the second layout standard.

14. The test method of claim 13, wherein the second layout verification process includes: The second antenna integrity parameter is compared with the second layout standard, which is calculated using the following equation: Where "T2" represents the second antenna integrity parameter, "A1" represents the first floating area, "A2" represents the second floating area, "C2" represents the second contact area, "R2" represents the second distance, and "M" represents a second positive number.

15. The test method as described in claim 14, further comprising: If the second antenna integrity parameter is less than or equal to the second layout standard, the second layout verification process is considered successful; if the second antenna integrity parameter is greater than the second layout standard, the second layout verification process is considered unsuccessful.

16. The test method of claim 14, wherein the second positive number is equal to 1 or 2.

Images