A voltage pre-modulation circuit for high voltage LDO

Abstract

This invention discloses a voltage pre-modulation circuit for a high-voltage LDO, relating to the field of integrated circuit design technology. It includes a voltage pre-regulation module, a current self-biasing circuit, and an output voltage detection module. The voltage pre-regulation module provides a low-voltage operating power supply; the current self-biasing circuit provides a bias current source; and the output voltage detection module provides a feedback control signal. The output voltage detection module also detects an external input voltage H_VDD. If H_VDD is less than a preset voltage, the output voltage detection module outputs a high-level control signal to control the high-voltage branch of the voltage pre-regulation module to turn off, making the LDO's output voltage equal to H_VDD. If H_VDD is greater than the preset voltage, the output voltage detection module outputs a low-level control signal to control the voltage pre-regulation module to generate an internal low-voltage power supply L_VDD. This invention separates the high and low voltage output branches, allowing for flexible adjustment of the low-voltage power supply output range. Furthermore, by utilizing the threshold hysteresis function of the control signal, it ensures that the output voltage does not repeatedly flip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a voltage pre-modulation circuit for a high-voltage LDO. Background Technology

[0002] A low-dropout linear regulator (LDO) consists of a bandgap reference circuit, an error amplifier, a power transistor, and a feedback resistor. With the rapid development of the integrated circuit industry, the complex electronic environment places higher demands on the operating voltage of LDOs. Due to the wider input voltage range, transient high voltages generated externally pose challenges to the reliability of the power supply system. At the same time, power consumption under high voltage conditions becomes increasingly important, and the large size of the LDMOS high-voltage transistor in CMOS technology also presents a significant challenge to chip area.

[0003] There are two traditional methods for generating voltage pre-modulation for high-voltage LDOs: one uses a voltage regulator circuit to stabilize the external input voltage and the control terminal voltage of the adjustment circuit within a preset voltage range; the other uses a common-source, common-gate transistor with cross-coupling to generate a low-voltage internal voltage.

[0004] The paper with DOI number 10.19304 / J.ISSN1000-7180.2023.0938 discloses an LDO design with a wide power supply range and high power supply rejection ratio. Its Zener diode pre-regulation control voltage range structure is as follows: Figure 1 As shown, this structure uses a Zener diode connected in series with the current bias to control the gate voltage of the NMOS and the source follower connection to generate a low-voltage power supply. Although it can ensure that the circuit can stabilize the high external input voltage within the preset voltage range, the voltage range is limited and cannot adapt to the pre-modulation of various complex input voltages. Furthermore, due to process deviations, working environment, and working voltage, the generated low-voltage power supply may have significant deviations.

[0005] Existing technologies also employ a voltage pre-modulation structure that uses multiple diodes connected in series to a MOSFET to generate a bias voltage, such as... Figure 2 As shown, it uses multiple diodes connected in series with the current bias to control the gate voltage of the NMOS transistor and the source follower connection to generate a low-voltage power supply. However, the circuit structure that uses MOS transistors to generate the bias voltage is greatly affected by the actual manufacturing process, resulting in significant variations in the final low-voltage power supply.

[0006] Figure 1Although the circuit shown can ensure that the circuit stabilizes the high external input voltage within the preset voltage range, the limited voltage range cannot adapt to the pre-modulation of various complex input voltages, thus limiting the adjustment method. Based on the problems of existing voltage pre-modulation technology not being able to flexibly adjust the low-voltage output power supply and being greatly affected by process deviations, it is necessary to design a voltage pre-modulation circuit that can flexibly adjust the low-voltage power supply output range, and to output a stable low-voltage power supply by designing a voltage threshold feedback circuit. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a voltage pre-modulation circuit for high-voltage LDOs.

[0008] The objective of this invention is achieved through the following technical solution: This application discloses a voltage pre-modulation circuit for a high-voltage LDO, comprising: a voltage pre-regulation module, a current self-biasing circuit, and an output voltage detection module; The voltage pre-regulation module includes a high-voltage branch and a low-voltage branch, and its output terminals are respectively connected to the output voltage detection module and the current self-biasing circuit to provide low-voltage operating power for both. The output terminal of the current self-biasing circuit is connected to the input terminal of the high-voltage branch to provide it with a bias current source. The output terminal of the output voltage detection module is connected to the input terminal of the voltage pre-regulation module to provide it with a feedback control signal; The output voltage detection module is also used to detect the external input voltage H_VDD. If H_VDD is less than the preset voltage, the output voltage detection module outputs a high-potential control signal to control the high-voltage branch of the voltage pre-regulation module to turn off, so that the output voltage of the LDO is equal to H_VDD. If H_VDD is greater than the preset voltage, the output voltage detection module outputs a low-potential control signal to control the voltage pre-regulation module to generate an internal low-voltage power supply L_VDD.

[0009] Furthermore, the current self-biasing circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM0, a second NMOS transistor NM1, a first transistor Q0, a second transistor Q1, a first resistor R0, and a second resistor R1; A first resistor R0 is connected between the collector of the first transistor Q0 and the output terminal of the voltage pre-regulation module; the emitter of the first transistor Q0 is grounded, and the collector of the first transistor Q0 is connected to its base and then connected to the base of the second transistor Q1. The emitter of the second transistor Q1 is connected to the second resistor R1 and then to the ground terminal; the gate of the first NMOS transistor NM0 is connected to its drain and then to the collector of the second transistor Q1; the source of the first NMOS transistor NM0 is connected to the output terminal of the voltage pre-regulation module. The source of the second PMOS transistor PM2 is connected to the output terminal of the voltage pre-regulation module, the gate of the second PMOS transistor PM2 is connected to the gate of the first NMOS transistor NM0, and the drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM0, the gate of the first NMOS transistor NM0, and the gate of the second NMOS transistor NM1. The source of the first NMOS transistor NM0 and the source of the second NMOS transistor NM1 are both connected to the ground terminal, and the drain of the second NMOS transistor NM1 is connected to the output terminal of the voltage pre-regulation module.

[0010] Preferably, the emitter area ratio of the first transistor Q0 to the second transistor Q1 is 1:8, the width-to-length ratio of the current mirror formed by the first PMOS transistor PM1 and the second PMOS transistor PM2 is 1:1, and the width-to-length ratio of the current mirror formed by the first NMOS transistor NM0 and the second NMOS transistor NM1 is 1:1; the current self-biasing circuit adopts a bipolar Willard micro-current source structure, and the bias current generated is I=(V be2 -V be1 ) / R1, where R1 represents the resistance value of the second resistor R1, V be2 V represents the base-emitter voltage of the first transistor Q0. be1 This represents the base-emitter voltage of the second transistor Q1, which provides bias current for the voltage pre-regulation module and the output voltage detection module.

[0011] Preferably, the output voltage detection module includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM2, a fourth NMOS transistor NM3, a third resistor R2, a fourth resistor R3, a fifth resistor R4, a sixth resistor R5, and a digital logic gate circuit; the digital logic gate circuit includes a first Schmitt trigger ST1, a second Schmitt trigger ST2, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4; The output terminal of the voltage pre-regulation module is connected to the third resistor R2, the source of the third PMOS transistor PM3, the source of the fourth PMOS transistor PM4, and the power supply terminal of the digital logic gate circuit; the third resistor R2 is also connected to the fourth resistor R3 and the drain of the third PMOS transistor PM3; the fourth resistor R3 is also connected to the fifth resistor R4 and the gate of the fourth PMOS transistor PM4; the fifth resistor R4 is also connected to the sixth resistor R5; the sixth resistor R5 is also connected to the drain of the third NMOS transistor NM2, the gate of the third NMOS transistor NM2, and the gate of the fourth NMOS transistor NM3. The source of the third NMOS transistor NM2, the source of the fourth NMOS transistor NM3, and the ground terminal of the digital logic gate circuit are all connected to the ground terminal; the gate of the third PMOS transistor PM3 is connected to the output terminal of the output voltage detection module. The drain of the fourth NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4 and the input of the first Schmitt trigger ST1, respectively. The output of the first Schmitt trigger ST1 is connected to the input of the first inverter INV1; the output of the first inverter INV1 is connected to the input of the second inverter INV2; the output of the second inverter INV2 is connected to the input of the second Schmitt trigger ST2; the output of the second Schmitt trigger ST2 is connected to the input of the third inverter INV3; the output of the third inverter INV3 is connected to the input of the fourth inverter INV4; and the output of the fourth inverter INV4 is connected to the VDC-CHANGE terminal.

[0012] Preferably, the high-voltage branch of the voltage pre-regulation module includes a first PLDMOS transistor PLD1, a second PLDMOS transistor PLD2, a first NLDMOS transistor NLD1, a second NLDMOS transistor NLD2, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3, a seventh resistor R6, an eighth resistor R7, a ninth resistor R8, and a tenth resistor R9. The source of the first PLDMOS transistor PLD1 is connected to the external input voltage H_VDD. The drain of the first PLDMOS transistor PLD1 is connected to its own gate, and then connected to the gate of the second PLDMOS transistor PLD2 and the seventh resistor R6. The seventh resistor R6 is also connected to the drain of the first NLDMOS transistor NLD1. The source of the first NLDMOS transistor NLD1 is connected to the output of the current self-biasing circuit, and the gate of the first NLDMOS transistor NLD1 is connected to the eighth resistor R7 and the cathode of the first Zener diode Z1 respectively; the eighth resistor R7 is also connected to the external input voltage H_VDD, and the anode of the first Zener diode Z1 is connected to the ground terminal. The source of the second PLDMOS transistor PLD2 is connected to the external input voltage H_VDD, and the drain of the second PLDMOS transistor PLD2 is connected to the ninth resistor R8. The ninth resistor R8 is also connected to the cathode of the second Zener diode Z2 and the gate of the second NLDMOS transistor NLD2. The anode of the second Zener diode Z2 is connected to the ground terminal. The drain of the second NLDMOS transistor NLD2 is connected to the external input voltage H_VDD, and the source of the second NLDMOS transistor NLD2 is connected to the cathode of the third Zener diode Z3; the anode of the third Zener diode Z3 is connected to the tenth resistor R9, and the tenth resistor R9 is also connected to the ground terminal.

[0013] Preferably, the width-to-length ratio of the current mirror formed by the first PLDMOS transistor PLD1 and the second PLDMOS transistor PLD2 is 1:N, where N is a positive integer; the high-voltage branch adopts a source follower connection, utilizing the clamping effect of the Zener diode to generate L_VDD=V zener -V GS V zener This represents the Zener diode voltage, V. GS This represents the gate-source voltage of the transistor.

[0014] Preferably, the low-voltage branch of the voltage pre-regulation module includes a third PLDMOS transistor PLD3, a fourth PLDMOS transistor PLD4, a fifth PLDMOS transistor PLD5, a third NLDMOS transistor NLD3, a fourth NLDMOS transistor NLD4, a fifth NMOS transistor NM4, a sixth NMOS transistor NM5, a fourth Zener diode Z4, an eleventh resistor R10, a twelfth resistor R11, a thirteenth resistor R12, a fourteenth resistor R13, and a fifteenth resistor R14; The eleventh resistor R10 is connected to the external input voltage H_VDD. The eleventh resistor R10 is also connected to the cathode of the fourth Zener diode Z4, the gate of the fourth NLDMOS transistor NLD4, the gate of the sixth NMOS transistor NM5, and the fifteenth resistor R14. The anode of the fourth Zener diode Z4 is connected to the ground terminal. The drain of the fifth NMOS transistor NM4 is connected to the source of the third NLDMOS transistor NLD3. The gate of the fifth NMOS transistor NM4 is connected to the tenth resistor R9, and the source of the fifth NMOS transistor NM4 is grounded. The drain of the third NLDMOS transistor NLD3 is connected to the twelfth resistor R11. The gate of the third NLDMOS transistor NLD3 is also connected to the anode of the third Zener diode Z3. The twelfth resistor R11 is connected to the drain of the third PLDMOS transistor PLD3, the gate of the third PLDMOS transistor PLD3, and the gate of the fourth PLDMOS transistor PLD4. The source of the third PLDMOS transistor PLD3 and the source of the fourth PLDMOS transistor PLD4 are both connected to the external input voltage H_VDD; the drain of the fourth PLDMOS transistor PLD4 is connected to the drain of the fourth NLDMOS transistor NLD4 and the gate of the fifth PLDMOS transistor PLD5; the source of the fourth NLDMOS transistor NLD4 is connected to the fourteenth resistor R12, which is also connected to the ground terminal. The fourteenth resistor R13 is connected between the drain of the fifth PLDMOS transistor PLD5 and the drain of the sixth NMOS transistor NM5. The fourteenth resistor R13 is also connected to the source of the second NLDMOS transistor NLD2, and the source of the sixth NMOS transistor NM5 is grounded. The drain of the fifth PLDMOS transistor PLD5 is also connected to the source of the second NLDMOS transistor NLD2.

[0015] Preferably, the width-to-length ratio of the current mirror formed by the third PLDMOS transistor PLD3 and the fourth PLDMOS transistor PLD4 is 1:M, where M is a positive integer; the low-voltage branch turns off the sixth NMOS transistor NM5 through the feedback control signal VDC-CHANGE output by the output voltage detection module, generating L_VDD=H_VDD.

[0016] The beneficial effects of this invention are: 1) This invention provides a voltage pre-modulation technology suitable for high-voltage LDOs. Utilizing a series resistor voltage divider and the different carrier migration capabilities of NMOS and PMOS transistors, it generates an internal low-voltage power supply to control the output thresholds of the internal high and low voltage power supplies. A feedback loop of the internal control signal forms a hysteresis function to prevent repeated switching of the output low-voltage power supply due to differences in carrier migration capabilities between different PMOS and NMOS chips caused by process variations. The reverse breakdown characteristic of a Zener diode stabilizes the control signal at high voltage to prevent excessive control gate voltage from causing MOS transistor breakdown when the external input voltage is too high. This structure also employs a source follower structure with separate high and low voltage output control and a Zener diode series resistor bias gate voltage, allowing for flexible adjustment of the output low-voltage power supply. This invention separates the high and low voltage output branches, enabling flexible adjustment of the low-voltage power supply output range, and utilizes the threshold hysteresis function of the control signal to ensure that the output voltage does not repeatedly switch. Attached Figure Description

[0017] Figure 1 A schematic diagram of the pre-regulator structure of a series reverse breakdown Zener diode in the prior art; Figure 2 This is a schematic diagram of a pre-regulatory structure with diodes connected in series, which is a prior art technique. Figure 3This is a schematic diagram of a voltage pre-modulation circuit for a high-voltage LDO according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the high-voltage LDO pre-stabilized structure according to an embodiment of the present invention; Figure 5 This is a circuit diagram of a self-biased current source module according to an embodiment of the present invention; Figure 6 This is a circuit diagram of the output voltage detection module according to an embodiment of the present invention; Figure 7 This is a circuit diagram of the voltage pre-regulation module according to an embodiment of the present invention. Detailed Implementation

[0018] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] See Figures 3-7 This application discloses a voltage pre-modulation circuit for a high-voltage LDO, comprising: a voltage pre-regulation module, a current self-biasing circuit, and an output voltage detection module; The voltage pre-regulation module includes a high-voltage branch and a low-voltage branch, and its output terminals are respectively connected to the output voltage detection module and the current self-biasing circuit to provide low-voltage operating power for both. The output terminal of the current self-biasing circuit is connected to the input terminal of the high-voltage branch to provide it with a bias current source. The output terminal of the output voltage detection module is connected to the input terminal of the voltage pre-regulation module to provide it with a feedback control signal; The output voltage detection module is also used to detect the external input voltage H_VDD. If H_VDD is less than the preset voltage, the output voltage detection module outputs a high-potential control signal to control the high-voltage branch of the voltage pre-regulation module to turn off, so that the output voltage of the LDO is equal to H_VDD. If H_VDD is greater than the preset voltage, the output voltage detection module outputs a low-potential control signal to control the voltage pre-regulation module to generate an internal low-voltage power supply L_VDD.

[0020] For example, the current self-biasing circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM0, a second NMOS transistor NM1, a first transistor Q0, a second transistor Q1, a first resistor R0, and a second resistor R1; A first resistor R0 is connected between the collector of the first transistor Q0 and the output terminal of the voltage pre-regulation module; the emitter of the first transistor Q0 is grounded, and the collector of the first transistor Q0 is connected to its base and then connected to the base of the second transistor Q1. The emitter of the second transistor Q1 is connected to the second resistor R1 and then to the ground terminal; the gate of the first NMOS transistor NM0 is connected to its drain and then to the collector of the second transistor Q1; the source of the first NMOS transistor NM0 is connected to the output terminal of the voltage pre-regulation module. The source of the second PMOS transistor PM2 is connected to the output terminal of the voltage pre-regulation module, the gate of the second PMOS transistor PM2 is connected to the gate of the first NMOS transistor NM0, and the drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM0, the gate of the first NMOS transistor NM0, and the gate of the second NMOS transistor NM1. The source of the first NMOS transistor NM0 and the source of the second NMOS transistor NM1 are both connected to the ground terminal, and the drain of the second NMOS transistor NM1 is connected to the output terminal of the voltage pre-regulation module.

[0021] For example, the emitter area ratio of the first transistor Q0 to the second transistor Q1 is 1:8, the width-to-length ratio of the current mirror formed by the first PMOS transistor PM1 and the second PMOS transistor PM2 is 1:1, and the width-to-length ratio of the current mirror formed by the first NMOS transistor NM0 and the second NMOS transistor NM1 is 1:1; the current self-biasing circuit adopts a bipolar Willard micro-current source structure, and the bias current generated is I=(V be2 -V be1 ) / R1, where R1 represents the resistance value of the second resistor R1, V be2 V represents the base-emitter voltage of the first transistor Q0. be1 This represents the base-emitter voltage of the second transistor Q1, which provides bias current for the voltage pre-regulation module and the output voltage detection module.

[0022] For example, the output voltage detection module includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM2, a fourth NMOS transistor NM3, a third resistor R2, a fourth resistor R3, a fifth resistor R4, a sixth resistor R5, and a digital logic gate circuit; the digital logic gate circuit includes a first Schmitt trigger ST1, a second Schmitt trigger ST2, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4; by using a series resistor voltage divider, and by utilizing the weaker pull-up capability of the PMOS transistor MP compared to the NMOS transistor MN of the same size, the shaping of the Schmitt triggers (ST1, ST2), and the drive delay of the multi-stage inverters, the output stability of the low-voltage output branch is controlled; The output terminal of the voltage pre-regulation module is connected to the third resistor R2, the source of the third PMOS transistor PM3, the source of the fourth PMOS transistor PM4, and the power supply terminal of the digital logic gate circuit; the third resistor R2 is also connected to the fourth resistor R3 and the drain of the third PMOS transistor PM3; the fourth resistor R3 is also connected to the fifth resistor R4 and the gate of the fourth PMOS transistor PM4; the fifth resistor R4 is also connected to the sixth resistor R5; the sixth resistor R5 is also connected to the drain of the third NMOS transistor NM2, the gate of the third NMOS transistor NM2, and the gate of the fourth NMOS transistor NM3. The source of the third NMOS transistor NM2, the source of the fourth NMOS transistor NM3, and the ground terminal of the digital logic gate circuit are all connected to the ground terminal; the gate of the third PMOS transistor PM3 is connected to the output terminal of the output voltage detection module. The drain of the fourth NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4 and the input of the first Schmitt trigger ST1, respectively. The output of the first Schmitt trigger ST1 is connected to the input of the first inverter INV1; the output of the first inverter INV1 is connected to the input of the second inverter INV2; the output of the second inverter INV2 is connected to the input of the second Schmitt trigger ST2; the output of the second Schmitt trigger ST2 is connected to the input of the third inverter INV3; the output of the third inverter INV3 is connected to the input of the fourth inverter INV4; and the output of the fourth inverter INV4 is connected to the VDC-CHANGE terminal.

[0023] For example, the high-voltage branch of the voltage pre-regulation module includes a first PLDMOS transistor PLD1, a second PLDMOS transistor PLD2, a first NLDMOS transistor NLD1, a second NLDMOS transistor NLD2, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3, a seventh resistor R6, an eighth resistor R7, a ninth resistor R8, and a tenth resistor R9. The source of the first PLDMOS transistor PLD1 is connected to the external input voltage H_VDD. The drain of the first PLDMOS transistor PLD1 is connected to its own gate, and then connected to the gate of the second PLDMOS transistor PLD2 and the seventh resistor R6. The seventh resistor R6 is also connected to the drain of the first NLDMOS transistor NLD1. The source of the first NLDMOS transistor NLD1 is connected to the output of the current self-biasing circuit, and the gate of the first NLDMOS transistor NLD1 is connected to the eighth resistor R7 and the cathode of the first Zener diode Z1 respectively; the eighth resistor R7 is also connected to the external input voltage H_VDD, and the anode of the first Zener diode Z1 is connected to the ground terminal. The source of the second PLDMOS transistor PLD2 is connected to the external input voltage H_VDD, and the drain of the second PLDMOS transistor PLD2 is connected to the ninth resistor R8. The ninth resistor R8 is also connected to the cathode of the second Zener diode Z2 and the gate of the second NLDMOS transistor NLD2. The anode of the second Zener diode Z2 is connected to the ground terminal. The drain of the second NLDMOS transistor NLD2 is connected to the external input voltage H_VDD, and the source of the second NLDMOS transistor NLD2 is connected to the cathode of the third Zener diode Z3; the anode of the third Zener diode Z3 is connected to the tenth resistor R9, and the tenth resistor R9 is also connected to the ground terminal.

[0024] For example, the width-to-length ratio of the current mirror formed by the first PLDMOS transistor PLD1 and the second PLDMOS transistor PLD2 is 1:N, where N is a positive integer; the high-voltage branch adopts a source follower connection, utilizing the clamping effect of the Zener diode to generate L_VDD=V zener -V GS V zener This represents the Zener diode voltage, V. GS This represents the gate-source voltage of the transistor.

[0025] For example, by separating the high and low voltage output branches, the module can clamp the gate voltage of the NLD2 transistor to a certain set voltage value by changing the bias current value of the current mirror, thus ensuring that it can flexibly adjust the low voltage power supply output range. The low voltage branch of the voltage pre-regulation module includes the third PLDMOS transistor PLD3, the fourth PLDMOS transistor PLD4, the fifth PLDMOS transistor PLD5, the third NLDMOS transistor NLD3, the fourth NLDMOS transistor NLD4, the fifth NMOS transistor NM4, the sixth NMOS transistor NM5, the fourth Zener diode Z4, the eleventh resistor R10, the twelfth resistor R11, the thirteenth resistor R12, the fourteenth resistor R13, and the fifteenth resistor R14. The eleventh resistor R10 is connected to the external input voltage H_VDD. The eleventh resistor R10 is also connected to the cathode of the fourth Zener diode Z4, the gate of the fourth NLDMOS transistor NLD4, the gate of the sixth NMOS transistor NM5, and the fifteenth resistor R14. The anode of the fourth Zener diode Z4 is connected to the ground terminal. The drain of the fifth NMOS transistor NM4 is connected to the source of the third NLDMOS transistor NLD3. The gate of the fifth NMOS transistor NM4 is connected to the tenth resistor R9, and the source of the fifth NMOS transistor NM4 is grounded. The drain of the third NLDMOS transistor NLD3 is connected to the twelfth resistor R11. The gate of the third NLDMOS transistor NLD3 is also connected to the anode of the third Zener diode Z3. The twelfth resistor R11 is connected to the drain of the third PLDMOS transistor PLD3, the gate of the third PLDMOS transistor PLD3, and the gate of the fourth PLDMOS transistor PLD4. The source of the third PLDMOS transistor PLD3 and the source of the fourth PLDMOS transistor PLD4 are both connected to the external input voltage H_VDD; the drain of the fourth PLDMOS transistor PLD4 is connected to the drain of the fourth NLDMOS transistor NLD4 and the gate of the fifth PLDMOS transistor PLD5; the source of the fourth NLDMOS transistor NLD4 is connected to the fourteenth resistor R12, which is also connected to the ground terminal. The fourteenth resistor R13 is connected between the drain of the fifth PLDMOS transistor PLD5 and the drain of the sixth NMOS transistor NM5. The fourteenth resistor R13 is also connected to the source of the second NLDMOS transistor NLD2, and the source of the sixth NMOS transistor NM5 is grounded. The drain of the fifth PLDMOS transistor PLD5 is also connected to the source of the second NLDMOS transistor NLD2.

[0026] For example, the current mirror formed by the third PLDMOS transistor PLD3 and the fourth PLDMOS transistor PLD4 has a width-to-length ratio of 1:M, where M is a positive integer; the low-voltage branch turns off the sixth NMOS transistor NM5 through the feedback control signal VDC-CHANGE output by the output voltage detection module, generating L_VDD=H_VDD.

[0027] For example, when the external voltage is lower than the reverse breakdown voltage of the Zener diode, the Zener diode turns off. At this time, the bias voltage V generated by the eleventh resistor R10 and the fourth Zener diode Z4 in series in the voltage pre-regulation module is... O2 It will be pulled to the power supply voltage, and the resulting bias voltage V O2 This will cause the fourth NLDMOS transistor NLD4 and the fifth NMOS transistor NM4 in the low-voltage power supply branch to conduct. At this time, in the high-voltage branch of the voltage pre-regulation module, because the input voltage is too low, the second Zener diode Z2 connected in series with the second PLDMOS transistor PLD2 cannot conduct. The second PLDMOS transistor PLD2 is cut off, and its drain voltage is pulled to the input voltage, thus turning off the high-voltage branch. At this time, in the low-voltage branch of the pre-regulation module, the fourth PLDMOS transistor PLD4, which controls the gate voltage of the low-voltage branch power transistor, is turned on because the fourth NLDMOS transistor NLD4 connected in series with it is conducting. The drain voltage of the fourth PLDMOS transistor PLD4 is pulled to the power supply ground, thus turning on the low-voltage branch power transistor PLD5. Since the size of the fourth PLDMOS transistor PLD4 in the low-voltage branch is larger than that of the sixth NMOS transistor NM5, the pull-up current capability of the PMOS is greater than that of the NMOS transistor pull-down current capability. At this time, the output voltage VDD of the voltage pre-regulation module is the external power supply voltage H_VDD of the LDO. To ensure the bias voltage V generated by the eleventh resistor R10 and the fourth Zener diode Z4 O2 There will be no intermediate state that would cause instability in the circuit's pre-modulation voltage. A control signal VDC-CHANGE needs to be generated through the circuit feedback loop to maintain the bias voltage V. O2 Escape from the intermediate state. For example... Figure 6 As shown, the resistor string consisting of the third resistor R2, the fourth resistor R3, the fifth resistor R4, and the sixth resistor R5 in the output voltage detection module generates a bias voltage V through a resistor divider. O1 Since the pull-up capability of PMOS transistor MP is weaker than that of NMOS transistor MN under the same size, the control signal VO3 is pulled to the low level "0" of the power supply ground. At this time, the control signal VO1 is then shaped by Schmitt triggers (ST1, ST2) and driven by multi-stage inverters to stabilize the output of the low-voltage output branch.

[0028] For example, when the external voltage is higher than the directional breakdown voltage of the Zener diode, due to the reverse breakdown characteristics of the Zener diode and the high-resistance resistor in series, the bias voltage V generated by the eleventh resistor R10 and the bias of the fourth Zener diode Z4 in the voltage pre-regulation module is... O2 It will be pulled to a low potential, thus generating a bias voltage V. O2 This will turn off the fourth NLDMOS transistor NLD4 and the fifth NMOS transistor NM4 in the low-voltage power supply branch. At this time, in the low-voltage branch, the fourth NLDMOS transistor NLD4, which is connected in series with the fourth PLDMOS transistor PLD4 that controls the gate voltage of the low-voltage branch power transistor, is turned off. Therefore, the drain voltage of the fourth PLDMOS transistor PLD4 will be pulled up to the power supply voltage, thereby turning off the high-voltage branch power transistor NLD2. At this time, in the high-voltage branch of the voltage pre-regulation module, since the input voltage is greater than the reverse breakdown voltage of the second Zener diode Z2, the voltage of the second Zener diode Z2, which is connected in series with the second PLDMOS transistor PLD2, is clamped to a value lower than the input power supply voltage. The drain voltage of the second PLDMOS transistor PLD2 will be pulled down to a low voltage. At this time, the high-voltage branch starts to work normally, and the self-bias current source provides bias current to the high-voltage branch current mirror. Then, the internal low-voltage power supply is output through the source follower. At this time, the output voltage VDD of the voltage pre-regulation module is the internal low-voltage power supply L_VDD of the LDO. The clamping voltage V generated by the bias of the seventh resistor R6 and the first Zener diode Z1 O1 Ensure that the gate voltage of the second NLDMOS transistor NLD2 does not exceed the maximum breakdown voltage. Additionally, when the LDO operates in high-voltage mode, excessive transient voltage may occur. Therefore, a Zener diode must be connected in series in the power transistor PM branch to clamp the voltage to below 5V to prevent excessive transient operating voltage from causing breakdown of internal low-voltage components.

[0029] For example, such as Figure 6 As shown, in order to ensure the bias voltage V generated by the eleventh resistor R10 and the fourth Zener diode Z4, O2 There should be no intermediate state causing instability in the circuit's pre-modulated voltage. A control signal VDC-CHANGE needs to be generated through the circuit feedback loop to remove the bias voltage VO2 from the intermediate state. The resistor string consisting of the third resistor R2, fourth resistor R3, fifth resistor R4, and sixth resistor R5 in the output voltage detection module generates the bias voltage V through a resistor divider. O1 At this time, since the operating voltage of the control signal module is L_VDD, although the pull-up capability of the PMOS transistor MP is weaker than that of the NMOS transistor MN of the same size, the gate-source voltage of the PMOS transistor MP is greater than that of the NMOS transistor MN. Therefore, the control signal VO1 is pulled to the L_VDD high level "1" by MP, and the control bias voltage V O1The low-voltage output branch is stabilized by shaping the output through the first Schmitt trigger ST1 and the drive delay of the multi-stage inverter. In the output voltage detection module, to prevent the carrier migration capability of the PMOS and NMOS transistors from repeatedly flipping due to process variations, operating voltage fluctuations, and ambient temperature, a third PMOS transistor PM3 is connected in parallel with the second resistor R2. Its gate is connected to the output of the voltage detection module. PM3 detects the flipping of the control signal and changes the gate voltages of the fourth PMOS transistor PM4 and the fourth NMOS transistor NM3. When the output voltage of the voltage pre-regulation module fluctuates, the control signal of the output voltage detection module may repeatedly flip. PM3 changes its on or off state to ensure that the operating states of PM4 and NM3 remain unchanged.

[0030] In summary, when an LDO circuit typically operates at 5V, such as Figure 7 As shown, in the voltage pre-modulation module, the high-voltage module experiences a low input voltage, causing the Zener diode Z2 connected in series in the PLD2 circuit to fail to reach its breakdown voltage and remain in the off state, resulting in PLD2 being turned off. At this time, the drain potential of PLD2 is pulled up to the power supply voltage, thus cutting off the working circuit of the high-voltage branch and achieving the high-voltage circuit's shutdown protection function. In the low-voltage module of the voltage pre-modulation module, when the external input voltage is lower than the reverse breakdown voltage of Zener diode Z4, Z4 is in the off state. At this time, the VO1 potential output by the bias circuit formed by resistor R10 and Zener diode Z4 connected in series in the voltage pre-regulation module will be pulled up to the power supply voltage. In the low-voltage branch of the pre-regulation module, the PLD4 power transistor biased by the low-voltage branch is turned on because its connected NLD4 transistor is conducting, causing the drain voltage of PLD4 to be pulled to ground, thereby turning on the low-voltage branch power transistor PLD5. In the low-voltage branch design, because the aspect ratio of the power PMOS transistor PLD5 is significantly larger than that of the NM4 transistor, the pull-up current capability provided by the PMOS transistor far exceeds that of the NMOS transistor. This asymmetrical drive capability design ensures that when both transistors are conducting simultaneously, the output node VDD of the voltage pre-modulation module will be forcibly pulled up to the LDO's power supply voltage H_VDD. To ensure that the V_VDD output of the bias circuit formed by resistor R10 and Zener diode Z4 in the voltage pre-modulation module is within acceptable limits... O1 To ensure stable and reliable voltage and prevent malfunctions of the pre-regulator module due to being in an intermediate state, a dedicated feedback control loop is required to generate an adjustment signal VDC-CHANGE, forcibly adjusting VDC-CHANGE. O1The bias voltage is locked at a defined level. The series resistors R2, R3, R4, and R5 in the output voltage detection module generate the bias voltage VO1 through a resistor divider. Due to the difference in driving capability between the PMOS transistor MP and the NMOS transistor MN of the same size (MP's pull-up capability < MN's pull-down capability), the control node VO1 is actively pulled down to a low level "0". This low-level signal is noise-shaped by the Schmitt trigger ST1, and then timing-adjusted through a multi-stage inverter chain, ultimately achieving closed-loop voltage regulation control of the low-voltage output branch.

[0031] When the LDO circuit operates at a high voltage of 5V, in the voltage premodulation module, when the input voltage exceeds the breakdown threshold of Zener diode Z4, Z4 undergoes reverse breakdown. At this time, the series high-resistance resistor R limits the current and biases the node V. O2 Forced pull-down to low level, the V of this low level O2 The signal cuts off the gate drive of the NMOS transistor MN in the low-voltage branch, putting it into the off state. In the high-voltage branch of the voltage pre-regulation module, when the input voltage exceeds the reverse breakdown threshold of the Zener diode Z1, the bias voltage generated by the resistor R7 and the bias of the Zener diode Z1 controls NLD1 to conduct. At the same time, the Zener diode Z2 undergoes reverse breakdown and enters the regulated conduction state. At this time, PLD2 conducts. By changing the width-to-length ratio of the current mirror biasing PLD1 and PLD2, the gate voltage of NLD2 is clamped at a certain set voltage value. Then, the internal low-voltage power supply is output through the source follower. At this time, the output voltage VDD of the voltage pre-regulation module is the internal low-voltage power supply L_VDD of the LDO. The clamping voltage generated by the resistor R6 and the bias of the Zener diode Z1 ensures that the gate voltage of the controlled NLD2 transistor will not exceed the maximum breakdown voltage. Meanwhile, when the LDO operates in high-voltage mode, the transient voltage can be excessive. Therefore, a Zener diode needs to be connected in series in the power transistor PM branch to clamp the voltage to below 5V to prevent excessive transient operating voltage from causing breakdown of internal low-voltage components. Furthermore, this application allows adjustment of the width-to-length ratio of the output detection module PM4 and NM3 according to specific needs. Utilizing symmetrical drive capability, it sets and changes the threshold voltage for high and low voltages, ultimately achieving a pre-stabilized voltage value.

[0032] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A voltage pre-modulation circuit for a high-voltage LDO, characterized in that, include: It includes a voltage pre-regulation module, a current self-biasing circuit, and an output voltage detection module; The voltage pre-regulation module includes a high-voltage branch and a low-voltage branch, and its output terminals are respectively connected to the output voltage detection module and the current self-biasing circuit to provide low-voltage operating power for both. The output terminal of the current self-biasing circuit is connected to the input terminal of the high-voltage branch to provide it with a bias current source. The output terminal of the output voltage detection module is connected to the input terminal of the voltage pre-regulation module to provide it with a feedback control signal; The output voltage detection module is also used to detect the external input voltage H_VDD. If H_VDD is less than the preset voltage, the output voltage detection module outputs a high-potential control signal to control the high-voltage branch of the voltage pre-regulation module to turn off, so that the output voltage of the LDO is equal to H_VDD. If H_VDD is greater than the preset voltage, the output voltage detection module outputs a low-potential control signal to control the voltage pre-regulation module to generate an internal low-voltage power supply L_VDD.

2. The voltage pre-modulation circuit for a high-voltage LDO according to claim 1, characterized in that: The current self-biasing circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a first NMOS transistor NM0, a second NMOS transistor NM1, a first transistor Q0, a second transistor Q1, a first resistor R0, and a second resistor R1; A first resistor R0 is connected between the collector of the first transistor Q0 and the output terminal of the voltage pre-regulation module; the emitter of the first transistor Q0 is grounded, and the collector of the first transistor Q0 is connected to its base and then connected to the base of the second transistor Q1. The emitter of the second transistor Q1 is connected to the second resistor R1 and then to the ground terminal; the gate of the first NMOS transistor NM0 is connected to its drain and then to the collector of the second transistor Q1; the source of the first NMOS transistor NM0 is connected to the output terminal of the voltage pre-regulation module. The source of the second PMOS transistor PM2 is connected to the output terminal of the voltage pre-regulation module, the gate of the second PMOS transistor PM2 is connected to the gate of the first NMOS transistor NM0, and the drain of the second PMOS transistor PM2 is connected to the drain of the first NMOS transistor NM0, the gate of the first NMOS transistor NM0, and the gate of the second NMOS transistor NM1. The source of the first NMOS transistor NM0 and the source of the second NMOS transistor NM1 are both connected to the ground terminal, and the drain of the second NMOS transistor NM1 is connected to the output terminal of the voltage pre-regulation module.

3. A voltage pre-modulation circuit for a high-voltage LDO according to claim 2, characterized in that: The emitter area ratio of the first transistor Q0 to the second transistor Q1 is 1:8; the width-to-length ratio of the current mirror formed by the first PMOS transistor PM1 and the second PMOS transistor PM2 is 1:1; the width-to-length ratio of the current mirror formed by the first NMOS transistor NM0 and the second NMOS transistor NM1 is 1:1; the current self-biasing circuit adopts a bipolar Willard micro-current source structure, and the bias current generated is I = (V be2 -V be1 ) / R1, where R1 represents the resistance value of the second resistor R1, V be2 V represents the base-emitter voltage of the first transistor Q0. be1 This represents the base-emitter voltage of the second transistor Q1, which provides bias current for the voltage pre-regulation module and the output voltage detection module.

4. A voltage pre-modulation circuit for a high-voltage LDO according to claim 1, characterized in that: The output voltage detection module includes a third PMOS transistor PM3, a fourth PMOS transistor PM4, a third NMOS transistor NM2, a fourth NMOS transistor NM3, a third resistor R2, a fourth resistor R3, a fifth resistor R4, a sixth resistor R5, and a digital logic gate circuit; the digital logic gate circuit includes a first Schmitt trigger ST1, a second Schmitt trigger ST2, a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4; The output terminal of the voltage pre-regulation module is connected to the third resistor R2, the source of the third PMOS transistor PM3, the source of the fourth PMOS transistor PM4, and the power supply terminal of the digital logic gate circuit; the third resistor R2 is also connected to the fourth resistor R3 and the drain of the third PMOS transistor PM3; the fourth resistor R3 is also connected to the fifth resistor R4 and the gate of the fourth PMOS transistor PM4; the fifth resistor R4 is also connected to the sixth resistor R5; the sixth resistor R5 is also connected to the drain of the third NMOS transistor NM2, the gate of the third NMOS transistor NM2, and the gate of the fourth NMOS transistor NM3. The source of the third NMOS transistor NM2, the source of the fourth NMOS transistor NM3, and the ground terminal of the digital logic gate circuit are all connected to the ground terminal; the gate of the third PMOS transistor PM3 is connected to the output terminal of the output voltage detection module. The drain of the fourth NMOS transistor NM3 is connected to the drain of the fourth PMOS transistor PM4 and the input of the first Schmitt trigger ST1, respectively. The output of the first Schmitt trigger ST1 is connected to the input of the first inverter INV1; the output of the first inverter INV1 is connected to the input of the second inverter INV2; the output of the second inverter INV2 is connected to the input of the second Schmitt trigger ST2; the output of the second Schmitt trigger ST2 is connected to the input of the third inverter INV3; the output of the third inverter INV3 is connected to the input of the fourth inverter INV4; and the output of the fourth inverter INV4 is connected to the VDC-CHANGE terminal.

5. A voltage pre-modulation circuit for a high-voltage LDO according to claim 1, characterized in that: The high-voltage branch of the voltage pre-regulation module includes a first PLDMOS transistor PLD1, a second PLDMOS transistor PLD2, a first NLDMOS transistor NLD1, a second NLDMOS transistor NLD2, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3, a seventh resistor R6, an eighth resistor R7, a ninth resistor R8, and a tenth resistor R9. The source of the first PLDMOS transistor PLD1 is connected to the external input voltage H_VDD. The drain of the first PLDMOS transistor PLD1 is connected to its own gate, and then connected to the gate of the second PLDMOS transistor PLD2 and the seventh resistor R6. The seventh resistor R6 is also connected to the drain of the first NLDMOS transistor NLD1. The source of the first NLDMOS transistor NLD1 is connected to the output of the current self-biasing circuit, and the gate of the first NLDMOS transistor NLD1 is connected to the eighth resistor R7 and the cathode of the first Zener diode Z1 respectively; the eighth resistor R7 is also connected to the external input voltage H_VDD, and the anode of the first Zener diode Z1 is connected to the ground terminal. The source of the second PLDMOS transistor PLD2 is connected to the external input voltage H_VDD, and the drain of the second PLDMOS transistor PLD2 is connected to the ninth resistor R8. The ninth resistor R8 is also connected to the cathode of the second Zener diode Z2 and the gate of the second NLDMOS transistor NLD2. The anode of the second Zener diode Z2 is connected to the ground terminal. The drain of the second NLDMOS transistor NLD2 is connected to the external input voltage H_VDD, and the source of the second NLDMOS transistor NLD2 is connected to the cathode of the third Zener diode Z3; the anode of the third Zener diode Z3 is connected to the tenth resistor R9, and the tenth resistor R9 is also connected to the ground terminal.

6. A voltage pre-modulation circuit for a high-voltage LDO according to claim 5, characterized in that: The current mirror formed by the first PLDMOS transistor PLD1 and the second PLDMOS transistor PLD2 has a width-to-length ratio of 1:N, where N is a positive integer; the high-voltage branch adopts a source follower connection and utilizes the clamping effect of the Zener diode to generate L_VDD=V zener -V GS V zener This represents the Zener diode voltage, V. GS This represents the gate-source voltage of the transistor.

7. A voltage pre-modulation circuit for a high-voltage LDO according to claim 5, characterized in that: The low-voltage branch of the voltage pre-regulation module includes the third PLDMOS transistor PLD3, the fourth PLDMOS transistor PLD4, the fifth PLDMOS transistor PLD5, the third NLDMOS transistor NLD3, the fourth NLDMOS transistor NLD4, the fifth NMOS transistor NM4, the sixth NMOS transistor NM5, the fourth Zener diode Z4, the eleventh resistor R10, the twelfth resistor R11, the thirteenth resistor R12, the fourteenth resistor R13, and the fifteenth resistor R14; The eleventh resistor R10 is connected to the external input voltage H_VDD. The eleventh resistor R10 is also connected to the cathode of the fourth Zener diode Z4, the gate of the fourth NLDMOS transistor NLD4, the gate of the sixth NMOS transistor NM5, and the fifteenth resistor R14. The anode of the fourth Zener diode Z4 is connected to the ground terminal. The drain of the fifth NMOS transistor NM4 is connected to the source of the third NLDMOS transistor NLD3. The gate of the fifth NMOS transistor NM4 is connected to the tenth resistor R9, and the source of the fifth NMOS transistor NM4 is grounded. The drain of the third NLDMOS transistor NLD3 is connected to the twelfth resistor R11. The gate of the third NLDMOS transistor NLD3 is also connected to the anode of the third Zener diode Z3. The twelfth resistor R11 is connected to the drain of the third PLDMOS transistor PLD3, the gate of the third PLDMOS transistor PLD3, and the gate of the fourth PLDMOS transistor PLD4. The source of the third PLDMOS transistor PLD3 and the source of the fourth PLDMOS transistor PLD4 are both connected to the external input voltage H_VDD; the drain of the fourth PLDMOS transistor PLD4 is connected to the drain of the fourth NLDMOS transistor NLD4 and the gate of the fifth PLDMOS transistor PLD5; the source of the fourth NLDMOS transistor NLD4 is connected to the fourteenth resistor R12, which is also connected to the ground terminal. The fourteenth resistor R13 is connected between the drain of the fifth PLDMOS transistor PLD5 and the drain of the sixth NMOS transistor NM5. The fourteenth resistor R13 is also connected to the source of the second NLDMOS transistor NLD2, and the source of the sixth NMOS transistor NM5 is grounded. The drain of the fifth PLDMOS transistor PLD5 is also connected to the source of the second NLDMOS transistor NLD2.

8. A voltage pre-modulation circuit for a high-voltage LDO according to claim 7, characterized in that: The current mirror formed by the third PLDMOS transistor PLD3 and the fourth PLDMOS transistor PLD4 has a width-to-length ratio of 1:M, where M is a positive integer; the low-voltage branch turns off the sixth NMOS transistor NM5 through the feedback control signal VDC-CHANGE output by the output voltage detection module, generating L_VDD=H_VDD.

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