FPGA-based PLC high-speed data acquisition and processing method and system

Abstract

This application discloses a high-speed data acquisition and processing method and system for PLC based on FPGA. First, it constructs a detailed real-time heat map and load vector by real-time sensing of multi-point temperature, data input rate, and task queue status on the FPGA chip. Based on this real-time information, it accurately predicts future power consumption and potential hotspot areas to optimize the modeling of internal thermal coupling effects and overcome the shortcomings of traditional models that underestimate peak power consumption. Finally, based on the prediction results, it intelligently generates task execution plans and refined clock gating masks, achieving proactive and adaptive management of FPGA resources. This approach significantly improves the operational stability and reliability of FPGA in high-speed data acquisition and processing scenarios, thus laying a solid foundation for precise industrial control and intelligent decision-making.

Description

Technical Field

[0001] This application relates to the field of data processing, specifically to a high-speed data acquisition and processing method and system based on FPGA and PLC. Background Technology

[0002] In today's wave of Industry 4.0 and smart manufacturing, unprecedented demands are being placed on real-time monitoring, precise control, and intelligent decision-making in production processes. As the core of industrial automation, the PLC (Programmable Logic Controller) is experiencing a dramatic increase in the amount and speed of data it processes. To meet the stringent requirements of higher-level applications such as high-precision equipment status correlation analysis, multi-axis cooperative motion control, and high-precision quality inspection, building an efficient and stable high-speed PLC data acquisition and processing solution has become crucial. FPGA, with its parallel processing capabilities and reconfigurability, has become a key technology for achieving this goal.

[0003] However, existing high-speed PLC data acquisition and processing solutions face a series of significant technical challenges in practice. Especially in complex industrial environments, ensuring that heterogeneous sensor data from different interface types (such as analog ADCs, digital encoders, and GigEVision cameras) and different physical locations can be assigned a unified and nanosecond-accurate timestamp within the FPGA that truly reflects the moment the physical event occurred is a pressing issue. Current technologies often mark the data arrival time rather than the event occurrence time, and generally lack a high-precision, unified global time scale covering all nodes. Furthermore, they fail to effectively compensate for the inherent and asymmetric delays in the data link, severely limiting the accuracy of data analysis and control.

[0004] Therefore, an optimized FPGA-based PLC high-speed data acquisition and processing method is needed. Summary of the Invention

[0005] To address the aforementioned technical problems, this application is proposed. Embodiments of this application provide a high-speed data acquisition and processing method and system for PLC based on FPGA. First, by real-time sensing of multi-point temperature, data input rate, and task queue status on the FPGA chip, a detailed real-time heat map and load vector are constructed. Based on this real-time information, future power consumption and potential hotspot areas are accurately predicted to optimize the modeling of internal thermal coupling effects and overcome the shortcomings of traditional models that underestimate peak power consumption. Finally, based on the prediction results, a task execution plan and a refined clock gating mask are intelligently generated, achieving proactive and adaptive management of FPGA resources. In this way, the operational stability and reliability of the FPGA in high-speed data acquisition and processing scenarios are significantly improved, thus laying a solid foundation for achieving precise industrial control and intelligent decision-making.

[0006] According to one aspect of this application, a high-speed data acquisition and processing method for PLC based on FPGA is provided, comprising: Acquire data from on-chip multi-point temperature sensors, data input rate, and task queue status; Multidimensional real-time status perception is performed on on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current thermal map and current load vector; Based on the current heat map and current load vector, load and thermal effects are predicted to obtain predicted power consumption and predicted hot spot areas; Intelligent scheduling is performed based on the current heatmap, predicted power consumption, and predicted hot spots to obtain task execution plans and fine-grained clock gating masks; The task execution plan and refined clock gating mask are used to perform planned execution and power consumption execution to obtain the final gating clock signal as well as module enable and configuration signals.

[0007] According to another aspect of this application, a high-speed data acquisition and processing system for PLC based on FPGA is provided, comprising: The data acquisition module is used to acquire data from the on-chip multi-point temperature sensor, data input rate, and task queue status. The multi-dimensional real-time state perception module is used to perform multi-dimensional real-time state perception on on-chip multi-point temperature sensor data, data input rate and task queue status to obtain the current heat map and current load vector. The load and thermal effect prediction module is used to predict the load and thermal effect based on the current heat map and the current load vector to obtain the predicted power consumption and predicted hot spot areas. The intelligent scheduling module is used to perform intelligent scheduling based on the current heat map, predicted power consumption, and predicted hot spots to obtain task execution plans and fine-grained clock gating masks; The plan execution and power consumption execution module is used to perform plan execution and power consumption execution based on the task execution plan and a fine-grained clock gating mask to obtain the final gating clock signal as well as the module enable and configuration signals.

[0008] Compared with existing technologies, this application provides a high-speed data acquisition and processing method and system for PLC based on FPGA. First, it constructs a detailed real-time heat map and load vector by real-time sensing of multi-point temperature, data input rate, and task queue status on the FPGA chip. Based on this real-time information, it accurately predicts future power consumption and potential hotspot areas to optimize the modeling of internal thermal coupling effects and overcome the shortcomings of traditional models that underestimate peak power consumption. Finally, based on the prediction results, it intelligently generates task execution plans and refined clock gating masks, achieving proactive and adaptive management of FPGA resources. This approach significantly improves the operational stability and reliability of FPGA in high-speed data acquisition and processing scenarios, thus laying a solid foundation for achieving precise industrial control and intelligent decision-making. Attached Figure Description

[0009] The above and other objects, features, and advantages of this application will become more apparent from the more detailed description of the embodiments of this application in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this application and form part of the specification. They are used together with the embodiments of this application to explain this application and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0010] Figure 1 This is a flowchart of a high-speed data acquisition and processing method based on FPGA and PLC according to an embodiment of this application; Figure 2 This is a schematic diagram of the data flow of the FPGA-based PLC high-speed data acquisition and processing method according to an embodiment of this application; Figure 3 This is a block diagram of an FPGA-based PLC high-speed data acquisition and processing system according to an embodiment of this application. Detailed Implementation

[0011] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0012] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0013] While this application makes various references to certain modules of the systems according to embodiments of this application, any number of different modules can be used and run on user terminals and / or servers. The modules described are merely illustrative, and different aspects of the systems and methods may use different modules.

[0014] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0015] Hereinafter, exemplary embodiments according to this application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this application, and not all embodiments of this application. It should be understood that this application is not limited to the exemplary embodiments described herein.

[0016] The technical solution of this application proposes a high-speed data acquisition and processing method for PLC based on FPGA. Figure 1 This is a flowchart of a high-speed data acquisition and processing method based on an FPGA PLC according to an embodiment of this application. Figure 2 This is a schematic diagram of the data flow in the FPGA-based PLC high-speed data acquisition and processing method according to an embodiment of this application. Figure 1 and Figure 2 As shown, the FPGA-based PLC high-speed data acquisition and processing method according to an embodiment of this application includes the following steps: S1, acquiring on-chip multi-point temperature sensor data, data input rate, and task queue status; S2, performing multi-dimensional real-time state perception on the on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current heat map and current load vector; S3, performing load and thermal effect prediction based on the current heat map and current load vector to obtain predicted power consumption and predicted hot spot areas; S4, performing intelligent scheduling based on the current heat map, predicted power consumption, and predicted hot spot areas to obtain a task execution plan and a refined clock gating mask; S5, performing plan execution and power consumption execution based on the task execution plan and refined clock gating mask to obtain the final gating clock signal and module enable and configuration signals.

[0017] Specifically, S1 involves acquiring on-chip multi-point temperature sensor data, data input rate, and task queue status. It should be understood that in high-density on-chip systems such as FPGAs, accurate prediction of future power consumption is the cornerstone of implementing proactive thermal management strategies. To ensure the stable and reliable operation of the PLC high-speed data acquisition and processing system in complex industrial scenarios and to effectively address the overheating risks that may arise from high-load operation, the system needs to understand its own health status and workload in real time. On-chip multi-point temperature, data input rate, and task queue status, as the most direct and critical operating environment and load indicators within the FPGA, are the core inputs for multi-dimensional real-time state perception, power consumption and thermal effect prediction, and intelligent scheduling. Their accurate acquisition directly affects the effectiveness of the entire system's thermal management and resource allocation strategies. Among them, on-chip multi-point temperature sensor data refers to real-time digital readings obtained from temperature sensors integrated in different physical locations or functional modules of the FPGA chip, which are used to reflect the local heat distribution inside the chip; data input rate refers to the amount of data or the frequency of data stream entering the FPGA per unit time, which is a key indicator for measuring the intensity of external load and input bandwidth requirements; task queue status refers to the current full load, free space, or number of tasks stored in the queues (such as FIFOs and buffers) used inside the FPGA to cache data to be processed or tasks to be executed, which reflects the real-time status of the internal processing pressure of the system.

[0018] In practical implementation, firstly, for on-chip multi-point temperature sensor data, FPGAs typically integrate multiple distributed temperature sensors (such as dedicated thermistors or ADC IP cores). These sensors can monitor the local temperature of different areas of the chip in real time. The data acquisition module periodically reads the raw digital temperature values ​​provided by these sensors as the basis data for the current chip temperature distribution. Secondly, for the data input rate, the system uses internal counters or rate monitoring logic to statistically analyze the total amount or frequency of various heterogeneous sensor data streams entering the FPGA (such as data from analog ADCs, digital encoders, and GigEVision cameras) per unit time, thereby quantifying the current input load intensity. Thirdly, acquiring the task queue status involves real-time monitoring of the FPGA's internal task scheduling or data buffer queues. The data acquisition module queries the current occupancy, depth, or number of waiting tasks in each task queue (such as FIFO, RAM, or dedicated task buffer) to reflect the current backlog of processing tasks and the system load. This raw data is typically collected by the data acquisition module through the FPGA's internal bus (such as AXI) or dedicated register interface.

[0019] Specifically, S2 involves multi-dimensional real-time sensing of on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current thermal map and current load vector. It should be understood that while raw sensor readings and status information are abundant, they are often scattered and unprocessed, insufficient to directly guide intelligent scheduling and thermal management decisions. Therefore, in the technical solution of this application, multi-dimensional real-time sensing of on-chip multi-point temperature sensor data, data input rate, and task queue status is performed to integrate, calibrate, and abstract these discrete raw data, transforming them into inputs that the system can understand and analyze. This approach helps the system comprehensively and intuitively grasp the real-time thermal distribution and dynamic workload of the FPGA chip, providing an accurate and unified data foundation for subsequent load and thermal effect prediction, and avoiding decision-making biases caused by fragmented or inaccurate information.

[0020] In specific implementation, the generation of the current heatmap involves the following process: First, based on chip calibration data, the on-chip multi-point temperature sensor data is calibrated to obtain calibrated on-chip multi-point temperature data. It should be understood that the initial multi-point temperature data acquired by the data acquisition module may contain systematic errors or offsets. Therefore, it is necessary to use pre-stored chip calibration data (e.g., compensation curves or parameters obtained by testing and fitting sensors under known temperature conditions) to correct these raw data to ensure the accuracy of temperature readings. The calibrated temperature data is then matched and associated with the precise physical location information of each sensor predefined within the FPGA chip. Second, the on-chip multi-point calibrated temperature data is associated with the sensor physical locations and spatial interpolation is performed to obtain the current heatmap. In other words, to obtain a continuous and comprehensive temperature distribution on the chip surface, the system performs spatial interpolation operations on these discrete calibrated temperature data points (e.g., using bilinear interpolation, Kriging interpolation, or finite element analysis algorithms) to generate a smooth, visualized current heatmap that intuitively reflects the real-time temperature distribution of various regions on the chip, including potential hotspot areas. Furthermore, the generation of the current load vector is specifically achieved by quantizing the workload status of the data input rate and task queue status. That is, the raw data input rate (e.g., MB / s or PPS) and task queue status (e.g., queue depth, number of tasks to be processed, or percentage full) obtained in the previous step are uniformly quantized. This process includes normalizing, weighting, or mapping different types of rates and statuses to predefined load levels, transforming heterogeneous workload metrics into a unified, multi-dimensional numerical array or vector. This vector concisely and comprehensively represents the current overall workload of the FPGA and the pressure on its various resources.

[0021] Specifically, S3 predicts load and thermal effects based on the current heatmap and load vector to obtain predicted power consumption and predicted hotspot areas. It should be understood that simply knowing the current state is insufficient for proactive task scheduling and power management. To effectively mitigate system overheating risks during high-speed data acquisition and processing, and to ensure the long-term, stable, and reliable operation of the FPGA system, the technical solution of this application predicts the chip's power consumption distribution and potential hotspot areas through analysis of the current heatmap and load vector. This provides accurate future thermal state information, offering reliable data support for subsequent intelligent scheduling and thermal management decisions, thereby effectively mitigating system overheating risks and ensuring the long-term, stable, and reliable operation of the FPGA system.

[0022] In practice, the first step is to estimate the future task load and execution sequence of the current load vector to obtain an estimated task sequence mapping and predict subsequent input rates. It should be understood that relying solely on the current load situation is insufficient to guide upcoming changes. By estimating future task load and execution sequences, we can anticipate the workload, task types, and processing order the system will face in the future, which is crucial for accurately predicting future power consumption distribution and potential hotspots. Simultaneously, predicting subsequent input rates helps the system pre-allocate bandwidth and resources, avoiding processing bottlenecks caused by sudden data flows. This predictive capability is the foundation for achieving proactive thermal management, ensuring the FPGA's continued high-performance operation under future conditions.

[0023] In this process, the system first analyzes the historical trends of the data input rate and task queue status reflected in the current load vector. For example, if a sustained increase in the data input rate is observed, the system may predict that the rate will remain high or continue to rise in the following time period. This can be done based on time series analysis methods (such as ARIMA models, Kalman filters) or machine learning algorithms (such as recurrent neural networks LSTM). These models predict future input load intensity by learning patterns and periodicity in historical data. Next, based on the types of tasks waiting to be processed in the current task queue and preset task priority rules, scheduling policies, or task flow graphs, the system estimates the sequence of tasks to be executed within a future time window (e.g., the next 10 milliseconds). This may include identifying newly arriving tasks, assessing the remaining execution time of existing tasks, and constructing a task execution order based on predefined task dependencies. For example, in a PLC control scenario, sensor acquisition tasks may have a higher priority, while data analysis or communication tasks may have a lower priority. Therefore, after determining the task sequence, the system estimates the future FPGA resource usage of each task based on its characteristics (e.g., required logic resources, DSP units, BRAM, trigger clock frequency, etc.). This information is used for subsequent "task sequence mapping estimation," which assigns tasks to specific physical areas of the FPGA. Combining the above analysis, the system obtains a sequence of virtual or actual mappings of future tasks on the FPGA—the estimated task sequence mapping. This mapping includes not only the execution order of the tasks but may also include a preliminary idea of ​​which functional module or physical area of ​​the FPGA the tasks will be assigned to. For example, it can be predicted that an image processing task will run on a specific DSP cluster, while a communication task will be executed on another IP core. Finally, combining trend analysis of the data input rate, the system outputs a predicted value for the rate of external data inflow over a future period. This predicted value can be a specific numerical value or a range or probability distribution to reflect the uncertainty of the prediction. Next, based on the task thermal characteristic database, the estimated task sequence mapping is queried using the task power consumption model and associated with hot regions to obtain the original predicted power consumption distribution. That is, by querying the task thermal characteristic database, these tasks are associated with preset power consumption models and physical locations to obtain the preliminary power consumption and heat distribution of the FPGA at future moments (i.e., the original predicted power consumption distribution). This information is the cornerstone for subsequent accurate prediction of total power consumption and hotspot areas, and can provide quantitative input for proactive thermal management strategies.

[0024] In this process, firstly, the corresponding power consumption model is retrieved from a pre-established task thermal characteristic database based on the current task's type and configuration parameters (e.g., amount of data processed, operating frequency, type of IP core used, etc.). This database stores the power consumption characteristics of various functional modules or tasks on the FPGA under different operating modes. These models can be simple constant values, linear / nonlinear functions based on input data rate or clock frequency, or even more complex models based on lookup tables or machine learning training. For example, a high-speed FFT task might correspond to a high-power model when running at full speed, and a different model in low-power mode. Simultaneously, the thermal region associated with the task is obtained from the task thermal characteristic database. This refers to the area where the task is actually physically located on the FPGA chip or the coordinates of its main resource consumption. For example, a DSP-intensive task might be associated with the DSP block area of ​​the FPGA, while a communication protocol stack task might be associated with the transceiver and logic resource areas. This correlation information ensures that the predicted power consumption can be accurately mapped to the heat source on the chip. Secondly, combining the queried task power consumption model and the predicted task operating parameters in the estimated task sequence mapping, the power consumption of the task at a specific future time point or time period is calculated. Then, this calculated task power consumption value is mapped to the corresponding physical area of ​​the FPGA chip based on its thermal region correlation information. By repeating the above process for all tasks in the estimated task sequence mapping and accumulating the power consumption of all simultaneously active tasks in their respective physical areas, the original predicted power consumption distribution is finally obtained. This is a preliminary power consumption distribution map in spatial and temporal dimensions, reflecting the power consumption generated on the chip when each task runs independently, but it does not yet consider the complex heat conduction and interaction effects inside the chip. Furthermore, based on the original predicted power consumption distribution, a comprehensive prediction of total power consumption and hotspots is performed to obtain the predicted power consumption and predicted hotspot regions. It should be understood that traditional power consumption prediction models often simplify the total system power consumption as a linear superposition of the power consumption of each independent functional module. However, this simplified model ignores the crucial physical interaction within the chip, namely the thermal coupling effect. This effect manifests as the heat generated by the high-power computing module (i.e., the heat source "attacker") during continuous operation significantly increasing the local junction temperature of neighboring modules (i.e., the passive "victim") through thermal conduction through the silicon substrate. Given the exponential positive correlation between leakage current and junction temperature in semiconductor devices, even if the "victim" module itself is under low load or even idle, its static power consumption will exhibit a significant non-linear increase due to the heat flux from the "attacker" module. Therefore, the original linear superposition model fails to account for the dynamic interactive power consumption caused by this inter-module thermal conduction, leading to a potentially serious underestimation of the total system power consumption prediction under extreme conditions such as the physical aggregation of high-power tasks. This can cause subsequent thermal management strategies to fail due to erroneous data, creating a hidden risk of overheating. To address the aforementioned technical issues, this application proposes a power consumption interaction modeling and correction prediction method based on thermal proximity effect. By introducing precise modeling of thermal coupling effect, it corrects the shortcomings of traditional prediction models, generates a more accurate prediction of total system power consumption, and accurately identifies potential hotspot areas in the future. This provides a solid and reliable data foundation for subsequent proactive thermal management and intelligent task scheduling, effectively avoids the risk of system overheating, and ensures the long-term, stable, and reliable operation of the FPGA system.

[0025] In this process, firstly, based on the original predicted power consumption distribution and the system's basic static power consumption, the linear predicted power consumption is determined. This involves first performing a simple linear summation of the power consumption of each module within the prediction time in the original predicted power consumption distribution, and then adding the FPGA chip's basic static power consumption (i.e., the inherent power consumption under no workload) to obtain a preliminary total power consumption value without thermal coupling effect correction, i.e., the linear predicted power consumption. This step provides a prediction benchmark for the traditional linear superposition model. Next, based on the task physical adjacency graph and the power consumption attacker threshold, attacker-victim pair identification and thermal impact factor calculation are performed on the original predicted power consumption distribution to obtain the attacker-victim impact set. During this process, the system traverses the power consumption of all tasks within the prediction time window. When the instantaneous power consumption of a task exceeds the preset power consumption attacker threshold, it is marked as an attacker. Subsequently, based on the pre-stored task physical adjacency graph, all neighboring task modules of this attacker are queried and identified as potential victims.

[0026] Furthermore, based on the victim leakage sensitivity database, the coupled increased power consumption of the attacker-victim impact set is calculated to obtain the total interactive power consumption. That is, after obtaining the thermal influence intensity between each module, it is further converted into the actual additional power consumption value. In this process, for each victim module, the system multiplies its own leakage sensitivity coefficient to temperature changes with the total thermal influence factor received from all neighboring attackers, thereby calculating the additional static power consumption of this victim module due to thermal coupling effects. Subsequently, the additional power consumption of all victim modules is accumulated to obtain the total interactive power consumption of the system at the current moment. Then, based on the total interactive power consumption and the linear predicted power consumption, the predicted power consumption is determined. That is, the newly calculated nonlinear interactive power consumption is integrated with the original linear power consumption prediction to form the final, comprehensive power consumption prediction result. In this process, the total interactive power consumption calculated in the previous steps is summed with the predicted power consumption calculated by linear superposition in the original mechanism. The total system power consumption is equal to the linear superposition of the independent operating power consumption of each module and the sum of the additional nonlinear power consumption generated by the thermal coupling effect between modules. In this way, a time series prediction of the total power consumption of the system, which is accurately corrected and reflects the real physical process, can be output. This prediction effectively overcomes the underestimation defect of traditional methods.

[0027] This approach fundamentally solves the power consumption prediction inaccuracy problem caused by the neglect of thermal coupling between modules in traditional linear superposition models. It generates a more accurate time series prediction of total system power consumption, especially effective in the most thermally challenging scenarios where multiple high-power tasks are physically clustered on the FPGA chip, thus avoiding a severe underestimation of peak power consumption. Ultimately, this high-precision power consumption prediction provides a solid and reliable data foundation for subsequent proactive thermal management and intelligent task scheduling strategies, enabling better decision-making. This effectively mitigates the risk of system overheating in harsh industrial environments, ensuring the long-term, stable, and reliable operation of the FPGA system.

[0028] Specifically, S4 involves intelligent scheduling based on the current heatmap, predicted power consumption, and predicted hotspot regions to obtain a task execution plan and a refined clock gating mask. It should be understood that in high-density on-chip systems like FPGAs, high-intensity computing tasks with concentrated power consumption can easily lead to localized temperature increases. If not properly managed, this can trigger the chip's built-in thermal protection mechanism, reducing performance or even causing permanent hardware damage, severely impacting system stability and reliability. Therefore, in the technical solution of this application, intelligent scheduling is performed based on the current heatmap, predicted power consumption, and predicted hotspot regions. Upon receiving accurate predicted power consumption and hotspot region information, combined with real-time thermal status, it can proactively and intelligently avoid potential thermal risks. In this way, the system can obtain a more realistic and comprehensive system thermal prospect, thereby providing a basis for scheduling decisions, preventing scheduling errors caused by underestimating peak power consumption in traditional methods, and ultimately ensuring the stability and durability of the FPGA system in high-speed data acquisition and processing scenarios.

[0029] The task execution plan refers to the specific execution sequence, allocation method, and operating parameters (such as frequency and voltage) of tasks determined after intelligent scheduling at a specific time point and on specific resources (such as processing units and storage blocks). A fine-grained clock gating mask is a low-level hardware control instruction composed of a series of binary bits, used to precisely control the on / off state of clock signals for various functional modules or registers within an FPGA. Selectively shutting down the clocks of inactive or non-critical modules to reduce dynamic and static power consumption is a key technology for achieving fine-grained power management.

[0030] In practice, the first step is to conduct a thermal risk assessment and budget quantification of the current heatmap, predicted power consumption, and predicted hotspot areas to obtain thermal violation flags and thermal budget margins. That is, a comprehensive analysis of the current heatmap, predicted power consumption, and predicted hotspot areas is performed to assess whether the system has the risk of reaching or exceeding a preset safe temperature threshold, and to quantify how much additional thermal load (thermal budget margin) the system can withstand while maintaining safe operation. During this process, the scheduling unit or thermal management module comprehensively analyzes this information and compares it with preset chip safe temperature thresholds, power consumption limits, and temperature limits for specific areas. Specifically, it checks whether there are areas in the current heatmap that are close to or have already reached dangerous levels, and simultaneously assesses whether there are potential risks of exceeding safe operating ranges within the predicted power consumption and predicted hotspot areas in the future time window. If the prediction results show that any thermal parameter will exceed the set critical value, the system will generate and set a thermal violation flag, indicating a clear thermal risk. Simultaneously, the system quantifies the thermal budget margin, typically obtained by calculating the difference between the current state and the safety limit. For example, this represents the additional power dissipation that individual areas or the chip as a whole can withstand while meeting the current task's performance requirements and without activating thermal violation flags, or the difference from the maximum permissible temperature. For instance, if a module's predicted temperature is 80°C and its safety limit is 90°C, then the thermal budget margin for that area is 10°C. These assessments serve as key inputs for subsequent scheduling decisions. Next, based on the hot violation flag and the hot budget margin, a multi-strategy trade-off and avoidance decision is made on the estimated task sequence map to obtain the selected mitigation strategy. During this process, the scheduler uses the hot violation flag and the hot budget margin to guide the decision-making process. When the hot violation flag is set, or the hot budget margin falls below a certain warning threshold, the scheduler recognizes that the system needs to take action to avoid overheating. At this point, the scheduler refers to and analyzes the previously obtained estimated task sequence map. It selects and weighs various predefined hot management mitigation strategies, which may include, but are not limited to: Task timing adjustment: Move high-power tasks from areas that have formed or are about to form hotspots to relatively cooler areas on the chip for execution; Reduce task execution frequency or voltage: Reduce the power consumption of the processing unit used by the task by reducing its operating frequency or supply voltage. Activate or enhance clock gating: Enable a stricter clock gating strategy for modules that do not need to be executed immediately or are inactive, so that they stop receiving clock signals, thereby saving energy; The scheduler will perform multi-objective optimization trade-offs based on the severity of the thermal violation flag, the size of the thermal budget margin, and the impact of each mitigation strategy on system performance (e.g., delaying tasks increases latency, and reducing frequency reduces throughput) to select the mitigation strategy that most effectively eliminates thermal risks while having the least impact on overall system performance. Furthermore, based on the selected mitigation strategy and the estimated task sequence mapping, a task execution plan and a fine-grained clock gating mask are generated. During this process, the scheduler applies the selected mitigation strategy to the original estimated task sequence mapping, generating a new, thermally optimized task execution plan. For example, if the selected strategy is to "reduce the frequency of a high-power module," then the operating frequency of that module in the task execution plan will be updated. If the strategy is to "delay a task," then the start time of that task will be rescheduled. Next, the system generates a fine-grained clock gating mask based on this new task execution plan and the current system state. The fine-grained clock gating mask is a binary bit sequence generated by the intelligent scheduling module, used to precisely control the clock signal on / off of various hardware modules or register groups within the FPGA. Its fine-grained nature allows for independent clock control of smaller logic units within the chip, achieving ultimate dynamic power management. Specifically, this mask is a set of specific hardware control bits that precisely indicate which clock trees within the FPGA should be activated and which should be gated (disabled). For example, if the "task execution plan" determines that a module will not run or will be in a low-power state for the next period of time, then the corresponding clock gating mask will be configured to shut down the clock of that module. This fine-grained control can minimize the dynamic power consumption of the system and effectively control local heat dissipation, thereby achieving thermal management goals at the micro level.

[0031] Specifically, S5 performs planned execution and power consumption execution based on the task execution plan and a refined clock gating mask to obtain the final gating clock signal, as well as module enable and configuration signals. That is, the abstract task execution plan and refined clock gating mask generated by the intelligent scheduling module based on the real-time heat map, predicted power consumption, and predicted hot spots are transformed into actual operation instructions that the FPGA chip can understand and execute.

[0032] In practice, the process begins with parsing the task execution plan to generate module enable and configuration signals. During this process, the system's configuration controller or runtime management unit analyzes the task execution plan output by the intelligent scheduling module in real time. This plan contains detailed scheduling information for a series of tasks. Based on this information, the controller converts it into module enable and configuration signals for each functional module within the FPGA. For example, if the task execution plan indicates that a specific data acquisition module (such as a high-speed ADC interface) needs to be started within a certain time window, and its data processing path needs to be configured to a specific filtering mode, then the corresponding enable signal will be set high to activate the module. Simultaneously, a series of configuration bitstreams or register setting signals will be sent to the data acquisition module to load the specified filtering parameters. For modules not used by the task execution plan within the current time window, their enable signals may remain low, keeping them in a low-power or power-off state. This process involves dynamic configuration of the FPGA's programmable logic and control interface operations for specific hardware IP cores. Then, a fine-grained clock gating mask is applied to generate the final gated clock signal. During this process, the system uses a fine-grained clock gating mask provided by the intelligent scheduling module. This mask is directly sent to the gated clock generation unit or clock gating logic within the FPGA. Each functional module or smaller logic area of ​​the FPGA has a corresponding clock gating control entry point. Based on the corresponding bit value in the mask, the clock gating logic determines whether to allow the master clock signal to pass through, thus providing the module with its operating clock. If the mask bit is 0, it indicates that the module's clock is gated (off), and the module will not receive a clock signal, entering a non-operating state, thereby significantly reducing its dynamic power consumption and even reducing leakage current (static power consumption). If the mask bit is 1, it indicates that the module needs to operate, and the clock signal will be allowed to pass through. This process is highly dynamic; the clock gating mask can switch at the microsecond or even nanosecond level according to the real-time progress of the task and the power execution plan to achieve the finest power management. Through these two closely coordinated processes, the FPGA chip can perform corresponding computations and data flow operations in real time according to the task execution plan, while simultaneously managing power consumption in real time based on a fine-grained clock gating mask. The final output consists of the final gating clock signal and module enable and configuration signals that actually operate within the chip, jointly driving the efficient and stable operation of the FPGA system.

[0033] In summary, the FPGA-based PLC high-speed data acquisition and processing method according to the embodiments of this application is explained. First, it constructs a detailed real-time heat map and load vector by real-time sensing of multi-point temperature, data input rate, and task queue status on the FPGA chip. Based on this real-time information, it accurately predicts future power consumption and potential hotspot areas to optimize the modeling of internal thermal coupling effects and overcome the shortcomings of traditional models that underestimate peak power consumption. Finally, based on the prediction results, it intelligently generates task execution plans and refined clock gating masks, achieving proactive and adaptive management of FPGA resources. In this way, the operational stability and reliability of the FPGA in high-speed data acquisition and processing scenarios are significantly improved, thus laying a solid foundation for achieving precise industrial control and intelligent decision-making.

[0034] Furthermore, a high-speed data acquisition and processing system based on FPGA and PLC is also provided.

[0035] Figure 3 This is a block diagram of a high-speed data acquisition and processing system based on an FPGA and a PLC according to an embodiment of this application. Figure 3 As shown, the FPGA-based PLC high-speed data acquisition and processing system 300 according to an embodiment of this application includes: a data acquisition module 310, used to acquire on-chip multi-point temperature sensor data, data input rate, and task queue status; a multi-dimensional real-time state perception module 320, used to perform multi-dimensional real-time state perception on the on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current heat map and current load vector; a load and thermal effect prediction module 330, used to perform load and thermal effect prediction based on the current heat map and current load vector to obtain predicted power consumption and predicted hot spot areas; an intelligent scheduling module 340, used to perform intelligent scheduling based on the current heat map, predicted power consumption, and predicted hot spot areas to obtain a task execution plan and a fine-grained clock gating mask; and a plan execution and power consumption execution module 350, used to perform plan execution and power consumption execution based on the task execution plan and fine-grained clock gating mask to obtain the final gating clock signal and module enable and configuration signals.

[0036] As described above, the FPGA-based PLC high-speed data acquisition and processing system 300 according to the embodiments of this application can be implemented in various wireless terminals, such as servers with FPGA-based PLC high-speed data acquisition and processing algorithms. In one possible implementation, the FPGA-based PLC high-speed data acquisition and processing system 300 according to the embodiments of this application can be integrated into the wireless terminal as a software module and / or hardware module. For example, the FPGA-based PLC high-speed data acquisition and processing system 300 can be a software module in the operating system of the wireless terminal, or it can be an application developed for the wireless terminal; of course, the FPGA-based PLC high-speed data acquisition and processing system 300 can also be one of many hardware modules of the wireless terminal.

[0037] Alternatively, in another example, the FPGA-based PLC high-speed data acquisition and processing system 300 and the wireless terminal can also be separate devices, and the FPGA-based PLC high-speed data acquisition and processing system 300 can be connected to the wireless terminal via wired and / or wireless networks, and transmit interactive information in accordance with an agreed data format.

[0038] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A high-speed data acquisition and processing method for PLC based on FPGA, characterized in that, include: Acquire data from on-chip multi-point temperature sensors, data input rate, and task queue status; Multidimensional real-time status perception is performed on on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current thermal map and current load vector; Based on the current heat map and current load vector, load and thermal effects are predicted to obtain predicted power consumption and predicted hot spot areas; Intelligent scheduling is performed based on the current heatmap, predicted power consumption, and predicted hot spots to obtain task execution plans and fine-grained clock gating masks; The task execution plan and refined clock gating mask are used to perform planned execution and power consumption execution to obtain the final gating clock signal as well as module enable and configuration signals.

2. The FPGA-based PLC high-speed data acquisition and processing method according to claim 1, characterized in that, Multi-dimensional real-time status sensing is performed on on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current thermal map and current load vector, including: Based on the chip calibration data, the on-chip multi-point temperature sensor data is calibrated to obtain the on-chip multi-point calibrated temperature data; The temperature data after multi-point calibration on the chip is correlated with the physical location of the sensor and spatial interpolation is performed to obtain the current thermal map.

3. The FPGA-based PLC high-speed data acquisition and processing method according to claim 2, characterized in that, Multidimensional real-time state perception is performed on on-chip multi-point temperature sensor data, data input rate, and task queue status to obtain the current thermal map and current load vector, including: workload state quantization of data input rate and task queue status to obtain the current load vector.

4. The FPGA-based PLC high-speed data acquisition and processing method according to claim 1, characterized in that, Based on the current heatmap and current load vector, load and thermal effects are predicted to obtain predicted power consumption and predicted hotspot regions, including: The current load vector is used to estimate the future task load and execution sequence to obtain an estimated task sequence mapping and predict the subsequent input rate; Based on the task thermal characteristics database, the task power consumption model is queried and associated with the thermal region to obtain the original predicted power consumption distribution by estimating the task sequence mapping. Based on the original predicted power consumption distribution, a comprehensive prediction of total power consumption and hotspots is performed to obtain the predicted power consumption and predicted hotspot areas.

5. The FPGA-based PLC high-speed data acquisition and processing method according to claim 4, characterized in that, Based on the original predicted power consumption distribution, a comprehensive prediction of total power consumption and hotspots is performed to obtain the predicted power consumption and predicted hotspot regions, including: Based on the original predicted power distribution and the system's basic static power, the linear predicted power is determined. Based on the task physical adjacency graph and the power consumption attacker threshold, attacker-victim pair identification and thermal impact factor calculation are performed on the original predicted power consumption distribution to obtain the attacker-victim impact set; Based on the victim leakage sensitivity database, coupled power consumption calculation is performed on the attacker-victim impact set to obtain the total interactive power consumption; The predicted power consumption is determined based on the total interactive power consumption and the linear predicted power consumption.

6. The FPGA-based PLC high-speed data acquisition and processing method according to claim 5, characterized in that, The predicted power consumption is determined based on the total interactive power consumption and the linear predicted power consumption, including adding the total interactive power consumption and the linear predicted power consumption to obtain the predicted power consumption.

7. The FPGA-based PLC high-speed data acquisition and processing method according to claim 1, characterized in that, Intelligent scheduling is performed based on the current heatmap, predicted power consumption, and predicted hotspot areas to obtain task execution plans and fine-grained clock gating masks, including: Thermal risk assessment and budget quantification are performed on the current heat map, predicted power consumption, and predicted hotspot areas to obtain thermal violation indicators and thermal budget margins; Based on hot violation flags and hot budget margins, a multi-strategy trade-off and avoidance decision is made on the estimated task sequence mapping to obtain the selected mitigation strategy. Based on the selected mitigation strategy and estimated task sequence mapping, a task execution plan and a fine-grained clock gating mask are generated.

8. A high-speed data acquisition and processing system for PLC based on FPGA, characterized in that, include: The data acquisition module is used to acquire data from the on-chip multi-point temperature sensor, data input rate, and task queue status. The multi-dimensional real-time state perception module is used to perform multi-dimensional real-time state perception on on-chip multi-point temperature sensor data, data input rate and task queue status to obtain the current heat map and current load vector. The load and thermal effect prediction module is used to predict the load and thermal effect based on the current heat map and the current load vector to obtain the predicted power consumption and predicted hot spot areas. The intelligent scheduling module is used to perform intelligent scheduling based on the current heat map, predicted power consumption, and predicted hot spots to obtain task execution plans and fine-grained clock gating masks; The plan execution and power consumption execution module is used to perform plan execution and power consumption execution based on the task execution plan and a fine-grained clock gating mask to obtain the final gating clock signal as well as the module enable and configuration signals.

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