Dynamic switching method and system for multi-protocol communication interfaces

Abstract

This invention relates to the field of communication interface technology and discloses a dynamic switching method and system for multi-protocol communication interfaces. The method includes: performing GPIO level detection on the first and second sets of jumper pins of the serial communication interface; triggering protocol switching when a change in the jumper pin level is detected to obtain a protocol selection signal; controlling the enable pins of the RS232 level conversion chip and the RS485 transceiver chip; controlling the transmit / receive direction pins of the RS485 transceiver chip according to the write state of the UART controller's transmit register, and switching the level state of the transmit / receive direction pins after a one-byte transmission time delay after transmission is completed. This invention realizes plug-and-play functionality for RS232, RS485, and TTL communication protocols through a hardware jumper-driven protocol identification mechanism, without requiring software reconfiguration or system restart, thus reducing the complexity of field deployment.

Description

Technical Field

[0001] This invention relates to the field of communication interface technology, and in particular to a method and system for dynamic switching of multi-protocol communication interfaces. Background Technology

[0002] In industrial control systems, industrial PCs need to interact with peripherals using different communication protocols, including programmable logic controllers (PLCs) using the RS232 protocol, distributed sensor networks using the RS485 protocol, and machine tool control modules using the TTL protocol. Traditional industrial PCs have fixed serial communication protocols at the factory. When a production line needs to replace peripherals using different protocols, the system must be shut down to replace the communication module or the entire motherboard, resulting in significant downtime losses and maintenance costs. While existing technologies offer solutions for switching protocols via software configuration, the fixed design of the hardware circuitry prevents the conversion of electrical characteristics between RS232 single-ended signals, RS485 differential signals, and TTL levels, and lacks data integrity protection mechanisms during protocol switching. Furthermore, in applications with multiple serial ports operating in parallel, different ports may need to connect peripherals using different protocols. Existing technologies typically configure independent physical interfaces for each protocol, leading to wasted hardware resources and increased wiring complexity. They also have shortcomings in timing control for switching transmit and receive directions, failing to effectively address technical issues such as stop bit truncation and bus conflicts, thus affecting communication reliability. Summary of the Invention

[0003] This invention provides a method and system for dynamic switching of multi-protocol communication interfaces. Through a protocol identification mechanism driven by a hardware jumper cap, this invention realizes the plug-and-play function of RS232, RS485 and TTL communication protocols without the need for software reconfiguration or system restart, thus reducing the complexity of on-site deployment.

[0004] In a first aspect, the present invention provides a method for dynamically switching multi-protocol communication interfaces, the method comprising: S1: GPIO level detection is performed on the first and second groups of jumper pins of the serial communication interface. When a change in the jumper pin level is detected, protocol switching is triggered to obtain the protocol selection signal. S2: Configure the channel enable of the digital isolation chip according to the protocol selection signal and control the selection pin of the analog switch to switch the signal transmission path, and control the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip. S3: Control the transmit / receive direction pin of the RS485 transceiver chip according to the transmit register write state of the UART controller, and switch the level state of the transmit / receive direction pin after a one-byte transmission time delay after the transmission is completed.

[0005] In conjunction with the first aspect, in a first implementation of the first aspect of the present invention, S1 includes: The connection status of the first group of jumper pins and the second group of jumper pins in the serial communication interface is acquired by the GPIO detection circuit to obtain the level status of the first group of jumper pins and the level status of the second group of jumper pins. When the first group of jump cap levels is low and the second group of jump cap levels is high, the protocol selection signal is determined to be RS485 protocol; When the first group of jump cap levels is high and the second group of jump cap levels is low, the protocol selection signal is determined to be TTL protocol; When both the first group of jump cap level states and the second group of jump cap level states are high, the protocol selection signal is determined to be RS232 protocol.

[0006] In conjunction with the first aspect, in a second implementation of the first aspect of the present invention, S2 includes: S21: When the protocol selection signal is RS485 protocol, the first and second channels of the digital isolation chip are configured as differential transmit pairs, the third and fourth channels of the digital isolation chip are configured as differential receive pairs, and the first, second, third and fourth channels are enabled. S22: When the protocol selection signal is RS232 protocol or TTL protocol, enable the first channel of the digital isolation chip as a transmitting line, enable the second channel of the digital isolation chip as a receiving line, and disable the third channel and the fourth channel. S23: According to the protocol selection signal, output a control level combination to the first control pin and the second control pin of the analog switch, switch the conduction path of the analog switch, and connect the output of the digital isolation chip to the input of the RS232 level conversion chip, the differential input / output of the RS485 transceiver chip, or the TTL signal terminal through the conduction path respectively. S24: Select the signal control pin of the analog switch to switch the signal transmission path according to the protocol, and select the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip according to the protocol.

[0007] In conjunction with the first aspect, in a third implementation of the first aspect of the present invention, S23 includes: According to the protocol selection signal, a combination of control levels is output to the first control pin and the second control pin of the analog switch. When the protocol selection signal is RS232 protocol, a combination of two low levels is output. When the protocol selection signal is RS485 protocol, a combination of low and high levels is output. When the protocol selection signal is TTL protocol, a combination of high and low levels is output. The conduction path of the analog switch is switched according to the control level combination, and the output of the digital isolation chip is connected to the input of the RS232 level conversion chip, the differential input / output of the RS485 transceiver chip, or the TTL signal terminal through the conduction path.

[0008] In conjunction with the first aspect, in a fourth implementation of the first aspect of the present invention, S24 includes: When the protocol selection signal is RS232, the enable pin of the RS232 level conversion chip is set to high and the enable pin of the RS485 transceiver chip is set to low; when the protocol selection signal is RS485, the enable pin of the RS232 level conversion chip is set to low and the enable pin of the RS485 transceiver chip is set to high; when the protocol selection signal is TTL, both the enable pins of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip are set to low. The operating state of the corresponding chip is controlled according to the enable pin level of the RS232 level conversion chip and the enable pin level of the RS485 transceiver chip. When the enable pin is high, the corresponding chip is activated to work, and when the enable pin is low, the corresponding chip is turned off.

[0009] In conjunction with the first aspect, in the fifth implementation of the first aspect of the present invention, S3 includes: When data is detected being written to the transmit register of the UART controller, the transmit enable pin and receive enable pin of the RS485 transceiver chip are simultaneously set to high level, thereby enabling the UART controller to read data from the transmit FIFO buffer and output it to the RS485 transceiver chip. The transmit FIFO empty status flag of the UART controller is monitored in real time. When the transmit FIFO empty status flag is set, the single-byte transmission time is calculated according to the baud rate and the single-byte transmission time is delayed. The transmit enable pin and the receive enable pin are simultaneously set to low level to switch to the receive state.

[0010] In conjunction with the first aspect, the sixth implementation of the first aspect of the present invention further includes: S4: Periodically read the status register of the UART controller to obtain the values ​​of the transmit FIFO counter, the receive FIFO counter, and the status of the transmit shift register busy flag. When the values ​​of the transmit FIFO counter and the receive FIFO counter are both zero and the transmit shift register busy flag is zero, disable the transmit interrupt and receive interrupt of the UART controller. S5: Update the control pin level of the analog switch according to the new protocol selection signal, and update the enable pin level of the RS232 level conversion chip and the enable pin level of the RS485 transceiver chip. After completing the protocol switch, re-enable the transmit and receive interrupts of the UART controller.

[0011] In conjunction with the first aspect, in the seventh implementation of the first aspect of the present invention, S5 includes: The current baud rate division coefficient, data frame format parameters, and parity bit configuration parameters of the UART controller are stored in the protocol configuration backup register. According to the new protocol selection signal, the corresponding level combination is output to the control pin of the analog switch and the enable pin level state of the RS232 level conversion chip and the RS485 transceiver chip is updated. After performing a soft reset on the UART controller to clear the internal state machine, the corresponding baud rate division coefficient and data frame format parameters are written to the configuration register of the UART controller according to the new protocol selection signal, and the transmit interrupt and the receive interrupt are re-enabled to complete the protocol switching process.

[0012] In conjunction with the first aspect, the eighth implementation of the first aspect of the present invention further includes: S6: Periodically read the UART error status register of each serial port in the multi-channel serial port, extract the status values ​​of the frame error flag, check error flag and overflow error flag, and record any error flag as a single error event when it is detected. S7: Write the single error event into the sliding window error counter of the corresponding serial port. The sliding window error counter contains a preset number of storage bits. Each time an error event is detected, the corresponding storage bit is set. Each time normal communication occurs, the earliest storage bit is moved out and a new normal status bit is added. S8: Count the number of set storage bits in the sliding window error counter. When the number of set storage bits exceeds a preset threshold, control the analog switch disconnect signal of the corresponding serial port to put the analog switch into the off state and isolate the faulty serial port.

[0013] Secondly, the present invention provides a dynamic switching system for multi-protocol communication interfaces, the dynamic switching system for multi-protocol communication interfaces comprising: The protocol selection module is used to perform GPIO level detection on the first and second groups of jumper pins of the serial communication interface. When a change in the jumper pin level is detected, the protocol switching is triggered to obtain the protocol selection signal. The control module is used to configure the channel enable of the digital isolation chip according to the protocol selection signal and control the selection pin of the analog switch to switch the signal transmission path, and control the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip. The switching module is used to control the transmit / receive direction pins of the RS485 transceiver chip according to the write state of the transmit register of the UART controller, and to switch the level state of the transmit / receive direction pins after a one-byte transmission time delay after transmission is completed.

[0014] The technical solution provided by this invention achieves plug-and-play functionality for RS232, RS485, and TTL communication protocols through a hardware jumper cap-driven protocol identification mechanism. Operators only need to adjust the physical position of the jumper cap to select the protocol. The GPIO detection circuit completes jumper cap status acquisition and protocol mapping within 100ms, eliminating the need for software reconfiguration or system restart, thus reducing the complexity of on-site deployment. Addressing the differences in signal transmission characteristics between different protocols, this invention achieves topology reconstruction between differential and single-ended transmission modes through dynamic channel configuration of a digital isolation chip: under the RS485 protocol, four channels form a differential transmit pair and a differential receive pair; under the RS232 / TTL protocol, only two channels are enabled for single-ended transmission. Combined with signal path switching of an analog switch matrix and selective activation of a level conversion chip, seamless conversion between ±12V single-ended, differential ±7V, and 0-5V single-ended electrical standards is achieved. To address the transmit / receive conflict issue in the RS485 half-duplex protocol, this invention establishes a precise timing control mechanism based on FIFO empty state monitoring. After transmission is completed, the single-byte transmission time is calculated based on the baud rate and a delay is applied to ensure that the stop bit is completely transmitted before switching the transmit / receive direction, effectively preventing frame truncation and bus conflicts. During the protocol switching transition period, this invention detects the transmit FIFO counter, receive FIFO counter, and the busy flag bit of the transmit shift register. Hardware circuit reconfiguration is only performed after confirming that the transmit and receive channels are completely idle, and the current protocol parameters are backed up to registers for rollback recovery in case of switching failure, ensuring data integrity and switching reliability. For the parallel management requirements of multiple serial ports, this invention uses a sliding window error counter to statistically analyze frame errors, checksum errors, and overflow errors. When the error rate exceeds a threshold, the faulty serial port is isolated using an analog switch. A single-channel failure does not affect the normal operation of other channels, achieving distributed fault isolation and high-reliability operation. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram illustrating the steps of the dynamic switching method for multi-protocol communication interfaces in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a dynamic switching system for multi-protocol communication interfaces in an embodiment of the present invention. Detailed Implementation

[0017] This invention provides a method and system for dynamic switching of multi-protocol communication interfaces. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" or "having" and any variations thereof are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0018] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 One embodiment of the dynamic switching method for multi-protocol communication interfaces in this invention includes: S1: GPIO level detection is performed on the first and second groups of jumper pins of the serial communication interface. When a change in the jumper pin level is detected, protocol switching is triggered to obtain the protocol selection signal. S2: Configure the channel enable of the digital isolation chip according to the protocol selection signal and control the selection pin of the analog switch to switch the signal transmission path, and control the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip. S3: Controls the transmit / receive direction pins of the RS485 transceiver chip according to the state written to the transmit register of the UART controller, and switches the level state of the transmit / receive direction pins after a one-byte transmission time delay after transmission is completed.

[0019] In one specific embodiment, the process of performing step S1 may specifically include the following steps: (1) The connection status of the first group of jump cap pins and the second group of jump cap pins in the serial communication interface is acquired by the GPIO detection circuit to obtain the level status of the first group of jump cap pins and the level status of the second group of jump cap pins; (2) When the first group of jump cap levels is low and the second group of jump cap levels is high, the protocol selection signal is determined to be RS485 protocol; (3) When the first group of jump cap levels is high and the second group of jump cap levels is low, the protocol selection signal is determined to be TTL protocol; (4) When both the first group of jump cap level states and the second group of jump cap level states are high, the protocol selection signal is determined to be RS232 protocol.

[0020] Specifically, a protocol determination mechanism based on the physical connection status of jumper caps is established. This mechanism is based on a GPIO detection circuit. It acquires the jumper cap connection status and derives the selected communication protocol type by real-time acquisition of the level status of the first and second sets of jumper cap pins on each serial port interface. Each jumper cap structure contains two pins: one connected to the GPIO input of the main control chip, and the other connected to a reference voltage node. When the jumper cap is shorted, forming a conduction loop across the two pins, the GPIO pin is pulled down to a low level. When the jumper cap is removed or floating, the GPIO pin is held high by a pull-up resistor. Based on this jumper cap status acquisition mechanism, the main control chip sets fixed protocol determination rules and periodically scans the level of the two sets of GPIO pins. If, within a certain cycle, the GPIO detection result corresponding to the first group of jumper pins is low, it indicates that the jumper is shorted, while the GPIO detection result corresponding to the second group of jumper pins is high, indicating that the jumper is in an open state. In this case, according to the set rules, this combination is determined to be the RS485 communication protocol, triggering the activation operation of the differential signal path and the RS485 transceiver. If the first group of jumper pins is high and the second group is low, it indicates that the first group of jumper pins is not connected and the second group is shorted. Based on this, the communication mode is identified as the TTL protocol, thus skipping the level conversion chip and directly enabling the signal channel corresponding to the TTL signal and configuring the corresponding buffer driver. If both groups of jumper pins are high, i.e., both are in an open circuit state, it indicates that no jumper is connected. In this case, according to the default strategy, the current interface is determined to use the RS232 protocol, automatically enabling the MAX3232 level conversion chip corresponding to the serial port and the RS232 single-ended signal path, and completing the relevant configuration of the digital isolation channel. The serial communication protocol identification result is written as a protocol selection signal into the internal protocol configuration register. Meanwhile, the main control chip is set to poll the cap switching status for 100ms, and immediately triggers a protocol reconfiguration interrupt after detecting a change in the level status, so that the communication system can complete the entire identification and initialization process within milliseconds after the cap switching.

[0021] In one specific embodiment, the process of performing step S2 may specifically include the following steps: S21: When the protocol selection signal is RS485 protocol, configure the first and second channels of the digital isolation chip as differential transmit pairs, configure the third and fourth channels of the digital isolation chip as differential receive pairs, and enable the first, second, third and fourth channels at the same time. S22: When the protocol selection signal is RS232 protocol or TTL protocol, enable the first channel of the digital isolation chip as the transmitting line, enable the second channel of the digital isolation chip as the receiving line, and disable the third and fourth channels. S23: Select the signal control analog switch according to the protocol, and connect the output of the digital isolation chip to the input of the RS232 level conversion chip, the differential input / output of the RS485 transceiver chip, or the TTL signal terminal respectively; S24: Select the analog switch's selection pin according to the protocol to switch the signal transmission path, and select the RS232 level conversion chip's enable pin and the RS485 transceiver chip's enable pin according to the protocol.

[0022] Specifically, based on the current protocol selection signal, the operating channels of the digital isolation chip, the analog switches of the signal path, and various level conversion chips are dynamically controlled and configured to achieve physical layer signal switching. When the protocol selection signal is RS485, the first and second channels of the digital isolation chip are configured as the positive and negative terminals of the differential signal transmission, forming a differential transmit pair. Simultaneously, the third and fourth channels are configured as the positive and negative terminals of the receive signal, forming a differential receive pair, thus constructing an RS485 differential transmit / receive path. All four channels must be enabled simultaneously to establish the bidirectional differential channel required by the RS485 protocol and ensure signal isolation and complete transmission. When the protocol selection signal is RS232 or TTL, since these two communication modes use a single-ended transmission structure, only the first and second channels of the digital isolation chip need to be enabled, serving as the transmit and receive lines respectively, connected to the UART transmit and receive pins of the main control chip. The third and fourth channels are disabled to avoid resource waste and potential signal interference. Based on the protocol selection signal, the channel states of the analog switch matrix are controlled, ensuring that the outputs of the digital isolation chip are connected to the correct downstream interface modules. In RS232 protocol mode, the output of the isolation chip needs to be connected to the input of a MAX3232-type level converter chip to convert from standard TTL level to ±7.5V single-ended level. In RS485 mode, the four-channel differential output is connected to the A / B differential input / output pins of the MAX3485 transceiver chip to meet bidirectional differential transmission requirements. If the current protocol is TTL, the output of the isolation chip bypasses all level conversion steps and is directly connected to the TTL signal pin of the terminal. A simple drive enhancement is performed through a buffer to ensure signal shaping and sufficient drive current output. Based on the above, the selection pins of the analog switch are synchronously controlled to complete the conduction or cutoff of the actual signal transmission path. Analog switches such as the ADG733 have multiple input / output channel combinations. Their selection pins S0 and S1 are output by the main control chip with logic levels, determining the current conduction path combination. For example, when S0S1 is 00, the RS232 path is selected; 01 selects the RS485 path; and 10 selects the TTL path. The enable states of the RS232 level conversion chip and the RS485 transceiver chip are controlled simultaneously according to the protocol type. In RS232 mode, the EN pin of the MAX3232 is pulled high to activate the charge pump boost circuit, while in other modes it is pulled low to turn off. The RS485 transceiver chip is always in working state in RS485 mode, but in non-RS485 mode, the differential driver and receiver are turned off to prevent bus disturbances.

[0023] In one specific embodiment, S23 includes: (1) Output a combination of control levels to the first and second control pins of the analog switch according to the protocol selection signal. When the protocol selection signal is RS232 protocol, output a combination of double low levels. When the protocol selection signal is RS485 protocol, output a combination of low and high levels. When the protocol selection signal is TTL protocol, output a combination of high and low levels. (2) According to the control level combination switching analog switch conduction path, connect the output of the digital isolation chip to the input of the RS232 level conversion chip, the differential input / output of the RS485 transceiver chip or the TTL signal terminal through the conduction path.

[0024] Specifically, the conduction state of the analog switch is controlled according to the specific type of the protocol selection signal, thereby achieving correct connection between the output of the digital isolation chip and downstream interface modules with different levels. Based on the current protocol selection signal, the main control chip outputs a set of preset level combinations to the first and second control pins of the analog switch array, where each level combination logically corresponds to a specific path conduction scheme. When the protocol selection signal is RS232, a combination of low and low levels is output to the control pins of the analog switch. At this time, the analog switch is in the first channel conduction state, and its internal switching structure connects the transmit output and receive input of the digital isolation chip to the input of the MAX3232 level conversion chip, thereby supporting the conversion of TTL levels to ±7.5V RS232 standard levels. When the protocol selection signal is RS485, the main control chip outputs a low level to the first control pin and a high level to the second control pin, forming a low-high combination. This corresponds to the analog switch entering the second conduction channel. The differential transmit and receive pairs of the digital isolation chip are connected to the A / B ports of the RS485 transceiver MAX3485 through the conduction path, thus closing the differential signal transmit / receive link. If the protocol selection signal is identified as TTL, the main control chip outputs a high level to the first control pin and a low level to the second control pin, thus entering a high-low combination. This corresponds to the analog switch selecting the TTL path. In this case, the output of the digital isolation chip bypasses all level conversion chips and directly connects to the TTL signal terminal of the terminal. A buffer driver provides current boosting and impedance matching to meet the requirements of high-speed single-ended signal transmission.

[0025] In one specific embodiment, S24 includes: (1) When the protocol selection signal is RS232 protocol, set the enable pin of RS232 level conversion chip to high level and set the enable pin of RS485 transceiver chip to low level; when the protocol selection signal is RS485 protocol, set the enable pin of RS232 level conversion chip to low level and set the enable pin of RS485 transceiver chip to high level; when the protocol selection signal is TTL protocol, set both the enable pin of RS232 level conversion chip and the enable pin of RS485 transceiver chip to low level. (2) Control the working state of the corresponding chip according to the enable pin level of the RS232 level conversion chip and the enable pin level of the RS485 transceiver chip. When the enable pin is high, the corresponding chip is activated to work. When the enable pin is low, the corresponding chip is turned off.

[0026] Specifically, when the protocol selection signal is RS232, the main control chip sets the enable pin of the RS232 level conversion chip to a high level by controlling the GPIO output, activating its internal charge pump boost and level conversion circuit, enabling it to convert TTL levels to ±7.5V levels conforming to the EIA-232 standard. Simultaneously, to prevent conflicts caused by parallel connection of different level signals, the enable pin of the RS485 transceiver chip is pulled low, putting the RS485 transceiver chip into a shutdown state. Its internal differential drive and receiver circuits are shut down and in a high-impedance state, thus having no impact on the bus. When the protocol selection signal is RS485, the enable pin of the RS232 chip is pulled low, stopping its internal charge pump and leaving the level output floating, entering a low-power, high-impedance state. At the same time, the enable pin of the RS485 transceiver chip is set high, activating its internal differential transmitter and receiver, providing effective driving capability for the RS485 bus. If the protocol selection signal is TTL protocol, it means that the current communication task does not involve any level standard conversion. Therefore, pull all the enable pins of the RS232 and RS485 chips low to make them both turn off. At this time, the TTL signal will bypass all level conversion modules and be directly output to the signal terminal by the isolation chip through the buffer driver, forming a simple, high-speed, low-loss single-ended signal path.

[0027] In one specific embodiment, the process of performing step S3 may specifically include the following steps: (1) When data is detected being written to the transmit register of the UART controller, the transmit enable pin and receive enable pin of the RS485 transceiver chip are simultaneously set to high level, and the UART controller is started to read data from the transmit FIFO buffer and output it to the RS485 transceiver chip. (2) Monitor the empty status flag of the transmit FIFO of the UART controller in real time. When the empty status flag of the transmit FIFO is set, calculate the single-byte transmission time according to the baud rate and delay the single-byte transmission time. Simultaneously set the transmit enable pin and the receive enable pin to low level to switch to the receive state.

[0028] Specifically, upon detecting the UART controller's initiation of a transmission task, the key control pins of the RS485 transceiver chip are synchronously configured. When the main control system recognizes that data has been written to the UART controller's transmit register by the upper-layer application, indicating that the transmission phase is about to begin, the control logic simultaneously sets the transmit enable pin (DE) and receive enable pin (RE) of the RS485 transceiver chip to high level, thereby switching the transceiver to transmit mode. The internal differential driver starts working, preparing to convert the data level output by the UART controller into the differential signal required by the RS485 bus. After the DE and RE pins are set high, the UART controller begins to read the bytes to be transmitted sequentially from its transmit FIFO buffer and outputs the data byte by byte to the RS485 transceiver, driving the transmission of valid communication content on the differential signal A / B lines. Simultaneously, to ensure a safe switch to receive mode after data transmission is completed without signal interruption or frame truncation due to premature driver release, the transmit FIFO empty status flag (TXE) of the UART controller is continuously monitored in real time. This flag indicates whether there are any data bytes to be transmitted inside the transmit FIFO. When the TXE flag is set, it indicates that all data has been transferred from the transmit FIFO to the shift register inside the UART and has been shifted out, entering the physical transmission stage. After detecting that TXE is set, the transmission duration of a complete byte on the bus is calculated based on the currently configured UART baud rate. The calculation formula is: Single byte transmission time = 10 bits ÷ baud rate (considering the combined duration of the start bit, data bits, parity bit, and stop bit). For example, at a baud rate of 115200bps, the single byte transmission time is approximately 87 microseconds. After TXE is set, a delay period is waited to ensure that the stop bit signal of the last byte is completely transmitted on the bus, thereby avoiding tail signal distortion or frame errors at the receiving end due to premature cancellation of the transmit enable. After the delay, both the DE and RE pins are pulled low simultaneously, causing the RS485 transceiver to exit transmit mode and enter receive mode. The differential driver stops outputting, and the differential receiver starts listening, ready to receive responses or data frames from other bus nodes.

[0029] In one specific embodiment, it further includes: S4: Periodically read the status register of the UART controller to obtain the values ​​of the transmit FIFO counter, receive FIFO counter, and transmit shift register busy flag. When both the transmit and receive FIFO counter values ​​are zero and the transmit shift register busy flag is zero, disable the transmit and receive interrupts of the UART controller. S5: Based on the new protocol selection signal, update the control pin level of the analog switch and update the enable pin level of the RS232 level conversion chip and the enable pin level of the RS485 transceiver chip. After completing the protocol switch, re-enable the transmit and receive interrupts of the UART controller.

[0030] Specifically, to ensure that no data loss, frame truncation, or bus anomalies occur during protocol switching operations in the multi-protocol communication interface, the system does not immediately perform circuit reconfiguration upon receiving a protocol switching request. Instead, it enters a buffer state stabilization determination phase. This phase involves periodically reading the UART controller's internal status register to assess whether the current transceiver channel's operating status meets the safe switching conditions. The main control chip polls the UART controller's status register at a set period, obtaining the values ​​of the transmit FIFO counter, receive FIFO counter, and the busy flag of the transmit shift register. The transmit FIFO counter reflects the amount of data currently awaiting transmission, the receive FIFO counter indicates the number of bytes of received data that have not yet been read, and the busy flag (BUSY) of the transmit shift register indicates whether any bytes are still in transmission. Only when all three conditions are simultaneously met—that is, the transmit FIFO counter is zero, the receive FIFO counter is zero, and the BUSY flag is zero—is the UART controller confirmed to be in an idle state, with no data awaiting transmission, transmission, or reception. At this point, a safe protocol switching is performed. After determining that the UART controller has entered an idle state, the transmit and receive interrupts of the UART controller are disabled to prevent upper-layer applications from continuing to write to or read from the transmit FIFO during protocol switching, ensuring that the hardware and software data paths are completely frozen. Based on the new protocol selection signal, the control pin levels of the analog switch matrix are updated. By adjusting the high-low level combination of the first and second control pins, the signal transmission path corresponding to the new communication protocol is selected, establishing a new conductive connection between the output of the digital isolation chip and the target level conversion module or terminal pin. Simultaneously, the enable pin levels of the RS232 level conversion chip and the RS485 transceiver chip are modified synchronously according to the protocol type. For example, when switching to the RS232 protocol, the EN pin of the RS232 chip is pulled high to activate the boost circuit, and the EN pin of the RS485 chip is pulled low to enter a high-impedance state. If switching to the RS485 protocol, the reverse operation is performed. If switching to the TTL protocol, both chips are pulled low to remain off to avoid level conflicts and unnecessary power consumption. After completing the hardware path and level configuration update, perform a configuration parameter reload operation on the UART controller to ensure that its internal baud rate divider register, data format register, and control register are synchronized according to the current protocol type. This includes ensuring that frame format settings such as data bits, stop bits, and parity bits are consistent with the target protocol to avoid communication errors caused by format mismatch. After all configurations are completed and confirmed to be correct, re-enable the UART controller's transmit and receive interrupts to restore the serial port's normal data transmission and reception capabilities and begin accepting a new round of communication tasks from upper-layer applications.

[0031] In one specific embodiment, S5 includes: (1) Store the current baud rate division coefficient, data frame format parameters and parity bit configuration parameters of the UART controller to the protocol configuration backup register, and output the corresponding level combination to the control pin of the analog switch according to the new protocol selection signal and update the enable pin level status of the RS232 level conversion chip and the RS485 transceiver chip. (2) After performing a soft reset on the UART controller to clear the internal state machine, write the corresponding baud rate division coefficient and data frame format parameters to the configuration register of the UART controller according to the new protocol selection signal, and re-enable the transmit interrupt and receive interrupt to complete the protocol switching process.

[0032] Specifically, before performing the protocol switching operation, the key configuration parameters of the current UART controller are backed up, enabling a quick recovery to the previous normal communication state in case of switching failure or communication anomalies. The baud rate division coefficient, data frame format parameters, and parity bit configuration parameters currently used in the UART controller are written into a preset protocol configuration backup register, forming a snapshot structure, while retaining the control logic identifier corresponding to the current protocol. After completing the configuration snapshot recording, according to the updated protocol selection signal, the corresponding level combination is output to the control pin of the analog switch, thereby switching the conduction signal path. This ensures that the output of the digital isolation chip can correctly connect to the input of the RS232 level converter chip, the differential input / output of the RS485 transceiver chip, or directly to the TTL signal output terminal. Simultaneously, the enable pin states of the RS232 and RS485 level converters are updated synchronously to ensure that only the conversion chip corresponding to the current protocol is active, while other conversion modules are in a high-impedance off state, thus preventing signal conflicts, level interference, or bus drive anomalies caused by simultaneous power-on of multiple level modules. After the signal channel switching and peripheral chip enable status updates are completed, a soft reset operation is performed on the UART controller. This is achieved by writing a reset instruction to the control register, clearing the internal state machine, including clearing residual data from the transmit and receive FIFOs, and resetting the transmit shift register and receive status flags. This ensures that subsequent configuration writes are not affected by residual states. After the reset, new configuration parameters are rewritten to the UART controller registers according to the new protocol type. These include frame structure parameters such as the prescaler, data bit length, number of stop bits, and whether parity is enabled, set according to the baud rate requirements. The timing and enable logic of the parameters are ensured to match after writing. Once all configurations are complete, the UART controller's transmit and receive interrupts are re-enabled, officially starting the communication process under the new protocol mode and preparing to receive new data tasks from upper-layer applications.

[0033] In one specific embodiment, it further includes: S6: Periodically read the UART error status register of each serial port in the multi-channel serial port, extract the status values ​​of the frame error flag, check error flag and overflow error flag, and record any error flag as a single error event when it is detected. S7: Write a single error event to the sliding window error counter of the corresponding serial port. The sliding window error counter contains a preset number of storage bits. Each time an error event is detected, the corresponding storage bit is set. Each time normal communication occurs, the earliest storage bit is moved out and a new normal status bit is added. S8: Count the number of set storage bits in the sliding window error counter. When the number of set storage bits exceeds the preset threshold, control the analog switch disconnect signal of the corresponding serial port to put the analog switch into the off state and isolate the faulty serial port.

[0034] Specifically, the error status registers of the UART controllers corresponding to all serial interfaces are periodically read. The reading period is set to the tens of milliseconds to ensure response speed. In each period, the main control chip sequentially accesses each serial channel and extracts key flag bits related to communication anomalies from its error status register, including the frame error flag (FE), parity error flag (PE), and receive overflow error flag (OE). If any flag bit is detected as set, it indicates that a data format error, parity failure, or receive buffer overload has occurred in the current period. This phenomenon is immediately recorded as a valid single error event and the error accumulation process begins. Each detected error event is written into the sliding window error counter of the corresponding serial port. The counter consists of a fixed number of bit units, such as 8 or 16 bits, with each bit representing the status of a communication event. When an error event occurs, the latest bit in the sliding window is set to "1", indicating an error has occurred. Whenever the serial port successfully completes an error-free communication, the window is shifted to the left and a "0" status bit is added, indicating that the communication in that period was normal. The sliding window forms a binary sequence containing the most recent consecutive communication states, reflecting the current stability trend of the serial port channel and possessing tolerance for intermittent errors. The number of "1" status bits set in the sliding window is periodically counted. When this number exceeds a preset error threshold (e.g., more than 5 bits), it indicates that the serial port channel has frequently experienced anomalies during recent communications, classifying it as a high-error-rate channel. At this point, a fault isolation mechanism is triggered. The main control chip controls the control pin of the analog switch corresponding to the serial port channel, disconnecting its signal path from the digital isolation chip to the external terminal, causing the analog switch to enter the off state, achieving physical-layer serial port isolation.

[0035] The above describes the dynamic switching method for multi-protocol communication interfaces in embodiments of the present invention. The following describes the dynamic switching system for multi-protocol communication interfaces in embodiments of the present invention. Please refer to [link / reference]. Figure 2 One embodiment of the dynamic switching system for multi-protocol communication interfaces in this invention includes: The protocol selection module 201 is used to perform GPIO level detection on the first group of jumper pins and the second group of jumper pins of the serial communication interface. When a change in the jumper pin level is detected, the protocol switching is triggered to obtain the protocol selection signal. Control module 202 is used to configure the channel enable of the digital isolation chip according to the protocol selection signal and control the selection pin of the analog switch to switch the signal transmission path, and control the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip. The switching module 203 is used to control the transmit / receive direction pins of the RS485 transceiver chip according to the state written to the transmit register of the UART controller, and to switch the level state of the transmit / receive direction pins after a one-byte transmission time delay after transmission is completed.

[0036] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0037] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0038] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for dynamically switching multi-protocol communication interfaces, characterized in that, include: S1: GPIO level detection is performed on the first and second groups of jumper pins of the serial communication interface. When a change in the jumper pin level is detected, protocol switching is triggered to obtain the protocol selection signal. S2: Configure the channel enable of the digital isolation chip according to the protocol selection signal and control the selection pin of the analog switch to switch the signal transmission path, and control the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip. S3: Control the transmit / receive direction pin of the RS485 transceiver chip according to the transmit register write state of the UART controller, and switch the level state of the transmit / receive direction pin after a one-byte transmission time delay after transmission is completed.

2. The dynamic switching method for multi-protocol communication interfaces according to claim 1, characterized in that, S1 includes: The connection status of the first group of jumper pins and the second group of jumper pins in the serial communication interface is acquired by the GPIO detection circuit to obtain the level status of the first group of jumper pins and the level status of the second group of jumper pins. When the first group of jump cap levels is low and the second group of jump cap levels is high, the protocol selection signal is determined to be RS485 protocol; When the first group of jump cap levels is high and the second group of jump cap levels is low, the protocol selection signal is determined to be TTL protocol; When both the first group of jump cap level states and the second group of jump cap level states are high, the protocol selection signal is determined to be RS232 protocol.

3. The dynamic switching method for multi-protocol communication interfaces according to claim 1, characterized in that, S2 include: S21: When the protocol selection signal is RS485 protocol, the first and second channels of the digital isolation chip are configured as differential transmit pairs, the third and fourth channels of the digital isolation chip are configured as differential receive pairs, and the first, second, third and fourth channels are enabled. S22: When the protocol selection signal is RS232 protocol or TTL protocol, enable the first channel of the digital isolation chip as a transmitting line, enable the second channel of the digital isolation chip as a receiving line, and disable the third channel and the fourth channel. S23: According to the protocol selection signal, output a control level combination to the first control pin and the second control pin of the analog switch, switch the conduction path of the analog switch, and connect the output of the digital isolation chip to the input of the RS232 level conversion chip, the differential input / output of the RS485 transceiver chip, or the TTL signal terminal through the conduction path respectively. S24: Select the signal control pin of the analog switch to switch the signal transmission path according to the protocol, and select the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip according to the protocol.

4. The dynamic switching method for multi-protocol communication interfaces according to claim 3, characterized in that, S23 includes: According to the protocol selection signal, a combination of control levels is output to the first control pin and the second control pin of the analog switch. When the protocol selection signal is RS232 protocol, a combination of two low levels is output. When the protocol selection signal is RS485 protocol, a combination of low and high levels is output. When the protocol selection signal is TTL protocol, a combination of high and low levels is output. The conduction path of the analog switch is switched according to the control level combination, and the output of the digital isolation chip is connected to the input of the RS232 level conversion chip, the differential input / output of the RS485 transceiver chip, or the TTL signal terminal through the conduction path.

5. The dynamic switching method for multi-protocol communication interfaces according to claim 4, characterized in that, S24 includes: When the protocol selection signal is RS232, the enable pin of the RS232 level conversion chip is set to high and the enable pin of the RS485 transceiver chip is set to low; when the protocol selection signal is RS485, the enable pin of the RS232 level conversion chip is set to low and the enable pin of the RS485 transceiver chip is set to high; when the protocol selection signal is TTL, both the enable pins of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip are set to low. The operating state of the corresponding chip is controlled according to the enable pin level of the RS232 level conversion chip and the enable pin level of the RS485 transceiver chip. When the enable pin is high, the corresponding chip is activated to work, and when the enable pin is low, the corresponding chip is turned off.

6. The dynamic switching method for multi-protocol communication interfaces according to claim 1, characterized in that, S3 includes: When data is detected being written to the transmit register of the UART controller, the transmit enable pin and receive enable pin of the RS485 transceiver chip are simultaneously set to high level, thereby enabling the UART controller to read data from the transmit FIFO buffer and output it to the RS485 transceiver chip. The transmit FIFO empty status flag of the UART controller is monitored in real time. When the transmit FIFO empty status flag is set, the single-byte transmission time is calculated according to the baud rate and the single-byte transmission time is delayed. The transmit enable pin and the receive enable pin are simultaneously set to low level to switch to the receive state.

7. The dynamic switching method for multi-protocol communication interfaces according to claim 6, characterized in that, Also includes: S4: Periodically read the status register of the UART controller to obtain the values ​​of the transmit FIFO counter, the receive FIFO counter, and the status of the transmit shift register busy flag. When the values ​​of the transmit FIFO counter and the receive FIFO counter are both zero and the transmit shift register busy flag is zero, disable the transmit interrupt and receive interrupt of the UART controller. S5: Update the control pin level of the analog switch according to the new protocol selection signal, and update the enable pin level of the RS232 level conversion chip and the enable pin level of the RS485 transceiver chip. After completing the protocol switch, re-enable the transmit and receive interrupts of the UART controller.

8. The dynamic switching method for multi-protocol communication interfaces according to claim 7, characterized in that, S5 include: The current baud rate division coefficient, data frame format parameters, and parity bit configuration parameters of the UART controller are stored in the protocol configuration backup register. According to the new protocol selection signal, the corresponding level combination is output to the control pin of the analog switch and the enable pin level state of the RS232 level conversion chip and the RS485 transceiver chip is updated. After performing a soft reset on the UART controller to clear the internal state machine, the corresponding baud rate division coefficient and data frame format parameters are written to the configuration register of the UART controller according to the new protocol selection signal, and the transmit interrupt and the receive interrupt are re-enabled to complete the protocol switching process.

9. The dynamic switching method for multi-protocol communication interfaces according to claim 8, characterized in that, Also includes: S6: Periodically read the UART error status register of each serial port in the multi-channel serial port, extract the status values ​​of the frame error flag, check error flag and overflow error flag, and record any error flag as a single error event when it is detected. S7: Write the single error event into the sliding window error counter of the corresponding serial port. The sliding window error counter contains a preset number of storage bits. Each time an error event is detected, the corresponding storage bit is set. Each time normal communication occurs, the earliest storage bit is moved out and a new normal status bit is added. S8: Count the number of set storage bits in the sliding window error counter. When the number of set storage bits exceeds a preset threshold, control the analog switch disconnect signal of the corresponding serial port to put the analog switch into the off state and isolate the faulty serial port.

10. A dynamic switching system for multi-protocol communication interfaces, characterized in that, A method for dynamically switching a multi-protocol communication interface as described in any one of claims 1-9, comprising: The protocol selection module is used to perform GPIO level detection on the first and second groups of jumper pins of the serial communication interface. When a change in the jumper pin level is detected, the protocol switching is triggered to obtain the protocol selection signal. The control module is used to configure the channel enable of the digital isolation chip according to the protocol selection signal and control the selection pin of the analog switch to switch the signal transmission path, and control the enable pin of the RS232 level conversion chip and the enable pin of the RS485 transceiver chip. The switching module is used to control the transmit / receive direction pins of the RS485 transceiver chip according to the write state of the transmit register of the UART controller, and to switch the level state of the transmit / receive direction pins after a one-byte transmission time delay after transmission is completed.

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