Matrix multiplier operation method and device, graphics processor and storage medium

By identifying the data arrangement of the operation matrix and performing a transpose write operation, the problem of reduced bandwidth when reading untranspose matrices from the tensor core is solved, thus improving the computational efficiency of matrix multiplication operators.

CN122132654APending Publication Date: 2026-06-02广州壁仞智能科技有限公司 +1
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Patent Information

Application Number
CN202610243930.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2026-02-28
Publication Date
2026-06-02

AI Technical Summary

Technical Problem

The tensor core's bandwidth for reading untransposed input block matrices from the General Matrix Main Cache (GMB) decreases, failing to meet computational requirements and resulting in matrix multiplication operator performance falling short of expectations.

Method used

By identifying the data arrangement of the operation matrix, matrices with transposed data arrangement are preferentially input into the GMB, and transpose write operations are performed using the registration register to ensure that the tensor core reads data in transpose read mode.

Benefits of technology

It improves the computational efficiency of matrix multiplication operators, avoids hardware performance defects during non-transpose reads, and ensures that the tensor core maintains full bandwidth data input.

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Abstract

The invention provides an operation method and device of a matrix multiplier, a graphics processor and a storage medium, and relates to the technical field of artificial intelligence, the method comprises the following steps: reading two operation matrixes in a high-bandwidth memory; based on the two operation matrixes, determining a first target input matrix input into a general matrix main cache GMB, and determining the other operation matrix as a second target input matrix; the data arrangement mode of the first target input matrix is a transposition arrangement mode; and writing the first target input matrix and the second target input matrix into a tensor core for matrix multiplication to obtain a target output matrix output by the tensor core. By identifying the data arrangement mode of the two operation matrixes, the first target input matrix of which the data arrangement mode is a transposition arrangement mode is preferentially input into the GMB, so that the hardware performance defect during non-transposition reading is effectively avoided, the tensor core keeps full-bandwidth data input, and the calculation efficiency of a matrix multiplier is remarkably improved.
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