Chip screening methods, apparatus, electronic devices and storage media

Abstract

This application provides a chip screening method, apparatus, electronic device, and storage medium, comprising: acquiring an electrical test dataset, wherein the electrical test dataset contains test data of multiple chips, and the test data of each chip includes multiple electrical parameter values; performing a first screening on the multiple chips based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset to obtain a preliminary qualified chip set; inputting the multiple electrical parameter values ​​of each chip in the preliminary qualified chip set into a pre-trained neural network model, so that the neural network model outputs a correlation evaluation result of each chip, wherein the correlation evaluation result is used to characterize whether the correlation characteristics between the multiple electrical parameter values ​​of each chip meet the characteristics of a good product; and performing a second screening on the preliminary qualified chip set based on the correlation evaluation result to identify and remove potentially defective chips from the preliminary qualified chip set.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip screening method, apparatus, electronic device and storage medium. Background Technology

[0002] In the semiconductor manufacturing industry, electrical performance testing before chips leave the factory is a core step in ensuring the quality and reliability of the final product. This process measures and judges multiple key electrical parameters of the chip according to pre-set specifications. Due to the limitations of the testing technology itself and cost considerations, it is impossible to achieve 100% coverage of all potential defect modes, thus posing a risk of mistakenly classifying defective chips as qualified products and releasing them.

[0003] To address these challenges, the industry commonly employs a statistical analysis-based method for setting test limits: local averaging testing. This method first collects historical test data from multiple batches of chips during the early stages of production. For each electrical parameter under test, a statistically robust mean and robust standard deviation are calculated. Then, based on these statistics, an internal test control limit that is more stringent than the product specification standard is set. In subsequent production testing, if any parameter measurement value of a chip exceeds its corresponding internal control limit, even if the value is still within the range allowed by the product specification standard, the chip will be deemed unqualified. The core of this method lies in utilizing the statistical distribution characteristics of the production data itself to eliminate individuals whose parameter values ​​significantly deviate from the normal range due to common process fluctuations.

[0004] However, existing methods can only make isolated, numerical-based judgments on individual electrical parameters, and are completely unable to identify chips where multiple parameters are normal, but the inherent correlation between these parameters has become abnormal. This type of defect constitutes a quality blind spot in existing testing solutions. Summary of the Invention

[0005] This application provides a chip screening method, apparatus, electronic device, and storage medium to solve the problem in the prior art that can only make isolated, numerical-based judgments on individual electrical parameters, and cannot identify chips where multiple parameters are normal, but the inherent correlation between these parameters has become abnormal.

[0006] In a first aspect, this application provides a chip screening method, including: Obtain an electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values; Based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, the chips are first screened to obtain a preliminary set of qualified chips. The electrical parameter values ​​of each chip in the preliminary qualified chip set are input into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip. The correlation evaluation results are used to characterize whether the correlation characteristics between the multiple electrical parameter values ​​of each chip meet the characteristics of a good product. Based on the correlation assessment results, a second screening is performed on the preliminary qualified chip set to identify and remove potentially defective chips from the preliminary qualified chip set.

[0007] In one possible implementation, obtaining the electrical test dataset includes: For each chip, acquire multiple raw electrical data of that chip; The original electrical data are normalized to obtain multiple electrical parameter values ​​corresponding to the chip. The electrical test dataset is generated based on the electrical parameter values ​​of all chips.

[0008] In one possible implementation, acquiring multiple raw electrical data of the chip includes: Determine the chip type of the chip; Based on the chip type, determine the types of multiple electrical parameters to be collected; Based on the multiple electrical parameter types, multiple raw electrical data are collected.

[0009] In one possible implementation, the method further includes: Obtain a historical chip sample set containing multiple historical chip samples. Each historical chip sample contains multiple electrical parameter values ​​and test result labels for the corresponding historical chip. The historical chip sample set is divided into a training subset, a validation subset, and a test subset; The initial neural network model is iteratively trained using multiple electrical parameter values ​​of each historical chip sample in the training subset as input and the corresponding test result label as supervision signal, so that the initial neural network model learns the correlation features between multiple electrical parameter values ​​of good chips. During iterative training, the learning effect of the initial neural network model on the relevance features is evaluated based on the validation subset. Training stops when the learning effect reaches a preset standard, and a candidate neural network model is obtained. The candidate neural network models are evaluated using the test subset, and the qualified candidate neural network models are used as the pre-trained neural network models.

[0010] In one possible implementation, the second screening of the preliminary qualified chip set based on the correlation assessment results includes: For each chip in the preliminary qualified chip set, the correlation evaluation result of the chip is compared with a preset threshold, wherein the preset threshold is determined based on the correspondence between the correlation evaluation result of historical chip data and the known quality status, in order to ensure that the defective product detection rate and the good product loss rate meet preset requirements; If the correlation assessment result exceeds the preset threshold, the chip is determined to be a potential defective product; Chips identified as potentially defective are removed from the initial set of qualified chips.

[0011] In one possible implementation, the method further includes: After completing the testing of all chips on an entire wafer, an electrical test dataset containing multiple electrical parameter values ​​for each chip is obtained; Based on the electrical test dataset, the first screening and the second screening are performed in batches to obtain the identification results of all potential defective chips on the entire wafer; Based on the identification results, guidance information is generated for removing the potentially defective chips in subsequent packaging stages.

[0012] In one possible implementation, the method further includes: The neural network model is deployed as a decision service that can be invoked in real time; During the chip testing process, after each chip test is completed and multiple electrical parameter values ​​of the chip are obtained, the judgment service is called to perform the second screening and generate the correlation evaluation result corresponding to the chip. Based on the correlation assessment results, the quality test results of the chip are determined.

[0013] Secondly, this application provides a chip screening device, comprising: The acquisition module is used to acquire an electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values; The first screening module is used to perform a first screening of multiple chips based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, so as to obtain a preliminary qualified chip set. The input module is used to input multiple electrical parameter values ​​of each chip in the preliminary qualified chip set into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip, wherein the correlation evaluation results are used to characterize whether the correlation characteristics between multiple electrical parameter values ​​of each chip meet the characteristics of a good product. The second screening module is used to perform a second screening on the preliminary qualified chip set based on the correlation assessment results, so as to identify and remove potential defective chips from the preliminary qualified chip set.

[0014] In one possible implementation, the acquisition module is specifically used for For each chip, acquire multiple raw electrical data of that chip; The original electrical data are normalized to obtain multiple electrical parameter values ​​corresponding to the chip. The electrical test dataset is generated based on the electrical parameter values ​​of all chips.

[0015] In one possible implementation, the acquisition module is further configured to: Determine the chip type of the chip; Based on the chip type, determine the types of multiple electrical parameters to be collected; Based on the multiple electrical parameter types, multiple raw electrical data are collected.

[0016] In one possible implementation, the device further includes a training module for: Obtain a historical chip sample set containing multiple historical chip samples. Each historical chip sample contains multiple electrical parameter values ​​and test result labels for the corresponding historical chip. The historical chip sample set is divided into a training subset, a validation subset, and a test subset; The initial neural network model is iteratively trained using multiple electrical parameter values ​​of each historical chip sample in the training subset as input and the corresponding test result label as supervision signal, so that the initial neural network model learns the correlation features between multiple electrical parameter values ​​of good chips. During iterative training, the learning effect of the initial neural network model on the relevance features is evaluated based on the validation subset. Training stops when the learning effect reaches a preset standard, and a candidate neural network model is obtained. The candidate neural network models are evaluated using the test subset, and the qualified candidate neural network models are used as the pre-trained neural network models.

[0017] In one possible implementation, the second filtering module is specifically used for: For each chip in the preliminary qualified chip set, the correlation evaluation result of the chip is compared with a preset threshold, wherein the preset threshold is determined based on the correspondence between the correlation evaluation result of historical chip data and the known quality status, in order to ensure that the defective product detection rate and the good product loss rate meet preset requirements; If the correlation assessment result exceeds the preset threshold, the chip is determined to be a potential defective product; Chips identified as potentially defective are removed from the initial set of qualified chips.

[0018] In one possible implementation, the device further includes an offline processing module for: After completing the testing of all chips on an entire wafer, an electrical test dataset containing multiple electrical parameter values ​​for each chip is obtained; Based on the electrical test dataset, the first screening and the second screening are performed in batches to obtain the identification results of all potential defective chips on the entire wafer; Based on the identification results, guidance information is generated for removing the potentially defective chips in subsequent packaging stages.

[0019] In one possible implementation, the apparatus further includes an online processing module for: The neural network model is deployed as a decision service that can be invoked in real time; During the chip testing process, after each chip test is completed and multiple electrical parameter values ​​of the chip are obtained, the judgment service is called to perform the second screening and generate the correlation evaluation result corresponding to the chip. Based on the correlation assessment results, the quality test results of the chip are determined.

[0020] Thirdly, this application provides an electronic device, including: a processor and a memory, wherein the processor is configured to execute a chip screening program stored in the memory to implement the chip screening method described in any one of the first aspects.

[0021] Fourthly, this application provides a storage medium storing one or more programs that can be executed by one or more processors to implement the chip screening method described in any one aspect.

[0022] Compared with the prior art, the technical solution provided in this application has the following advantages: The method provided in this application first obtains a test dataset containing multiple chips and multiple parameter values, providing a data foundation for subsequent analysis; then, based on the statistical distribution characteristics of each parameter in the dataset, a first screening is performed to initially eliminate chips with outlier parameter values; next, the multidimensional parameter values ​​of each chip in the preliminary qualified chip set are input into a neural network model, which is trained to output an evaluation result characterizing whether the correlation characteristics between multiple parameter values ​​of each chip meet the characteristics of a good product; finally, a second screening is performed based on this correlation evaluation result. This application adds multi-parameter correlation feature analysis and screening based on neural networks (second screening) after the traditional single-parameter screening (first screening), thereby accurately identifying and eliminating chips whose single-parameter values ​​are all normal but whose correlation patterns between parameters are abnormal, fundamentally filling the quality inspection blind spot of the prior art and improving product reliability. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0026] Figure 1 A flowchart illustrating an embodiment of a chip screening method provided in this application; Figure 2 A flowchart illustrating another embodiment of the chip screening method provided in this application; Figure 3 A flowchart illustrating another embodiment of the chip screening method provided in this application; Figure 4 A schematic diagram of the core steps of the second screening provided in the embodiments of this application; Figure 5 The distribution of all test results for Icc (operating current) and Idd (quiescent current); Figure 6 This is a distribution chart of the test results for Icc-Idd good chips; Figure 7 The combined voltage distribution of the BG (bandgap reference) and the frequency distribution of the RC32K (32kHz oscillator) are shown. Figure 8 A block diagram illustrating an embodiment of a chip screening device provided in this application; Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0027] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0028] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0029] To address the technical problem that existing technologies can only make isolated, numerical-based judgments on individual electrical parameters, and cannot identify chips where multiple parameters are normal but the inherent correlation between these parameters is abnormal, this application provides a chip screening method that can identify and eliminate chips where all individual parameter values ​​are normal but the correlation pattern between parameters is abnormal. This fundamentally fills the quality inspection blind spot in existing technologies and improves product reliability.

[0030] Figure 1 This is a flowchart illustrating an embodiment of a chip screening method provided in this application. Figure 1 As shown, the method includes the following steps: Step 101: Obtain the electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values.

[0031] Test data refers to the quantified results of raw electrical signals collected, measured and recorded by the test equipment during the execution of predetermined test items on the chip by the semiconductor automatic test equipment. This includes multiple electrical parameter values ​​(specific measured values ​​used to characterize the specific electrical performance or characteristics of the chip, such as static power consumption current, dynamic operating current, input leakage current, output drive voltage level, etc.).

[0032] Electrical test dataset: refers to a structured data collection formed by summarizing the test data of all the chips under test after the semiconductor wafer testing or finished product testing is completed.

[0033] In this embodiment, after the wafer testing or finished product testing phase is completed, a structured data file containing all the identifiers of the chips under test and their corresponding electrical parameter values ​​is exported from the test system database or log file, forming an electrical test dataset. Each record in this dataset corresponds to an independent chip, and each record contains the specific measured values ​​of multiple electrical parameters obtained by the chip during testing, thereby providing a complete data foundation for subsequent statistical analysis and model inference.

[0034] Step 102: Based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, perform a first screening of multiple chips to obtain a preliminary qualified chip set.

[0035] Statistical distribution characteristics: These refer to the mathematical characteristics used to describe the central tendency and dispersion of a specific electrical parameter after statistical analysis of all chip measurements of that parameter in an electrical test dataset. Examples include robust mean, robust standard deviation, median, and quantiles.

[0036] First screening: refers to the process of setting a dynamic screening limit for each electrical parameter, which is usually more stringent than the product specification limit, based on the statistical distribution characteristics of each parameter, and then determining whether the chip is qualified or not based on this limit.

[0037] Preliminary qualified chip set: refers to the subset of chips that, after the first screening, are determined to have all the electrical parameter values ​​of the inspected chips not exceeding their corresponding screening limits.

[0038] In this embodiment, the PAT (Part Average Test) method is used for the initial screening. Specifically, for each electrical parameter in the electrical test dataset, a robust average and robust standard deviation are calculated for the measured values ​​(i.e., electrical parameter values) of all chips for that electrical parameter. For example, for a parameter called "static current," its robust average and robust standard deviation are calculated based on the static current measurements of all chips in the dataset. Subsequently, the range of "robust average ± N times robust standard deviation" (e.g., N=6) is set as the screening limit for that parameter; each chip in the electrical test dataset is traversed, and it is checked whether the measured value of each electrical parameter falls within the screening limit of the corresponding parameter; chips whose measured values ​​of all parameters do not exceed the limit are classified to form a "preliminary qualified chip set," while chips with any parameter exceeding the limit are recorded or marked. This step mainly screens out chips whose parameter values ​​deviate significantly from the normal statistical distribution range due to common process fluctuations.

[0039] Step 103: Input the multiple electrical parameter values ​​of each chip in the preliminary qualified chip set into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip, wherein the correlation evaluation results are used to characterize whether the correlation characteristics between the multiple electrical parameter values ​​of each chip meet the characteristics of a good product.

[0040] A pre-trained neural network model refers to an artificial intelligence model that has been trained and optimized, with its internal weight parameters fixed, and can be used to predict or classify new input data, such as an ANN (Artificial Neural Network). In one embodiment, the neural network model is preferably a feedforward neural network with at least two hidden layers.

[0041] Correlation assessment result: refers to a scalar value output by the neural network model after it is calculated by its internal network layers for multiple electrical parameter values ​​as input to a single chip. This value is used to quantify the degree of conformity or deviation risk between the joint distribution pattern of multiple electrical parameter values ​​of the chip and the normal multi-parameter correlation pattern learned by the model from historical good chip data.

[0042] In this embodiment of the application, for each chip in the "preliminary qualified chip set" obtained in step 102, the multiple electrical parameter values ​​of the chip are combined into an n-dimensional vector, which is then input into the pre-trained neural network model as an input vector. The neural network model performs calculations based on the input vector and outputs a continuous correlation evaluation result (e.g., a value between 0 and 1). The higher the result value (or the lower, depending on the model definition), the greater the risk that the parameter correlation characteristics of the chip deviate from the good product mode.

[0043] Step 104: Based on the correlation assessment results, a second screening is performed on the preliminary qualified chip set to identify and remove potentially defective chips from the preliminary qualified chip set.

[0044] Second screening: refers to the process of re-evaluating the chips in the "preliminary qualified chip set" based on the correlation assessment results obtained in step 103.

[0045] Potentially defective chips: These are chips that, during the second screening, are deemed to have potential defects and should be removed because their correlation assessment results indicate a high risk.

[0046] In this embodiment, a judgment threshold needs to be determined first. This threshold can be determined by analyzing the distribution of correlation evaluation results of the model on the historical verification dataset. For example, a value can be selected that allows the proportion of actual defective chips (detection rate) and the proportion of actual good chips being falsely judged (false kill rate) to reach an acceptable balance. Then, the correlation evaluation result of each chip in the "preliminary qualified chip set" is compared with the judgment threshold: if the evaluation result of a chip indicates that it is high-risk (e.g., its value exceeds the threshold), then the chip is judged as a "potentially defective chip". Finally, all chips judged as potentially defective are logically or physically removed from the "preliminary qualified chip set" (e.g., marked as failed in the test result record, or excluded in the subsequent packaging and production process), thereby completing the entire screening process.

[0047] The technical solution provided in this application first obtains a test dataset containing multiple chips and multiple parameter values, providing a data foundation for subsequent analysis. Then, based on the statistical distribution characteristics of each parameter in the dataset, a first screening is performed to initially eliminate chips with outlier parameter values. Next, the multidimensional parameter values ​​of each chip in the initially qualified chip set are input into a neural network model. This model is trained to output an evaluation result characterizing whether the correlation characteristics between multiple parameter values ​​of each chip meet the characteristics of a good product. Finally, a second screening is performed based on this correlation evaluation result. This application adds a multi-parameter correlation feature analysis and screening based on neural networks (second screening) after the traditional single-parameter screening (first screening), thereby accurately identifying and eliminating chips where all single-parameter values ​​are normal but the correlation patterns between parameters are abnormal. This fundamentally fills the quality inspection blind spot in existing technologies and improves product reliability.

[0048] Figure 2 A flowchart illustrating an embodiment of another chip screening method provided in this application. Figure 2 The process shown is in Figure 1 Based on the illustrated process, the following steps are included: Step 201: For each chip, acquire multiple raw electrical data of the chip.

[0049] Raw electrical data refers to the raw measurement readings or waveform quantization results obtained directly from the application of test signals or the measurement of chip pins by semiconductor automated test equipment during test procedures, without systematic processing such as standardization or normalization. Examples include unscaled current readings, unconverted voltage code values, or frequency count values.

[0050] In this embodiment of the application, during the wafer testing or final testing stage, a series of predetermined electrical test items are executed sequentially or in parallel on each chip under test by the test program instructions of the automatic test equipment, and the measurement unit of the test equipment directly collects and records the original measurement readings corresponding to each test item. These readings are the original electrical data.

[0051] Step 202: Normalize the original electrical data to obtain multiple electrical parameter values ​​corresponding to the chip.

[0052] Normalization processing: refers to the data processing process that maps the values ​​of raw electrical data to a unified and standardized numerical range through a preset mathematical function, so as to eliminate the inconsistency of data scale caused by differences in dimensions, orders of magnitude or test conditions between different electrical parameters.

[0053] In this embodiment, specific normalization functions are applied to process the multiple raw electrical data acquired for each chip. For example, the arctangent function is used to map the difference between the upper and lower specification limits corresponding to each raw electrical data to a continuous interval from -1 to 1, thereby obtaining multiple electrical parameter values ​​for the chip with uniform scale, suitable for subsequent neural network model processing. The corresponding formula is as follows: .

[0054] Where, y: normalized output value (usually in the range of 0-1); x: original input data (variables that need to be standardized); USL: Upper Specification Limit (the maximum value allowed in quality control); LSL: Lower Specification Limit (the minimum value allowed in quality control); π: pi, used to calculate the output of the arctangent function (range...). π / 2 - π / 2) scaled to 0-1.

[0055] Step 203: Generate the electrical test dataset based on the electrical parameter values ​​of all chips.

[0056] Electrical test dataset: refers to a structured data set that is formed by collecting and integrating multiple electrical parameter values ​​obtained after normalization of all the chips under test. Each record in the set corresponds to a chip, and each record contains the normalized values ​​of all selected electrical parameters of that chip.

[0057] In this embodiment of the application, after completing the acquisition and normalization of the original electrical data of all chips, the identifier of each chip (such as wafer coordinates, chip serial number) is systematically associated with its corresponding multiple normalized electrical parameter values, and stored and organized according to a unified data structure (such as a two-dimensional table or database table) to generate the electrical test dataset that can be used for subsequent statistical analysis and model inference.

[0058] Figure 2 The process described first involves directly acquiring raw electrical data from the testing equipment, ensuring the objectivity and completeness of the data source. Second, normalization processes map raw data of different dimensions and orders of magnitude to a unified range, eliminating the interference of data scale differences on model training and allowing the neural network to focus on the correlation patterns between parameters rather than absolute values. Finally, standardized parameter values ​​from all chips are integrated into a structured dataset, facilitating subsequent batch processing. This not only satisfies the neural network's requirement for consistent input data but also improves data quality and comparability from the source. This ensures that the neural network model can stably and effectively learn and identify the multi-parameter correlation characteristics of good chips in subsequent steps, ultimately providing the necessary guarantee for the reliability and accuracy of the entire screening method.

[0059] Furthermore, in one embodiment, acquiring multiple raw electrical data of the chip may include the following steps: determining the chip type of the chip; determining multiple electrical parameter types to be collected based on the chip type; and collecting multiple raw electrical data based on the multiple electrical parameter types.

[0060] Chip type: refers to the category identifier that classifies chips based on their design specifications, functions, manufacturing processes, or product models, such as microcontrollers, memory chips, and power management chips.

[0061] Electrical parameter type: refers to the type of name that characterizes the specific electrical performance or test items of the chip, such as static current, dynamic operating current, input high-level voltage, output low-level current, etc.

[0062] In this embodiment, for the chip under test, its specific chip type is first determined based on its product identifier or test program configuration. Then, according to the product specifications and test specifications corresponding to that chip type, a set of target parameters that are physically or technologically related are selected from all measurable electrical parameters; these are determined as the types of electrical parameters to be collected. Finally, during the test execution phase, according to the selected electrical parameter types, the corresponding test items are executed sequentially or in parallel by automated testing equipment, thereby collecting multiple raw electrical data corresponding to each chip.

[0063] In a specific example, taking the testing of a wafer of the GM6601 chip as an example, the types of key electrical parameters to be collected are determined according to its product model (chip type), including operating current (Icc), quiescent current (Idd), quiescent power supply current (Iddq), scan test current (IccScan, IddScan), standby current (IccStandby, IddStandby), output high / low level voltage (Voh, Vol), and input high / low level current (Iih, Iil), etc.

[0064] This approach ensures that the collected data closely matches the actual design characteristics and testing requirements of the chip, providing a reasonable and targeted input source for subsequent normalization processing and neural network analysis. It avoids the introduction of irrelevant or redundant parameters, thereby improving the effectiveness and efficiency of the entire screening method from the data source.

[0065] In another embodiment, the pre-trained neural network model can be trained as follows: A historical chip sample set containing multiple historical chip samples is obtained, each historical chip sample containing multiple electrical parameter values ​​and test result labels corresponding to the historical chip; the historical chip sample set is divided into a training subset, a validation subset, and a test subset; the initial neural network model is iteratively trained using the multiple electrical parameter values ​​of each historical chip sample in the training subset as input and the corresponding test result labels as supervision signals, so that the initial neural network model learns the correlation features between the multiple electrical parameter values ​​of good-quality chips; during the iterative training process, the learning effect of the initial neural network model on the correlation features is evaluated based on the validation subset, and training is stopped when the learning effect reaches a preset standard, obtaining a candidate neural network model; the candidate neural network model is evaluated using the test subset, and the qualified candidate neural network model is used as the pre-trained neural network model.

[0066] Historical chip sample set: refers to a data set that was collected and preserved in past production tests, containing a large number of complete chip test records and their final quality judgment results.

[0067] Training subset, validation subset, and test subset: These refer to three independent parts of the historical dataset that are proportionally divided for the development of machine learning models. The training subset is used to directly update model parameters, the validation subset is used to monitor the training process and adjust hyperparameters, and the test subset is used to finally evaluate model performance.

[0068] Test result label: refers to the classification label assigned to the chip after final quality judgment according to the test specifications in the historical production test process. It is usually represented in binary form as "pass" (corresponding to good product) or "fail" (corresponding to defective product), and may also include specific failure code.

[0069] Initial neural network model: refers to a neural network instance that has not been learned before training begins and only has a basic network structure.

[0070] In this embodiment, data containing multi-dimensional electrical parameter values ​​of chips and their corresponding final test results (pass / fail) labels is first extracted from the historical production database to form a historical chip sample set. This dataset is then randomly divided into a training subset, a validation subset, and a test subset according to a preset ratio (e.g., 70%, 15%, 15%). During training, the normalized electrical parameter value vector of each sample in the training subset is used as input, and the corresponding test result label is used as a supervision signal. The weights of the initial neural network model are iteratively optimized through the backpropagation algorithm, allowing it to gradually learn the inherent correlation patterns exhibited by good chips in the multi-dimensional parameter space. Simultaneously, the validation subset is used to monitor the model's generalization ability to unknown data to prevent overfitting. Training is terminated early when the performance reaches a preset accuracy or loss threshold, resulting in a candidate model. Finally, the candidate model is independently evaluated using the test subset, which did not participate in training and tuning. Only when it exhibits stable high recognition performance (e.g., high good product recognition rate and high defective product detection rate) on the test set is it determined to be a pre-trained neural network model that can be put into practical use.

[0071] This approach ensures that the final model can reliably extract and identify health correlation features among multiple parameters from chip test data, thus providing a stable and accurate analytical foundation for subsequent online or offline screening.

[0072] Figure 3 This is a flowchart illustrating another embodiment of the chip screening method provided in this application. Figure 3 The process shown is in Figure 1 Based on the illustrated process, the following steps are included: Step 301: For each chip in the preliminary qualified chip set, compare the correlation evaluation result of the chip with a preset threshold. The preset threshold is determined based on the correspondence between the correlation evaluation result of historical chip data and the known quality status, in order to ensure that the defective product detection rate and the good product loss rate meet preset requirements.

[0073] Preset threshold: refers to a pre-defined numerical boundary point used to divide the correlation assessment results into two categories: "risk acceptable" and "risk unacceptable".

[0074] Defective product detection rate: refers to the proportion of chips that are actually defective among those identified as potentially defective by the model.

[0075] Good product loss rate: refers to the proportion of chips that are actually good products among those chips that are judged as potentially defective by the model (i.e., false positive rate).

[0076] In this embodiment, a preset threshold for judgment must first be determined. This threshold is obtained through optimization based on historical data: A batch of historical chip correlation evaluation results and their known final quality status (good / defective) are collected; the defective product detection rate and good product loss rate corresponding to different candidate thresholds are analyzed; and an optimal value is selected from the candidate thresholds as the preset threshold, based on the optimization principle of achieving a preset quality control target (e.g., maximizing the defective product detection rate while ensuring the good product loss rate is no higher than 0.1%). In application, for each chip in the initial qualified chip set, its correlation evaluation result is numerically compared with the preset threshold determined by optimization.

[0077] Step 302: If the correlation assessment result exceeds the preset threshold, the chip is determined to be a potential defective product.

[0078] In this embodiment, based on the comparison results in step 301, if the correlation assessment result (e.g., risk score) of a chip exceeds a preset threshold, the chip is determined to be a "potentially defective product". This determination means that although all the single-parameter test values ​​of the chip have passed the first screening, the correlation characteristics between its multiple parameters have shown a significant deviation from the normal good product pattern.

[0079] Step 303: Remove chips that are identified as potentially defective from the preliminary qualified chip set.

[0080] In this embodiment, all chips identified as "potentially defective" in step 302 are logically or physically removed from the initial set of qualified chips. For example, the final test results of these chips are marked as "fail" in the test result database, or they are excluded from subsequent packaging and production processes to ensure that they do not flow into later stages or be delivered to customers.

[0081] Figure 3 The process described achieves a quantifiable and controllable engineering balance between defective product detection rate and good product loss rate by using preset thresholds optimized based on historical data. This maximizes the elimination of potentially defective chips while keeping the cost of mistakenly rejecting good products within an acceptable range. This process transforms the continuous risk assessment (correlation assessment results) output by the neural network into clear and reliable production decisions (eliminating potentially defective products). Ultimately, it effectively identifies and intercepts chips that fall outside the traditional single-parameter screening blind spot (chips with normal parameter values ​​but abnormal correlation), significantly improving the final product's quality and reliability.

[0082] This application provides two specific implementation architectures, enabling the above screening method to be flexibly adapted to different production scenarios and efficiency requirements.

[0083] One implementation architecture operates in an offline batch processing mode: after completing the testing of all chips on an entire wafer, an electrical test dataset containing multiple electrical parameter values ​​for each chip is obtained; based on the electrical test dataset, the first screening and the second screening are performed in batches to obtain the identification results of all potentially defective chips on the entire wafer; based on the identification results, guidance information for removing the potentially defective chips in the subsequent packaging stage is generated.

[0084] Guidance information refers to instruction files or data lists generated based on the screening results, which are used to directly drive physical production equipment or indicate the production process, such as packaging diagram files containing the coordinates of defective product chips.

[0085] This embodiment describes a specific offline implementation architecture for the screening method. After the wafer testing phase is completed, the system acquires a complete electrical test dataset of all chips (i.e., dies) on the wafer. Subsequently, on a separate backend server or computing node, based on this dataset, the system performs a first screening (outlier removal based on statistical distribution) and a second screening (correlation feature analysis based on neural networks) in batches and sequentially, thereby obtaining a list of all identified potentially defective chips and their location information across the entire wafer. Finally, based on the identification results, structured guidance information (e.g., a standard-format package map file) is automatically generated. This file can be directly provided to subsequent dicing, sorting, or packaging equipment, enabling it to accurately skip or remove dies marked as potentially defective.

[0086] This offline batch processing architecture decouples time-consuming neural network model calculations from real-time chip testing processes, avoiding the occupation of expensive testing equipment time and thus significantly reducing testing costs. Simultaneously, by centrally processing data from the entire wafer, it can more comprehensively evaluate the statistical characteristics and correlation patterns within a batch, improving the overall consistency of screening. The resulting guidance information can be imported into the production line, achieving a seamless transition from "data analysis" to "physical rejection." Without disrupting the production line's rhythm, it efficiently intercepts abnormally correlated chips that traditional testing cannot cover, improving the return on investment in the wafer packaging process and the final product yield.

[0087] Another implementation architecture operates in an online integration manner: the neural network model is deployed as a decision service that can be invoked in real time; during the chip testing process, when the test of each chip is completed and multiple electrical parameter values ​​of the chip are obtained, the decision service is invoked to perform the second screening and generate the correlation evaluation result corresponding to the chip; based on the correlation evaluation result, the quality test result of the chip is determined.

[0088] Judgment service: refers to a software service module that encapsulates a trained neural network model, has a standard interface, and can be accessed in real time by external systems through network or local calls.

[0089] This embodiment describes another online implementation architecture for the screening method. First, a pre-trained neural network model is engineered and deployed as a judgment service that can be accessed in real-time by the chip automated testing program via function calls or network requests. During the execution of the chip testing process, whenever the testing machine completes the measurement of all predetermined parameters of a chip and obtains its multiple electrical parameter values, the testing program immediately calls the judgment service, sending the current chip's parameter value vector to the service. After receiving the data, the judgment service instantly performs a second screening process (i.e., neural network forward inference calculation) and generates a correlation evaluation result corresponding to the chip, returning it to the testing program. The testing program then, based on the returned evaluation result, determines and updates the final quality test result of the chip in real-time according to preset rules (such as comparison with a threshold) and marks it as "pass" or "fail".

[0090] This online integrated architecture enables real-time and automated quality screening, seamlessly embedding correlation anomaly detection into existing testing processes without interruption or post-processing. It can instantly intercept every identified high-risk chip, preventing it from flowing into subsequent stages, making it particularly suitable for scenarios requiring immediate final judgment, such as post-packaging testing. Because the model is deployed as a service, updates and maintenance do not require modification of the main testing program, improving system flexibility and maintainability. This approach ensures timely screening while achieving "instant detection and immediate handling" of potentially defective chips, further compressing the quality risk window and enhancing the real-time quality control capabilities of the production line.

[0091] To enable those skilled in the art to better understand the technical solution of this application and verify its effectiveness in practical applications, the chip screening method provided in this application is described in detail below using test data of a specific chip model (GM6601). This embodiment demonstrates the complete process from data acquisition, preprocessing, two screenings to final decision-making, and visualizes the correlation characteristics between key parameters. The following description will be based on the process shown in the accompanying drawings of this application (e.g., Figure 1 Overall flowchart Figure 2 , Figure 3 Detailed flowcharts of the sub-processes, and Figure 4 The diagram illustrating the core steps of the second screening process will be used to explain this.

[0092] 1. Data Acquisition and Preprocessing In this embodiment, a GM6601 wafer is used as the object. During the wafer testing phase, a predetermined test program is executed by an automated test device to collect multiple raw electrical data for each die. Based on the design specifications and test requirements of this chip type, the following key electrical parameter types are selected for acquisition: operating current (Icc), quiescent current (Idd), scan test current (IccScan, IddScan), standby current (IccStandby, IddStandby), output high / low level voltage (Voh, Vol), and input high / low level current (Iih, Iil), etc.

[0093] After data acquisition, the raw electrical data for each chip are normalized. Specifically, the arctangent function is used to map the raw measured value of each parameter to a continuous interval [-1, 1] based on the difference between its upper and lower specification limits, resulting in a scaled electrical parameter value. Finally, the identifiers of all chips on the wafer and their normalized electrical parameter values ​​are integrated to generate a structured electrical test dataset.

[0094] 2. First screening: Outlier removal based on statistical distribution After obtaining the electrical test dataset, the PAT method is used for the first screening of each electrical parameter (e.g., Icc) in the dataset. The robust mean (μ) and robust standard deviation (σ) of the parameter's measurements across all chips are calculated, and the range of "μ ± 6σ" is set as the dynamic screening limit for the parameter.

[0095] For each chip in the dataset, check whether the measured values ​​of all its selected electrical parameters fall within their respective screening limits. Chips with all parameters within the limits are grouped together to form a "preliminary qualified chip set". This step aims to eliminate chips whose single parameters deviate significantly from the normal statistical distribution due to obvious common process variations.

[0096] 3. Second screening: Correlation feature analysis based on neural network model The normalized electrical parameter values ​​(such as Icc, Idd, Voh, etc.) of each chip in the preliminary qualified chip set are combined into an n-dimensional vector, which is then used as the input vector and fed into the pre-trained neural network model. Figure 4 This core step is visually demonstrated: For a single chip in the initial qualified chip set, the measurement results of its various electrical parameters are normalized to form an input vector; this vector is input into a trained neural network model; the model calculates and outputs a "risk value" that characterizes the abnormal risk of the correlation between the chip parameters.

[0097] The neural network model is a feedforward neural network with three hidden layers. Its training process is as follows: Recent historical test data of the GM6601 chip is collected. Each data point contains the same electrical parameter vector and the final test result label (Pass=1, Fail=0). The historical dataset is randomly divided into training, validation, and test subsets at a ratio of 70%, 15%, and 15%, respectively. The model is trained using the training subset to learn the intrinsic correlation patterns between multiple parameters of the good chip. The validation subset is used to monitor the training process and prevent overfitting. Finally, the test subset is used to evaluate the model's performance, ensuring it has stable high recognition accuracy and generalization ability.

[0098] After receiving the input vector, the model performs internal calculations and outputs a continuous correlation evaluation result (represented in this embodiment as a "risk value" between 0 and 1). The lower the risk value, the more consistent the parameter combination pattern of the chip is with the good product characteristics learned by the model; the higher the risk value, the greater the risk that its correlation characteristics deviate from the normal pattern.

[0099] 4. Risk assessment and elimination of potential defective products In order to transform the risk value output by the model into a clear screening decision, a decision threshold needs to be determined. Figure 4The latter part illustrates the judgment process: the risk value output by the neural network is compared with a preset threshold. If the risk value is greater than the threshold, the chip is judged as a "potential defective product" and discarded; otherwise, its original qualified judgment (i.e., the "original result") is retained.

[0100] By analyzing the risk values ​​and known quality status of a large number of historical chips, a clear boundary was observed, with normal chips clustered in the low-risk area. Further analysis of the screening effect under different candidate thresholds was conducted, with the core principle of balancing the "defective product detection rate" and the "good product loss rate." For example, when the threshold was set to 0.7, the system could capture 81.25% of potential defective products not detected by the testing procedure, while only misclassifying 0.07% of good products. Therefore, 0.7 was determined as the preferred preset threshold for the current production batch.

[0101] For each chip in the initial qualified chip set, its risk value is compared with a preset threshold of 0.7: if the risk value is higher than 0.7, the chip is determined to be a "potential defective product"; if the risk value is not higher than 0.7, its original qualified status is retained. Finally, all chips determined to be potential defective products are removed from the initial qualified chip set, generating the final qualified chip list.

[0102] 5. Explanation of the Implementation and Selection Logic of the Solution This embodiment can be implemented using the aforementioned "offline batch processing" architecture. After wafer testing is completed, the electrical test dataset of the entire wafer is exported, and the two screening processes described above are performed in batches on the server. Based on the screening results, a packaging map file (guidance information) containing the coordinates of high-risk dies is generated to guide subsequent dicing and packaging processes to physically reject them.

[0103] To illustrate the theoretical basis and screening logic of this application, an analysis of parameter correlation is presented: Taking the two key parameters Icc and Idd as examples, the test results of all chips that passed the first screening show a clear clustering and linear correlation trend in two-dimensional space. The vast majority of good chips fall within specific correlation clustering regions, while a few chips deviating from this correlation trend exhibit abnormal correlations, even if their individual values ​​are within specification limits. The core of this application lies in automatically and quantitatively learning and evaluating the complex correlation patterns between such high-dimensional parameters through a neural network model. The risk value output by the model is essentially a quantification of the degree to which a chip deviates from the "good cluster" in the multi-dimensional parameter space. This allows this method to accurately identify potentially defective chips where all individual parameters are "normal," but the inherent correlation patterns between parameters have become abnormal, thus achieving a deeper level of control over chip quality.

[0104] As can be seen from this comprehensive embodiment, the chip screening method provided in this application, by combining traditional statistical screening with artificial intelligence multi-parameter correlation analysis, significantly reduces the risk of potential defective products flowing downstream and improves the reliability and yield of the final product.

[0105] To facilitate understanding, the principle of this solution is briefly explained below. The core principle of this solution is that the electrical parameters of a functionally and performance-compliant chip are not independent of each other, but are jointly determined by its design, manufacturing process, and materials, thus exhibiting a specific, inherent correlation pattern. This pattern reflects the chip's health status within the normal manufacturing tolerance range.

[0106] Traditional testing methods primarily focus on whether a single parameter exceeds the specification limit or statistical outlier limit (such as the PAT limit), representing a one-dimensional quality assessment. This solution, however, introduces a neural network model to achieve multi-dimensional correlation analysis: Feature learning: The neural network model is trained using multidimensional electrical parameter data of historical good chips, enabling the model to automatically learn from the data and extract stable parameter correlation features common to good chips of this model.

[0107] Feature Comparison and Risk Quantification: For the chip under test, the model analyzes the combination of multiple electrical parameter values ​​and outputs a correlation assessment result (such as a risk score). This result quantifies the degree of deviation between the current chip's parameter correlation pattern and the "good product feature" pattern learned by the model. The greater the deviation, the higher the risk of potential defects (such as latent damage, parameter mismatch, etc.) in the chip, even if all its individual parameter test values ​​fall within the traditional screening limits.

[0108] Figure Description: The following figures use a two-dimensional parameter space as an example to intuitively illustrate the multi-parameter correlation principle upon which this scheme is based: Figure 5 This graph shows the distribution of all test results for Icc (operating current) and Idd (quiescent current). The outer box area represents the upper and lower limits of the parameter based on the product specification (Spec); the inner box area represents the more stringent dynamic screening limit range determined by the Local Average Test (PAT) method. The data points within the inner box represent chips screened using traditional single-parameter screening.

[0109] Figure 6 Distribution of Icc-Idd good chip test results (enlarged rectangular area). This figure focuses on chips that passed the traditional screening (i.e., Figure 5(Data within the inner frame). It can be observed that the data points of most good chips are closely distributed within the trend area (dashed line) reflecting the inherent correlation between parameters. In contrast, a small number of data points that significantly deviate from this main correlation area (within the solid elliptical area in the figure) exhibit abnormal parameter combination patterns, and these have been verified to be mostly potential defective products. This proves that abnormal correlation patterns between parameters are an effective indicator for identifying defective chips within the blind zone of single-parameter screening.

[0110] Figure 7 The graph shows the combined distribution of the BG (bandgap reference) voltage and the RC32K (32kHz oscillator) frequency. This graph illustrates another pair of physically related parameter combinations, whose data points also exhibit a clear linear correlation trend, further validating the prevalence of stable correlation patterns among parameters of good-quality chips.

[0111] The core function of the neural network model in this solution is to automatically and quantitatively learn and identify complex, nonlinear correlation patterns in a high-dimensional parameter space. By learning from historical good product data, the model constructs a "good product feature" space. During the screening process, by calculating the deviation between the data of the chip to be tested and this space (i.e., the correlation evaluation result), it is possible to accurately identify patterns such as… Figure 6 The potential defective products shown have an abnormal association pattern.

[0112] In short, this solution adds an intelligent discrimination layer based on the inherent correlation of multiple parameters to the traditional single-parameter screening, thereby identifying potential defective products with "normal parameter values ​​but abnormal relationships between parameters", filling the blind spot of traditional testing methods.

[0113] Figure 8 This is a block diagram illustrating an embodiment of a chip screening device provided in this application. Figure 8 As shown, the device includes: The acquisition module 81 is used to acquire an electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values; The first screening module 82 is used to perform a first screening of multiple chips based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, so as to obtain a preliminary qualified chip set. The input module 83 is used to input multiple electrical parameter values ​​of each chip in the preliminary qualified chip set into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip, wherein the correlation evaluation results are used to characterize whether the correlation characteristics between multiple electrical parameter values ​​of each chip meet the characteristics of a good product. The second screening module 84 is used to perform a second screening on the preliminary qualified chip set based on the correlation evaluation results, so as to identify and remove potential defective chips from the preliminary qualified chip set.

[0114] In one possible implementation, the acquisition module is specifically used for For each chip, acquire multiple raw electrical data of that chip; The original electrical data are normalized to obtain multiple electrical parameter values ​​corresponding to the chip. The electrical test dataset is generated based on the electrical parameter values ​​of all chips.

[0115] In one possible implementation, the acquisition module is further configured to: Determine the chip type of the chip; Based on the chip type, determine the types of multiple electrical parameters to be collected; Based on the multiple electrical parameter types, multiple raw electrical data are collected.

[0116] In one possible implementation, the device further includes a training module for: Obtain a historical chip sample set containing multiple historical chip samples. Each historical chip sample contains multiple electrical parameter values ​​and test result labels for the corresponding historical chip. The historical chip sample set is divided into a training subset, a validation subset, and a test subset; The initial neural network model is iteratively trained using multiple electrical parameter values ​​of each historical chip sample in the training subset as input and the corresponding test result label as supervision signal, so that the initial neural network model learns the correlation features between multiple electrical parameter values ​​of good chips. During iterative training, the learning effect of the initial neural network model on the relevance features is evaluated based on the validation subset. Training stops when the learning effect reaches a preset standard, and a candidate neural network model is obtained. The candidate neural network models are evaluated using the test subset, and the qualified candidate neural network models are used as the pre-trained neural network models.

[0117] In one possible implementation, the second filtering module is specifically used for: For each chip in the preliminary qualified chip set, the correlation evaluation result of the chip is compared with a preset threshold, wherein the preset threshold is determined based on the correspondence between the correlation evaluation result of historical chip data and the known quality status, in order to ensure that the defective product detection rate and the good product loss rate meet preset requirements; If the correlation assessment result exceeds the preset threshold, the chip is determined to be a potential defective product; Chips identified as potentially defective are removed from the initial set of qualified chips.

[0118] In one possible implementation, the device further includes an offline processing module for: After completing the testing of all chips on an entire wafer, an electrical test dataset containing multiple electrical parameter values ​​for each chip is obtained; Based on the electrical test dataset, the first screening and the second screening are performed in batches to obtain the identification results of all potential defective chips on the entire wafer; Based on the identification results, guidance information is generated for removing the potentially defective chips in subsequent packaging stages.

[0119] In one possible implementation, the apparatus further includes an online processing module for: The neural network model is deployed as a decision service that can be invoked in real time; During the chip testing process, after each chip test is completed and multiple electrical parameter values ​​of the chip are obtained, the judgment service is called to perform the second screening and generate the correlation evaluation result corresponding to the chip. Based on the correlation assessment results, the quality test results of the chip are determined.

[0120] like Figure 9 As shown in the figure, this application provides a device including a processor 111, a communication interface 112, a memory 113, and a communication bus 114, wherein the processor 111, the communication interface 112, and the memory 113 communicate with each other through the communication bus 114. Memory 113 is used to store computer programs; In one embodiment of this application, when the processor 111 executes the program stored in the memory 113, it implements the chip screening method provided in any of the foregoing method embodiments, including: Obtain an electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values; Based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, the chips are first screened to obtain a preliminary set of qualified chips. The electrical parameter values ​​of each chip in the preliminary qualified chip set are input into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip. The correlation evaluation results are used to characterize whether the correlation characteristics between the multiple electrical parameter values ​​of each chip meet the characteristics of a good product. Based on the correlation assessment results, a second screening is performed on the preliminary qualified chip set to identify and remove potentially defective chips from the preliminary qualified chip set.

[0121] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the chip screening method provided in any of the foregoing method embodiments.

[0122] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0123] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Based on this understanding, the above technical solutions, in essence or the parts that contribute to the related technology, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0124] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0125] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A chip screening method, characterized in that, The method includes: Obtain an electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values; Based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, the chips are first screened to obtain a preliminary set of qualified chips. The electrical parameter values ​​of each chip in the preliminary qualified chip set are input into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip. The correlation evaluation results are used to characterize whether the correlation characteristics between the multiple electrical parameter values ​​of each chip meet the characteristics of a good product. Based on the correlation assessment results, a second screening is performed on the preliminary qualified chip set to identify and remove potentially defective chips from the preliminary qualified chip set.

2. The method according to claim 1, characterized in that, The acquisition of the electrical test dataset includes: For each chip, acquire multiple raw electrical data of that chip; The original electrical data are normalized to obtain multiple electrical parameter values ​​corresponding to the chip. The electrical test dataset is generated based on the electrical parameter values ​​of all chips.

3. The method according to claim 2, characterized in that, The acquisition of multiple raw electrical data of the chip includes: Determine the chip type of the chip; Based on the chip type, determine the types of multiple electrical parameters to be collected; Based on the multiple electrical parameter types, multiple raw electrical data are collected.

4. The method according to claim 1, characterized in that, The method further includes: Obtain a historical chip sample set containing multiple historical chip samples. Each historical chip sample contains multiple electrical parameter values ​​and test result labels for the corresponding historical chip. The historical chip sample set is divided into a training subset, a validation subset, and a test subset; The initial neural network model is iteratively trained using multiple electrical parameter values ​​of each historical chip sample in the training subset as input and the corresponding test result label as supervision signal, so that the initial neural network model learns the correlation features between multiple electrical parameter values ​​of good chips. During iterative training, the learning effect of the initial neural network model on the relevance features is evaluated based on the validation subset. Training stops when the learning effect reaches a preset standard, and a candidate neural network model is obtained. The candidate neural network models are evaluated using the test subset, and the qualified candidate neural network models are used as the pre-trained neural network models.

5. The method according to claim 1, characterized in that, The second screening of the preliminary qualified chip set based on the correlation assessment results includes: For each chip in the preliminary qualified chip set, the correlation evaluation result of the chip is compared with a preset threshold, wherein the preset threshold is determined based on the correspondence between the correlation evaluation result of historical chip data and the known quality status, in order to ensure that the defective product detection rate and the good product loss rate meet preset requirements; If the correlation assessment result exceeds the preset threshold, the chip is determined to be a potential defective product; Chips identified as potentially defective are removed from the initial set of qualified chips.

6. The method according to claim 1, characterized in that, The method further includes: After completing the testing of all chips on an entire wafer, an electrical test dataset containing multiple electrical parameter values ​​for each chip is obtained; Based on the electrical test dataset, the first screening and the second screening are performed in batches to obtain the identification results of all potential defective chips on the entire wafer; Based on the identification results, guidance information is generated for removing the potentially defective chips in subsequent packaging stages.

7. The method according to claim 1, characterized in that, The method further includes: The neural network model is deployed as a decision service that can be invoked in real time; During the chip testing process, after each chip test is completed and multiple electrical parameter values ​​of the chip are obtained, the judgment service is called to perform the second screening and generate the correlation evaluation result corresponding to the chip. Based on the correlation assessment results, the quality test results of the chip are determined.

8. A chip screening device, characterized in that, The device includes: The acquisition module is used to acquire an electrical test dataset, which contains test data for multiple chips, and the test data for each chip includes multiple electrical parameter values; The first screening module is used to perform a first screening of multiple chips based on the statistical distribution characteristics of each electrical parameter value in the electrical test dataset, so as to obtain a preliminary qualified chip set. The input module is used to input multiple electrical parameter values ​​of each chip in the preliminary qualified chip set into a pre-trained neural network model, so that the neural network model outputs the correlation evaluation results of each chip, wherein the correlation evaluation results are used to characterize whether the correlation characteristics between multiple electrical parameter values ​​of each chip meet the characteristics of a good product. The second screening module is used to perform a second screening on the preliminary qualified chip set based on the correlation assessment results, so as to identify and remove potential defective chips from the preliminary qualified chip set.

9. An electronic device, characterized in that, include: A processor and a memory, the processor being configured to execute a chip screening program stored in the memory to implement the chip screening method according to any one of claims 1-7.

10. A storage medium, characterized in that, The storage medium stores one or more programs, which can be executed by one or more processors to implement the chip screening method according to any one of claims 1-7.

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