Method for locating electrical anomalies in an electronic component testing process

Abstract

The application discloses a kind of electrical abnormality positioning methods in electronic component testing process, specifically relates to electronic component testing technical field, in conventional test, electrical signal is collected and its chaos degree is calculated, and it is triggered in-depth analysis if it exceeds threshold value.First wide-area scanning generates abnormal probability graph to plan adaptive scanning grid.When scanning in grid, signal chaos degree local increment caused by physical detection is calculated in real time, and it is regulated accordingly: capture transient signal when starting focused in-depth analysis, generate fault behavior dynamic atlas, associated analysis is carried out in combination with atlas and design layout, physical defect is located and diagnostic result is output;The application is fused by closed loop of electrical test and physical analysis, with signal chaos degree and its local increment as intelligent regulation core, the efficient and accurate positioning of dynamic implicit defect is realized.The method can adaptively allocate analysis resources and quickly focus on high-suspected areas, and the final output diagnostic result provides direct basis for failure analysis and process improvement.

Description

Technical Field

[0001] This invention relates to the field of electronic component testing technology, and more specifically, to a method for locating electrical anomalies during electronic component testing. Background Technology

[0002] Electronic components, as the core building blocks of modern electronic systems, directly determine the quality of the entire device through their performance and reliability. As semiconductor technology continues to evolve to the nanoscale, electronic components are developing towards higher integration, higher operating frequencies, and more complex functions. This trend makes the internal electrical behavior of components increasingly complex, their dynamic characteristics more pronounced, and also introduces many new and more subtle failure modes. In production testing and reliability verification, accurately and efficiently identifying and locating the physical defects behind these electrical anomalies has become a key challenge in ensuring the quality of electronic components, conducting failure analysis, and improving processes.

[0003] Currently, a segmented approach is commonly used in the field of electronic component testing and fault analysis within the industry. First, automated testing equipment applies preset test vectors to the component to perform functional and parameter tests, determining whether its electrical characteristics meet specifications. When a failure (such as open circuit, short circuit, parameter drift, or functional error) is detected, the fault analysis phase begins. This phase typically relies on limited information provided by test logs and failure vectors to roughly infer possible failure areas. Then, various physical failure analysis techniques are employed sequentially, such as optical microscopy, infrared thermography, photon emission microscopy, and laser beam induction, to systematically examine the chip layer by layer from the surface inwards, until specific physical defects (such as broken metal wires, gate oxide breakdown, and dielectric voids) are observed using equipment like scanning electron microscopes.

[0004] While the aforementioned methods are widely used, their limitations are becoming increasingly apparent when dealing with the growing number of dynamic latent defects in advanced electronic components. Such defects (e.g., leakage, transient short circuits, or signal integrity degradation triggered only by high-frequency switching, specific temperatures, or load conditions) may be completely hidden during conventional static or low-speed testing, only manifesting as electrical anomalies under complex dynamic operating scenarios. The existing two-stage process—first performing electrical testing and then initiating independent physical analysis—results in sluggish and unidirectional feedback between the two. The physical analysis stage often lacks the deep feature information extracted from dynamic electrical anomalies sufficient to guide precise localization, thus necessitating extensive, "carpet-bombing" scans, which are inefficient and costly. More importantly, static physical analysis scanning modes struggle to reproduce and capture the dynamic operating conditions closely related to defect activation, easily leading to missed detections. Therefore, this invention proposes a method for locating electrical anomalies during electronic component testing to address the aforementioned problems. Summary of the Invention

[0005] To achieve the above objectives, the present invention provides the following technical solution: A method for locating electrical anomalies during the testing of electronic components includes the following steps: In the routine automated testing of electronic components, dynamic electrical signals from multiple electrical ports are acquired in real time and synchronously, and the signal chaos degree is calculated based on the dynamic electrical signals. The signal chaos level is compared with a preset chaos threshold. If the signal chaos level is lower than the preset chaos threshold, the process ends; if the signal chaos level reaches or exceeds the preset chaos threshold, the deep analysis mode is triggered. After entering the deep analysis mode, a preliminary wide-area scan is first performed under the test conditions that cause electrical anomalies. An anomaly probability distribution map is generated based on the scan results, and an adaptive scan grid is planned based on the anomaly probability distribution map. Within the adaptive scanning grid, electronic components are scanned using physical detection methods. Local electrical signals in the vicinity of the scanned point are collected synchronously and in real time, and the local increment of signal chaos under physical detection stimulation is calculated. Based on the local incremental dynamic control scanning process, when the local increment is lower than the increment threshold, the scanning speed is accelerated through the current scanning area; when the local increment reaches or exceeds the increment threshold, the focusing depth analysis is started at the current coordinate point, the physical detection parameters and the working status of electronic components are dynamically adjusted, the transient characteristic signals are captured and the fault behavior dynamic map is generated. By correlating the dynamic fault behavior graph with the design layout information of electronic components, the physical defects that cause electrical abnormalities are located and diagnostic results are output.

[0006] In a preferred embodiment, real-time synchronous acquisition of dynamic electrical signals from multiple electrical ports includes: Multi-channel time-domain synchronous acquisition is performed, and the acquisition timing is synchronized with the test vector of the automated test equipment. During automated testing, based on the applied test vector, transient voltage and transient current waveforms of the power supply port, ground port, and key input / output ports of electronic components are acquired in parallel. The key input / output ports are dynamically determined by the test vector and circuit logic. The acquired transient voltage and current waveforms are preprocessed by bandpass filtering and downsampling to extract effective signal sequences containing nonlinear dynamic characteristics within a preset frequency band.

[0007] In a preferred embodiment, the key input / output ports are dynamically determined by test vectors and circuit logic, including: Based on the currently applied test vectors and the circuit netlist of electronic components, logic simulation is performed to identify internal circuit nodes whose logic states change or are within a preset load range within a test cycle. Map internal circuit nodes to their corresponding physical input / output ports, and identify these ports as critical input / output ports; The set of key input / output ports is dynamically updated as the test vector changes.

[0008] In a preferred embodiment, bandpass filtering and downsampling preprocessing of the acquired transient voltage and current waveforms refers to: Set a preset frequency band range for the bandpass filter, wherein the lower limit of the frequency band range is determined based on the operating clock base frequency of the electronic component, and the upper limit is determined based on the expected resonant frequency caused by the packaging parasitic parameters of the electronic component. The acquired transient voltage and transient current waveforms are filtered using a preset frequency band range; Based on the upper limit frequency of the preset frequency band, the target sampling rate is determined according to the Nyquist sampling theorem, and the filtered waveform data is downsampled. The discrete data sequence obtained after downsampling is used as the effective signal sequence for calculating the chaos index of the signal.

[0009] In a preferred embodiment, the logic for calculating the signal chaos degree is as follows: Extract multiple consecutive subsequences of fixed length from the effective signal sequence in chronological order; For each subsequence, based on the direction of amplitude change of adjacent data point pairs, each data point pair is marked as a change mode of amplitude increase, decrease, or no change, and a preset value is assigned to each change mode to generate an assignment sequence. Count the occurrence frequency of each of the three change patterns in each subsequence, and normalize the occurrence frequency of each of the three change patterns to obtain the normalized frequency. The assignment sequence corresponding to each subsequence is combined with the normalization number to form an extended feature vector; Calculate the Euclidean distance between each pair of extended feature vectors corresponding to all subsequences, and take the average of all Euclidean distances. Use the average value as the signal chaos degree.

[0010] In a preferred embodiment, the planning logic for the adaptive scan grid is as follows: By analyzing the signal strength data acquired in the initial wide-area scan, potential abnormal regions with signal strength exceeding a preset threshold of background noise level are identified, and their abnormality probability is generated based on the relative signal strength value of each potential abnormal region. An anomaly probability distribution map is generated based on the anomaly probability, where the probability values ​​correspond to spatial coordinates; Based on the anomaly probability distribution map and the preset scanning density standard, adaptive scanning of grid areas with different anomaly probabilities is performed according to the corresponding scanning density standard.

[0011] In a preferred embodiment, the local increment of signal chaos is calculated through the following steps: Determine the geometric neighborhood centered on the current scan coordinates of the physical detection method. The geometric neighborhood includes the central coordinates and multiple predefined spatial points around them. When physical detection methods are applied to the current scanning coordinates, local transient electrical signals corresponding to each spatial point in the geometrically adjacent area are simultaneously acquired. For each local transient electrical signal acquired within the geometrically adjacent region, calculate its signal chaos value; The overall chaos value after applying physical detection stimulus is obtained by averaging the signal chaos values ​​corresponding to all spatial points, including the center coordinates, within the geometric neighborhood. The difference between the overall chaos value and the baseline overall chaos value of the geometrically neighboring region when no physical detection stimulus is applied is the local increment of the signal chaos.

[0012] In a preferred embodiment, when the local increment is lower than the increment threshold, accelerating the passage through the current scan region means: Based on the scan density of the current region in the adaptive scan grid, a corresponding initial reference scan speed is determined; Calculate the percentage of local increments that are lower than the increment threshold; Based on the preset linear mapping relationship between the percentage value and the speed adjustment coefficient, the corresponding speed adjustment coefficient is obtained according to the percentage value; Multiply the initial baseline scan speed by the speed adjustment factor to obtain the adjusted accelerated scan speed, and complete the scan of the current area at this speed.

[0013] In a preferred embodiment, the logic for generating the dynamic fault behavior map includes: Start focusing depth analysis at the current coordinate point and pause the scanning motion; According to the preset modulation sequence, at least one parameter of the physical detection method is cyclically adjusted, and under each parameter adjustment, the operating voltage, operating frequency or input signal mode of the electronic components is synchronously modulated. During each synchronization modulation process, at least one type of transient characteristic signal excited by physical detection means is acquired and recorded; The current coordinates, the combination of all adjusted physical detection parameters and the working status of electronic components, and the corresponding acquired transient characteristic signals are correlated and integrated to form a dynamic fault behavior map.

[0014] In a preferred embodiment, association analysis refers to: Multidimensional feature parameters of transient feature signals are extracted from the dynamic spectrum of fault behavior to form the feature vector to be analyzed. The similarity between the feature vector to be analyzed and multiple reference feature vectors in the pre-stored typical physical defect feature signal library is calculated. The similarity calculation adopts the cosine similarity method, which evaluates the directional consistency by calculating the cosine value of the angle between the vectors. Based on the calculated cosine similarity value, the reference feature vector with the highest similarity is matched from the feature signal library, and the physical defect type corresponding to the reference feature vector is determined as the cause of the electrical abnormality. By combining the current coordinates in the fault behavior dynamic map with the design layout information, the precise location of the physical defect can be determined. Generate and output diagnostic results, which include the type of physical defect located, precise location information, and similarity criteria for matching.

[0015] The technical effects and advantages of this invention are as follows: This invention deeply integrates and links conventional automated electrical testing processes with subsequent non-destructive physical analysis and detection processes, constructing an integrated workflow from real-time electrical anomaly detection and intelligent assessment to precise physical defect localization. This method breaks down the information barriers and process silos between electrical testing and physical analysis in traditional segmented processing, enabling dynamic electrical anomalies discovered during testing to be analyzed instantly and in-depth, directly transformed into intelligent instructions guiding physical detection. This deep integration allows the entire localization process to adaptively respond to the actual behavior of the electronic components under test, effectively addressing latent defects that only manifest under dynamic operating conditions. This fundamentally solves the problems of feedback lag, blind analysis, and low efficiency caused by fragmented processes in traditional methods, achieving a synergistic leap forward in both analytical efficiency and localization accuracy.

[0016] This invention introduces signal chaos degree, a dynamic behavioral quantification index, as the core criterion, and establishes a real-time feedback control mechanism based on the local increment of signal chaos degree, endowing the physical detection process with unprecedented intelligence and adaptability. Signal chaos degree can sensitively capture the order degradation and nonlinear distortion in electrical signals that are difficult to detect by traditional amplitude or frequency analysis, thereby identifying potential dynamic anomalies in the early stages. In the depth scanning stage, by calculating the local chaos degree increment caused by physical stimuli in real time, the system can dynamically judge the suspicion level of each scanning point and make autonomous decisions accordingly: quickly passing through low-increase areas to save time, and immediately initiating multi-parameter joint focused depth analysis for high-increase areas. This dynamic control capability, similar to a detective tracking clues, allows valuable analytical resources to be prioritized in the most suspicious areas, greatly optimizing the detection path and resource allocation, and significantly improving the success rate of capturing intermittent and conditionally sensitive defects and the overall positioning speed.

[0017] The final output of this invention is not a simple defect coordinate, but a dynamic fault behavior map containing rich information. Through deep correlation analysis with the design layout database and a typical physical defect feature signal library, the location result is elevated to the level of knowledge discovery. The dynamic fault behavior map not only records the physical location of the defect, but also completely encapsulates the full-spectrum transient feature signals excited at that point under various combinations of physical detection parameters and electrical operating states, forming a unique defect dynamic behavior fingerprint. By performing high-dimensional spatial similarity matching of this fingerprint with a known defect feature library, the specific physical type of the defect, such as gate oxide damage or metal electromigration, can be determined with high confidence. Therefore, the diagnostic results provided by this invention simultaneously include the defect type, precise physical location, and its activation condition characteristics, providing a direct, in-depth, and operable basis for subsequent root cause tracing, process improvement, and even reliability design, realizing an upgrade from passive location to active cognition. Attached Figure Description

[0018] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings; Figure 1 This is a schematic diagram of an electrical anomaly location method during the testing of electronic components according to the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] Reference Figure 1 The following examples were obtained: Example 1: A method for locating electrical anomalies during electronic component testing, comprising the following steps: In the routine automated testing of electronic components, dynamic electrical signals from multiple electrical ports are acquired in real time and synchronously, and the signal chaos degree is calculated based on the dynamic electrical signals. The signal chaos level is compared with a preset chaos threshold. If the signal chaos level is lower than the preset chaos threshold, the process ends; if the signal chaos level reaches or exceeds the preset chaos threshold, the deep analysis mode is triggered. After entering the deep analysis mode, a preliminary wide-area scan is first performed under the test conditions that cause electrical anomalies. An anomaly probability distribution map is generated based on the scan results, and an adaptive scan grid is planned based on the anomaly probability distribution map. Within the adaptive scanning grid, electronic components are scanned using physical detection methods. Local electrical signals in the vicinity of the scanned point are collected synchronously and in real time, and the local increment of signal chaos under physical detection stimulation is calculated. Based on the local incremental dynamic control scanning process, when the local increment is lower than the increment threshold, the scanning speed is accelerated through the current scanning area; when the local increment reaches or exceeds the increment threshold, the focusing depth analysis is started at the current coordinate point, the physical detection parameters and the working status of electronic components are dynamically adjusted, the transient characteristic signals are captured and the fault behavior dynamic map is generated. By correlating the dynamic fault behavior graph with the design layout information of electronic components, the physical defects that cause electrical abnormalities are located and diagnostic results are output.

[0021] In one specific implementation, real-time synchronous acquisition of dynamic electrical signals from multiple electrical ports is achieved through the following process: A timing control logic for multi-channel data acquisition is established, phase-locked with the internal clock reference of the automated test equipment. This ensures that the sampling clock edge of the acquisition operation is synchronized at the nanosecond level with the precise moment when the test equipment applies the test vector, thereby eliminating signal phase misalignment and distortion caused by timing deviations. Specifically, when the test equipment begins driving a preset test vector sequence to the pins of electronic components, its main controller sends a synchronization trigger pulse to the multi-channel data acquisition unit. This pulse simultaneously initializes the analog-to-digital converters of all acquisition channels to start sampling, ensuring that the response signals of each port are captured in parallel and with time-base alignment from the initial instant of test stimulus application.

[0022] Based on the specific test vector content loaded in the current testing phase, the set of electrical ports to be monitored is determined. This set always includes power supply ports that power electronic components and ground ports that serve as a common reference, as well as a set of key signal ports dynamically selected according to circuit logic. After the acquisition process starts, current probes and differential voltage probes arranged on the power supply port path, sampling resistors and monitoring probes arranged on the ground path, and high-impedance differential probes arranged on each key signal port will work simultaneously. These probes will continuously capture the instantaneous voltage and current values ​​that change over time at their respective target ports, forming high-sampling-rate raw transient voltage waveform data and raw transient current waveform data that completely correspond to the test vector execution cycle.

[0023] The raw waveform data acquired from all channels is transmitted in real time for subsequent processing. To avoid data congestion and ensure real-time performance, each acquisition channel is typically equipped with a first-in-first-out (FIFO) buffer, which can temporarily store waveform data blocks within a certain time window. These data blocks are read sequentially, and a pre-configured strategy is executed on each data block. Bandpass filtering and downsampling preprocessing are performed on the acquired transient voltage and current waveforms to extract effective signal sequences containing nonlinear dynamic characteristics within a preset frequency band. The aim is to extract effective signal components that can reflect the internal nonlinear dynamic characteristics of electronic components from the raw data, preparing a clean and feature-rich signal sequence for subsequent chaos analysis.

[0024] For example, when performing functional testing on a high-speed communication chip, the test vector might be a set of high-speed serial data patterns. In this case, the synchronous acquisition process not only captures the ripple and current spikes generated on the power port due to the activity of the core logic switches, as well as noise in the ground loop, but also simultaneously captures the differential voltage waveforms and their corresponding drive current waveforms on multiple high-speed serial transceiver input / output channels. All these cross-port transient signals are assigned a unified and precise timestamp, thus forming a multi-dimensional, time-domain aligned dynamic electrical signal dataset that fully characterizes the chip's overall electrical behavior response under test vector excitation.

[0025] In one specific implementation, the dynamic determination of critical input / output ports is accomplished through a real-time analysis process tightly integrated with the test flow. This process begins in the test preparation phase, first loading the circuit netlist description of the electronic components, such as a register-transfer level design file written in a standard hardware description language, into a dedicated logic simulation environment. Simultaneously, the sequence of test vectors defined by the current test program and about to be applied is also imported into this environment. The logic simulation environment does not perform comprehensive functional verification, but rather initiates a lightweight, rapid simulation process whose sole purpose is to accurately simulate the state transitions of each internal logic node and memory cell in the circuit under test vector excitation during one or more upcoming full test cycles.

[0026] In existing technologies, configuring a logic simulation environment typically begins with installing and running professional electronic design automation (EDA) software tools on a workstation or high-performance computing server. These tools often have a built-in or integrated dedicated digital circuit simulation engine. Users first need to import the complete circuit design of the electronic component under test (ECU) into the simulation project in the form of a gate-level netlist or register-transfer level hardware description language (RTL) source code. They then configure the corresponding standard cell library or intellectual property core timing and functional model files to ensure simulation accuracy. Next, users need to prepare test vector files, which define the sequence of logic values ​​applied to each input port of the device at specific simulation time points. These files are then loaded as simulation stimulus sources using the simulation tool's test platform function or direct scripting. Further configuration includes setting the simulation time range, selecting the internal node signals to be observed, and specifying the waveform database storage format. Finally, by executing simulation commands, the simulation engine calculates the response of each node in the circuit to the stimulus step-by-step based on an event-driven or period-driven computational model, generating waveform files containing the timing changes of all specified signals for designers to perform functional verification and timing analysis.

[0027] After the simulation runs, a detailed node activity report is generated. Dynamic deterministic logic will analyze this report meticulously, focusing on identifying two types of internal nodes: The first type consists of nodes whose logic state transitions from high to low or low to high within a test cycle. This typically indicates a signal flip and is a major source of dynamic power consumption and transient noise. The second type consists of nodes whose logic state does not ultimately flip within the cycle, but whose internal transistors experience intense charging and discharging activity, causing their simulated equivalent load current to exceed a preset threshold, i.e., a preset load activity range. This reflects potential race conditions or high-load paths. These two types of nodes are collectively referred to as high-activity internal nodes.

[0028] Based on the complete interconnect path from internal nodes to final package pins recorded in the circuit netlist, a reverse tracing mapping is performed. For each identified high-activity internal node, the algorithm traces upstream or downstream along its driver or receiver network until it finds the top-level input / output unit directly connected to the external physical pads or ball grid of the chip. The physical electrical port corresponding to this input / output unit is marked as the critical input / output port under the current test vector and added to the monitoring list for this test step.

[0029] For example, when functionally testing an embedded microcontroller, the applied test vector keeps its arithmetic logic unit continuously active. Real-time simulation can identify multiple internal nodes on the adder carry chain and data bus driver nodes as high-activity nodes. These nodes are mapped to specific external data bus pins and clock enable pins. Therefore, the next time the functional test vector is executed, monitoring resources are prioritized for these dynamically identified critical pins, capturing their transient waveforms in real time, rather than mechanically monitoring all input / output ports. Crucially, when the test program switches to the next test item, such as testing the static memory interface, the simulation analysis is re-executed based on the new vector, and the set of critical ports is updated to the physical ports associated with memory address lines and write enable signals, achieving a fully adaptive dynamic configuration of the monitoring targets.

[0030] In one specific implementation, the acquired transient voltage and current waveforms undergo bandpass filtering and downsampling preprocessing, a process that begins with the scientific determination of a preset frequency band range. The determination of the lower limit of the frequency band range relies on the predetermined operating clock frequency of the electronic components, a known parameter directly obtainable from the device datasheet or test specifications. To avoid missing the core switching activity characteristics driven by the clock signal and its low-order harmonics, the lower limit frequency is typically set to half the operating clock frequency, ensuring coverage of the dynamic response corresponding to the basic operating frequency. The determination of the upper limit of the frequency band range involves evaluating the parasitic effects introduced by the package, typically accomplished using existing electronic design automation tools. By establishing a parasitic parameter model including package lead inductance, pad capacitance, and substrate coupling paths, and performing frequency domain simulations, the frequency corresponding to the expected resonant peak dominated by inductance and capacitance on the signal path can be extracted. This resonant frequency is multiplied by an empirical safety factor (e.g., 0.8) as the upper limit, aiming to capture signal integrity issues and high-frequency noise caused by package limitations, while effectively suppressing interference components far exceeding this limit that are of no analytical value.

[0031] After determining the frequency band range, the preprocessing process enters the signal filtering stage. A digital bandpass filter with linear phase characteristics, such as a finite-length unit impulse response filter designed using the window function method or an existing technique that performs the same function, is applied to the raw transient waveform data acquired from each channel. The passband of this filter is precisely configured to the previously calculated lower to upper frequency range, and its stopband attenuation characteristics are optimized to filter out DC bias, power frequency interference, and UHF noise outside the passband to the greatest extent possible. This preserves the signal frequency components that reflect the nonlinear dynamic nature of the device, resulting in pre-filtered waveform data.

[0032] Based on the Nyquist sampling theorem, the filtered waveform is downsampled. The Nyquist sampling theorem, a well-known principle in signal processing, clearly states that to reconstruct a band-limited signal without distortion, the sampling frequency must be at least twice the highest frequency component of the signal. Here, the highest effective frequency component of the filtered signal is the upper limit frequency of the preset frequency band. Therefore, the target sampling rate is determined to be 2.5 to 4 times this upper limit frequency. This range represents an engineering balance between meeting the theorem requirements and reducing the amount of data required for subsequent computation. Based on this target sampling rate, the filtered waveform data with a high sampling rate is resampled. This process is typically implemented using existing mature algorithms that first perform anti-aliasing filtering followed by decimation, ultimately resulting in a discrete-time series with significantly reduced data point density but complete preservation of effective frequency band information.

[0033] Aligning and combining the discrete data sequences from each channel obtained through the downsampling process described above constitutes an effective signal sequence for subsequent calculation of signal chaos. For example, when testing a central processing unit with a 1GHz operating clock, its preset lower frequency limit might be set to 500MHz. Simulation using a package model reveals that the main resonant point of its power supply network is 2.5GHz, so the upper limit can be set to 2.0GHz. Subsequently, the power noise waveform with an original sampling rate of 20GS / s will first pass through a filter with a passband of 500MHz to 2.0GHz, and then, based on the highest 2.0GHz frequency component, the sampling rate will be reduced to, for example, 5.0GS / s or 8.0GS / s, thereby generating an effective signal sequence of moderate length and focused features for processing by the chaos analysis algorithm.

[0034] In one specific implementation, the calculation of signal chaos follows a structured data analysis workflow. This workflow begins with dividing the pre-processed, valid signal sequence into time windows. Specifically, the entire sequence is sequentially divided into multiple temporally continuous and non-overlapping segments, each containing a fixed number of data points; these segments are called subsequences. The choice of subsequence length requires a trade-off between temporal resolution and statistical reliability; for example, it can be determined based on an integer multiple of the signal's fundamental period or an empirical value such as 128 data points, to ensure that each subsequence captures a complete and independent segment of local dynamic behavior. After partitioning, each subsequence serves as the basic unit for subsequent independent analysis.

[0035] For each subsequence, a fine-grained encoding of its internal dynamic characteristics is performed. The core of this step is analyzing the amplitude relationship between every two adjacent data points in the subsequence. Starting with the first data point, the numerical values ​​of each pair of adjacent data points are compared sequentially. Based on the comparison results, each pair of adjacent points is categorized into one of three predefined change patterns: if the amplitude of the latter point is strictly greater than that of the former, it is marked as an upward pattern; if the amplitude of the latter point is strictly less than that of the former, it is marked as a downward pattern; if the amplitudes of the two points are equal or considered equal within a preset small tolerance range, it is marked as an unchanged pattern. For ease of mathematical processing, each change pattern is assigned a unique scalar value, for example, 0 represents upward, 1 represents downward, and 2 represents unchanged. After traversing the entire subsequence, the change patterns of all adjacent point pairs are arranged in chronological order, thus forming an assigned sequence reflecting the local fluctuation trend of the subsequence.

[0036] The variation patterns exhibited by each subsequence are statistically analyzed and normalized. For each subsequence, the total number of occurrences of values ​​representing rising, falling, and stationary patterns in its assigned sequence is counted. Then, these three counts are divided by the total number of adjacent pairs within the subsequence (i.e., the subsequence length minus one), resulting in three ratio values ​​between 0 and 1. These three ratio values ​​represent the probability estimates of whether the signal amplitude exhibits an upward, downward, or stationary trend within the time window of the corresponding subsequence, respectively. Together, they constitute the normalized statistical characteristics of the subsequence's variation pattern.

[0037] Finally, the complete assignment sequence of each subsequence is combined with its corresponding three normalized scaling values ​​to construct a high-dimensional extended feature vector. The first half of this vector consists of the sequential arrangement of all scalar values ​​of the assignment sequence, while the second half is formed by concatenating the three normalized scaling values. The core step in calculating the signal chaos is to calculate the Euclidean distance between each pair of extended feature vectors corresponding to all subsequences. The Euclidean distance is the standard method for measuring the straight-line distance between two points in vector space; it involves taking the square root of the sum of the squares of the differences between the two vectors in each corresponding dimension. After obtaining the distances between all possible vector pairs, the arithmetic mean of these distances is calculated. This average is ultimately defined as the signal chaos of the effective signal sequence; the larger the value, the more significant the differences in the dynamic patterns of the signal within different time periods, the higher the overall disorder and unpredictability of the behavior, and the greater the possibility of potential anomalies.

[0038] For example, when analyzing the effective voltage noise sequence at a microprocessor core power port, it is first divided into hundreds or thousands of subsequences of length 128. For one subsequence, its assigned sequence might be found to contain 70 rising markers, 50 falling markers, and 8 invariant markers, which, after normalization, yield proportions of approximately 0.546, 0.391, and 0.063. Combining the 127-point assigned sequence with these three proportions forms a 130-dimensional extended feature vector. After performing this operation on all subsequences, the pairwise Euclidean distances between all 130-dimensional vectors are calculated and averaged. If the power supply is in a stable and efficient operating state, the noise patterns at different time periods are relatively similar, resulting in a lower average value (i.e., signal chaos). However, if there are intermittent abnormally large current spikes caused by internal defects, the dynamic patterns of different subsequences will differ significantly, leading to a significantly higher calculated signal chaos value.

[0039] In one specific implementation, when the calculated signal chaos level reaches or exceeds a preset chaos threshold, the process is automatically triggered and enters deep analysis mode. The preset chaos threshold is not set arbitrarily, but rather is a reference benchmark obtained by applying statistical methods after performing the aforementioned signal chaos level calculations on a large number of known good electronic components of the same model. Specifically, by collecting the chaos level values ​​of these good products under the same test vector, calculating the mean and standard deviation of their distribution, and setting the threshold to the mean plus three times the standard deviation, this method is based on the control limit principle commonly found in statistics. It aims to identify abnormal behavior exceeding the normal fluctuation range with high confidence, thereby ensuring that deep analysis is only initiated when there is a significant deviation from the normal state, effectively balancing detection sensitivity and analysis efficiency.

[0040] After the deep analysis mode is activated, a rapid, low-resolution preliminary wide-area scan is first performed. This scan employs non-destructive physical detection methods, such as infrared thermal imaging at low optical magnification or photon emission microscopy with large scan steps, to conduct a rapid signal strength survey of the entire chip or a specific functional area under test conditions that induce abnormal electrical behavior. After the scan is completed, the signal strength data from all collected points are analyzed to distinguish between real potential anomalies and background fluctuations. The preset threshold for background noise level is determined using common techniques in image processing and signal detection. For example, by statistically analyzing the histogram distribution of signal intensity in non-peak areas of the entire scan area, the mode or median is taken as the background baseline. Then, the absolute median difference of this baseline is added by a certain multiple (e.g., five times) as the threshold to effectively filter out random noise. Subsequently, all spatial points with signal strength exceeding the threshold are marked as potential anomalous regions. For each such region, the average signal strength of all points within the region is compared with the global average signal strength of the entire scanned image. This ratio is mapped to a range of 0 to 1 using a preset normalization function (e.g., the Sigmoid function). The result is then used as the anomalous probability value for that region, thus realizing the transformation from absolute strength to relative probability.

[0041] Based on the calculated probability values ​​and spatial coordinates of each potential anomaly region, an anomaly probability distribution map is generated. Conceptually, this distribution map is equivalent to a heatmap, where each pixel's location corresponds to its physical coordinates on the chip, and the pixel's grayscale value or color intensity is proportional to the anomaly probability value of the region it represents. This probability distribution map is stored in memory as a digital matrix, providing a direct data foundation for subsequent adaptive scan planning.

[0042] Finally, based on the anomaly probability distribution map and the preset scan density standard, the final adaptive scan grid is planned. The preset scan density standard references the inspection requirements for defects of different confidence levels in industrial testing and is usually defined by the number of scan points per unit area. The core of the planning logic is to map probability values ​​to specific scan densities. For example, several probability intervals can be set: areas with probability values ​​below 0.3 are considered low-probability areas and use the sparsest basic scan density; areas with probability values ​​between 0.3 and 0.7 are medium-probability areas and use medium scan density; areas with probability values ​​above 0.7 are high-probability areas and use the finest scan density. In practice, the algorithm generates a dense scan point matrix in high-probability areas and a sparse dot matrix in low-probability areas. For example, in the failure analysis of a graphics processing unit chip, the initial infrared scan may show several weak hot spots in the power grid area, with an anomaly probability calculated to be between 0.6 and 0.9, while the probability in other areas is below 0.2. The adaptive scanning grid designed accordingly will perform high-precision laser voltage detection scanning at a density of 5 points per square micrometer in these hot spots, while rapidly sweeping across other broad areas at a density of 0.5 points per square micrometer. This concentrates valuable depth analysis time resources on the most suspicious locations, achieving an optimized balance between detection accuracy and efficiency.

[0043] In one specific implementation, the calculation of the local increment of signal chaos is achieved through a fine-grained micro-area response analysis process centered around the physical probe point. This process begins by defining the surrounding environment of the current physical probe's point of action, i.e., determining a geometrically adjacent region centered on its current scan coordinates. This region is typically defined as a regular square or hexagonal grid, with the center coordinates located at the grid's center. It contains multiple predefined spatial points, such as an eight-neighborhood layout with the center point as the origin and a fixed step size as the radius. This means the center point and its adjacent points above, below, left, right, and along the four diagonals together form a local analysis cluster containing nine spatial points. The extent and point density of this geometrically adjacent region can be pre-configured according to the probe's resolution and chip feature size, aiming to cover the main spatial diffusion range of the electrical response that may be triggered by a single-point stimulus.

[0044] When a physical probe, such as a focused laser or ion beam, is precisely applied to the current scanning coordinates to locally stimulate that point, a parallel, high-temporal-resolution electrical monitoring unit is simultaneously activated. This monitoring unit, via a test interface connected to electronic components or utilizing existing monitoring circuitry within the chip, acquires in parallel the local transient electrical signals corresponding to all nine predefined spatial points within the aforementioned geometrically adjacent region. These signals reflect the transient disturbances in carrier activity, potential changes, or current flow near the corresponding locations within the chip under external physical probe stimulation. The acquisition process is strictly synchronized with the application of the physical stimulus, ensuring that the captured data is the transient response directly triggered by the stimulus, rather than background activity.

[0045] For each local transient electrical signal acquired from the geometrically nearest neighbor region, the signal chaos degree calculation logic described in detail above is applied independently. Specifically, after performing the same bandpass filtering and downsampling preprocessing on each signal, a series of standard steps are taken, including subsequence division, encoding change patterns, statistical normalization, constructing extended feature vectors, and calculating the average Euclidean distance, to calculate an independent signal chaos degree value for that point under the current physical detection stimulus. Thus, within the geometrically nearest neighbor region corresponding to the current scanning coordinates, each spatial point obtains a quantified chaos degree value, collectively forming a numerical set characterizing the degree of dynamic behavioral disorder in that micro-region under stimulus.

[0046] The signal chaos values ​​calculated from all nine spatial points, including the center coordinate point, are arithmetically averaged. This average is defined as the overall chaos value of the geometrically adjacent region after the application of the physical probe stimulus. To assess the additional disturbance effect introduced by the physical stimulus, an increment needs to be calculated. This increment is obtained by subtracting the baseline overall chaos value of the same geometrically adjacent region, which was measured or calculated before the application of the physical probe stimulus, from the currently obtained overall chaos value. The baseline value is usually obtained after the start of deep analysis mode, before the formal scan begins, or moment before the stimulus is applied at each scan coordinate point. This is done by acquiring the background electrical signal of the region under the same test conditions but without external physical stimulus, and calculating its overall chaos value using the same method. Finally, the difference between the two overall chaos values ​​is the local increment of the signal chaos value. This increment directly quantifies the disturbance intensity caused by the external physical probe stimulus to the local dynamic behavior of the chip; the larger the increment, the more sensitive the point is to external stimuli, and the more significant the anomaly or vulnerability of its local electrical characteristics may be.

[0047] For example, when scanning a transistor region suspected of having gate oxide leakage using a laser beam, the laser beam is focused on a specific coordinate point above the gate. The nine-grid region centered on this point is defined as the geometrically nearest neighbor. Simultaneously with laser irradiation, the monitoring circuit reads the transient current fluctuations in nine tiny regions corresponding to these nine grid points. After calculating the chaos degree of each fluctuation signal, abnormally high values ​​are found at the center point and the lower right corner. Averaging the chaos degrees of the nine points yields a comprehensive chaos degree of 0.85 under this laser stimulation. The baseline comprehensive chaos degree of this region measured instantaneously before laser irradiation is 0.15. Subtracting the two yields a local increment of 0.70 in signal chaos degree. This significantly higher increment than other scan points strongly suggests that the currently irradiated coordinate point and its immediate vicinity have an electrical defect that is abnormally sensitive to optical excitation, thus marking this location as a high-suspect point requiring further focused depth analysis.

[0048] In one specific implementation, when the calculated local increment of signal chaos is lower than a preset increment threshold, a dynamic adjustment process to accelerate the current scan area is performed. This process begins by determining the initial reference scan speed corresponding to the current scan area. This speed setting directly depends on the scan density level pre-assigned to the area when planning the adaptive scan grid. For example, for areas designated as high-probability regions in the anomaly probability distribution map and thus using fine scan density, the initial reference scan speed is set to a lower value to ensure sufficient point dwell time for high-precision measurement; conversely, for low-probability sparse scan areas, a higher initial reference scan speed is assigned. This correspondence is achieved through a pre-established speed-density lookup table based on engineering experience, ensuring that the base rate of the scan motion matches the preset accuracy requirements of the detection.

[0049] The calculation determines the extent to which the local increment of the current signal's chaos level falls below a preset increment threshold and quantifies it as a percentage. This percentage is calculated by subtracting the calculated local increment from the preset increment threshold, dividing the difference by the preset increment threshold, and finally multiplying the result by 100%. This percentage directly reflects the degree to which the current scan point's response is "normal" or "insensitive"; a larger percentage indicates a smaller actual increment compared to the warning threshold, suggesting a lower probability of anomalies at that point, thus providing stronger quantitative evidence for accelerating the scan.

[0050] Based on a pre-defined linear mapping relationship, the percentage value calculated in the previous step is converted into a specific speed adjustment coefficient. This linear mapping relationship defines a continuous adjustment range between zero and one hundred percent. For example, it can be set that when the percentage value is zero (i.e., the local increment equals the threshold), the speed adjustment coefficient is 1.0, meaning no acceleration; when the percentage value is one hundred percent (i.e., the local increment is zero, far below the threshold), the speed adjustment coefficient reaches its maximum value, such as three.0. In this example, the percentage value and the adjustment coefficient form a straight line from point (zero, 1.0) to point (one hundred, three.0), and the adjustment coefficient corresponding to any intermediate percentage value can be accurately calculated using the linear interpolation formula of this line. This design ensures that the magnitude of acceleration is proportional to the degree of reduction in the probability of anomalies, achieving smoothness and rationality in regulation.

[0051] The initial baseline scan speed set for this region is multiplied by the calculated speed adjustment factor, and the product is the final accelerated scan speed applied to complete the scan of the current region. The actuator controlling the movement of the physical detection platform then receives this speed command and drives the probe to traverse the current low-suspicion area at a higher speed, thereby significantly reducing the total time spent in this area. After completing the scan of this region, the process automatically continues to the location and evaluation of the next scan point. For example, when scanning the power network of a large chip, a certain grid area initially judged to be low-probability is initially set to a baseline scan speed of 100 micrometers per second. When scanning a certain point in this area, the calculated local increment is only 40% of the increment threshold, i.e., 60% below the threshold. According to the linear mapping relationship, 60% below the threshold percentage may correspond to a speed adjustment factor of 2.2. Multiplying the initial speed of 100 micrometers per second by 2.2 yields a new execution speed of 220 micrometers per second. The physical detection platform then quickly completed the scanning of the remaining points in the area at a speed of 220 micrometers per second, without having to perform detailed measurements of each point at the original speed. This allowed the scanning resources to be efficiently concentrated on subsequent, more suspicious, high-incremental areas without any omissions.

[0052] In one specific implementation, when the local increment of signal chaos reaches or exceeds the increment threshold, the process immediately initiates focused depth analysis at the current scan coordinate point. The movement of the physical detection platform is immediately paused, and the scanning beam or probe precisely resides at the coordinate point that triggered the high increment response, ceasing movement to the next grid point. Simultaneously, the original test vector that triggered the electrical anomaly is continuously applied to the electronic component, ensuring the device under test remains in an active state capable of reproducing the fault, and preparing the signal interface and data acquisition channel for subsequent multi-parameter joint debugging.

[0053] The process begins by executing a parameter joint modulation sequence that dynamically replaces parameters according to a predefined correspondence. This sequence predefines various pairing combinations between key parameters of the physical detection method (such as laser power, beam wavelength, and ion beam intensity) and the operating states of electronic components (such as core operating voltage, clock frequency, and digital excitation mode of specific input pins). The analysis process cyclically selects and applies each pairing combination in sequence. For example, the first cycle uses the lower power parameters of the physical detection method while simultaneously modulating the operating voltage of the electronic components to a standard value; the second cycle uses the higher power parameters of the physical detection method while maintaining the operating voltage at the standard value; the third cycle again uses the higher power parameters, but simultaneously modulates the operating voltage to a stress voltage lower than the standard value. Each cycle is a joint stimulus applying a unique combination of internal and external conditions to the measured point, aiming to explore the sensitive excitation conditions of defects from multiple dimensions.

[0054] During each instance of combined stimulation using a specific parameter combination, the high-speed data acquisition unit is synchronously triggered to capture transient characteristic signals elicited by that stimulus. The types of target signals to be acquired are also pre-defined, typically including transient thermal radiation changes in the vicinity of the coordinate point, photon emission intensity in a specific wavelength band, transient current pulses on the power path, or voltage perturbation waveforms at specific internal nodes. These signals are acquired with high precision and converted into digital waveform data, each waveform data being timestamped and uniquely associated with the currently applied parameter combination.

[0055] All the information generated in the above process is structured, correlated, and integrated to form a dynamic fault behavior map of the coordinate point. The core content of this map comprises three parts: the first part is the absolute physical location information of the current scanned coordinate point; the second part is a list of all combinations of physical detection parameters and electronic component operating states applied sequentially; and the third part is the digital waveform data of the acquired transient characteristic signals, strictly corresponding to each combination, along with their extracted key characteristic parameters (such as pulse peak value, rise time, and spectral components). This information is collectively encapsulated in a single data object, which fully characterizes the dynamic response behavior pattern of the potential defect at the current coordinate point to a series of external physical stimuli and changes in internal electrical state.

[0056] For example, when scanning a region in a digital signal processor suspected of having gate oxide weaknesses, a point exhibits extremely high local increments under laser stimulation. In focused depth analysis, the laser beam is fixed at this point and dynamically adjusted sequentially: first, it is irradiated with 5 mW laser power while the chip operates at a core voltage of 1.2 V, acquiring a weak hot spot signal; then, the laser power is increased to 10 mW, maintaining the 1.2 V voltage, acquiring enhanced thermal signals and detectable photon emission; finally, the 10 mW laser power is maintained, but the core voltage is reduced to 1.0 V, acquiring an abnormally strong burst of photon emission and synchronous power current glitches. The fault behavior dynamic graph records this coordinate, as well as the three parameter combinations "5mW laser + 1.2V", "10mW laser + 1.2V", and "10mW laser + 1.0V", and stores all signal waveforms acquired under each combination. This atlas reveals the unique fingerprint of the defect under the condition of "high laser power superimposed with low operating voltage", providing irreproducible key dynamic data for subsequent accurate determination of the defect type.

[0057] In one specific implementation, the correlation analysis process begins with deep data mining and feature extraction of the generated dynamic fault behavior map. From the digital waveform data of the transient characteristic signals corresponding to each synchronous modulation process stored in the map, a series of pre-configured signal processing and feature extraction steps are used to extract multiple numerical parameters that comprehensively characterize the signal morphology, intensity, timing, and spectral characteristics. These parameters typically include peak amplitude, rise time, fall time, pulse width, and root mean square value in the time domain, as well as the amplitude and center frequency of the dominant frequency component obtained after conversion to the frequency domain via Fast Fourier Transform. For a complete focused deep analysis involving multiple modulation cycles, all parameters extracted from each cycle are concatenated in a fixed order to form a high-dimensional numerical array. This array is defined as the feature vector to be analyzed, representing the dynamic behavior of the current fault point. This vector comprehensively reflects the full-spectrum response characteristics of the potential defect under different physical and electrical excitation conditions.

[0058] A pattern matching and similarity assessment process is initiated. The core of this process is comparing the feature vector to be analyzed obtained in the previous step with a pre-built database of typical physical defect feature signals. The feature signal database stores reference feature vectors obtained under similar experimental conditions for various known physical defect types, such as gate oxide breakdown, metal electromigration, open contact holes, and latch-up effects. The comparison method uses cosine similarity calculation, a mathematical method that measures the difference in direction between two vectors. Other similarity comparison algorithms can also be used depending on the specific situation. Specifically, the feature vector to be analyzed is dot-producted with each reference feature vector in the signal database, and then divided by the product of the magnitudes of the two vectors (i.e., the square root of the sum of the squares of all components). The result is a scalar value between -1 and +1. The closer the value is to +1, the more consistent the directions of the two vectors are, meaning the more similar the unknown fault behavior to be analyzed is to the characteristics of known defect types.

[0059] After completing all similarity calculations, the algorithm iterates through the comparison results to find the reference feature vector with the highest cosine similarity value to the feature vector to be analyzed. This reference feature vector is pre-associated with a specific physical defect type in the feature signal library; for example, the highest similarity points to a reference vector in the feature library labeled "interface state proliferation caused by hot carrier injection." Based on this, the analysis logic determines that this physical defect type is the most likely root cause of the electrical anomaly and records the specific cosine similarity value used for this match as a quantitative indicator of the confidence level.

[0060] Finally, the defect type determination result is combined with the precisely recorded current scan coordinates in the fault behavior dynamic map, and the electronic component design layout information database is invoked. Through coordinate mapping, the current coordinates in the scanning device coordinate system are converted into the corresponding specific layer and physical structure on the design layout, such as locating the midpoint of a specific wire on a certain metal layer, or the gate region of a transistor. This obtains the precise location information of the physical defect on the chip's internal microstructure. After integrating all the information, a structured diagnostic report is automatically generated. This report clearly lists the type of physical defect located, its layer and coordinate position on the design layout, and the matching similarity value used as the basis for judgment. For example, the diagnostic result might be stated as: "A defect with a feature highly matching (cosine similarity 0.92) with 'metal electromigration causing local narrowing of wires' was found at coordinates (X: 1024.5 μm, Y: 768.2 μm) on the third metal layer of the chip." This defect is determined to be the main cause of abnormal dynamic current at the power port.

[0061] The above algorithms or formulas are all dimensionless and numerical calculations, and the results are obtained by software simulation based on a large amount of collected data to obtain the most recent real-world results. The preset parameters are set by those skilled in the art according to the actual situation.

[0062] It should be understood that in the various embodiments of this application, the order of the above-mentioned processes does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0063] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0064] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0065] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for locating electrical anomalies during the testing of electronic components, characterized in that, Includes the following steps: In the routine automated testing of electronic components, dynamic electrical signals from multiple electrical ports are acquired in real time and synchronously, and the signal chaos degree is calculated based on the dynamic electrical signals. The signal chaos level is compared with a preset chaos threshold. If the signal chaos level is lower than the preset chaos threshold, the process ends. If the signal chaos level reaches or exceeds the preset chaos threshold, the deep analysis mode is triggered. After entering the deep analysis mode, a preliminary wide-area scan is first performed under the test conditions that cause electrical anomalies. An anomaly probability distribution map is generated based on the scan results, and an adaptive scan grid is planned based on the anomaly probability distribution map. Within the adaptive scanning grid, electronic components are scanned using physical detection methods. Local electrical signals in the vicinity of the scanned point are collected synchronously and in real time, and the local increment of signal chaos under physical detection stimulation is calculated. Based on the local incremental dynamic control scanning process, when the local increment is lower than the increment threshold, the scanning speed is accelerated through the current scanning area; when the local increment reaches or exceeds the increment threshold, the focusing depth analysis is started at the current coordinate point, the physical detection parameters and the working status of electronic components are dynamically adjusted, the transient characteristic signals are captured and the fault behavior dynamic map is generated. By correlating the dynamic fault behavior graph with the design layout information of electronic components, the physical defects that cause electrical abnormalities are located and diagnostic results are output.

2. The method for locating electrical anomalies during the testing of electronic components according to claim 1, characterized in that, Real-time synchronous acquisition of dynamic electrical signals from multiple electrical ports includes: Multi-channel time-domain synchronous acquisition is performed, and the acquisition timing is synchronized with the test vector of the automated test equipment. During automated testing, based on the applied test vector, transient voltage and transient current waveforms of the power supply port, ground port, and key input / output ports of electronic components are acquired in parallel. The acquired transient voltage and current waveforms are preprocessed by bandpass filtering and downsampling to extract effective signal sequences containing nonlinear dynamic characteristics within a preset frequency band.

3. The method for locating electrical anomalies during the testing of electronic components according to claim 2, characterized in that, Key input / output ports are dynamically determined by test vectors and circuit logic, including: Based on the currently applied test vectors and the circuit netlist of electronic components, logic simulation is performed to identify internal circuit nodes whose logic states change or are within a preset load range within a test cycle. Map internal circuit nodes to their corresponding physical input / output ports and identify these ports as critical input / output ports.

4. The method for locating electrical anomalies during the testing of electronic components according to claim 3, characterized in that, Bandpass filtering and downsampling preprocessing of the acquired transient voltage and current waveforms refer to: The acquired transient voltage and transient current waveforms are filtered using a preset frequency band range; Based on the upper limit frequency of the preset frequency band, the target sampling rate is determined according to the Nyquist sampling theorem, and the filtered waveform data is downsampled. The discrete data sequence obtained after downsampling is used as the effective signal sequence for calculating the chaos index of the signal.

5. The method for locating electrical anomalies during the testing of electronic components according to claim 4, characterized in that, The logic for calculating the chaos level of a signal is as follows: Extract multiple consecutive subsequences of fixed length from the effective signal sequence in chronological order; For each subsequence, based on the direction of amplitude change of adjacent data point pairs, each data point pair is marked as a change mode of amplitude increase, decrease, or no change, and a preset value is assigned to each change mode to generate an assignment sequence. Count the occurrence frequency of each of the three change patterns in each subsequence, and normalize the occurrence frequency of each of the three change patterns to obtain the normalized frequency. The assignment sequence corresponding to each subsequence is combined with the normalization number to form an extended feature vector; Calculate the Euclidean distance between each pair of extended feature vectors corresponding to all subsequences, and take the average of all Euclidean distances. Use the average value as the signal chaos degree.

6. The method for locating electrical anomalies during the testing of electronic components according to claim 5, characterized in that, The planning logic for adaptive scan grids is as follows: By analyzing the signal strength data acquired in the initial wide-area scan, potential abnormal regions with signal strength exceeding a preset threshold of background noise level are identified, and their abnormality probability is generated based on the relative signal strength value of each potential abnormal region. An anomaly probability distribution map is generated based on the anomaly probability, where the probability values ​​correspond to spatial coordinates; Based on the anomaly probability distribution map and the preset scanning density standard, adaptive scanning of grid areas with different anomaly probabilities is performed according to the corresponding scanning density standard.

7. The method for locating electrical anomalies during the testing of electronic components according to claim 5, characterized in that, The local increment of signal chaos is calculated through the following steps: Determine the geometric neighborhood centered on the current scan coordinates of the physical detection method. The geometric neighborhood includes the central coordinates and multiple predefined spatial points around them. When physical detection methods are applied to the current scanning coordinates, local transient electrical signals corresponding to each spatial point in the geometrically adjacent area are simultaneously acquired. For each local transient electrical signal acquired within the geometrically adjacent region, calculate its signal chaos value; The overall chaos value after applying physical detection stimulus is obtained by averaging the signal chaos values ​​corresponding to all spatial points, including the center coordinates, within the geometric neighborhood. The difference between the overall chaos value and the baseline overall chaos value of the geometrically neighboring region when no physical detection stimulus is applied is the local increment of the signal chaos.

8. The method for locating electrical anomalies during the testing of electronic components according to claim 5, characterized in that, When the local increment is lower than the increment threshold, accelerating the passage through the current scan region refers to: Based on the scan density of the current region in the adaptive scan grid, a corresponding initial reference scan speed is determined; Calculate the percentage of local increments that are lower than the increment threshold; Based on the preset linear mapping relationship between the percentage value and the speed adjustment coefficient, the corresponding speed adjustment coefficient is obtained according to the percentage value; Multiply the initial baseline scan speed by the speed adjustment factor to obtain the adjusted accelerated scan speed, and complete the scan of the current area at this speed.

9. The method for locating electrical anomalies during the testing of electronic components according to claim 8, characterized in that, The logic for generating the dynamic fault behavior graph includes: Start focusing depth analysis at the current coordinate point and pause the scanning motion; According to the preset modulation sequence, at least one parameter of the physical detection method is cyclically adjusted, and under each parameter adjustment, the operating voltage, operating frequency or input signal mode of the electronic components is synchronously modulated. During each synchronization modulation process, at least one type of transient characteristic signal excited by physical detection means is acquired and recorded; The current coordinates, the combination of all adjusted physical detection parameters and the working status of electronic components, and the corresponding acquired transient characteristic signals are correlated and integrated to form a dynamic fault behavior map.

10. The method for locating electrical anomalies during the testing of electronic components according to claim 9, characterized in that, Association analysis refers to: Multidimensional feature parameters of the transient feature signal are extracted from the dynamic spectrum of fault behavior to form the feature vector to be analyzed. The similarity between the feature vector to be analyzed and multiple reference feature vectors in the pre-stored typical physical defect feature signal library is calculated. The similarity calculation adopts the cosine similarity method, which evaluates the directional consistency by calculating the cosine value of the angle between the vectors. Based on the calculated cosine similarity value, the reference feature vector with the highest similarity is matched from the feature signal library, and the physical defect type corresponding to the reference feature vector is determined as the cause of the electrical abnormality. By combining the current coordinates in the fault behavior dynamic map with the design layout information, the precise location of the physical defect can be determined. Generate and output diagnostic results, which include the type of physical defect located, precise location information, and similarity criteria for matching.

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