A verification method for anti-radiation chip RTL error injection
By extracting the register structured information from the RING BUS module of the radiation-resistant chip, generating an RTL code-level error injection model and performing simulation, the problems of long verification cycle and low efficiency in the existing technology are solved, and rapid fault location and low-cost chip verification are achieved.
CN122133572APending Publication Date: 2026-06-02WHITE BOX (SHANGHAI) MICROELECTRONICS TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WHITE BOX (SHANGHAI) MICROELECTRONICS TECH CO LTD
- Filing Date
- 2026-01-08
- Publication Date
- 2026-06-02
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Figure CN122133572A_ABST
Abstract
This invention relates to a verification method for RTL (Real-Time Level) error injection in radiation-resistant chips, comprising: extracting structured information of registers in the RING BUS module RTL code; using the structured information of the target register as error injection parameters to generate a RING BUS module RTL code-level error injection model; generating a UCLI instruction set corresponding to the RTL hierarchical path based on the RING BUS module RTL code-level error injection model; building a RING BUS module-level verification simulation EDA platform; executing the RING BUS module-level verification simulation EDA platform and the UCLI instruction set; and analyzing the RING BUS module RTL code error injection simulation results based on the scoreboard section and simulation logs of the RING BUS module-level verification simulation EDA platform. This invention can improve fault location efficiency.
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