A wiring method, device and equipment for a quantum chip layout

Abstract

This invention discloses a routing method, apparatus, and device for quantum chip layout, relating to the field of quantum chip design technology. The method includes: mapping the layout to be routed into a gridded two-dimensional array; wherein the values ​​in the gridded two-dimensional array are identifiers of preset graphic information of the quantum chip layout; pairing port identifiers according to their position information to determine port pairs; sorting the port pairs according to their port distances to determine the routing order; and sequentially searching for paths for each port pair in the gridded two-dimensional array according to the routing order to obtain the routing paths for each port pair. This invention, by sequentially searching for paths for each port pair in the gridded two-dimensional array according to the routing order, can determine the routing paths for each pair of ports in the quantum chip layout, achieving automated routing of the quantum chip layout, reducing the workload of relevant personnel, and improving routing efficiency.

Description

Technical Field

[0001] This invention relates to the field of quantum chip design technology, and in particular to a wiring method, apparatus and device for quantum chip layout. Background Technology

[0002] With the development of quantum computing technology, traditional EDA (Electronic Design Automation) software can no longer specifically support quantum chip design and cannot quickly draw complex device structures. In the layout design of quantum chips (such as superconducting quantum chips), after drawing the layout graphics of circuit entities such as components and pads, wiring is required between the connection points of each layout graphic to represent the circuit connection relationship.

[0003] In related technologies, the routing of quantum chip layouts is mostly done manually. This involves repeatedly attempting to stitch together line segments and arcs using basic drawing software like KLayout (a layout design tool). This method is extremely tedious and time-consuming when processing large batches of layout graphics, resulting in very low routing efficiency. Therefore, how to automate the routing of quantum chip layouts, reduce the workload of relevant personnel, and improve routing efficiency is an urgent problem to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a wiring method, apparatus, and device for quantum chip layout, so as to realize automated wiring of quantum chip layout, reduce the workload of relevant personnel, and improve wiring efficiency.

[0005] To address the aforementioned technical problems, this invention provides a wiring method for a quantum chip layout, comprising: The layout to be wired is mapped as a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are the identifiers of each preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics, and obstacle graphics; Based on the location information of each port identifier, the port identifiers are paired to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair; Based on the port distance between each port pair, the port pairs are sorted to determine the wiring order; According to the wiring order, path search is performed on each of the port pairs in the rasterized two-dimensional array to obtain the wiring path of each port pair.

[0006] On the other hand, mapping the layout to be wired into a rasterized two-dimensional array includes: The layout to be routed is divided into regions to obtain each layout region; Based on the area density of each of the aforementioned map regions, the grid size of each map region is determined; wherein, the grid size of the first map region is smaller than the grid size of the second map region, the area density of the first map region is greater than the area density of the second map region, and the first map region and the second map region are any two of the aforementioned map regions; Based on the grid size, each of the map regions is rasterized and modeled to obtain the rasterized two-dimensional array.

[0007] On the other hand, the step of pairing the port identifiers according to the location information of each port identifier to determine each port pair includes: Based on the coordinate positions of each port identifier in the preset coordinate system, the port identifiers are grouped into quadrants to obtain each quadrant group; According to the priority pairing strategy within the group, the port identifiers in each quadrant group are paired to determine each port pair.

[0008] On the other hand, the step of sorting the port pairs according to the port distance of each port pair to determine the wiring order includes: Calculate the cabling difficulty weight for each of the port pairs; wherein, the cabling difficulty weight for the current port pair is a weight calculated based on the port distance of the current port pair and the obstacle density of the cabling area corresponding to the current port pair; the current port pair is any of the port pairs. The port pairs are sorted according to the wiring difficulty weight to determine the wiring order.

[0009] On the other hand, the calculation of the wiring difficulty weight for each of the port pairs includes: The obstacle density is obtained by calculating the quotient of the area occupied by obstacles in the cabling area corresponding to the current port and the cabling area. The cabling difficulty weight of the current port pair is obtained by multiplying the sum of the obstacle density and 1 by the port distance of the current port pair.

[0010] On the other hand, the step of sequentially performing path searches for each of the port pairs in the rasterized two-dimensional array according to the wiring order to obtain the wiring path for each of the port pairs includes: A depth-first search algorithm is used to perform a path search for the current port pair in the rasterized two-dimensional array according to the direction search strategy to obtain the wiring path of the current port pair; wherein, the direction search strategy includes a low obstacle density direction priority strategy; the current port pair is any of the port pairs.

[0011] On the other hand, the step of sequentially performing path searches for each of the port pairs in the rasterized two-dimensional array according to the wiring order to obtain the wiring path for each of the port pairs includes: If the path search for the current port pair fails, and the number of backtracking attempts for the current port pair reaches a preset number of backtracking attempts, a multi-level backtracking strategy is triggered. The multi-level backtracking strategy includes at least one of the following backtracking strategies: backtracking to adjust the wiring order, backtracking to adjust the port pair, and backtracking to adjust the grid precision of the rasterized two-dimensional array. The current port pair is any of the aforementioned port pairs.

[0012] On the other hand, the multi-level backtracking strategy includes: If the first-level backtracking count does not reach the first threshold, the first-level backtracking count is incremented by 1, and the routing order of the port pairs is adjusted. The step of performing path search in the rasterized two-dimensional array for each port pair according to the routing order to obtain the routing path of each port pair is then executed. If the first-level backtracking count reaches the first threshold, the first-level backtracking count is cleared to zero, and if the second-level backtracking count does not reach the second threshold, the second-level backtracking count is incremented by 1, the port pairs are adjusted, and the steps of sorting the port pairs according to the port distance of each port pair and determining the wiring order are executed. When the number of secondary backtracking reaches the second threshold, the number of secondary backtracking is cleared to zero. When the number of tertiary backtracking does not reach the third threshold, the number of tertiary backtracking is incremented by 1. The grid precision is adjusted, and the layout to be routed is mapped to a new gridded two-dimensional array. The step of pairing the port identifiers according to the position information of each port identifier to determine each port pair is executed.

[0013] The present invention also provides a wiring device for a quantum chip layout, comprising: A rasterization module is used to map the layout to be wired into a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are the identifiers of various preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics, and obstacle graphics; A pairing module is used to pair the port identifiers according to the location information of each port identifier to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair; The sorting module is used to sort the port pairs according to the port distance of each port pair to determine the wiring order; The wiring module is used to perform path search in the rasterized two-dimensional array for each port pair in the wiring order to obtain the wiring path for each port pair.

[0014] Furthermore, the present invention also provides a wiring device for a quantum chip layout, comprising: Memory, used to store computer programs; A processor, used to implement the wiring method of the quantum chip layout as described above when executing the computer program.

[0015] The present invention provides a routing method for a quantum chip layout, comprising: mapping the layout to be routed into a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are identifiers of preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics, and obstacle graphics; pairing port identifiers according to the position information of each port identifier to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair; sorting the port pairs according to the port distance of each port pair to determine the routing order; and performing path search in the rasterized two-dimensional array for each port pair according to the routing order to obtain the routing path of each port pair.

[0016] As can be seen, this invention, by sequentially searching for the routing path of each port pair in a gridded two-dimensional array according to the routing sequence, can determine the routing path of each port pair in the quantum chip layout, thereby achieving automated routing of the quantum chip layout, reducing the workload of relevant personnel, and improving routing efficiency. Furthermore, this invention also provides a routing device and apparatus for quantum chip layouts, which also have the aforementioned beneficial effects. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a wiring method for a quantum chip layout provided in an embodiment of the present invention; Figure 2 This is a wiring example diagram of a quantum chip layout provided in an embodiment of the present invention; Figure 3 This is a demonstration of the wiring result of a wiring method for a quantum chip layout provided in an embodiment of the present invention; Figure 4 This is a schematic flowchart of another wiring method for a quantum chip layout provided in an embodiment of the present invention; Figure 5This is a structural block diagram of a wiring device for a quantum chip layout provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of a wiring device for a quantum chip layout provided in an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating a wiring method for a quantum chip layout provided in an embodiment of the present invention. The method may include: Step 101: Map the layout to be wired as a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are the identifiers of each preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics and obstacle graphics.

[0021] It is understood that the layout to be wired in this embodiment can be the layout of a quantum chip that requires wiring (e.g., Figure 4 The layout file (such as the layout of a superconducting quantum chip) can be used in this step. In this step, the layout to be routed can be mapped to a corresponding two-dimensional array (i.e., a rasterized two-dimensional array, or a rasterized data model) through rasterization modeling. The numbers in this two-dimensional array correspond to the graphic information (i.e., preset graphic information) in the layout to be routed, thus realizing the graphic data representation.

[0022] Correspondingly, the preset graphic information in this step can be the graphic information in the pre-set quantum chip layout, so as to realize the mapping between the graphic information in the layout to be wired and the values ​​in the rasterized two-dimensional array; that is, the values ​​in the rasterized two-dimensional array can be preset identifiers (i.e., the identifiers of each preset graphic information).

[0023] Correspondingly, the specific quantity and type of preset graphic information can be set by the designer according to the practical scenario and user needs. For example, preset graphic information may include port graphics (such as pads, capacitors, and resonant cavities), blank graphics, and obstacle graphics (such as air bridges and vias). It may also include other graphics such as routed graphics. For example, in a rasterized two-dimensional array, 0 represents blank, 1 represents obstacle, 2 represents port, and 3 represents routed. This embodiment does not impose any restrictions on this.

[0024] The specific method for mapping the layout to be routed into a rasterized two-dimensional array in this step can be set by the designer according to the practical scenario and user needs. For example, the layout to be routed can be mapped into a rasterized two-dimensional array according to a fixed raster precision; that is, a pre-set fixed-size raster can be used to map the layout to be routed into a corresponding two-dimensional array. Since superconducting quantum bits require nanometer-level precision Josephson junctions and resonant cavity coupling, while peripheral circuits such as control lines and readout lines only require micrometer-level wiring, uniform raster precision will lead to an imbalance between resource redundancy in high-density areas and insufficient precision in low-density areas. For example, it may result in excessive memory consumption under high-precision requirements and high routing failure rate under low precision. Therefore, dynamic rasterization modeling can be used in this step to map the layout to be routed into a rasterized two-dimensional array, so that the raster precision of different areas in the layout to be routed can be different, such as at least two areas having different raster precisions, to achieve adaptive dynamic setting of raster precision; for example, Figure 4 As shown, the automatic routing engine can use dynamic rasterization modeling to map the layout file (i.e., the layout to be routed) into a corresponding two-dimensional array (i.e., a rasterized two-dimensional array). This embodiment does not impose any limitations on this.

[0025] Correspondingly, the specific method of using dynamic rasterization modeling to map the layout to be routed into a rasterized two-dimensional array can be set by the designer. For example, the layout to be routed can be divided into regions (e.g., divided according to a preset region size) to obtain each layout region; the raster size of each layout region can be determined according to the region density; and rasterization modeling can be performed on each layout region according to the raster size to obtain a rasterized two-dimensional array. That is, rasterization modeling is performed on each layout region according to the raster size of each layout region, and the results are combined to obtain the complete two-dimensional array (i.e., rasterized two-dimensional array) corresponding to the layout to be routed. Among these, the smaller the raster size, the higher the raster accuracy. Therefore, the layout regions with higher region density can use smaller raster sizes to improve the raster accuracy of high-density regions. In other words, the raster size of the first layout region is smaller than the raster size of the second layout region, the region density of the first layout region is greater than the region density of the second layout region, and the first and second layout regions are any two layout regions.

[0026] Correspondingly, the calculation method for the area density of the aforementioned layout regions can be set by the designer according to the practical scenario and user needs. The area density of the layout region can be the proportion (ratio of the area of ​​the target graphic to the area of ​​the layout region) or the number of target graphics (such as pads and pins) within the layout region. The specific method for determining the grid size of each layout region based on its area density can be set by the designer. For example, the layout regions can be graded according to their area density, and the preset grid size corresponding to each grade level can be determined as the area density of each layout region. Alternatively, the preset density range of each layout region can be determined first, and the grid size of each layout region can be determined according to the preset grid size corresponding to each preset density range.

[0027] Step 102: Pair the port identifiers according to the location information of each port identifier to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair.

[0028] It is understood that the port identifier in this step can be a value (i.e., an identifier) ​​in the rasterized two-dimensional array corresponding to the port graphic in the layout to be routed. The position information of the port identifier in this step can be the position information of the port identifier in the rasterized two-dimensional array or the position information of the port graphic corresponding to the port identifier in the layout to be routed.

[0029] Correspondingly, such as Figure 2 and Figure 3 As shown, since the selection of the two ports (i.e., port pairs) that need to be wired in the quantum chip layout is related to their location, this step can pair the port identifiers based on the location information of each port identifier to improve the accuracy of the paired port pairs (e.g., ...). Figure 4 The accuracy of the port mapping relationship (in the diagram). Regarding the specific method of pairing port identifiers based on their location information to determine each port pair, designers can set it themselves according to practical scenarios and user needs. For example, port identifiers can be grouped into quadrants based on their coordinates in a preset coordinate system; then, port identifiers within each quadrant group can be paired according to a priority pairing strategy within the group to determine each port pair. In other words, quadrant grouping is based on port coordinates, prioritizing matching ports within the same quadrant. The origin of the preset coordinate system can be the center point of the layout to be routed or a rasterized two-dimensional array, dividing all port identifiers into four quadrant groups to achieve... Figure 3 The port grouping of the quantum chip layout shown; the origin of the preset coordinate system can also be a point on a boundary line (such as the center point) of the layout to be wired or a rasterized two-dimensional array, such as the center point of the upper boundary, to achieve... Figure 2 Port groupings in the quantum chip layout shown.

[0030] Accordingly, the specific method for pairing port identifiers in each quadrant group to determine each port pair, based on the aforementioned intra-group priority pairing strategy, can be set by the designer. For example, port identifiers in each quadrant group can be paired according to preset port pairing rules. If all port identifiers in each quadrant group are successfully paired, all port pairs are determined. If there are unpaired port identifiers, the preset port pairing rules are continued to be applied to pair the unpaired port identifiers (i.e., cross-quadrant pairing) to determine all port pairs. The preset port pairing rules can be pre-defined rules, such as rules based on port type (e.g., pins and pads) and port distance.

[0031] In each port pair, the two port identifiers can be divided into a start port and an end port to further represent the mapping relationship between the start and end ports, facilitating the subsequent determination of the start and end points of each connection that needs to be wired. The port pairs determined in this step can be stored in list form, such as in a port pair allocation list, for convenient later use and display.

[0032] Step 103: Sort the port pairs according to the port distance of each port pair to determine the wiring order.

[0033] In this step, the port distance can be the distance between ports, such as the distance between the two port identifiers in the layout to be routed or the rasterized two-dimensional array. Based on the port distances of each port pair, the port pairs can be sorted to determine the routing order, and then the port pairs can be routed sequentially according to this routing order.

[0034] Correspondingly, the specific method for sorting port pairs based on their port distances to determine the wiring order in this step can be set by the designer according to the practical scenario and user needs. For example, the port pairs can be directly sorted in ascending order according to their port distances to obtain the wiring order, that is, the port pairs with shorter port distances are placed earlier in the wiring order, so that the port pairs with shorter distances are routed first. Alternatively, the wiring difficulty weight of each port pair can be calculated based on its port distance; the port pairs can then be sorted according to the wiring difficulty weight to determine the wiring order. This embodiment does not impose any restrictions on this.

[0035] Accordingly, the specific method for calculating the wiring difficulty weight of each port pair based on the port distance can be set by the designer. For example, the wiring difficulty weight of each port pair can be calculated using only the port distance, with a smaller port distance resulting in a smaller wiring difficulty weight. Alternatively, the wiring difficulty weight of each port pair can be calculated based on the port distance and the obstacle density of the wiring area corresponding to each port pair. In other words, the above process can calculate the wiring difficulty weight of each port pair; where the wiring difficulty weight of the current port pair is the weight calculated based on the port distance of the current port pair and the obstacle density of the wiring area corresponding to the current port pair; the current port pair can be any port pair.

[0036] The process of calculating the routing difficulty weight for each port pair can include calculating the quotient of the area occupied by obstacles in the routing region corresponding to the current port pair and the routing region to obtain the obstacle density; and calculating the product of the sum of the obstacle density and 1 and the port distance of the current port pair to obtain the routing difficulty weight of the current port pair. For example, if the routing region area of ​​a certain port pair is 100μm, of which the qubit array occupies 30μm and the air bridge and via occupy 10μm, then the obstacle density = (30+10) / 100 = 0.4; the routing difficulty weight W = port distance × (1 + obstacle density).

[0037] Correspondingly, when calculating the wiring difficulty weight using the above method, the smaller the wiring difficulty weight, the higher the priority for wiring. The process of sorting port pairs according to the wiring difficulty weight and determining the wiring order can be done by arranging the port pairs in ascending order according to the wiring difficulty weight to obtain the wiring order.

[0038] Step 104: According to the wiring order, perform path search in the rasterized two-dimensional array for each port pair to obtain the wiring path of each port pair.

[0039] Understandably, in this step, a path search can be performed one by one for each port pair in a rasterized two-dimensional array according to a determined routing order to obtain the routing path for each port pair. The specific path search method in this step can be set by the designer based on the practical scenario and user requirements. For example, a depth-first search algorithm or other path search algorithms can be used to avoid obstacle graphics, already routed graphics, and already routed paths (such as the routing paths of port pairs preceding the current port pair in the routing order), and perform a path search for the current port pair in the rasterized two-dimensional array to obtain the routing path for the current port pair.

[0040] Furthermore, in this embodiment, a depth-first search algorithm can be used to perform path searching for the current port pair in a rasterized two-dimensional array according to a direction search strategy to obtain the wiring path for the current port pair. The direction search strategy includes a low-obstacle-density direction priority strategy; the current port pair can be any port pair. For example, when the current port pair includes a start port and an end port, the direction search strategy can include a preset direction strategy to require the wiring path to proceed from the start port to the end port, without going in the opposite direction (i.e., going back); it can also include a low-obstacle-density direction priority strategy to require selecting the direction with low obstacle density. Combined with the depth-first search algorithm, it avoids obstacle graphics, already wired graphics, and already wired paths to achieve optimal path finding. For example, the depth-first search algorithm can determine the wiring path for the current port pair based on the path estimation value of each optional path, such as determining the optional path with the largest or smallest path estimation value as the wiring path for the current port pair; the path estimation value can be the number of steps taken + the estimated number of remaining steps + (obstacle avoidance penalty coefficient × number of obstacle avoidance attempts); for example, the obstacle avoidance penalty coefficient can be 0.3.

[0041] Correspondingly, the path search process described above can also include a backtracking mechanism. When the path search for the current port pair fails, backtracking information is obtained, and based on this information, a path search is performed again for the current port in a rasterized two-dimensional array. If successful, the wiring path for the current port pair is obtained; if unsuccessful, backtracking information is obtained again until success is achieved or the number of backtracking iterations for the current port pair reaches a preset number, at which point wiring failure is confirmed. This backtracking mechanism can be combined with a depth-first search algorithm. If a dead end is encountered (i.e., the path search fails), the previous path is backtracked to find another path, utilizing the depth-first search algorithm to achieve optimal path finding.

[0042] The preset backtracking number can be the maximum number of line backtrackings for each port pair that is set in advance. This embodiment does not limit the specific value of the preset backtracking number. For example, the preset backtracking number can be a rasterized two-dimensional array or the total number of grids in the wiring area corresponding to the current port pair.

[0043] Furthermore, to avoid the frequent occurrence of deadlocks due to the ineffective handling of complex obstacle scenarios by a single backtracking strategy, this embodiment triggers a multi-level backtracking strategy when the path search for the current port pair fails, if the number of line backtracking attempts for the current port pair reaches a preset number. The multi-level backtracking strategy includes at least one of the following: backtracking to adjust the wiring order (i.e., adjusting the wiring order determined in step 103), backtracking to adjust the port pair (i.e., adjusting the port pair determined in step 102), and backtracking to adjust the raster precision of the rasterized two-dimensional array (i.e., adjusting the rasterized two-dimensional array in step 101). The current port pair can be any port pair. By combining the multi-level backtracking strategy with line backtracking in path search, a deadlock prevention mechanism is achieved, resolving wiring conflicts and resource allocation issues.

[0044] Correspondingly, when the path search for the current port pair fails and the number of backtracking steps for the current port pair has not reached the preset number of backtracking steps, backtracking information can be obtained, and based on the backtracking information, a path search can be performed again for the current port in the rasterized two-dimensional array (such as using the depth-first search algorithm mentioned above, and performing a path search for the current port pair in the rasterized two-dimensional array according to the direction search strategy).

[0045] Correspondingly, the specific process of triggering the multi-level backtracking strategy, i.e., the specific settings of the multi-level backtracking strategy, can be set by the designer. For example, the multi-level backtracking strategy can include three backtracking strategies: backtracking to adjust the routing order, backtracking to adjust port pairs, and backtracking to adjust the grid precision of the rasterized two-dimensional array. That is, when the multi-level backtracking strategy is triggered, if the number of first-level backtrackings has not reached the first threshold, the number of first-level backtrackings is incremented by 1, and the routing order of port pairs is adjusted, proceeding to step 104; if the number of first-level backtrackings reaches the first threshold, the number of first-level backtrackings is reset to zero, and if the number of second-level backtrackings has not reached the second threshold, the number of second-level backtrackings is incremented by 1, and port pairs are adjusted, proceeding to step 103; if the number of second-level backtrackings reaches the second threshold, the number of second-level backtrackings is reset to zero, and if the number of third-level backtrackings has not reached the third threshold, the number of third-level backtrackings is incremented by 1, the grid precision is adjusted, and the layout to be routed is mapped to a new rasterized two-dimensional array, proceeding to step 102. This enables a three-level rollback mechanism: the first level adjusts the wiring sequence; the second level optimizes port mapping; and the third level improves grid accuracy and reconstructs the two-dimensional array.

[0046] If the number of backtracking steps reaches the third threshold, it can be determined that the automated routing of the layout to be routed has failed, and an automated routing failure message can be output to prompt the user to perform manual routing or adjust the layout to be routed.

[0047] Specifically, the adjustments to routing order, port pairs, and grid precision in the aforementioned multi-level backtracking strategy can be customized by designers based on practical scenarios and user needs. For example, the routing order of all port pairs can be updated by adjusting the routing difficulty weight of the current port pair (i.e., the port pair where path search failed). Alternatively, the routing difficulty weight of the current port pair can be increased, for instance, by updating it to its product with 1.5, i.e., the routing difficulty weight W = W × 1.5. Port pairs can be adjusted by modifying the pairing strategy, such as changing the intra-group priority pairing strategy to an adjacent quadrant group priority pairing strategy, a horizontal adjacent quadrant group priority pairing strategy, or a vertical adjacent quadrant group priority pairing strategy. The rasterized two-dimensional array obtained from the mapping of the layout to be routed can be updated by increasing the grid precision (e.g., increasing it by one level) of all or part of the layout area in the layout to be routed (e.g., the layout area traversed by the routing area of ​​the current port pair).

[0048] Furthermore, in this embodiment, after obtaining the wiring path for each port pair, the Bézier curve method can be used to smooth the corners (such as right angles) of each wiring path to obtain the optimized wiring path for each port pair. In other words, this embodiment can use the Bézier curve method to achieve wiring path smoothing and reduce signal reflection caused by right-angle turns.

[0049] In this embodiment, the present invention obtains the wiring path of each port pair by sequentially searching the path in a gridded two-dimensional array according to the wiring order. This enables the determination of the wiring path of each pair of ports in the quantum chip layout, realizes automated wiring of the quantum chip layout, reduces the workload of relevant personnel, and improves wiring efficiency.

[0050] Corresponding to the above method embodiments, this invention also provides a wiring device for a quantum chip layout. The wiring device for a quantum chip layout described below and the wiring method for a quantum chip layout described above can be referred to in correspondence.

[0051] Please refer to Figure 5 , Figure 5 This is a structural block diagram of a wiring device for a quantum chip layout provided in an embodiment of the present invention. The device may include: The rasterization module 10 is used to map the layout to be wired into a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are the identifiers of each preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics and obstacle graphics; The pairing module 20 is used to pair port identifiers according to the location information of each port identifier to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair; The sorting module 30 is used to sort the port pairs according to the port distance of each port pair and determine the wiring order; The wiring module 40 is used to perform path search in a rasterized two-dimensional array for each port pair according to the wiring order, and obtain the wiring path for each port pair.

[0052] In some embodiments, the rasterization module 10 may include: The partitioning submodule is used to divide the routing layout into regions, resulting in each layout region. The size determination submodule is used to determine the grid size of each map region based on the area density of each map region; wherein, the grid size of the first map region is smaller than the grid size of the second map region, the area density of the first map region is greater than the area density of the second map region, and the first map region and the second map region are any two map regions. The modeling submodule is used to perform raster modeling on each map area according to the grid size, and obtain a rasterized two-dimensional array.

[0053] In some embodiments, the pairing module 20 may include: The grouping submodule is used to group the port identifiers into quadrants based on the coordinate positions of each port identifier in the preset coordinate system, thus obtaining each quadrant group. The pairing submodule is used to pair port identifiers in each quadrant group according to the group priority pairing strategy to determine each port pair.

[0054] In some embodiments, the sorting module 30 may include: The weight calculation submodule is used to calculate the cabling difficulty weight of each port pair; wherein, the cabling difficulty weight of the current port pair is calculated based on the port distance of the current port pair and the obstacle density of the cabling area corresponding to the current port pair; the current port pair is any port pair; The port pair sorting submodule is used to sort port pairs according to the difficulty weight of routing to determine the routing order.

[0055] In some embodiments, the weight calculation submodule can be specifically used to calculate the quotient of the area occupied by obstacles in the cabling area corresponding to the current port pair and the cabling area to obtain the obstacle density; calculate the product of the sum of the obstacle density and 1 and the port distance of the current port pair to obtain the cabling difficulty weight of the current port pair.

[0056] In some embodiments, the wiring module 40 may include: The path search submodule is used to perform path search in a rasterized two-dimensional array for the current port pair using a depth-first search algorithm and a direction search strategy to obtain the wiring path for the current port pair; wherein, the direction search strategy includes a low obstacle density direction priority strategy; the current port pair can be any port pair.

[0057] In some embodiments, the wiring module 40 may include: The multi-level backtracking submodule is used to trigger a multi-level backtracking strategy when the path search for the current port pair fails and the number of backtracking attempts for the current port pair reaches a preset number of backtracking attempts. The multi-level backtracking strategy includes at least one of the following backtracking strategies: backtracking to adjust the wiring order, backtracking to adjust the port pair, and backtracking to adjust the grid precision of the rasterized two-dimensional array. The current port pair can be any port pair.

[0058] In some embodiments, the multi-level backtracking submodule may include: The first-level backtracking unit is used to increment the first-level backtracking count by 1 and adjust the wiring order of the port pair if the first-level backtracking count has not reached the first threshold, and send a start signal to the wiring module 40. The secondary backtracking unit is used to reset the primary backtracking count to zero if the primary backtracking count reaches the first threshold, and to increment the secondary backtracking count by 1 if the secondary backtracking count does not reach the second threshold, adjust the port pair, and send a start signal to the sorting module 30. The third-level backtracking unit is used to reset the second-level backtracking count to zero when the second-level backtracking count reaches the second threshold, and to increment the third-level backtracking count by 1 when the third-level backtracking count does not reach the third threshold. It adjusts the grid precision, maps the layout to be routed into a new gridded two-dimensional array, and sends a start signal to the pairing module 20.

[0059] In this embodiment, the sorting module 30 searches for the routing path of each port pair in a gridded two-dimensional array according to the routing order to obtain the routing path of each port pair. This can determine the routing path of each pair of ports in the quantum chip layout, realize automated routing of the quantum chip layout, reduce the workload of relevant personnel, and improve routing efficiency.

[0060] Corresponding to the above method embodiments, this invention also provides a wiring device for a quantum chip layout. The wiring device for a quantum chip layout described below and the wiring method for a quantum chip layout described above can be referred to in correspondence.

[0061] Please refer to Figure 6 , Figure 6 This is a schematic diagram of a wiring device for a quantum chip layout provided in an embodiment of the present invention. The device may include: Memory D1 is used to store computer programs; Processor D2 is used to implement the wiring method of the quantum chip layout provided in the above method embodiments when executing a computer program.

[0062] In this embodiment, the wiring device for the quantum chip layout can specifically be a computer device or a server.

[0063] Corresponding to the above method embodiments, this invention also provides a computer program product. The computer program product described below and the wiring method for a quantum chip layout described above can be referred to each other.

[0064] A computer program product includes a computer program / instructions that, when executed by a processor, implement the wiring method for the quantum chip layout provided in the above-described method embodiments.

[0065] Corresponding to the above method embodiments, this invention also provides a computer-readable storage medium. The computer-readable storage medium described below and the wiring method for a quantum chip layout described above can be referred to in correspondence.

[0066] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the wiring method for a quantum chip layout as provided in the above method embodiments.

[0067] The computer-readable storage medium can specifically be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0068] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, computer-readable storage media, and computer program products disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0069] The wiring method, apparatus, and device for quantum chip layout provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A wiring method for a quantum chip layout, characterized in that, include: The layout to be wired is mapped as a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are the identifiers of each preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics, and obstacle graphics; Based on the location information of each port identifier, the port identifiers are paired to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair; Based on the port distance between each port pair, the port pairs are sorted to determine the wiring order; According to the wiring order, path search is performed on each of the port pairs in the rasterized two-dimensional array to obtain the wiring path of each port pair.

2. The wiring method for quantum chip layout according to claim 1, characterized in that, The step of mapping the layout to be wired into a rasterized two-dimensional array includes: The layout to be routed is divided into regions to obtain each layout region; Based on the area density of each of the aforementioned map regions, the grid size of each map region is determined; wherein, the grid size of the first map region is smaller than the grid size of the second map region, the area density of the first map region is greater than the area density of the second map region, and the first map region and the second map region are any two of the aforementioned map regions; Based on the grid size, each of the map regions is rasterized and modeled to obtain the rasterized two-dimensional array.

3. The wiring method for quantum chip layout according to claim 1, characterized in that, The step of pairing the port identifiers according to their location information to determine each port pair includes: Based on the coordinate positions of each port identifier in the preset coordinate system, the port identifiers are grouped into quadrants to obtain each quadrant group; According to the priority pairing strategy within the group, the port identifiers in each quadrant group are paired to determine each port pair.

4. The wiring method for quantum chip layout according to claim 1, characterized in that, The step of sorting the port pairs according to the port distance of each port pair to determine the wiring order includes: Calculate the cabling difficulty weight for each of the port pairs; wherein, the cabling difficulty weight for the current port pair is a weight calculated based on the port distance of the current port pair and the obstacle density of the cabling area corresponding to the current port pair; the current port pair is any of the port pairs. The port pairs are sorted according to the wiring difficulty weight to determine the wiring order.

5. The wiring method for quantum chip layout according to claim 4, characterized in that, The calculation of the cabling difficulty weight for each of the port pairs includes: The obstacle density is obtained by calculating the quotient of the area occupied by obstacles in the cabling area corresponding to the current port and the cabling area. The cabling difficulty weight of the current port pair is obtained by multiplying the sum of the obstacle density and 1 by the port distance of the current port pair.

6. The wiring method for quantum chip layout according to claim 1, characterized in that, The step of performing path search in the rasterized two-dimensional array for each port pair according to the wiring order to obtain the wiring path for each port pair includes: A depth-first search algorithm is used to perform a path search for the current port pair in the rasterized two-dimensional array according to the direction search strategy to obtain the wiring path of the current port pair; wherein, the direction search strategy includes a low obstacle density direction priority strategy; the current port pair is any of the port pairs.

7. The wiring method for quantum chip layout according to any one of claims 1 to 6, characterized in that, The step of performing path search in the rasterized two-dimensional array for each port pair according to the wiring order to obtain the wiring path for each port pair includes: If the path search for the current port pair fails, and the number of backtracking attempts for the current port pair reaches a preset number of backtracking attempts, a multi-level backtracking strategy is triggered. The multi-level backtracking strategy includes at least one of the following backtracking strategies: backtracking to adjust the wiring order, backtracking to adjust the port pair, and backtracking to adjust the grid precision of the rasterized two-dimensional array. The current port pair is any of the aforementioned port pairs.

8. The wiring method for quantum chip layout according to claim 7, characterized in that, The multi-level backtracking strategy includes: If the first-level backtracking count does not reach the first threshold, the first-level backtracking count is incremented by 1, and the routing order of the port pairs is adjusted. The step of performing path search in the rasterized two-dimensional array for each port pair according to the routing order to obtain the routing path of each port pair is then executed. If the first-level backtracking count reaches the first threshold, the first-level backtracking count is cleared to zero, and if the second-level backtracking count does not reach the second threshold, the second-level backtracking count is incremented by 1, the port pairs are adjusted, and the steps of sorting the port pairs according to the port distance of each port pair and determining the wiring order are executed. When the number of secondary backtracking reaches the second threshold, the number of secondary backtracking is cleared to zero. When the number of tertiary backtracking does not reach the third threshold, the number of tertiary backtracking is incremented by 1. The grid precision is adjusted, and the layout to be routed is mapped to a new gridded two-dimensional array. The step of pairing the port identifiers according to the position information of each port identifier to determine each port pair is executed.

9. A wiring device for a quantum chip layout, characterized in that, include: A rasterization module is used to map the layout to be wired into a rasterized two-dimensional array; wherein, the values ​​in the rasterized two-dimensional array are the identifiers of various preset graphic information of the quantum chip layout; the preset graphic information includes port graphics, blank graphics, and obstacle graphics; A pairing module is used to pair the port identifiers according to the location information of each port identifier to determine each port pair; wherein, the port identifier is the identifier of the port graphic, each port pair includes two port identifiers, and each port identifier belongs to one port pair; The sorting module is used to sort the port pairs according to the port distance of each port pair to determine the wiring order; The wiring module is used to perform path search in the rasterized two-dimensional array for each port pair in the wiring order to obtain the wiring path for each port pair.

10. A wiring device for quantum chip layout, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the wiring method for a quantum chip layout as described in any one of claims 1 to 8 when executing the computer program.

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