Dynamic layout optimization

Abstract

The present disclosure relates to layout recommendations, and more specifically to a dynamic layout optimization system, process, and method of use. The method includes determining a mismatch between design annotations and layout data for an integrated circuit; generating a suggestion to correct the mismatch between the design annotations and the layout data for the integrated circuit; providing an output regarding the mismatch between the design annotations and the layout data for the integrated circuit including the suggestion; and saving the mismatch and the suggestion to a log file.

Description

Technical Field

[0001] This disclosure relates to layout recommendations, and more specifically to dynamic layout optimization systems, processes, and methods of use. Background Technology

[0002] As process technology improves, the fabrication of integrated circuit devices has become more complex. To meet the challenge of building more complex and higher-performance integrated circuits, software tools, including computer-aided design (CAD), computer-aided engineering (CAE), or electronic design automation (EDA) suites, are used.

[0003] Furthermore, netlists and layouts can be used to define integrated circuits. A netlist provides information about the devices or components of an integrated circuit and their connections. An integrated circuit layout is a representation of the integrated circuit in terms of its geometry, pattern, and features corresponding to the mask used to manufacture the circuit. Certain features in the layout or a specific mask can be automatically generated, such as the automatic placement and routing of components. Summary of the Invention

[0004] In one aspect of this disclosure, a method includes: determining a mismatch between design notes and layout data of an integrated circuit; generating suggestions to correct the mismatch between the design notes and the layout data of the integrated circuit; providing an output including the suggestions regarding the mismatch between the design notes and the layout data of the integrated circuit; and saving the mismatch and the suggestions to a log file.

[0005] In one aspect of this disclosure, a computer program product includes one or more computer-readable storage media on which program instructions are collectively stored. The program instructions are executable to: parse guidance text annotations in a schematic into rules; check the rules relative to a corresponding layout to determine matches and mismatches between the rules and the corresponding layout; and generate a report indicating whether the parsed guidance text annotations conform to the corresponding layout.

[0006] In one aspect of this disclosure, a system includes: a processor, a computer-readable storage medium, one or more computer-readable storage media, and program instructions collectively stored on the one or more computer-readable storage media, the program instructions being executable to: extract schematic design annotations of an integrated circuit; parse a netlist and determine a layout geometry of the integrated circuit; compare the layout geometry with the schematic annotations to determine mismatches and matches between the layout geometry and the schematic annotations; and based on the comparison between the layout geometry and the schematic annotations, align the design intent with the schematic design. Attached Figure Description

[0007] In the following detailed description, the present disclosure is described with reference to the various accompanying drawings, using non-limiting examples of exemplary embodiments of the present disclosure.

[0008] Figure 1 A cloud computing node according to an embodiment of the present disclosure is depicted.

[0009] Figure 2 A block diagram of an exemplary environment according to aspects of this disclosure is shown.

[0010] Figure 3 A general flowchart according to an aspect of the invention is shown.

[0011] Figure 4 The aspects of this disclosure are illustrated, for example, using Figure 3 A sample report format for a general flowchart (e.g., a table).

[0012] Figure 5 A portion of the design layout and mismatched graphical representation and reporting formats (e.g., tables) according to aspects of this disclosure are shown.

[0013] Figure 6 A flowchart of an aspect according to this disclosure is shown.

[0014] Figure 7 A flowchart is shown for contextual design discrepancy detection (CDDD), which is used to identify mismatches between design annotations and layout data according to aspects of this disclosure.

[0015] Figure 8 A flowchart is shown of a custom-formatted discrepancy reporting (CFDR) used to provide reports on mismatch and matching information according to aspects of this disclosure.

[0016] Figure 9A flowchart of a context-aware correction suggestion (CACS) for generating suggestions is shown according to aspects of this disclosure.

[0017] Figure 10 A flowchart is shown of an artificial intelligence (AI) context-aware process for implementing aspects of this disclosure.

[0018] Figure 11 An illustrative SPICE netlist / CDL for use with embodiments of this disclosure is shown. Detailed Implementation

[0019] This disclosure relates to layout recommendations, and more specifically to dynamic layout optimization systems, processes, and methods of use. More specifically, this disclosure relates to a dynamic layout optimization method utilizing embedded schematic design recommendations. For example, the process, system, and computer program product provide a layout check in which guidance text annotations in the schematic can be parsed into rules for checking relative to the corresponding layout. Thus, the process and system provide layout recommendations by cross-referencing schematic design annotations with layout data and generating corrective suggestions to ensure compliance with design intent.

[0020] In more specific embodiments, the processes, systems, and computer program products (also referred to as “tools”) described herein provide technical solutions to technical problems. Specifically, in embodiments, this disclosure addresses the problem of placement engineers lacking critical design annotations from analog design engineers. These critical design annotations are essential in design tools for ensuring the proper configuration and matching of devices (e.g., transistors, etc.) during placement creation. The lack of annotations can lead to significant performance problems in high-precision circuits. However, by implementing the processes and systems described herein, a unique integration of schematic design annotations can now be introduced into the placement phase, providing continuous feedback, predictive suggestions, and context-aware corrective actions. Therefore, unlike known systems and processes that focus on placement automation or design obfuscation, this tool (e.g., system and process) automatically cross-references schematics with placement data, detects mismatches, and generates actionable reports.

[0021] Advantageously, the dynamic layout optimization method described herein offers faster turnaround time, reduced costs, and improved quality. For example, this dynamic layout optimization accelerates the design process (reducing delays) and eliminates the need for layout engineers to switch between schematic and layout views. Furthermore, this dynamic layout optimization minimizes errors and modifications, thereby reducing manufacturing costs, while also ensuring design accuracy and reliability, thus improving product performance.

[0022] This disclosure can be any possible system, method, and / or computer program product at any level of integration technical detail. The computer program product may comprise a computer-readable storage medium having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0023] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital universal disc (DVD), memory sticks, floppy disks, mechanical encoding devices (such as punched cards or raised structures in grooves having instructions recorded thereon), and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0024] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a corresponding computing / processing device, or downloaded to an external computer or external storage device via a network (e.g., the Internet, a local area network, a wide area network, and / or a wireless network). The network may include copper transmission cables, optical fiber transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the corresponding computing / processing device.

[0025] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​(e.g., Smalltalk, C++, etc.) and procedural programming languages ​​(e.g., the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)) or may be connected to an external computer (e.g., via the Internet provided by an Internet service provider). In some embodiments, electronic circuitry (including, for example, programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs)) may execute the computer-readable program instructions to personalize the electronic circuitry in order to perform aspects of this invention by utilizing the state information of the computer-readable program instructions.

[0026] This document describes aspects of the invention with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0027] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more boxes of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer-readable storage medium having the instructions stored therein includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0028] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0029] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutively shown blocks may actually be implemented as a single step, executed in parallel, executed substantially in parallel, executed in a manner that partially or completely overlaps in time, or they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0030] It should be understood that although this disclosure includes a detailed description of cloud computing, the implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention can be implemented in conjunction with any other type of computing environment now known or developed hereafter.

[0031] Cloud computing is a service delivery model for convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing power, memory, storage, applications, virtual machines, and services) that can be rapidly deployed and released with minimal management costs or minimal interaction with the service provider. This cloud model may include at least five features, at least three service models, and at least four deployment models.

[0032] The characteristics are as follows:

[0033] On-demand self-service: Cloud consumers can unilaterally and automatically deploy computing power such as server time and network storage on demand without human interaction with service providers.

[0034] Wide network access: Capabilities are available on the network and accessed through standard mechanisms that facilitate the use of heterogeneous thin or thick client platforms such as mobile phones, laptops, and PDAs.

[0035] Resource Pool: The provider's computing resources are grouped into a resource pool and served to multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and reallocated on demand. Generally, consumers cannot control or even know the exact location of the provided resources, but can specify the location at a higher level of abstraction (e.g., country, state, or data center), thus exhibiting location independence.

[0036] Rapid and elastic: The ability to rapidly and elastically (sometimes automatically) deploy computing power for quick scaling up and down. From the consumer's perspective, the available computing power for deployment often appears unlimited, with any amount of computing power available at any time. In this embodiment, the model implemented in the cloud is scalable.

[0037] Measurable services: Cloud systems automatically control and optimize resource utilization by leveraging metering capabilities at a certain level of abstraction appropriate to service types (such as storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both service providers and consumers.

[0038] The service model is as follows:

[0039] Software as a Service (SaaS): This provides consumers with the ability to use applications running on a provider's cloud infrastructure. These applications can be accessed from various client devices via thin client interfaces such as web browsers (e.g., web-based email). Aside from limited user-specific application configuration settings, consumers neither manage nor control the underlying cloud infrastructure, including the network, servers, operating system, storage, and even individual application capabilities.

[0040] Platform as a Service (PaaS): This provides consumers with the ability to deploy consumer-created or acquired applications on cloud infrastructure, using programming languages ​​and tools supported by the provider. Consumers neither manage nor control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but they have control over the deployed applications and may also have control over the configuration of the application hosting environment.

[0041] Infrastructure as a Service (IaaS): This provides consumers with the capability to deploy and run any software, including operating systems and applications, on the underlying cloud infrastructure, providing them with processing, storage, networking, and other basic computing resources. Consumers neither manage nor control the underlying cloud infrastructure, but they have control over the operating system, storage, and deployed applications, and may have limited control over chosen network components (such as host firewalls).

[0042] The deployment model is as follows:

[0043] Private cloud: The cloud infrastructure runs exclusively for a single organization. The cloud infrastructure can be managed by that organization or a third party and can exist inside or outside the organization.

[0044] Community cloud: A cloud infrastructure shared by several organizations that supports a specific community with common interests (such as mission, security requirements, policy, and compliance considerations). A community cloud can be managed by multiple organizations or third parties and can exist inside or outside the community.

[0045] Public cloud: Cloud infrastructure that is available to the public or large industrial groups and is owned by organizations that sell cloud services.

[0046] Hybrid cloud: A cloud infrastructure consisting of two or more clouds (private, community, or public) that remain distinct entities but are bound together by standardized or proprietary technologies that enable data and applications to be ported together, such as cloud bursts for load balancing between clouds.

[0047] Cloud computing environments are service-oriented, characterized by statelessness, loose coupling, modularity, and semantic interoperability. The core of cloud computing is its infrastructure, which comprises a network of interconnected nodes.

[0048] Now for reference Figure 1 The diagram illustrates an example of a cloud computing node. Cloud computing node 10 is merely one example of a suitable cloud computing node and is not intended to imply any limitation on the functionality or scope of use of the embodiments of the invention described herein. In summary, cloud computing node 10 can be used to implement and / or perform any of the functions described above.

[0049] Cloud computing node 10 includes a computer system / server 12, which can operate with a wide range of other general-purpose or special-purpose computing system environments or configurations. Well-known examples of computing systems, environments, and / or configurations suitable for use with computer system / server 12 include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing technology environments that include any of the aforementioned systems or devices, etc.

[0050] Computer system / server 12 can be described in the general context of computer system executable instructions (such as program modules) executed by the computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., that perform specific tasks or implement specific abstract data types. Computer system / server 12 can be implemented in a distributed cloud computing environment where tasks are performed on remote processing devices linked via a communication network. In a distributed cloud computing environment, program modules can reside on local and remote computer system storage media, including memory storage devices.

[0051] like Figure 1 As shown, the computer system / server 12 in cloud computing node 10 is illustrated in the form of a general-purpose computing device. The components of the computer system / server 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 that couples various system components (including system memory 28) to the processor 16.

[0052] Bus 18 represents one or more bus architectures of any type among several types, including memory buses or memory controllers, peripheral buses, graphics acceleration ports, and local buses of processors or any of the multiple bus architectures. For example, such architectures include, but are not limited to, Industry Standard Architecture (ISA) buses, Micro Channel Architecture (MAC) buses, Enhanced ISA (EISA) buses, Video Electronics Standards Association (VESA) local buses, and Peripheral Component Interconnect (PCI) buses.

[0053] Computer system / server 12 typically includes various computer system readable media. Such media can be any available media that can be accessed by computer system / server 12, including volatile and non-volatile media, removable and non-removable media.

[0054] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer system / server 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be provided for reading and writing to non-removable non-volatile magnetic media (not shown, generally referred to as "hard disk drives"). Although not shown, disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disk drives for reading and writing to removable non-volatile optical disks (e.g., CD-ROMs, DVD-ROMs, or other optical media) may be provided. In these examples, each may be connected to bus 18 via one or more data media interfaces. As will be further shown and described below, memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of embodiments of the present invention.

[0055] A program / utility 40 having a set (at least one) of program modules 42 may be stored in memory 28, such as, but not limited to, an operating system, one or more applications, other program modules, and program data. Each of the operating system, one or more applications, other program modules, and program data, or some combination thereof, may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods of embodiments of the invention described herein.

[0056] Computer system / server 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.); one or more devices that enable a user to interact with computer system / server 12; and / or any device that enables computer system / server 12 to communicate with one or more other computing devices (e.g., network interface card, modem, etc.). This communication can occur through input / output (I / O) interface 22. Furthermore, computer system / server 12 can communicate with one or more networks (e.g., local area network (LAN), general wide area network (WAN), and / or public network (e.g., the Internet)) via network adapter 20. As shown, network adapter 20 communicates with other components of computer system / server 12 via bus 18. It should be understood that, although not shown, other hardware and / or software components can be used in conjunction with computer system / server 12. Examples include, but are not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archiving storage systems.

[0057] Those skilled in the art will understand that a cloud computing environment includes one or more cloud computing nodes 10, and local computing devices are used by cloud consumers along with the cloud computing nodes 10. Nodes 10 can communicate with each other. They can be physically or virtually grouped (not shown) in one or more networks (e.g., the aforementioned private cloud, community cloud, public cloud, or hybrid cloud, or a combination thereof). This allows the cloud computing environment to provide Infrastructure as a Service, Platform as a Service, and / or Software as a Service without requiring cloud consumers to maintain resources on their local computing devices. The model described herein can be scalable with the cloud computing environment.

[0058] In an embodiment, the computer system / server 12 may include different modules to perform the functions described herein, such as:

[0059] (i) Schematic annotations are integrated into the layout environment associated with specific devices in real time;

[0060] (ii) Continuous verification of layout adherence to design recommendations and standards (e.g., transistor matching in current mirrors);

[0061] (iii) Predictive feedback that does not conform to design recommendations, such as asymmetry in high-precision current mirrors leading to uneven etching and performance issues;

[0062] (iv) Generate and display design annotations and related layout objects (e.g., transistors, resistors, capacitors, inductors);

[0063] (v) Context-aware guidance that dynamically updates based on the layout engineer's current area of ​​interest within the Cadence Virtuoso environment; and

[0064] (vi) A real-time feedback mechanism that alerts layout engineers when design standards are not met during the layout process.

[0065] As further described herein, the system and process described can provide the above functionality through a transformation script and a design recommendation algorithm. The transformation script converts schematic design annotations into a format suitable for comparison with layout data, and the design recommendation algorithm analyzes the schematic and layout comparison results. Based on this analysis, the system generates executable recommendations to correct any mismatches or potential problems in the layout.

[0066] Figure 2 A block diagram of an exemplary environment according to aspects of the present invention is shown. In an embodiment, the environment includes... Figure 1At least one processing tool 100, such as a schematic-to-layout verification tool 100, communicates with the computer system / server 12. The processing tool 100 verifies and optimizes the IC layout by comparing schematic design annotations with layout data, detecting discrepancies using transformation scripts and rule-based algorithms, and providing corrective suggestions, thereby ensuring alignment with design intent. Figure 1 This will improve the accuracy and efficiency of the design process.

[0067] More specifically, the processing tool 100 can be implemented through transformation scripts and a design recommendation algorithm. The transformation scripts convert schematic design annotations into a format suitable for comparison with layout data, and the design recommendation algorithm analyzes the results of the schematic and layout comparison. Based on this analysis, the system generates executable recommendations to correct any mismatches or potential problems in the layout. For example, the processing tool 100 can communicate with, and / or include, a transformation script module 105 and a design recommendation module 110. The transformation script module 105 can transform scripts from different netlists; while the design recommendation module 110 can make recommendations using the actual design layout and the transformation of the scripts.

[0068] Those skilled in the art will understand that a netlist is a textual representation of an electronic circuit that describes how its components are connected. Similar to the source code of a circuit, a netlist can be a fundamental part of electronic design and is used to ensure the accuracy of the code.

[0069] Netlists can be used in several ways, including:

[0070] (i) Code Management: Netlists are used to manage the code used on printed circuit boards (PCBs);

[0071] (ii) Component placement: Netlists are used to place each component and its connections on the PCB;

[0072] (iii) Ensuring accuracy: Netlists are used to ensure the accuracy of any code; and / or

[0073] (iv) Bare board testing: Netlists are used by bare board manufacturers to compare the connectivity of the finished board to the input data.

[0074] In a more specific embodiment, the transformation script module 105 can transform the script by, for example, parsing the script, extracting circuit components and their connections, and generating a text file in a standard netlist format (e.g., SPICE), wherein the text file describes the circuit topology by listing each component and its corresponding node, essentially translating the script's logic into a format understandable by the circuit simulator. The design recommendation module 110 can compare the actual design layout with the transformed script (as further described herein, particularly regarding...) Figure 6-9 Based on the description, recommendations are made.

[0075] Figure 3 A general flowchart according to aspects of this disclosure is shown. In step 300, the process extracts schematic design annotations. This may include key design specifications. In step 305, the process extracts layout data. This may include component placement, layer information, and other layout information. In step 310, the process provides data transformation. This may include transforming both the schematic annotations and the layout data.

[0076] In step 315, the process performs netlist parsing and determines the layout geometry. In step 320, the process compares the layout geometry with schematic annotations, such as key aspects of the design. This can be performed using a cross-comparison algorithm that tracks mismatches between the layout geometry and the intended design (e.g., from layout data). In step 325, the process takes corrective actions. This can include aligning the design intent with the schematic itself, for example, making recommendations to correct any issues with the layout geometry. The process then continues again at step 305.

[0077] Figure 4 It shows the use of, for example Figure 3 A sample report format for a general flowchart (e.g., a table). Figure 4 Example table 400 includes several columns: design note 405, layout data 410, mismatch 415, suggestion 420, and match status 425. In the example, table 400 shows a mismatch between design note 405 and layout data 410 in rows 2, 3, and 5. On the other hand, a match between design note 405 and layout data 410 is visible in rows 1 and 4. For illustration, in row 2, design note 405 includes "Keep capacitor C5 and C6 close to power lines," while layout data 410 states "Capacitors C5 and C6 are far from the power lines." The process of this disclosure will indicate the mismatch in row 415 and make a suggestion in row 420.

[0078] As another example, Figure 5A portion of the design layout and mismatched diagrammatic representation, as well as a reporting format (e.g., a table), according to aspects of this disclosure are shown. In this example, design note 405 includes "Match transistors M1 and M2 in the middle of the current mirror," while layout data 410 indicates "Transistors M1 and M2 are not in the middle of the current mirror." Layout 500a represents a design note, and layout 500b represents a layout view. These layouts (and others) can be represented graphically in reports as described herein. Figure 5 The diagram also shows 500b, which represents... Figure 11 SPICE netlist / CDL circuit 1100.

[0079] Figure 6 A flowchart illustrating aspects of this disclosure is shown. Specifically, Figure 6 It shows the relationship with Figure 2 The block diagram illustrates the associated processing steps, more specifically, the process performed by the schematic-to-layout verification tool 100. Those skilled in the art will understand that the schematic-to-layout verification tool 100 represents transforming schematic and layout data into a comparable format, applying rule-based algorithms to check for discrepancies, and ensuring that the layout conforms to design intent as specified in the schematic. Tool 100 checks component matching, correct connections, and parameter compliance, thereby generating recommendations for corrective actions as needed, as described in more detail herein.

[0080] exist Figure 6 In the flowchart, two options, among others, can be used for data input: (i) SPICE netlist / CDL and GDSII / OASIS; and (ii) schematic view and layout view. Figure 11 An exemplary SPICE netlist / CDL1100 is shown. Data extraction (design annotations and layout data) will be placed into the schematic-to-layout verification tool 100 at step 600. The schematic-to-layout verification tool 100 will use this information to determine at step 605 whether there is a mismatch between the design annotations and the layout data. This can be achieved through methods such as... Figure 7 The context design difference detection (CDDD) shown and described is used to provide a determination of whether a match or not is made.

[0081] At step 610, the process is formatted, for example, as shown in... Figure 4 The report provides information on mismatches and matches. This processing step can be achieved through methods such as... Figure 8 This is accomplished using the Custom Format Difference Report (CFDR) shown and described. At step 615, the process generates recommendations based on the mismatch. This processing step can be performed as follows: Figure 9 The Context-Aware Correction Suggestion (CACS) method, as shown and described, is used to complete this process. At step 620, the results of processing steps 605, 610, and 615 (e.g., including mismatches and suggestions) are saved to a log file. This step ensures that all processed data, identified problems, and suggested corrections are properly recorded and stored. At step 625, the process will highlight the differences, for example, such as... Figure 4 and Figure 5 The matching and non-matching are shown. In this way, predictive feedback can be provided for results that do not conform to the design recommendations.

[0082] Figure 7 A flowchart of Contextual Design Difference Detection (CDDD), according to aspects of this disclosure, is shown. The process described herein identifies mismatches between schematic designs and their corresponding layouts by understanding and analyzing the context of the design annotations.

[0083] For example, at step 700, the process extracts design notes. This may include, for example, electrical specifications, component requirements, and connection rules. At step 705, the process provides output. As an example, the output could be “[{'Component': 'Capacitor C1', 'Node 1': 'A', 'Node 2': 'B', 'Tolerance': '5%'}]”.

[0084] At step 710, the process provides a context map of the output. In an embodiment, context mapping is a technique used in data processing and analysis to organize, link, and visualize relationships between data objects (typically in the form of domain-driven design).

[0085] At step 715, the process performs a check to determine whether the layout conforms to the schematic design intent. At step 720, the process outputs a result, for example, mismatch or match. In an embodiment, the output may be, for example, whether the mismatch is within tolerance, such as capacitor C1 being within 5% of its design parameters.

[0086] At step 725, the process maps the extracted design annotations to corresponding layout elements. At step 730, the process determines whether there are any discrepancies between the extracted design annotations and the corresponding layout elements. At step 735, the process compares the expected design with the parameters. If the comparison is not above a specific threshold or is determined to be insignificant (e.g., minimal impact), the process ends, and all results are saved, as per [reference to previous steps]. Figure 6 As described in step 620.

[0087] If the comparison is above a specific threshold or is not insignificant, then at step 740, the process flags, for example, any difference above the specific threshold. As an illustrative example, if it is determined that capacitor connections in the layout are between different nodes or that the tolerance exceeds a specific threshold, such as 5%, the process can flag the difference. The process then proceeds to... Figure 6 Step 610 (about Figure 8 (To be described in more detail). In this way, the process provides continuous verification of the layout's adherence to design recommendations.

[0088] Figure 8 A flowchart of a Custom Format Difference Report (CFDR) for providing reports of mismatch and matching information, according to aspects of this disclosure, is shown. For example, Figure 8 The process can generate visual and text-based reports that are easy to interpret and can be used to implement actions, such as specific recommendations.

[0089] As an example, at step 800, the process generates a visual and text-based report. This report can be generated by collecting data and then, using conventional data visualization tools (e.g., a dedicated data visualization platform), can create graphs, charts, and tables illustrating the matching, non-matching, and other data points described herein, while writing descriptive text to explain the data and insights within the visuals, ensuring coherent presentation.

[0090] At step 805, the process can apply formatting rules to highlight key issues. At step 810, reports can be output to the user. These reports can represent... Figure 4 and Figure 5 The table shown. These reports can highlight key differences and tolerance mismatches. Explanatory reports can be “'Critical': [], 'Non-critical': ['Tolerance mismatch of capacitor C1']”. The process then proceeds to… Figure 6 Step 615 (about Figure 9 (To be described in more detail).

[0091] Figure 9 A flowchart of a Context-Aware Correction Suggestion (CACS) for generating suggestions is shown according to aspects of this disclosure. Figure 9 Specifically, the process of generating corrective recommendations based on identified differences, taking into account the design context, is illustrated.

[0092] Specifically, at step 900, the process performs contextual analysis. As mentioned earlier, contextual analysis is a method for understanding the environment in which something operates and how the different elements of that environment fit together. At step 905, the process identifies and generates the root cause of any discrepancies. The root cause could be a tolerance mismatch, manufacturing variation, etc.

[0093] At step 915, the process provides an output. The output can relate to any discrepancies found. For example, the output could be a suggestion regarding a tolerance mismatch for a specific feature of the design (i.e., the capacitor). This suggestion could be to increase the tolerance range or correct component placement.

[0094] At step 920, the process can generate customized suggestions from the output. At step 925, the process determines if any node mismatches are detected and if any suggestions are available. If not, the process proceeds to step 935, where executable suggestions are saved. At step 925, if any node mismatches are detected and suggestions are provided, the process continues to step 930. At step 930, a final suggestion can be made. The final suggestion may be, for example:

[0095] Recommendation: At word 6: Place components 'close to' each other instead of 'far from' each other. Proximity reduces parasitic inductance and resistance, improving performance. At word 7: Expected to be 'to', but found to be 'from'. Consider correcting this to conform to design specifications.

[0096] Recommendation: At the second point: Maintain a 'symmetrical' layout instead of an 'asymmetrical' layout. Symmetry helps balance electrical paths and avoid imbalance.

[0097] Recommendation: At the second word: Use a 'thick' metal layer instead of a 'thin' metal layer. A thicker metal layer reduces resistance and increases current carrying capacity.

[0098] The final recommendation can be saved at step 930.

[0099] Figure 10 An artificial intelligence (AI) context-aware process for implementing aspects of this disclosure is illustrated. These steps can be used, for example, to formulate recommendations based on differences and past experiences.

[0100] At step 1000, the process loads the dataset. The dataset may include, for example, a schematic view, extracted schematic design annotations, a layout view, a backup database, etc., where the backup database includes the LLM model and corrective actions. At step 1015, the process generates labels from the dataset. For example, "1" could represent a matching layout, and "0" could represent an incorrect layout. At step 1020, the process splits the data into training and testing data. The data can be split in various ways, such as 80% training data and 20% testing data. At step 1025, the process loads the pre-trained data into the model and performs tokenization. For example, as a non-limiting example, the pre-trained data could be a "DistilBERT-base-uncased" LLM model.

[0101] At step 1030, the process segments the data. For example, the input data used for the model can be segmented. At step 1035, the process customizes the dataset. This may include, for example, converting the segmented data into a customized dataset object. At step 1040, the process defines the trainer. This may include the model, training parameters, and metrics. At step 1045, the process trains the model on the training dataset.

[0102] In step 1050, the process is provided by the schematic to layout verification tool 100, such as... Figure 6-9 As shown. At step 1055, the data is saved. At step 1060, the process optionally backs up the LLM model (e.g., in the event of a primary model failure). At step 1065, the process optionally backs up corrective actions (e.g., in the event of a primary corrective action failure). At step 1070, the process terminates or waits for new data. The process may return to step 1010 to load a new or updated dataset and continue the process described herein.

[0103] Figure 11 An illustrative SPICE netlist / CDL 1100 is shown. For example, the SPICE netlist / CDL 1100 could be a circuit diagram 100 showing the matching of transistors M1 and M2 in the middle of a current mirror. This is also illustrated, for example, in graphical form. Figure 5 It is shown in reference numeral 500b.

[0104] Example use case #1:

[0105] In differential amplifier circuits, schematic notes specify the following: ensure symmetrical matching of transistors in the differential pair; shield output signals to prevent coupling and performance degradation; place symmetrical terminals to maintain balance; and use guard rings around sensitive components to reduce latch-up risk. The tool displays these recommendations in real time and continuously verifies that the layout adheres to these guidelines. If the layout does not meet these standards, the tool will alert the engineer and suggest corrective action.

[0106] Example use case #2:

[0107] In a precise current mirror circuit, schematic annotations specify the following: ensure that the transistors in the current mirror are matched in size and layout to minimize offset; maintain layout symmetry to prevent performance degradation; and use dummy transistors at the array edges to ensure uniform etching and reduce edge effects. The tool ensures these recommendations are followed during layout and provides immediate feedback if any issues arise, suggesting possible layout adjustments to maintain symmetry and matching.

[0108] Example use case #3:

[0109] For high-frequency amplifier blocks, the schematic includes notes on minimizing parasitic capacitance by avoiding long interconnects; using thick metal for signal paths to reduce resistance; and ensuring sufficient spacing between signal lines to prevent crosstalk. The tool monitors the placement process and informs engineers if any design options increase parasitic effects or crosstalk, thus recommending optimized routing paths.

[0110] Example use case #4:

[0111] In power management ICs, schematic annotations highlight: ensuring power transistors have appropriate heat sink and heat dissipation structures; using multiple vias for high-current paths to reduce resistance and inductance; and keeping analog and digital ground planes separated to minimize noise coupling. This tool provides real-time feedback on these aspects, alerting layout engineers when thermal management or noise isolation guidelines are not met.

[0112] The methods described in this paper can be utilized in System-on-Chip (SoC) technology. An SoC is an integrated circuit (also called a “chip”) that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated on a single substrate, an SoC consumes significantly less power and occupies a much smaller area compared to a multi-chip design with equivalent functionality. Therefore, SoCs are becoming a dominant force in the mobile computing (e.g., in smartphones) and edge computing markets. SoCs are also used in embedded systems and the Internet of Things (IoT).

[0113] The methods described above are used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in single-chip packages (e.g., plastic carriers with leads attached to a motherboard or other higher-level carriers) or multi-chip packages (e.g., ceramic carriers with surface interconnects or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0114] Various embodiments of this disclosure have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method comprising: Identify mismatches between integrated circuit design annotations and layout data; Proposals are generated to correct the mismatch between the design annotations and the layout data of the integrated circuit; Provides an output including the proposed design notes regarding the integrated circuit and the mismatch between the design notes and the layout data; as well as Save the mismatch and the suggestion to a log file.

2. The method according to claim 1, wherein, Determining the mismatch includes: The mismatch between the schematic design and its corresponding layout is identified by analyzing the context of the design annotations. Extract the design annotations; Provide a context mapping for the output, the context mapping including mapping the extracted design annotations to corresponding layout elements; and The layout is determined to conform to the intent of the schematic design.

3. The method according to claim 2, wherein, The design notes include at least one of electrical specifications, component requirements, or connection rules.

4. The method according to claim 2, wherein, The context mapping includes visualizing the relationship between the design annotations and the layout data.

5. The method according to claim 2, further comprising: Identify any discrepancies between the extracted design annotations and the corresponding layout elements; And compare the parameters between the expected design and the corresponding layout element.

6. The method according to claim 5, further comprising: The difference is marked above a predetermined threshold.

7. The method according to claim 1, further comprising: Report both mismatched and matching outputs, along with the suggested recommendations.

8. The method according to claim 7, wherein, The report includes generating visual and text-based reports to implement the recommendations.

9. The method according to claim 7, wherein, The report includes a chart layout that provides the recommendations.

10. The method according to claim 7, wherein, The report includes the application of formatting rules to highlight key issues in the integrated circuit.

11. The method according to claim 1, wherein, The generated suggestions include: Perform contextual analysis of at least the design annotations described above; Determine the root cause of any discrepancies, including at least tolerance mismatch and manufacturing variations; and Generate customized, executable recommendations related to the aforementioned differences.

12. A computer program product comprising one or more computer-readable storage media, wherein program instructions are collectively stored on the one or more computer-readable storage media, the program instructions being executable to: Parse the instruction text annotations in the schematic diagram into rules; The rules are checked relative to the corresponding layout to determine matches and mismatches between the rules and the corresponding layout; and Generate a report indicating whether the parsed guidance text annotations conform to the corresponding layout.

13. The computer program product of claim 12 further includes integrating the schematic diagram into a layout environment associated with a particular integrated circuit in real time.

14. The computer program product of claim 12 further includes continuous verification of the layout conformity to design recommendations.

15. The computer program product of claim 12 further includes predictive feedback for results that do not meet design recommendations.

16. The computer program product of claim 12 further includes generating and displaying design annotations by aligning with the relevant layout object.

17. A system comprising: A processor, a computer-readable storage medium, one or more computer-readable storage media, and program instructions collectively stored on said one or more computer-readable storage media, said program instructions being executable to: Extract schematic design annotations from integrated circuits; The netlist is parsed and the layout geometry of the integrated circuit is determined; Compare the layout geometry with the schematic annotation to determine mismatches and matches between the layout geometry and the schematic annotation; and Based on the comparison between the layout geometry and the schematic annotations, the design intent is made consistent with the schematic design.

18. The system according to claim 17, wherein, The comparison between the layout geometry and the schematic annotations includes a cross-comparison algorithm that tracks mismatches between the layout geometry and the intended design.

19. The system according to claim 17, wherein, The extraction includes extracting key design specifications, which include the layout data of the integrated circuit.

20. The system according to claim 19, wherein, The key design specifications include at least one of component placement or layer information and other layout information.

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